Semiconductor device and manufacturing method thereof

Abstract

To improve reliability of a semiconductor device.SOLUTION: A pad electrode PAD is formed in a wiring layer of the uppermost layer of a multi-layer wiring layer formed onto a semiconductor substrate. An insulation film IF1 is formed so as to cover the pad electrode PAD. In the insulation film IF1, an open part OP1 is formed so as to reach the pad electrode PAD. In the open part OP1, a conductive film PF1 as one part of a conductive layer OPM is electrically connected to the pad electrode PAD. In a side surface of the conductive film PF1, an oxide layer OX1 in which a material contained in the conductive film PF1 is oxidized is formed. The width of the oxide layer OX1 is 200nm or more.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a conductive layer formed on a pad electrode and a manufacturing method thereof. [Background technology]

[0002] To meet the demand for improved reliability of semiconductor devices, a structure has been proposed in which a conductive layer called an OPM (Over Pad Metal) electrode is formed on a pad electrode, which is part of the top-layer wiring of the multi-layer wiring formed on a semiconductor substrate. External connection members such as wire bonding are connected to this OPM electrode.

[0003] For example, Patent Document 1 describes a technique for forming rewiring by forming a conductive layer on a pad electrode by plating. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-206938 Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, efforts have been made to reduce the space between pad electrodes in order to facilitate design and reduce chip area. Furthermore, there is a demand for reducing the space between conductive layers, such as OPM electrodes or rewiring, formed on pad electrodes. This has led to factors such as conductive layer residue and electromigration, which have led to a decrease in the insulation between conductive layers and increased susceptibility to leakage current. Therefore, a technology is needed to resolve these issues and improve the reliability of semiconductor devices.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A brief summary of a representative embodiment of the present invention will be given below.

[0008] In one embodiment, a semiconductor device includes a multilayer wiring layer formed on a semiconductor substrate, a pad electrode formed in a top wiring layer of the multilayer wiring layer, an insulating film formed to cover the pad electrode, an opening formed in the insulating film to reach the pad electrode, and a first conductive film electrically connected to the pad electrode within the opening, wherein an oxide layer formed by oxidizing a material contained in the first conductive film is formed on a side surface of the first conductive film, and the width of the oxide layer is 200 nm or more.

[0009] A method for manufacturing a semiconductor device according to one embodiment includes the steps of: (a) forming a multilayer wiring layer on a semiconductor substrate; (b) forming an insulating film to cover a pad electrode formed in a topmost wiring layer of the multilayer wiring layer; (c) forming an opening in the insulating film to reach the pad electrode; (d) forming a first conductive film by plating on the pad electrode in the opening; and (e) performing an oxidation treatment on the first conductive film to form an oxide layer on a side surface of the first conductive film by oxidizing a material contained in the first conductive film, wherein the width of the oxide layer is 200 nm or more. [Effects of the Invention]

[0010] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2]1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 3] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 4] 4 is a cross-sectional view showing a manufacturing process of the semiconductor device following FIG. 3. [Figure 5] 5 is a cross-sectional view showing a manufacturing process of the semiconductor device following FIG. 4. [Figure 6] 6A to 6C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. 5. [Figure 7] 7A to 7C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. 6. [Figure 8] 8 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 7. [Figure 9] 9 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 8. [Figure 10] 10A to 10C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. [Figure 11] 1A to 1C are cross-sectional views showing a manufacturing process of a semiconductor device in a study example. [Figure 12] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 13] FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 14] FIG. 10 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. [Figure 15] FIG. 13 is a cross-sectional view showing a semiconductor device according to a modification of the fourth embodiment. [Figure 16] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a fourth embodiment. [Figure 17] 17A to 17C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. 16. [Figure 18] 18 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 17. [Figure 19] 19 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 18. [Figure 20] 19A to 19C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. [Figure 21]21 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 20. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0013] (Embodiment 1) <Structure of semiconductor device> 1 and 2, a semiconductor device 100 according to a first embodiment will be described below. In the first embodiment, the semiconductor device 100 is described as a single semiconductor chip, but the semiconductor device 100 may be a stacked body with other semiconductor chips, or may be a semiconductor module in which a semiconductor chip is mounted on a mounting substrate.

[0014] Fig. 1 is a plan view showing a semiconductor device 100. The semiconductor device 100 is an MCU (Memory Controller Unit) having a nonvolatile memory element such as a flash memory, and has a rectangular shape in a plan view. In Fig. 1, regions in which semiconductor elements constituting circuits used for respective applications are formed are shown as circuit regions C1 to C4.

[0015] The circuit region C1 is, for example, a CPU (Central Processing Unit), and is an area where low-voltage metal insulator semiconductor field effect transistors (MISFETs) that operate at high speed at a relatively low voltage are formed as semiconductor elements. The circuit region C2 is, for example, a nonvolatile memory cell, and is formed as semiconductor elements with nonvolatile memory elements such as MONOS (Metal Oxide Nitride Oxide Silicon) memory. The circuit region C3 is, for example, a static random access memory (SRAM), and is formed as semiconductor elements with low-voltage MISFETs having substantially the same structure as the circuit region C1. The circuit region C4 is, for example, an analog circuit, and is formed as semiconductor elements with high-voltage MISFETs having a higher voltage resistance than the low-voltage MISFETs, capacitive elements, resistive elements, bipolar transistors, etc.

[0016] A multi-layer wiring layer is formed on the semiconductor substrate, and a pad electrode PAD is formed on the uppermost wiring layer of the multi-layer wiring layer. The pad electrode PAD is electrically connected to the semiconductor elements in each of the circuit regions C1 to C4 via the multi-layer wiring layer. A conductive layer OPM is formed on the pad electrode PAD and is electrically connected to the multi-layer wiring layer via the pad electrode PAD. A plurality of such pad electrodes PAD and conductive layers OPM are formed in the semiconductor device 100.

[0017] 2 is an enlarged cross-sectional view of the pad electrode PAD and the conductive layer OPM. As shown in FIG. 2, a fourth wiring M4 having a damascene structure is formed in an interlayer insulating film IL4 in the upper part of the semiconductor device 100. That is, the fourth wiring M4 is formed by burying a conductive film mainly made of copper in a groove formed in the interlayer insulating film IL4.

[0018] Since the main feature of the first embodiment is the structure of the conductive layer OPM, the fourth wiring M4 and the structure above it are shown in Fig. 2, but the structure below the fourth wiring M4 is not shown. The structure below and a manufacturing method therefor will be described later in <Method for manufacturing a semiconductor device> with reference to Fig. 3.

[0019] An interlayer insulating film IL5 is formed on the fourth wiring M4, and a via V4 is formed in the interlayer insulating film IL5. The interlayer insulating film IL5 is, for example, a silicon oxide film or a fluorine-added silicon oxide film, and the via V4 is, for example, a conductive film mainly made of tungsten.

[0020] A fifth wiring M5 is formed on the interlayer insulating film IL5, and the fifth wiring M5 is electrically connected to the fourth wiring M4 through a via V4. A plurality of fifth wirings M5 are formed in the uppermost layer of the multilayer wiring layer, and some of the plurality of wirings are used as the pad electrode PAD. The pad electrode PAD is composed of a barrier metal film BM1, a conductive film AL formed on the barrier metal film BM1, and a barrier metal film BM2 formed on the conductive film AL. The barrier metal films BM1 and BM2 are each a titanium nitride film or a laminated film of a titanium nitride film and a titanium film. The conductive film AL is a conductive film mainly composed of aluminum.

[0021] An insulating film IF1 is formed on the interlayer insulating film IL5 so as to cover the pad electrode PAD. The insulating film IF1 is, for example, a silicon oxide film, a silicon nitride film, or a polyimide film, or a laminated film obtained by appropriately laminating these. The thickness of the insulating film IF1 is, for example, 200 nm or more and 1000 nm or less. An opening OP1 is formed in the insulating film IF1 so as to reach the pad electrode PAD. Furthermore, the barrier metal film BM2 is removed from within the opening OP1.

[0022] The conductive layer OPM is formed on the insulating film IF1 so as to fill the opening OP1 and is electrically connected to the pad electrode PAD. The conductive layer OPM has an OPM electrode structure. The conductive layer OPM includes a barrier metal film BM3, a seed layer SD formed on the barrier metal film BM3, a conductive film PF1 formed on the seed layer SD, a conductive film PF2 formed on the conductive film PF1, and a conductive film PF3 formed on the conductive film PF2.

[0023] The conductive film PF1 and seed layer SD are made of, for example, a material whose main component is copper. Although the seed layer SD is ultimately incorporated into the conductive film PF1 and integrated, they are shown separately here for ease of understanding the invention. The barrier metal film BM3 is, for example, a titanium film, a tantalum film, or a chromium film, and functions to prevent the diffusion of the conductive film PF1 (copper). The barrier metal film BM3 may be a single-layer film made of the above materials, or it may be a laminated film made by stacking these single-layer films with a nitride film such as a titanium nitride film or a tantalum nitride film.

[0024] The conductive film PF2 is made of a different material from the conductive film PF1, for example, a material primarily composed of nickel. The conductive film PF3 is made of a different material from the conductive films PF1 and PF2, for example, a material primarily composed of gold. The conductive film PF3 is provided to improve adhesion with the wire bonding WB and to prevent the surface of the conductive layer OPM from being oxidized. The wire bonding WB is connected to the conductive film PF3 and is made of a material primarily composed of, for example, copper or gold.

[0025] It is also possible to use solder bump electrodes instead of wire bonding WB as external connection members formed on the pad electrodes of a semiconductor chip. When using solder bump electrodes, when mounting the semiconductor chip on a mounting substrate, the positions of the pad electrodes on the semiconductor chip and the pad electrodes on the mounting substrate must be precisely aligned. This requires a high-precision substrate, which increases the substrate cost. Furthermore, forming solder bump electrodes on a semiconductor chip requires a rewiring process and a solder bump electrode formation process after forming the pad electrodes, which makes forming solder bump electrodes expensive. Therefore, using wire bonding WB as external connection members has the advantage of being less expensive than solder bump electrodes.

[0026] The thickness of the conductive film PF1 is, for example, 1 μm or more and 2 μm or less, the thickness of the conductive film PF2 is, for example, 1 μm or more and 2 μm or less, and the thickness of the conductive film PF3 is, for example, 100 nm or more and 200 nm or less.

[0027] An oxide layer OX1, which is formed by oxidizing a material contained in the conductive film PF1, is formed on the side surface of the conductive film PF1. The oxide layer OX1 covers the entire side surface of the conductive film PF1. Therefore, the conductive film PF1 is surrounded by the oxide layer OX1, the conductive film PF2, and the barrier metal film BM3 and is not exposed.

[0028] When the conductive film PF1 is made of a material mainly composed of copper, the oxide layer OX1 is a copper oxide such as CuO or CuO2 and has insulating properties. The width of the oxide layer OX1 is 200 nm or more, for example, 200 nm or more and 400 nm or less. In this specification, "width" means the length (thickness) in the direction perpendicular to the thickness direction.

[0029] As shown in FIG. 1, the plurality of conductive layers OPM are adjacent to each other, but in the first embodiment, the space between each conductive layer OPM is 10 μm or less, about 5 μm.

[0030] The main feature of the first embodiment is that an oxide layer OX1 is formed on the side surface of the conductive film PF1, and the effect of such a feature will be described in detail later using an example (FIG. 11).

[0031] <Method of manufacturing a semiconductor device> A manufacturing method of the semiconductor device 100 in the first embodiment will be described below with reference to Figures 3 to 10. Figure 3 is a cross-sectional view showing the fourth wiring M4 and the structure below it. Figures 4 to 10 are cross-sectional views showing the fourth wiring M4 and the structure above it. Here, a case where the multilayer wiring layer is composed of five wiring layers will be described, but the number of wiring layers may be less than five or more than five.

[0032] First, as shown in Figure 3, a semiconductor substrate SUB made of p-type single crystal silicon or the like is prepared. At this stage, the semiconductor substrate SUB is in a wafer state. Next, a plurality of element isolation regions STI that define active regions are formed in the semiconductor substrate SUB. The element isolation regions STI can be formed by forming trenches in the semiconductor substrate SUB and filling these trenches with an insulating film made mainly of, for example, silicon oxide.

[0033] Next, impurities are introduced into the semiconductor substrate SUB to form a well region WL, followed by forming MISFET1Q and MISFET2Q, each of which includes a gate electrode formed on the well region WL via a gate insulating film and a source / drain region formed in the well region WL.

[0034] Next, an interlayer insulating film IL0 is formed on the semiconductor substrate SUB by, for example, CVD so as to cover MISFET1Q and MISFET2Q. The interlayer insulating film IL0 is, for example, a silicon oxide film. Next, contact holes are formed in the interlayer insulating film IL0 by photolithography and dry etching. Next, plugs PG are formed by filling the contact holes with a metal film made of, for example, tungsten. The plugs PG are connected to MISFET1Q or MISFET2Q, etc.

[0035] Next, an interlayer insulating film IL1 is formed on the interlayer insulating film IL0 by, for example, a CVD method. The interlayer insulating film IL1 is made of a material having a lower dielectric constant than silicon oxide, for example, a silicon oxide film containing carbon such as SiOC. The first wiring M1 is formed using a so-called damascene technique. That is, a trench is formed in the interlayer insulating film IL1, a conductive film mainly made of copper is embedded in the trench, and the conductive film formed outside the trench is removed by a CMP (Chemical Mechanical Polishing) method, thereby forming the first wiring M1. Note that a barrier metal film that prevents copper diffusion may be formed between the copper and the interlayer insulating film IL1. Note that the first wiring M1 is connected to the upper surface of the plug PG.

[0036] Next, an interlayer insulating film IL2 is formed on the interlayer insulating film IL1 by, for example, CVD so as to cover the first wiring M1. The interlayer insulating film IL2 is made of the same material as the interlayer insulating film IL1. Next, a via hole and a wiring groove are formed in the interlayer insulating film IL2, a copper-based conductive film is embedded in the via hole and the wiring groove, and the conductive film formed outside the via hole and the wiring groove is removed by CMP, thereby forming the via V1 and the second wiring M2. That is, the via V1 and the second wiring M2 are formed by the Dual Damascene method, which is a type of damascene method, and are integrated. Note that a barrier metal film to prevent copper diffusion may be formed between the copper and the interlayer insulating film IL2. The via V1 is connected to the upper surface of the first wiring M1.

[0037] Next, an interlayer insulating film IL3 is formed on the interlayer insulating film IL2 by, for example, CVD, so as to cover the second wiring M2. Next, using the same technique as when the via V1 and the second wiring M2 were formed, a via V2 and a third wiring M3 are formed in the interlayer insulating film IL3. Next, an interlayer insulating film IL4 is formed on the interlayer insulating film IL3 by, for example, CVD, so as to cover the third wiring M3. Next, using the same technique as when the via V1 and the second wiring M2 were formed, a via V3 and a fourth wiring M4 are formed in the interlayer insulating film IL4. The materials of the interlayer insulating films IL3 and IL4 are the same as those of the interlayer insulating film IL2.

[0038] Next, as shown in FIG. 4, an interlayer insulating film IL5 is formed on the interlayer insulating film IL4 by, for example, CVD so as to cover the fourth wiring M4. The interlayer insulating film IL5 is, for example, a silicon oxide film or a fluorine-added silicon oxide film. Next, a via hole is formed in the interlayer insulating film IL5 by photolithography and dry etching. Next, a via V4 is formed by filling the via hole with a conductive film mainly made of, for example, tungsten. The via V4 is connected to the upper surface of the fourth wiring M4.

[0039] Next, a fifth wiring M5 is formed on the interlayer insulating film IL5. First, a barrier metal film BM1, a conductive film AL, and a barrier metal film BM2 are sequentially stacked on the interlayer insulating film IL5 by CVD or sputtering. Next, these films are patterned by photolithography and dry etching to form the fifth wiring M5. The fifth wiring M5 is a plurality of wirings formed in the uppermost layer of the multilayer wiring layer, some of which become pad electrodes PAD. The fifth wiring M5 (pad electrode PAD) is connected to the upper surface of the via V4.

[0040] Next, an insulating film IF1 is formed on the interlayer insulating film IL5 by a CVD method so as to cover the fifth wiring M5 (pad electrode PAD). Next, an opening OP1 is formed in the insulating film IF1 by photolithography and dry etching so as to reach the pad electrode PAD. Thereafter, the barrier metal film BM2 located in the opening OP1 is removed. As a result, the conductive film AL is exposed in the opening OP1.

[0041] Through the above manufacturing steps, the semiconductor substrate SUB, the MISFETs 1Q and 2Q, the multilayer wiring layer including the pad electrodes PAD, and the insulating film IF1 formed so as to cover the pad electrodes PAD are prepared.

[0042] Next, as shown in FIG. 5, a barrier metal film BM3 is formed on the insulating film IF1 and in the opening OP1 by, for example, CVD or sputtering. The thickness of the barrier metal film BM3 is, for example, 50 nm or more and 200 nm or less. Next, a seed layer SD is formed on the barrier metal film BM3 by, for example, sputtering. The seed layer SD is made of the same material as the conductive film PF1 described below, for example, a material mainly composed of copper. The thickness of the seed layer SD is, for example, 100 nm or more and 300 nm or less.

[0043] Next, as shown in FIG. 6, a resist pattern RP1 having a pattern in which an area where a conductive layer OPM is to be formed is opened is formed on the seed layer SD.

[0044] Next, as shown in FIG. 7, a conductive film PF1 is formed by plating on the pad electrode PAD in the opening OP1. The conductive film PF1 is formed on the seed layer SD exposed from the resist pattern RP1. Note that the seed layer SD located directly below the conductive film PF1 is incorporated into and integrated with the conductive film PF1, but for ease of understanding the invention, these are shown separately here. Next, a conductive film PF2 is formed on the conductive film PF1 by plating. Next, a conductive film PF3 is formed on the conductive film PF2 by plating.

[0045] Next, as shown in FIG. 8, the resist pattern RP1 is removed by ashing.

[0046] 9, in the regions exposed from the conductive films PF1 to PF3 (regions where the conductive films PF1 to PF3 are not formed), the seed layer SD and the barrier metal film BM3 are sequentially removed by wet etching, thereby forming the conductive layer OPM.

[0047] In addition, this wet etching process is performed so as to overetch in order to reliably remove the seed layer SD and the barrier metal film BM3. Since the conductive film PF1 is made of the same material as the seed layer SD, the side surfaces of the conductive film PF1 are also etched. Therefore, the side surfaces of the conductive film PF1 are recessed from the side surfaces of the conductive films PF2 and PF3.

[0048] Next, as shown in FIG. 10, the conductive film PF1 is subjected to an oxidation process to form an oxide layer OX1 on the side surface of the conductive film PF1, in which the material contained in the conductive film PF1 is oxidized. The oxide layer OX1 is made of copper oxide, such as CuO or CuO, and has insulating properties. The width of the oxide layer OX1 is 200 nm or more, for example, 200 nm to 400 nm.

[0049] The oxidation treatment is a heat treatment carried out in an oxygen atmosphere under conditions of 100° C. or higher and 450° C. or lower. Alternatively, the oxidation treatment may be an oxygen plasma treatment carried out under conditions of 100° C. or higher and 250° C. or lower.

[0050] Furthermore, the oxidation process causes the volume of the oxide layer OX1 to expand, so that the side surfaces of the conductive film PF1 including the oxide layer OX1 approach the side surfaces of the conductive films PF2 and PF3. Here, the side surfaces of the conductive films PF1 to PF3 are at approximately the same position and are flush with each other.

[0051] However, by further increasing the wet etching time, the side surfaces of the conductive film PF1 can be further recessed, ultimately resulting in a structure in which the side surfaces of the conductive film PF1 including the oxide layer OX1 are recessed relative to the side surfaces of the conductive films PF2 and PF3. That is, the side surfaces of the oxide layer OX1 are located more inward than the side surfaces of the conductive films PF2 and PF3. In other words, the side surfaces of the conductive films PF2 and PF3 protrude relative to the side surfaces of the oxide layer OX1. The sum of the widths of the oxide layer OX1 and the conductive film PF1 (the width of the conductive film PF1 including the oxide layer OX1) is smaller than the widths of the conductive films PF2 and PF3. Here, the side surfaces of the oxide layer OX1 refer to the side surfaces of the oxide layer OX1 opposite to the conductive film PF1. In this case, the distance between adjacent conductive films PF1 is increased, which has the effect of reducing the likelihood of leakage current.

[0052] 2 is manufactured through the following manufacturing steps. First, the semiconductor substrate SUB in a wafer state is diced into a plurality of semiconductor chips. Next, an external connection member such as a wire bonding WB is connected to the conductive layer OPM.

[0053] <Semiconductor device as an example of the study> A semiconductor device as an example that was studied by the inventors of the present invention and its problems will be described below with reference to FIG.

[0054] Two adjacent conductive layers OPM (two pad electrodes PAD) are shown in Fig. 11. As shown in Fig. 11, in the semiconductor device of the study example, the conductive film PF1 is not subjected to an oxidation treatment, and an oxide layer OX1 is not formed on the side surface of the conductive film PF1.

[0055] Here, in the wet etching process for removing the seed layer SD and the barrier metal film BM3, they may not be completely removed and may remain on the insulating film IF1 as residues 10. If such residues 10 exist on the insulating film IF1, the residues 10 function as leak paths and reduce the insulation between the conductive layers OPM, which causes a problem that a leak current is likely to occur.

[0056] Furthermore, after the wet etching process, the etching solution used is discharged, and a phenomenon may occur in which copper constituting the seed layer SD is ionized and dissolved into the etching solution. Then, while the etching solution is being discharged, the ionized copper may re-deposit on the insulating film IF1. Since this re-deposited copper also functions in the same way as the residue 10, there is a problem in that leakage current is likely to occur between the conductive layers OPM.

[0057] Furthermore, some of the multiple conductive layers OPM have a large current flowing through them. Therefore, electromigration may cause deformation of the conductive film PF1. The deformed conductive film PF1 may then approach the adjacent conductive layer OPM and function as a leak path.

[0058] If the spaces between the conductive layers OPM are large, the above-mentioned problems are unlikely to occur. However, with the recent trend toward miniaturization, there is a demand to reduce the spaces between the pad electrodes PAD, and therefore the spaces between the conductive layers OPM. For example, while the spaces between the conductive layers OPM were previously 20 μm or more, in recent years, the spaces between the conductive layers OPM are 10 μm or less, and in some cases, even 5 μm or less. Therefore, the above-mentioned problems are likely to occur.

[0059] <Main features of the first embodiment> In the first embodiment, an oxidation treatment is performed on the conductive film PF1, and an oxide layer OX1 is formed on the side surface of the conductive film PF1. The conductive film PF1 is surrounded by the oxide layer OX1, the conductive film PF2, and the barrier metal film BM3 and is not exposed. The oxide layer OX1 is a copper oxide such as CuO or CuO2, and is a film with higher resistance than the conductive film PF1 (copper). Since the side surface of the conductive film PF1 is covered with the oxide layer OX1, deformation of the conductive film PF1 due to electromigration is easily suppressed.

[0060] Furthermore, even if the residue 10 remains on the insulating film IF1 or if copper redeposition occurs on the insulating film IF1, the oxidation process oxidizes not only the side surface of the conductive film PF1 but also the residue 10 and the redeposition. That is, the residue 10 and the redeposition also become high-resistance films. Therefore, deterioration of the insulation between the conductive layers OPM can be suppressed, and the occurrence of leakage current can be suppressed, thereby improving the reliability of the semiconductor device 100.

[0061] If the semiconductor device of the study example is left in the atmosphere, the conductive film PF1 may react with oxygen in the atmosphere and be oxidized, resulting in the formation of a native oxide film on the side surface of the conductive film PF1. The native oxide film may be, for example, 10 nm or less thick. However, the inventors' investigations have revealed that such a thin native oxide film makes it difficult to suppress deformation of the conductive film PF1 due to electromigration and also difficult to suppress the occurrence of leakage current. Furthermore, the residue 10 and redeposits on the insulating film IF1 cannot be sufficiently oxidized.

[0062] In the first embodiment, the width of the oxide layer OX1 is increased to 200 nm or more by actively performing oxidation treatment on the side surfaces of the conductive film PF1, which is a width that can solve the above-mentioned problems.

[0063] (Embodiment 2) The semiconductor device according to the second embodiment will be described below with reference to Fig. 12. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0064] In the second embodiment, the oxide layer OX1 is in contact with the insulating film IF1. That is, the oxide layer OX1 covers not only the side surfaces of the conductive film PF1 but also the side surfaces of the barrier metal film BM3. The formation of such an oxide layer OX1 can be achieved by adjusting the time of the oxidation treatment to increase the volume expansion of the oxide layer OX1.

[0065] If the change in the conductive film PF1 due to electromigration is very large, the oxide layer OX1 may peel off due to stress from the conductive film PF1. Here, since the oxide layer OX1 is in contact with the insulating film IF1, the adhesion of the oxide layer OX1 can be increased, which makes it easier to suppress peeling of the oxide layer OX1. Therefore, the reliability of the semiconductor device 100 can be further improved.

[0066] (Embodiment 3) The semiconductor device according to the third embodiment will be described below with reference to Fig. 13. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0067] In the first embodiment, the thickness of the conductive film PF3 is thinner than the thickness of each of the conductive films PF1 and PF2. In the third embodiment, the thickness of the conductive film PF3 is thicker than the thickness of each of the conductive films PF1 and PF2, and is, for example, 2 μm or more and 4 μm or less.

[0068] When connecting the wire bonding WB to the conductive layer OPM, a large pressure is applied to the conductive layer OPM. This pressure may deform the conductive film PF1, exposing the side surfaces of the conductive film PF1 that are covered with the oxide layer OX1. Furthermore, the impact caused by the deformation of the conductive film PF1 may cause cracks to form in the insulating film IF1.

[0069] Therefore, in order to absorb the pressure during the formation of the wire bonding WB, the thickness of the conductive film PF3, which is made of the softest material among the conductive layers OPM, is increased. In other words, the thickness of the conductive film PF3, which has the smallest Vickers hardness among the conductive layers OPM, is increased. This solves the above-mentioned problem.

[0070] When the conductive film PF3 is made of a material mainly containing gold, the Vickers hardness of the conductive film PF3 is 70 HV or less. When the conductive film PF2 is made of a material mainly containing nickel, the Vickers hardness of the conductive film PF2 is 400 HV or more and 500 HV or less. When the conductive film PF1 is made of a material mainly containing copper, the Vickers hardness of the conductive film PF1 is 80 HV or more and 200 HV or less.

[0071] Moreover, the technology disclosed in the second embodiment can also be applied to the third embodiment.

[0072] (Fourth embodiment) The semiconductor device according to the fourth embodiment will be described below with reference to Fig. 14. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0073] In the first embodiment, the conductive layer OPM has an OPM electrode structure, but in the fourth embodiment, the conductive layer OPM has a Cu pillar structure. Also, the semiconductor device 100 in the fourth embodiment is a semiconductor module including a mounting substrate 20.

[0074] 14, the conductive layer OPM in the fourth embodiment includes a barrier metal film BM3, a seed layer SD, a conductive film PF1, and a conductive film PF2. The mounting substrate 20 has a plurality of wirings including a wiring 21. The conductive film PF2 and the wiring 21 are joined by a solder layer SL.

[0075] In the fourth embodiment, an oxide layer OX1 is formed on the side surface of the conductive film PF1, as in the first embodiment. Therefore, in the fourth embodiment, deformation of the conductive film PF1 due to electromigration can be suppressed and the occurrence of leakage current between the conductive layers OPM can be suppressed, thereby improving the reliability of the semiconductor device 100.

[0076] Moreover, the technology disclosed in the second embodiment can also be applied to the fourth embodiment.

[0077] (Variation) 15 shows a semiconductor device 100 according to a modification of the fourth embodiment. As shown in FIG. 15, the conductive layer OPM according to the modification is formed on the pad electrode PAD in the opening OP1, and is not formed on the insulating film IF1. The conductive layer OPM may have such a Cu pillar structure.

[0078] <Method of Manufacturing Semiconductor Device in Fourth Embodiment> 16 to 21, a method for manufacturing the semiconductor device 100 according to the fourth embodiment will be described below. The Cu pillar structure of FIG.

[0079] The manufacturing process in Embodiment 4 is the same as that in Embodiment 1 up to the formation of the conductive film PF2. Next, as shown in Fig. 16, a solder layer SLa is formed on the conductive film PF2. Next, as shown in Fig. 17, a reflow treatment is performed on the solder layer SLa.

[0080] Before and after the manufacturing process of Fig. 17, a mounting substrate 20 having a solder layer SLb formed on a wiring 21 is prepared as shown in Fig. 18. The solder layer SLb is also subjected to a reflow treatment. The reflow treatment is performed in an inert gas atmosphere such as nitrogen so as to prevent the surfaces of the solder layers SLa and SLb from being oxidized.

[0081] Next, the solder layer SLa and the solder layer SLb are joined together as shown in Fig. 19. In Fig. 19, the joined solder layer SLa and solder layer SLb are shown as a solder layer SL.

[0082] 20, an oxidation process is performed on the conductive film PF1 to form an oxide layer OX1 on the side surface of the conductive film PF1, in which a material contained in the conductive film PF1 is oxidized. As in the first embodiment, the oxide layer OX1 is a copper oxide such as CuO or CuO, and the width of the oxide layer OX1 is 200 nm or more, for example, 200 nm or more and 400 nm or more.

[0083] The oxidation treatment in the fourth embodiment is performed at a low temperature so as not to melt the solder layer SL. That is, the oxidation treatment in the fourth embodiment is a heat treatment performed in an oxygen atmosphere under conditions of 100° C. or higher and 200° C. or lower. The oxidation treatment may also be an oxygen plasma treatment performed under conditions of 100° C. or higher and 200° C. or lower.

[0084] 21, sealing resin 30 is injected between the mounting substrate 20 and the insulating film IF1, and the conductive layer OPM, the solder layer SL, and the wiring 21 are covered with the sealing resin 30. In this manner, the semiconductor device 100 according to the fourth embodiment is manufactured.

[0085] The present invention has been specifically described above based on the above embodiment, but the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0086] 100 Semiconductor device 10 Residue 20 Mounting board 21 Wiring 30 Sealing resin 1Q, 2Q MISFET AL conductive film BM1, BM2, BM3 barrier metal film C1~C4 circuit area IF1 insulating film IL0~IL5 Interlayer insulating film M1~M5 1st wiring~5th wiring OP1 opening OPM conductive layer OX1 oxide layer PF1~PF3 Conductive film PAD Pad electrode PG plug RP1 resist pattern SD seed layer SL, SLa, SLb solder layer STI element isolation area SUB Semiconductor substrate V1~V4 vias WB Wire Bonding WL Well area

Claims

1. a multilayer wiring layer formed on a semiconductor substrate; a pad electrode formed on the uppermost wiring layer of the multilayer wiring layer; an insulating film formed to cover the pad electrode; an opening formed in the insulating film so as to reach the pad electrode; a barrier metal film formed in the opening and on the insulating film; a first conductive film formed on the barrier metal film and the insulating film so as to fill the opening and be located on the pad electrode, and electrically connected to the pad electrode; Equipped with an oxide layer formed on a side surface of the first conductive film by oxidizing a material contained in the first conductive film; the oxide layer covers a side surface of the barrier metal film and is in contact with the insulating film; The semiconductor device, wherein the oxide layer has a width of 200 nm or more.

2. 2. The semiconductor device according to claim 1, the material contained in the first conductive film is copper; The semiconductor device, wherein the oxide layer is copper oxide.

3. In the semiconductor device according to claim 2, The semiconductor device, wherein the barrier metal film is made of a titanium film, a tantalum film, or a chromium film.

4. 2. The semiconductor device according to claim 1, a second conductive film formed on the first conductive film; a third conductive film formed on the second conductive film; a wire bonding connected to the third conductive film; The semiconductor device further comprises:

5. 5. The semiconductor device according to claim 4, the Vickers hardness of the third conductive film is lower than the Vickers hardness of each of the first conductive film and the second conductive film; A semiconductor device, wherein the third conductive film is thicker than each of the first conductive film and the second conductive film.

6. 6. The semiconductor device according to claim 5, the material contained in the first conductive film is copper; the material contained in the second conductive film is nickel; the material contained in the third conductive film is gold; The semiconductor device, wherein the oxide layer is copper oxide.

7. 2. The semiconductor device according to claim 1, a second conductive film formed on the first conductive film; a mounting substrate having a first wiring; Further provided with The second conductive film and the first wiring are joined by a solder layer.

8. 5. The semiconductor device according to claim 4, a side surface of the oxide layer is recessed from each of side surfaces of the second conductive film and the third conductive film.

9. (a) forming a multilayer wiring layer on a semiconductor substrate; (b) after the step (a), forming an insulating film so as to cover the pad electrode formed on the uppermost wiring layer of the multilayer wiring layer; (c) after the step (b), forming an opening in the insulating film so as to reach the pad electrode; (d) after the step (c), forming a barrier metal film on the insulating film and in the opening; (e) after the step (d), forming a first conductive film on the pad electrode in the opening and on the insulating film by a plating method; (f) after the step (e), performing an oxidation treatment on the first conductive film to form an oxide layer on a side surface of the first conductive film by oxidizing a material contained in the first conductive film; Equipped with the oxide layer covers a side surface of the barrier metal film and is in contact with the insulating film; The method for manufacturing a semiconductor device, wherein the oxide layer has a width of 200 nm or more.

10. 10. The method for manufacturing a semiconductor device according to claim 9, the material contained in the first conductive film is copper; The method for manufacturing a semiconductor device, wherein the oxide layer is copper oxide.

11. 11. The method for manufacturing a semiconductor device according to claim 10, A method for manufacturing a semiconductor device, wherein the oxidation treatment is a heat treatment carried out in an oxygen atmosphere under conditions of 100°C or higher and 450°C or lower, or an oxygen plasma treatment carried out under conditions of 100°C or higher and 250°C or lower.

12. The method for manufacturing a semiconductor device according to claim 10, The method for manufacturing a semiconductor device, wherein the barrier metal film is made of a titanium film, a tantalum film, or a chromium film.

13. 10. The method for manufacturing a semiconductor device according to claim 9, (g) forming a second conductive film on the first conductive film by a plating method after the step (e) and before the step (f); (h) forming a third conductive film on the second conductive film by a plating method after the step (g) and before the step (f); The method for manufacturing a semiconductor device further comprises:

14. 14. The method for manufacturing a semiconductor device according to claim 13, the Vickers hardness of the third conductive film is lower than the Vickers hardness of each of the first conductive film and the second conductive film; A method for manufacturing a semiconductor device, wherein the third conductive film has a thickness greater than each of the first conductive film and the second conductive film.

15. 15. The method for manufacturing a semiconductor device according to claim 14, the material contained in the first conductive film is copper; the material contained in the second conductive film is nickel; the material contained in the third conductive film is gold; The method for manufacturing a semiconductor device, wherein the oxide layer is copper oxide.

16. 15. The method for manufacturing a semiconductor device according to claim 14, (i) after the step (f), connecting wire bonding to the third conductive film; The method for manufacturing a semiconductor device further comprises:

17. 10. The method for manufacturing a semiconductor device according to claim 9, (j) forming a second conductive film on the first conductive film by a plating method after the step (e) and before the step (f); (k) forming a first solder layer on the second conductive film after the step (j) and before the step (f); (l) preparing a mounting substrate having a first wiring and a second solder layer formed on the first wiring; (m) a step of joining the first solder layer and the second solder layer after the step (k) and the step (l) and before the step (f); The method for manufacturing a semiconductor device further comprises:

18. 18. The method for manufacturing a semiconductor device according to claim 17, the material contained in the first conductive film is copper; the oxide layer is copper oxide; A method for manufacturing a semiconductor device, wherein the oxidation treatment is a heat treatment carried out in an oxygen atmosphere under conditions of 100°C or higher and 200°C or lower, or an oxygen plasma treatment carried out under conditions of 100°C or higher and 200°C or lower.

19. 14. The method for manufacturing a semiconductor device according to claim 13, a side surface of the oxide layer is recessed from each of side surfaces of the second conductive film and the third conductive film.

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