Semiconductor Devices

Abstract

To provide a semiconductor device capable of reducing occupancy areas in a plan view of a first inductor and a second inductor.SOLUTION: A semiconductor device includes: a first semiconductor chip; a second semiconductor chip; and a re-wiring layer. The first semiconductor chip and the second semiconductor chip are arranged side by side with a gap in a second direction perpendicular to a first direction being a thickness direction of the semiconductor device. The re-wiring layer is arranged across on the first semiconductor chip and the second semiconductor chip. The re-wiring layer includes a first inductor and a second inductor. The first inductor and the second inductor face each other with a gap in a third direction perpendicular to the first direction and the second direction. The first inductor and the second inductor are electrically connected respectively with the first semiconductor chip and the second semiconductor chip. The first inductor and the second inductor are wound across the first semiconductor chip and the second semiconductor chip in a plane perpendicular in a third direction.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] The semiconductor device described in JP 2020-123599 A (Patent Document 1) has a first semiconductor chip, a second semiconductor chip, and a redistribution layer. The thickness direction of the semiconductor device is defined as a first direction. A direction perpendicular to the first direction is defined as a second direction. The first semiconductor chip and the second semiconductor chip are arranged at an interval in the second direction.

[0003] The redistribution layer is disposed across the first semiconductor chip and the second semiconductor chip. The redistribution layer has a first inductor and a second inductor. The first inductor and the second inductor face each other with a gap in between in a first direction. The redistribution layer has a plurality of wires stacked in the first direction. The first inductor is configured by winding one of the plurality of wires in the redistribution layer in a plane perpendicular to the first direction. The second inductor is configured by winding another of the plurality of wires in the redistribution layer in a plane perpendicular to the first direction. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2020-123599 Summary of the Invention [Problem to be solved by the invention]

[0005] In the semiconductor device described in Patent Document 1, the first inductor and the second inductor are configured by winding the wiring of the redistribution layer in a plane perpendicular to the first direction, so the area occupied by the first inductor and the second inductor in a planar view is large. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure includes a first semiconductor chip, a second semiconductor chip, and a redistribution layer. The first semiconductor chip and the second semiconductor chip are arranged side by side with a gap in a second direction perpendicular to a first direction, which is the thickness direction of the semiconductor device. The redistribution layer is disposed over the first semiconductor chip and the second semiconductor chip. The redistribution layer includes a first inductor and a second inductor. The first inductor and the second inductor face each other with a gap in a third direction perpendicular to the first and second directions. The first inductor is electrically connected to the first semiconductor chip. The second inductor is electrically connected to the second semiconductor chip. The first inductor and the second inductor are wound over the first semiconductor chip and the second semiconductor chip in a plane perpendicular to the third direction. [Effects of the Invention]

[0007] According to the semiconductor device of the present disclosure, the area occupied by the first inductor and the second inductor in plan view can be reduced. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a schematic configuration diagram of a semiconductor device DEV1. [Figure 2] FIG. 2 is a plan view of the semiconductor device DEV1. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. [Figure 5]FIG. 3 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 2 is an enlarged cross-sectional view of the semiconductor chip CHP1. [Figure 7] FIG. 2 is an enlarged cross-sectional view of the semiconductor chip CHP2. [Figure 8] 10A to 10C are process diagrams showing a manufacturing method of the semiconductor device DEV1. [Figure 9] FIG. 10 is a cross-sectional view illustrating a first step S21. [Figure 10] FIG. 10 is a cross-sectional view illustrating a second step S22. [Figure 11] FIG. 10 is a cross-sectional view illustrating a first step S31. [Figure 12] FIG. 10 is a cross-sectional view illustrating a second step S32. [Figure 13] FIG. 10 is a cross-sectional view illustrating a third step S33. [Figure 14] FIG. 10 is a cross-sectional view illustrating a fourth step S34. [Figure 15] FIG. 10 is a cross-sectional view illustrating a fifth step S35. [Figure 16] FIG. 2 is a plan view of the semiconductor device DEV2. [Figure 17] FIG. 10 is a plan view of a semiconductor device DEV2 according to a modified example. [Figure 18] FIG. 2 is a plan view of the semiconductor device DEV3. [Figure 19] 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18. [Figure 20] FIG. 19 is a cross-sectional view taken along the line XX-XX in FIG. 18. [Figure 21] FIG. 10 is a plan view of the semiconductor device DEV4. [Figure 22] FIG. 2 is a plan view of the semiconductor device DEV5. [Figure 23] FIG. 2 is a schematic perspective view of an inductor ID1. [Figure 24] FIG. 10 is a schematic perspective view of an inductor ID2. DETAILED DESCRIPTION OF THE INVENTION

[0009] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0010] (First embodiment) A semiconductor device according to a first embodiment will be described below. The semiconductor device according to the embodiment is designated as semiconductor device DEV1.

[0011] <Configuration of semiconductor device DEV1> Fig. 1 is a schematic configuration diagram of a semiconductor device DEV1. As shown in Fig. 1, the semiconductor device DEV1 has a semiconductor chip CHP1, a semiconductor chip CHP2, an inductor ID1, and an inductor ID2. The inductor ID1 is electrically connected to the semiconductor chip CHP1. The inductor ID2 is electrically connected to the semiconductor chip CHP2. The inductor ID1 and the inductor ID2 are magnetically coupled. The inductor ID1 and the inductor ID2 are electrically insulated from each other.

[0012] The semiconductor chip CHP1 can transmit and receive signals to and from the semiconductor chip CHP2 via the inductors ID1 and ID2 while being electrically insulated from the semiconductor chip CHP2. The semiconductor device DEV1 is a digital isolator. However, the semiconductor device DEV1 is not limited to a digital isolator.

[0013] FIG. 2 is a plan view of the semiconductor device DEV1. In FIG. 2, the redistribution layer FOL is omitted, and the inductors ID1 and ID2 are indicated by dotted lines. FIG. 3 is a cross-sectional view taken along III-III in FIG. 2. FIG. 4 is a cross-sectional view taken along IV-IV in FIG. 2. FIG. 5 is a cross-sectional view taken along VV in FIG. 2. FIG. 6 is an enlarged cross-sectional view of the semiconductor chip CHP1. FIG. 7 is an enlarged cross-sectional view of the semiconductor chip CHP2. As shown in FIGS. 2 to 7, the semiconductor device DEV1 has a semiconductor chip CHP1, a semiconductor chip CHP2, a sealing resin ER, and a redistribution layer FOL.

[0014] The semiconductor chip CHP1 includes a semiconductor substrate SUB1, an isolation film ISL1, a gate insulating film GI1, a gate electrode G1, a sidewall spacer SWS1, and a wiring layer WL1. The wiring layer WL1 includes an interlayer insulating film ILD1a, a contact plug CP1, an interlayer insulating film ILD1b, wirings WL1a, a plurality of interlayer insulating films ILD1c, a plurality of wirings WL1b, and a plurality of via plugs VP1.

[0015] The semiconductor substrate SUB1 has a first surface FS1 and a second surface SS1. The first surface FS1 and the second surface SS1 are end surfaces in the thickness direction of the semiconductor substrate SUB1. The second surface SS1 is the surface opposite to the first surface FS1. The semiconductor substrate SUB1 is formed of, for example, single crystal silicon (Si).

[0016] The semiconductor substrate SUB1 has a source region SR1, a drain region DR1, and a well region WR1. The source region SR1 and the drain region DR1 are formed on the first surface FS1 so as to be spaced apart from each other. The conductivity type of the source region SR1 and the drain region DR1 is the first conductivity type.

[0017] The source region SR1 has a first portion SR1a and a second portion SR1b. The first portion SR1a is closer to the drain region DR1 than the second portion SR1b. The drain region DR1 has a first portion DR1a and a second portion DR1b. The first portion DR1a is closer to the source region SR1 than the second portion DR1b. The dopant concentration in the first portion SR1a is lower than the dopant concentration in the second portion SR1b, and the dopant concentration in the first portion DR1a is lower than the dopant concentration in the second portion DR1b. In other words, the source region SR1 and the drain region DR1 have an LDD (Lightly Doped Diffusion) structure.

[0018] The well region WR1 is formed in the first surface FS1 so as to surround the source region SR1 and the drain region DR1. The well region WR1 has a second conductivity type, which is opposite to the first conductivity type.

[0019] The gate insulating film GI1 is disposed on the first surface FS1. More specifically, the gate insulating film GI1 is disposed on the first surface FS1 between the source region SR1 and the drain region DR1. The gate insulating film GI1 is formed of, for example, silicon oxide. The gate electrode G1 is disposed on the gate insulating film GI1. That is, the gate electrode G1 faces the well region WR1 between the source region SR1 and the drain region DR1 with the gate insulating film GI1 interposed therebetween. The gate electrode G1 is formed of, for example, polycrystalline silicon containing a dopant. The source region SR1, the drain region DR1, the well region WR1, the gate insulating film GI1, and the gate electrode G1 constitute a transistor.

[0020] The sidewall spacer SWS1 is arranged on the first surface FS1. More specifically, the sidewall spacer SWS1 is arranged on the first portion SR1a and the first portion DR1a so as to contact the side surface of the gate electrode G1. The sidewall spacer SWS1 is formed of, for example, silicon nitride. The element isolation film ISL1 is arranged on the first surface FS1 so as to surround the well region WR1 in plan view. More specifically, a trench TR1a extending toward the second surface SS1 is formed in the first surface FS1. The element isolation film ISL1 is embedded in the trench TR1a. The element isolation film ISL1 is formed of, for example, silicon oxide.

[0021] The wiring layer WL1 is disposed on the first surface FS1. The interlayer insulating film ILD1a is disposed on the first surface FS1 so as to cover the gate electrode G1, the sidewall spacer SWS1, and the element isolation film ISL1. The interlayer insulating film ILD1a is formed of, for example, silicon oxide. A contact hole CH1 is formed in the interlayer insulating film ILD1a. The source region SR1, the drain region DR1, or the gate electrode G1 is exposed from the contact hole CH1. A contact plug CP1 is buried in the contact hole CH1. The lower end of the contact plug CP1 is electrically connected to the source region SR1, the drain region DR1, or the gate electrode G1. The contact plug CP1 is formed of, for example, tungsten (W).

[0022] The interlayer insulating film ILD1b is disposed on the interlayer insulating film ILD1a. The interlayer insulating film ILD1b is made of, for example, silicon oxide. A trench TR1b is formed in the interlayer insulating film ILD1b. The trench TR1b penetrates the interlayer insulating film ILD1b in the thickness direction. The interconnect WL1a is buried in the trench TR1b. The interconnect WL1a is made of, for example, copper (Cu). The interconnect WL1a is electrically connected to the upper end of the contact plug CP1.

[0023] A plurality of interlayer insulating films ILD1c are stacked on the interlayer insulating film ILD1b. The interlayer insulating film ILD1c is made of silicon oxide. A trench TR1c is formed in the upper surface of the interlayer insulating film ILD1c. A via hole VH1 is formed in the interlayer insulating film ILD1c. The via hole VH1 penetrates the interlayer insulating film ILD1c in the thickness direction. The upper end of the via hole VH1 opens at the bottom surface of the trench TR1c, and the lower end of the via hole VH1 opens at the lower surface of the interlayer insulating film ILD1c.

[0024] The wiring WL1b is buried in the trench TR1c. The via plug VP1 is buried in the via hole VH1. The wiring WL1b and the via plug VP1 are integrally formed. The wiring WL1b and the via plug VP1 are made of copper. The via plug VP1 connects the wiring WL1a and the wiring WL1b in the lowermost layer, and connects two wirings WL1b adjacent to each other in the thickness direction of the wiring layer WL1.

[0025] The semiconductor chip CHP2 includes a semiconductor substrate SUB2, an isolation film ISL2, a gate insulating film GI2, a gate electrode G2, a sidewall spacer SWS2, and a wiring layer WL2. The wiring layer WL2 includes an interlayer insulating film ILD2a, a contact plug CP2, an interlayer insulating film ILD2b, a wiring WL2a, a plurality of interlayer insulating films ILD2c, a plurality of wirings WL2b, and a plurality of via plugs VP2.

[0026] The semiconductor substrate SUB2 has a first surface FS2 and a second surface SS2. The first surface FS2 and the second surface SS2 are end surfaces in the thickness direction of the semiconductor substrate SUB2. The second surface SS2 is the surface opposite to the first surface FS2. The semiconductor substrate SUB2 is formed of, for example, single crystal silicon.

[0027] The semiconductor substrate SUB2 has a source region SR2, a drain region DR2, and a well region WR2. The source region SR2 and the drain region DR2 are formed on the first surface FS2 so as to be spaced apart from each other. The conductivity type of the source region SR2 and the drain region DR2 is the first conductivity type.

[0028] The source region SR2 has a first portion SR2a and a second portion SR2b. The first portion SR2a is closer to the drain region DR2 than the second portion SR2b. The drain region DR2 has a first portion DR2a and a second portion DR2b. The first portion DR2a is closer to the source region SR2 than the second portion DR2b. The dopant concentration in the first portion SR2a is lower than the dopant concentration in the second portion SR2b, and the dopant concentration in the first portion DR2a is lower than the dopant concentration in the second portion DR2b. In other words, the source region SR2 and the drain region DR2 have an LDD structure.

[0029] The well region WR2 is formed in the first surface FS2 so as to surround the source region SR2 and the drain region DR2. The well region WR2 has a second conductivity type, which is opposite to the first conductivity type.

[0030] The gate insulating film GI2 is disposed on the first surface FS2. More specifically, the gate insulating film GI2 is disposed on the first surface FS2 between the source region SR2 and the drain region DR2. The gate insulating film GI2 is formed of, for example, silicon oxide. The gate electrode G2 is disposed on the gate insulating film GI2. That is, the gate electrode G2 faces the well region WR2 between the source region SR2 and the drain region DR2 with the gate insulating film GI2 interposed therebetween. The gate electrode G2 is formed of, for example, polycrystalline silicon containing a dopant. The source region SR2, the drain region DR2, the well region WR2, the gate insulating film GI2, and the gate electrode G2 constitute a transistor.

[0031] The sidewall spacer SWS2 is arranged on the first surface FS2. More specifically, the sidewall spacer SWS2 is arranged on the first portion SR2a and the first portion DR2a so as to contact the side surface of the gate electrode G2. The sidewall spacer SWS2 is formed of, for example, silicon nitride. The element isolation film ISL2 is arranged on the first surface FS2 so as to surround the well region WR2 in plan view. More specifically, a trench TR2a extending toward the second surface SS2 is formed in the first surface FS2. The element isolation film ISL2 is embedded in the trench TR2a. The element isolation film ISL2 is formed of, for example, silicon oxide.

[0032] The wiring layer WL2 is disposed on the first surface FS2. The interlayer insulating film ILD2a is disposed on the first surface FS2 so as to cover the gate electrode G2, the sidewall spacer SWS2, and the element isolation film ISL2. The interlayer insulating film ILD2a is formed of, for example, silicon oxide. A contact hole CH2 is formed in the interlayer insulating film ILD2a. The source region SR2, the drain region DR2, or the gate electrode G2 is exposed from the contact hole CH2. A contact plug CP2 is buried in the contact hole CH2. The lower end of the contact plug CP2 is electrically connected to the source region SR2, the drain region DR2, or the gate electrode G2. The contact plug CP2 is formed of, for example, tungsten.

[0033] The interlayer insulating film ILD2b is disposed on the interlayer insulating film ILD2a. The interlayer insulating film ILD2b is made of, for example, silicon oxide. A trench TR2b is formed in the interlayer insulating film ILD2b. The trench TR2b penetrates the interlayer insulating film ILD2b in the thickness direction. The interconnect WL2a is buried in the trench TR2b. The interconnect WL2a is made of, for example, copper. The interconnect WL2a is electrically connected to the upper end of the contact plug CP2.

[0034] A plurality of interlayer insulating films ILD2c are stacked on the interlayer insulating film ILD2b. The interlayer insulating film ILD2c is made of silicon oxide. A trench TR2c is formed in the upper surface of the interlayer insulating film ILD2c. A via hole VH2 is formed in the interlayer insulating film ILD2c. The via hole VH2 penetrates the interlayer insulating film ILD2c in the thickness direction. The upper end of the via hole VH2 opens at the bottom surface of the trench TR2c, and the lower end of the via hole VH2 opens at the lower surface of the interlayer insulating film ILD2c.

[0035] The wiring WL2b is buried in the trench TR2c. The via plug VP2 is buried in the via hole VH2. The wiring WL2b and the via plug VP2 are integrally formed. The wiring WL2b and the via plug VP2 are made of copper. The via plug VP2 connects the wiring WL2a and the wiring WL2b in the lowermost layer, and connects two wirings WL2b adjacent to each other in the thickness direction of the wiring layer WL2.

[0036] The sealing resin ER seals the semiconductor chip CHP1 and the semiconductor chip CHP2 so that the upper surfaces of the wiring layers WL1 and WL2 are exposed. The sealing resin ER has a first surface FS3 and a second surface SS3. The first surface FS3 and the second surface SS3 are end surfaces in the thickness direction of the sealing resin ER. The first surface FS3 is flush with the upper surfaces of the wiring layers WL1 and WL2. The second surface SS3 is the opposite surface of the first surface FS3. The sealing resin ER is made of a thermosetting resin material such as epoxy resin.

[0037] The redistribution layer FOL is arranged on the first surface FS3 so as to straddle the semiconductor chip CHP1 (wiring layer WL1) and the semiconductor chip CHP2 (wiring layer WL2). The redistribution layer FOL is arranged on the first surface FS3 so as to overlap the semiconductor chip CHP1 (wiring layer WL1) and the semiconductor chip CHP2 (wiring layer WL2). The redistribution layer FOL has interlayer insulating films ILD3a, ILD3b, and ILD3c, and wires WL3a, WL3b, and WL3c.

[0038] The interlayer insulating film ILD3a is arranged on the first surface FS3 so as to straddle the semiconductor chip CHP1 (wiring layer WL1) and the semiconductor chip CHP2 (wiring layer WL2). The interlayer insulating film ILD3a is arranged on the first surface FS3 so as to overlap the semiconductor chip CHP1 (wiring layer WL1) and the semiconductor chip CHP2 (wiring layer WL2). The interlayer insulating film ILD3a is made of a resin material such as polyimide. A via hole VH3a is formed in the interlayer insulating film ILD3a. The via hole VH3a penetrates the interlayer insulating film ILD3a in the thickness direction.

[0039] The wiring WL3a is disposed on the interlayer insulating film ILD3a. The wiring WL3a is also embedded in the via hole VH3a. This allows the wiring WL3a to be electrically connected to the uppermost layer WL1b or the uppermost layer WL2b. The wiring WL3a is made of, for example, copper.

[0040] The interlayer insulating film ILD3b is disposed on the interlayer insulating film ILD3a. The interlayer insulating film ILD3b is formed of, for example, a resin material such as polyimide. A via hole VH3b is formed in the interlayer insulating film ILD3b. The via hole VH3b penetrates the interlayer insulating film ILD3b in the thickness direction. The wiring WL3b is disposed on the interlayer insulating film ILD3b. The wiring WL3b is also buried in the via hole VH3b. As a result, the wiring WL3b is electrically connected to the wiring WL3a. The wiring WL3b is formed of, for example, copper.

[0041] The interlayer insulating film ILD3c is disposed on the interlayer insulating film ILD3b. The interlayer insulating film ILD3c is formed of, for example, a resin material such as polyimide. A via hole VH3c is formed in the interlayer insulating film ILD3c. The via hole VH3c penetrates the interlayer insulating film ILD3c in the thickness direction. The wiring WL3c is disposed on the interlayer insulating film ILD3c. The wiring WL3c is also buried in the via hole VH3c. As a result, the wiring WL3c is electrically connected to the wiring WL3b. The wiring WL3c is formed of, for example, copper.

[0042] The wiring WL3c has a pad electrode PAD1 and a pad electrode PAD2. The pad electrode PAD1 is electrically connected to the semiconductor chip CHP1 by the wiring WL3b and the wiring WL3a. The pad electrode PAD2 is electrically connected to the semiconductor chip CHP2 by the wiring WL3a and the wiring WL3b. The wiring WL3a, the wiring WL3b, and the wiring WL3c have an underlayer film BF as their base. The underlayer film BF is composed of a barrier metal layer and a seed layer disposed on the barrier metal layer.

[0043] The thickness direction of the semiconductor device DEV1 is defined as a first direction D1. A direction perpendicular to the first direction D1 is defined as a second direction D2. A direction perpendicular to the first direction D1 and the second direction D2 is defined as a third direction D3. The semiconductor chips CHP1 and CHP2 are arranged at an interval in the second direction D2.

[0044] The inductor ID1 is wound across the semiconductor chips CHP1 and CHP2 in a plane perpendicular to the third direction D3. The inductor ID1 is formed so as to overlap the semiconductor chips CHP1 and CHP2. The inductor ID1 is composed of wiring WL3a and wiring WL3b. More specifically, the wiring WL3a has straight line portions WL3aa and WL3ab, and the wiring WL3b has a straight line portion WL3ba. The straight line portions WL3aa, WL3ab, and WL3ba extend along the second direction D2 in a cross-sectional view perpendicular to the third direction D3.

[0045] One end of the straight portion WL3aa in the second direction D2 (the right side in FIG. 3) is electrically connected to the semiconductor chip CHP1 by a wiring WL3a embedded in a via hole VH3a. The other end of the straight portion WL3ab in the second direction D2 (the left side in FIG. 3) is electrically connected to the semiconductor chip CHP1 by a wiring WL3a embedded in a via hole VH3a. Both ends of the straight portion WL3ba in the second direction D2 are electrically connected to the other end of the straight portion WL3aa in the second direction D2 and one end of the straight portion WL3ab in the second direction D2, respectively, by wiring WL3b embedded in a via hole VH3b.

[0046] The inductor ID2 is wound across the semiconductor chips CHP1 and CHP2 in a plane perpendicular to the third direction D3. The inductor ID2 is formed so as to overlap the semiconductor chips CHP1 and CHP2. The inductor ID2 is composed of wiring WL3a and wiring WL3b. More specifically, the wiring WL3a has straight line portions WL3ac and WL3ad, and the wiring WL3b has a straight line portion WL3bb. The straight line portions WL3ac, WL3ad, and WL3bb extend along the second direction D2 in a cross-sectional view perpendicular to the third direction D3.

[0047] One end of the straight portion WL3ac in the second direction D2 is electrically connected to the semiconductor chip CHP2 by a wiring WL3a embedded in a via hole VH3a. The other end of the straight portion WL3ad in the second direction D2 is electrically connected to the semiconductor chip CHP2 by a wiring WL3a embedded in a via hole VH3a. Both ends of the straight portion WL3bb in the second direction D2 are electrically connected to the other end of the straight portion WL3ac in the second direction D2 and one end of the straight portion WL3ad in the second direction D2 by wiring WL3b embedded in a via hole VH3b.

[0048] The inductors ID1 and ID2 face each other with a gap in between in the third direction D3. The inductors ID1 and ID2 are insulated from each other by the interlayer insulating films ILD3a, ILD3b, and ILD3c. The inductors ID1 and ID2 are magnetically coupled to each other. Therefore, the semiconductor chips CHP1 and CHP2 can transmit and receive signals via the inductors ID1 and ID2 while being insulated from each other.

[0049] <Method of Manufacturing Semiconductor Device DEV1> A method for manufacturing the semiconductor device DEV1 will be described below.

[0050] 8 is a process diagram showing a manufacturing method of the semiconductor device DEV1. As shown in FIG. 8, the manufacturing method of the semiconductor device DEV1 includes a preparation step S1, a resin sealing step S2, and a rewiring step S3. The resin sealing step S2 is performed after the preparation step S1. The rewiring step S3 is performed after the resin sealing step S2.

[0051] The resin sealing process S2 includes a first step S21 and a second step S22. The second step S22 is performed after the first step S21. The rewiring process S3 includes a first step S31, a second step S32, a third step S33, a fourth step S34, and a fifth step S35. The second step S32 is performed after the first step S31. The third step S33 is performed after the second step S32. The fourth step S34 is performed after the third step S33. The fifth step S35 is performed after the fourth step S34.

[0052] In the preparation step S1, the semiconductor chips CHP1 and CHP2 are prepared. The semiconductor chips CHP1 and CHP2 may be manufactured by a conventionally known method, and therefore, a description thereof will be omitted here.

[0053] 9 is a cross-sectional view illustrating the first step S21. As shown in FIG. 9, in the first step S21, the semiconductor chip CHP1 and the semiconductor chip CHP2 are bonded to the support substrate SSUB with an adhesive AD. At this time, the wiring layer WL1 side of the semiconductor chip CHP1 and the wiring layer WL2 side of the semiconductor chip CHP2 are bonded to the support substrate SSUB.

[0054] 10 is a cross-sectional view illustrating the second step S22. As shown in FIG. 10, in the second step S22, the sealing resin ER is arranged on the support substrate SSUB so as to cover the semiconductor chips CHP1 and CHP2. After the sealing resin ER is arranged on the support substrate SSUB, the second surface SS3 is polished and planarized. This polishing is performed by, for example, CMP (Chemical Mechanical Polishing). After this polishing, the support substrate SSUB is detached from the semiconductor chips CHP1 and CHP2.

[0055] 11 is a cross-sectional view illustrating the first step S31. As shown in FIG. 11, in the first step S31, an interlayer insulating film ILD3a is formed. In the formation of the interlayer insulating film ILD3a, first, a constituent material of the interlayer insulating film ILD3a is deposited on the first surface FS3. Second, the deposited constituent material of the interlayer insulating film ILD3a is exposed and developed to form a via hole VH3a.

[0056] FIG. 12 is a cross-sectional view illustrating the second step S32. As shown in FIG. 12, in the second step S32, a base film BF is formed on the interlayer insulating film ILD3a, on the inner wall surface of the via hole VH3a, and on the wiring WL1b (wiring WL2b) exposed from the via hole VH3a. FIG. 13 is a cross-sectional view illustrating the third step S33. As shown in FIG. 13, in the third step S33, a resist pattern RP is formed on the base film BF. The resist pattern RP is formed by depositing a photoresist material on the base film BF and patterning the deposited photoresist material by exposing and developing it.

[0057] FIG. 14 is a cross-sectional view illustrating the fourth step S34. As shown in FIG. 14, in the fourth step S34, wiring WL3a is formed on the base film BF exposed from the resist pattern RP. The wiring WL3a is formed by passing a current through the base film BF to perform electrolytic plating on the base film BF exposed from the resist pattern RP. FIG. 15 is a cross-sectional view illustrating the fifth step S35. As shown in FIG. 15, in the fifth step S35, the resist pattern RP is removed, and then the base film BF that was under the resist pattern RP is removed by etching.

[0058] By repeating the same steps as the first step S31 to the fifth step S35, an interlayer insulating film ILD3b, a wiring WL3b, an interlayer insulating film ILD3c, and a wiring WL3c are formed. After the rewiring step S3, the semiconductor device DEV1 is singulated. In this way, the semiconductor device DEV1 having the structure shown in FIG. 2 is formed.

[0059] <Effects of semiconductor device DEV1> The effects of the semiconductor device DEV1 will be described below.

[0060] In the semiconductor device DEV1, the inductors ID1 and ID2 are wound in a plane perpendicular to the third direction D3. Therefore, in the semiconductor device DEV1, the area occupied by the inductors ID1 and ID2 in a plan view can be made smaller than when the inductors ID1 and ID2 are wound in a plane perpendicular to the first direction D1.

[0061] In the semiconductor device DEV1, the inductors ID1 and ID2 are formed across the semiconductor chips CHP1 and CHP2, so that the length of the wiring constituting the inductors ID1 and ID2 can be secured, and therefore the inductance values ​​of the inductors ID1 and ID2 can be secured.

[0062] When the inductors ID1 and ID2 face each other with a gap in the first direction D1, the dielectric strength between the inductors ID1 and ID2 is determined by the thickness of the interlayer insulating film of the redistribution layer FOL between the inductors ID1 and ID2. Changing the thickness of the interlayer insulating film of the redistribution layer FOL between the inductors ID1 and ID2 increases manufacturing costs. Furthermore, if the thickness of the interlayer insulating film of the redistribution layer FOL increases, stress from the interlayer insulating film will cause warping of the semiconductor chips CHP1 and CHP2.

[0063] On the other hand, in the semiconductor device DEV1, it is determined by the distance in the third direction D3 between the inductors ID1 and ID2. The distance in the third direction D3 between the inductors ID1 and ID2 can be freely set, and in the semiconductor device DEV1, it is possible to easily ensure the dielectric strength voltage between the inductors ID1 and ID2. Furthermore, in the semiconductor device DEV1, it is not necessary to increase the thickness of the interlayer insulating film of the redistribution layer FOL to ensure the dielectric strength voltage between the inductors ID1 and ID2, and therefore it is possible to suppress warping of the semiconductor chips CHP1 and CHP2.

[0064] (Second embodiment) A semiconductor device according to a second embodiment will be described. The semiconductor device according to the second embodiment will be referred to as semiconductor device DEV2. Here, differences from semiconductor device DEV1 will be mainly described, and overlapping descriptions will not be repeated.

[0065] <Configuration of semiconductor device DEV2> The configuration of the semiconductor device DEV2 will be described below.

[0066] 16 is a plan view of the semiconductor device DEV2. In FIG. 16, the redistribution layer FOL is not shown, and the inductors ID1 and ID2 are indicated by dotted lines. As shown in FIG. 16, in the semiconductor device DEV2, the end of the inductor ID1 on one side in the second direction D2 (the right side in FIG. 16) is shifted in the second direction D2 from the end of the inductor ID2 on one side in the second direction D2. In the semiconductor device DEV2, the end of the inductor ID1 on the other side in the second direction D2 (the left side in FIG. 16) is shifted in the second direction D2 from the end of the inductor ID2 on the other side in the second direction D2.

[0067] More specifically, in the semiconductor device DEV2, the width of inductor ID1 in the second direction D2 is smaller than the width of inductor ID2 in the second direction D2, and one and other ends of inductor ID1 in the second direction D2 are located more inward in the second direction D2 than one and other ends of inductor ID2 in the second direction D2, respectively. In these respects, the configuration of the semiconductor device DEV2 differs from the configuration of the semiconductor device DEV1. Note that, although not shown, the width of inductor ID1 in the second direction D2 may be larger than the width of inductor ID2 in the second direction D2, and one and other ends of inductor ID1 in the second direction D2 may be located more outward in the second direction D2 than one and other ends of inductor ID2 in the second direction D2, respectively.

[0068] Fig. 17 is a plan view of a semiconductor device DEV2 according to a modified example. In Fig. 17, the redistribution layer FOL is omitted, and the inductors ID1 and ID2 are indicated by dotted lines. As shown in Fig. 17, in the semiconductor device DEV2, it is sufficient that the ends of the inductor ID1 on one side and the other side in the second direction D2 are shifted in the second direction D2 from the ends of the inductor ID2 on one side and the other side in the second direction D2, respectively, and the width of the inductor ID1 in the second direction D2 may be equal to the width of the inductor ID2 in the second direction D2.

[0069] <Effects of semiconductor device DEV2> The effects of the semiconductor device DEV2 will be described below.

[0070] Electric field concentration is likely to occur at both ends of inductor ID1 and inductor ID2 in the second direction D2. In the semiconductor device DEV2, one and the other ends of inductor ID1 in the second direction D2 are offset in the second direction D2 from one and the other ends of inductor ID2 in the second direction D2, respectively, so that the locations in inductor ID1 where electric field concentration is likely to occur and the locations in inductor ID2 where electric field concentration is likely to occur are offset from each other. Therefore, the semiconductor device DEV2 makes it easier to ensure a dielectric strength voltage between inductor ID1 and inductor ID2.

[0071] (Third embodiment) A semiconductor device according to a third embodiment will be described. The semiconductor device according to the third embodiment will be referred to as semiconductor device DEV3. Here, differences from the semiconductor device DEV1 will be mainly described, and overlapping descriptions will not be repeated.

[0072] <Configuration of semiconductor device DEV3> The configuration of the semiconductor device DEV3 will be described below.

[0073] FIG. 18 is a plan view of the semiconductor device DEV3. In FIG. 18, the redistribution layer FOL is omitted, and inductors ID1, ID2, ID3, and ID4 are indicated by dotted lines. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18. FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 18. As shown in FIGS. 18 to 20, the semiconductor device DEV3 further includes inductors ID3 and ID4. The inductor ID3 is wound across the semiconductor chips CHP1 and CHP2 in a plane perpendicular to the third direction D3. The inductor ID3 is formed so as to overlap the semiconductor chips CHP1 and CHP2. The inductor ID3 is composed of wiring WL3a and wiring WL3b. The inductor ID3 is electrically connected to the semiconductor chip CHP1.

[0074] The inductor ID4 is wound across the semiconductor chips CHP1 and CHP2 in a plane perpendicular to the third direction D3. The inductor ID4 is formed so as to overlap the semiconductor chips CHP1 and CHP2. The inductor ID4 is composed of wiring WL3a and wiring WL3b. The inductor ID4 is electrically connected to the semiconductor chip CHP2. The inductors ID3 and ID4 face each other with a gap in between in the third direction D3. That is, the inductors ID3 and ID4 are magnetically coupled while being electrically insulated. The inductor ID2 is, for example, located between the inductors ID1 and ID3 in the third direction D3. The inductor ID3 is, for example, located between the inductors ID2 and ID4 in the third direction D3.

[0075] The distance between inductors ID2 and ID3 in the third direction D3 is defined as a first distance. The distance between inductors ID1 and ID2 in the third direction D3 is defined as a second distance, and the distance between inductors ID3 and ID4 in the third direction D3 is defined as a third distance. The first distance is, for example, larger than the second distance and the third distance. The first distance is preferably 10 times or more larger than the second distance and the third distance.

[0076] Inductor ID1 and inductor ID3 are independent of each other. Inductor ID2 and inductor ID4 are independent of each other. In these respects, the configuration of the semiconductor device DEV3 differs from the configuration of the semiconductor device DEV1.

[0077] <Effects of semiconductor device DEV3> The effects of the semiconductor device DEV3 will be described below.

[0078] In the semiconductor device DEV3, the inductors ID1 and ID3 are independent of each other, and the inductors ID2 and ID4 are independent of each other. Therefore, in the semiconductor device DEV2, signals can be transmitted and received between the semiconductor chips CHP1 and CHP2 via the inductors ID1 and ID2, and signals can be transmitted and received between the semiconductor chips CHP1 and CHP2 via the inductors ID3 and ID4. In this way, the semiconductor device DEV2 enables multi-channel signal transmission and reception between the semiconductor chips CHP1 and CHP2.

[0079] Note that Figures 18 to 20 show the case where there are two channels for transmitting and receiving signals between the semiconductor chip CHP1 and the semiconductor chip CHP2, but if the number of inductors is increased, it becomes possible to transmit and receive signals between the semiconductor chip CHP1 and the semiconductor chip CHP2 using three or more channels.

[0080] When the first spacing is larger than the second spacing and the third spacing, interference between the signal transmission / reception channel formed by inductors ID1 and ID2 and the signal transmission / reception channel formed by inductors ID3 and ID4 is suppressed. The coupling coefficient between inductors is proportional to the square of the insulation distance between the inductors. Therefore, for example, if the first spacing is 10 times or more the second spacing and the third spacing, interference between the signal transmission / reception channel formed by inductors ID1 and ID2 and the signal transmission / reception channel formed by inductors ID3 and ID4 can be reduced to 1 percent or less.

[0081] (Fourth embodiment) A semiconductor device according to a fourth embodiment will be described. The semiconductor device according to the fourth embodiment is designated as semiconductor device DEV4. Here, differences from semiconductor device DEV3 will be mainly described, and overlapping descriptions will not be repeated.

[0082] <Configuration of semiconductor device DEV4> The configuration of the semiconductor device DEV4 will be described below.

[0083] Fig. 21 is a plan view of the semiconductor device DEV4. In Fig. 21, the redistribution layer FOL is not shown, and inductors ID1, ID2, ID3, and ID4 are indicated by dotted lines. In Fig. 21, the uppermost wiring WL1b and the uppermost wiring WL2b are indicated by dotted lines.

[0084] 21, in the semiconductor device DEV4, the inductor ID1 and the inductor ID3 are electrically connected to each other by the wiring WL1b on the top layer. In the semiconductor device DEV4, the inductor ID2 and the inductor ID4 are electrically connected to each other by the wiring WL2b on the top layer. In these respects, the configuration of the semiconductor device DEV4 differs from the configuration of the semiconductor device DEV3.

[0085] <Effects of semiconductor device DEV4> The effects of the semiconductor device DEV4 will be described below.

[0086] In the semiconductor device DEV4, the inductors ID1 and ID3 are electrically connected to each other by the wiring WL1b on the top layer, and the inductors ID2 and ID4 are electrically connected to each other by the wiring WL2b on the top layer. Therefore, according to the semiconductor device DEV4, it is possible to configure a differential transformer using the inductors ID1 and ID3, and it is also possible to configure a differential transformer using the inductors ID2 and ID4.

[0087] (Fifth embodiment) A semiconductor device according to a fifth embodiment will be described. The semiconductor device according to the fifth embodiment is designated as semiconductor device DEV5. Here, differences from the semiconductor device DEV1 will be mainly described, and overlapping descriptions will not be repeated.

[0088] The configuration of the semiconductor device DEV5 will be described below.

[0089] FIG. 22 is a plan view of the semiconductor device DEV5. In FIG. 22, the redistribution layer FOL is omitted, and the inductors ID1 and ID2 are indicated by dotted lines. FIG. 23 is a schematic perspective view of the inductor ID1. FIG. 24 is a schematic perspective view of the inductor ID2. As shown in FIGS. 22 to 24, in the semiconductor device DEV5, the inductor ID1 has a first portion ID1a and a second portion ID1b. In the semiconductor device DEV5, the inductor ID2 has a first portion ID2a and a second portion ID2b.

[0090] The first portion ID1a and the second portion ID1b are wound across the semiconductor chips CHP1 and CHP2 in a plane perpendicular to the third direction D3. The first portion ID1a and the second portion ID1b are formed to overlap the semiconductor chips CHP1 and CHP2, respectively. The first portion ID1a and the second portion ID1b face each other with a gap in between in the third direction D3. One end of the first portion ID1a and the other end of the second portion ID1b are electrically connected to the semiconductor chip CHP1. The other end of the first portion ID1a and one end of the second portion ID1b are electrically connected to each other by a wiring WL3a (connection portion WL3ae). The connection portion WL3ae extends along the third direction D3.

[0091] The first portion ID2a and the second portion ID2b are wound across the semiconductor chips CHP1 and CHP2 in a plane perpendicular to the third direction D3. The first portion ID2a and the second portion ID2b are formed to overlap the semiconductor chips CHP1 and CHP2, respectively. The first portion ID2a and the second portion ID2b face each other with a gap in between in the third direction D3. One end of the first portion ID2a and the other end of the second portion ID2b are electrically connected to the semiconductor chip CHP1. The other end of the first portion ID2a and one end of the second portion ID2b are electrically connected to each other by a wiring WL3a (connection portion WL3af). The connection portion WL3af extends along the third direction D3. In these respects, the configuration of the semiconductor device DEV5 differs from the configuration of the semiconductor device DEV1.

[0092] 22 to 24, the number of turns of each of inductor ID1 and inductor ID2 is two, but the number of turns of each of inductor ID1 and inductor ID2 may be three or more. Also, in the examples shown in Fig. 22 to 24, the number of turns of each of inductor ID1 and inductor ID2 is multiple, but the number of turns of either inductor ID1 or inductor ID2 does not have to be multiple.

[0093] <Effects of semiconductor device DEV5> The effects of the semiconductor device DEV5 will be described below.

[0094] In the semiconductor device DEV5, the number of turns of each of the inductor ID1 and the inductor ID2 is multiple, so that the semiconductor device DEV5 can increase the coupling coefficient of the inductor ID1 and the inductor ID2.

[0095] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0096] AD adhesive, BF underlayer, CH1, CH2 contact holes, CHP1, CHP2 semiconductor chips, CP1, CP2 contact plugs, D1 first direction, D2 second direction, D3 third direction, DEV1 semiconductor device, DEV2, DEV3, DEV4, DEV5 semiconductor device, SR1a first portion, SR1b second portion, DR1 drain region, DR1a first portion, DR1b second portion, DR2 drain region, DR2a first portion, DR2b second portion, ER sealing resin, FOL redistribution layer, FS1, FS2, FS3 first surface, G1 gate electrode, G2 gate electrode, GI1 gate insulating film, GI2 gate insulating film, ID1 inductor, ID1a first portion, ID1b second portion, ID2 inductor, ID2a first portion, ID2b second portion, ID3 inductor, ID4 Inductor, ILD1a, ILD1b, ILD1c, ILD2a, ILD2b, ILD2c interlayer insulating film, ILD3a, ILD3b, ILD3c interlayer insulating film, ISL1 element isolation film, ISL2 element isolation film, PAD1 pad electrode, PAD2 pad electrode, RP resist pattern, S1 preparation process, S2 resin sealing process, S3 rewiring process, S21, S31 first process, S22, S32 second process, S33 third process, S34 fourth process, S35 fifth process, SR1 source region, SR1a first portion, SR1b second portion, SR2 source region, SR2a first portion, SR2b second portion, SS1, SS2, SS3 second surface, SSUB support substrate, SUB1, SUB2 semiconductor substrate, SWS1, SWS2 Sidewall spacers, TR1a, TR1b, TR1c, TR2a, TR2b, TR2c trenches, VH1, VH2, VH3b, VH3c, VH3a via holes, VP1 via plug, VP2 via plug, WL1, WL2 wiring layers, WL1a, WL1b, WL2a, WL2b wiring, WL3a wiring, WL3aa, WL3ab, WL3ac, WL3ad straight sections, WL3ae connection section, WL3af connection section, WL3b wiring, WL3ba, WL3bb straight sections, WL3c wiring, WR1, WR2 well regions.

Claims

1. a first semiconductor chip; a second semiconductor chip; a redistribution layer; the first semiconductor chip and the second semiconductor chip are arranged at intervals in a second direction perpendicular to a first direction that is a thickness direction of the semiconductor device, the rewiring layer is disposed across the first semiconductor chip and the second semiconductor chip; the redistribution layer includes a first inductor and a second inductor; the first inductor and the second inductor face each other with a gap in a third direction perpendicular to the first direction and the second direction, the first inductor is electrically connected to the first semiconductor chip; the second inductor is electrically connected to the second semiconductor chip; the first inductor and the second inductor are wound across the first semiconductor chip and the second semiconductor chip in a plane perpendicular to the third direction, the redistribution layer further includes a third inductor and a fourth inductor; the third inductor and the fourth inductor face each other with a gap in between in the third direction, the third inductor is electrically connected to the first semiconductor chip; the fourth inductor is electrically connected to the second semiconductor chip; the third inductor and the fourth inductor are wound across the first semiconductor chip and the second semiconductor chip in a plane perpendicular to the third direction, the second inductor is located between the first inductor and the third inductor in the third direction; The semiconductor device, wherein the third inductor is located between the second inductor and the fourth inductor in the third direction.

2. an end portion of the first inductor on one side in the second direction is shifted from an end portion of the second inductor on one side in the second direction; 2 . The semiconductor device according to claim 1 , wherein an end of said first inductor on the other side in said second direction is positioned offset from an end of said second inductor on the other side in said second direction.

3. 3. The semiconductor device according to claim 2, wherein a width of said first inductor in said second direction is different from a width of said second inductor in said second direction.

4. 2. The semiconductor device according to claim 1, wherein a first distance between the second inductor and the third inductor is greater than a second distance between the first inductor and the second inductor and a third distance between the third inductor and the fourth inductor.

5. The semiconductor device according to claim 4 , wherein the first interval is at least ten times as large as the second interval and the third interval.

6. the first inductor and the third inductor are independent of each other; The semiconductor device according to claim 1 , wherein the second inductor and the fourth inductor are independent of each other.

7. the first inductor and the third inductor are electrically connected to each other, The semiconductor device according to claim 1 , wherein the second inductor and the fourth inductor are electrically connected to each other.

8. the first semiconductor chip has a first wiring layer including a plurality of first wirings stacked along the first direction; the second semiconductor chip has a second wiring layer including a plurality of second wirings stacked along the first direction; the rewiring layer is on the first wiring layer and the second wiring layer, the first inductor and the third inductor are electrically connected to each other by one of the plurality of first wirings that is closest to the redistribution layer; 8. The semiconductor device according to claim 7, wherein the second inductor and the fourth inductor are electrically connected to each other by one of the plurality of second wirings that is closest to the rewiring layer.

9. At least one of the first inductor and the second inductor has a plurality of portions electrically connected to each other, 2. The semiconductor device according to claim 1, wherein each of said plurality of portions is wound across said first semiconductor chip and said second semiconductor chip in a plane perpendicular to said third direction.

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