Integrated circuit, manufacturing method thereof, power amplifier, and electronic device

Abstract

An integrated circuit, a method for manufacturing the same, a power amplifier, and an electronic device are provided. The integrated circuit includes a substrate (1), a first nucleation layer (2) located on the substrate (1), a buffer layer (3) located on the first nucleation layer (2), a channel layer (4) located on the buffer layer (3), a barrier layer (5) located on the channel layer (4), and a source (6), a drain (7), and a gate (8) separately located on the barrier layer (5). The dislocation density of the buffer layer (3) is 1e8 cm -2 Because the crystal quality can be improved and higher quality epitaxially grown material can be obtained, improving device performance and long-term reliability of integrated circuits.

Description

[Technical Field]

[0001] This application relates to the field of semiconductor technology, and in particular to integrated circuits, methods for fabricating the same, power amplifiers, and electronic devices. [Background technology]

[0002] Typically, metalorganic chemical vapor deposition (M In integrated circuits obtained through heteroepitaxial growth on heterosubstrates based on OCVD (organic chemical vapor deposition) techniques, the performance and reliability of the integrated circuits need to be improved. Summary of the Invention [Means for solving the problem]

[0003] The present application provides integrated circuits, methods for fabricating the same, power amplifiers, and electronic devices for improved performance and reliability.

[0004] According to a first aspect, the present application provides an integrated circuit including a substrate 1, a first nucleation layer located on the substrate, a buffer layer located on the first nucleation layer, a channel layer located on the buffer layer, a barrier layer located on the channel layer, and a source, a drain, and a gate located separately on the barrier layer. The dislocation density of the buffer layer is 1e8cm -2 Specifically, the integrated circuit is (H It may be an EMT.

[0005] In the integrated circuit provided in this embodiment of the present application, the dislocation density of the buffer layer is 1e8 cm -2 Because the crystal quality is less than 1000 nm, the crystal quality can be improved and higher quality epitaxially grown material can be obtained, improving the device performance and long-term reliability of the integrated circuit.

[0006] In a possible implementation of the present application, the dislocation density of the buffer layer is 1e6 cm -2The crystal quality can be further improved, and higher quality epitaxially grown material can be obtained, improving device performance and long-term reliability of integrated circuits.

[0007] In a possible implementation of the present application, the lattice mismatch between the first nucleation layer and the buffer layer can be controlled to less than 2%, so that the crystal quality can be improved and higher quality epitaxial growth material can be obtained, improving the device performance and long-term reliability of the integrated circuit.

[0008] In a possible implementation of the present application, the buffer layer may include doped GaN or doped AlGaN, and the first nucleation layer may include an AlScN material, an AlInN material, or the like. The doping material of the buffer layer may be Fe, C, or the like, and the resistivity of the buffer layer may be improved by doping with Fe or C. When the first nucleation layer uses an AlScN material, the Sc atoms in the AlScN increase the atomic spacing between Al and N, increasing the lattice constant and achieving a good lattice match with the GaN material and minimizing the lattice mismatch. Similarly, in the present application, when the first nucleation layer uses an AlInN material, the In atoms in the AlInN increase the atomic spacing between Al and N, increasing the lattice constant and achieving a good lattice match with the GaN material and minimizing the lattice mismatch. In addition, specifically, the percentage of Sc or In in the material of the first nucleation layer may be adjusted to achieve a good lattice match with the GaN material and minimizing the lattice mismatch.

[0009] In possible implementations of the present application, the atomic percentage of Sc or In in the first nucleation layer is typically less than 40%, so the lattice mismatch between the first nucleation layer and the buffer layer can be less than 2%. In addition, as the percentage of Sc or In in the first nucleation layer gradually increases from 0%, the lattice mismatch with GaN gradually decreases.

[0010] In a possible implementation of the present application, the atomic percentage of Sc or In in the first nucleation layer can be in the range of 15% to 20%. Specifically, the atomic percentage of Sc in the first nucleation layer is 18.75%, i.e., Al. 0.8125 Sc 0.1875 When the atomic percentage of In in the first nucleation layer reaches 17%, the lattice of the AlScN material and the lattice of the GaN material perfectly matches, and the mismatch between the atoms is minimized. 0.83 In 0.17 At N, the lattice of the AlInN material matches perfectly with the lattice of the GaN material, resulting in the smallest mismatch between the atoms.

[0011] In a possible implementation of the present application, when the first nucleation layer is fabricated using AlScN or AlInN, the first nucleation layer can be fabricated by a PVD or PLD process. Compared to when AlN is fabricated as a nucleation layer through an MOCVD process, the first nucleation layer fabricated through PVD and PLD processes has lower substrate selectivity, i.e., the requirements for substrate quality are reduced, so that the growth of the subsequent channel layer material is substrate-independent. The first nucleation layer can be obtained by deposition on a substrate of slightly lower or normal quality. The obtained first nucleation layer can be used to directly grow doped GaN material as a buffer layer, and then high-quality GaN material can be epitaxially grown based on the buffer layer as the channel layer. Therefore, the substrate can be directly SiC or Si material, so that high-quality GaN epitaxial growth can also be performed on a Si substrate with a large lattice mismatch.

[0012] In a possible implementation of the present application, when the substrate uses a SiC material, the lattice constant of SiC is closer to that of AlN compared to when the first nucleation layer uses an AlScN material, an AlInN material, etc. Therefore, the atomic percentage of Sc or In at different positions of the first nucleation layer can be adjusted, specifically, the atomic percentage of Sc or In at the surface of the first nucleation layer in contact with the substrate is adjusted to be smaller than the atomic percentage of Sc or In at the surface of the first nucleation layer in contact with the buffer layer, so that the lattice constant of the surface of the first nucleation layer in contact with the substrate is smaller than the lattice constant of the surface of the first nucleation layer in contact with the buffer layer. In this way, the lattice constant of the surface of the first nucleation layer in contact with the substrate is closer to the lattice constant of SiC, resulting in a better lattice match at the contact interface between the first nucleation layer and the substrate; and the lattice constant of the surface of the first nucleation layer in contact with the buffer layer is closer to the lattice constant of the buffer layer, resulting in a better lattice match at the contact interface between the first nucleation layer and the buffer layer, reducing lattice defects in the first nucleation layer and the buffer layer and improving the crystal quality.

[0013] In a possible implementation of the present application, when the first nucleation layer uses a material such as AlScN, the atomic percentage of Sc in the first nucleation layer can vary from 0% to 18%, so the first nucleation layer is used as a gradient layer. In some gradient layers, the material of the surface in contact with the substrate is AlN to best match the lattice of SiC. The atomic percentage of Sc in the gradient layer gradually increases. In some gradient layers, the atomic percentage of Sc in the AlScN on the surface in contact with the buffer layer is the highest to best match the lattice of GaN. In some gradient layers, the material of the surface in contact with the buffer layer is AlInN to best match the lattice of SiC, so the first nucleation layer is used as a gradient layer. In some gradient layers, the material of the surface in contact with the substrate is AlN to best match the lattice of SiC. The atomic percentage of In in the graded layer gradually increases, and the atomic percentage of In in the AlInN on the surface of the graded layer in contact with the buffer layer is the largest due to the lattice match of GaN.

[0014] In a possible implementation of the present application, compared to using an MOCVD process to fabricate the first nucleation layer, using a PVD or PLD process to fabricate the first nucleation layer can result in a high deposition rate during the generation of the first nucleation layer, saving more than 20% production capacity and significantly reducing production costs. In addition, the PVD or PLD process can support substrates from 8 inches to 12 inches or larger. Specifically, to form the first nucleation layer on the substrate, direct sputtering can be performed using an AlScN or AlInN target, or reactive sputtering can be performed using an Al target, an Sc target (or an In target), and ammonia gas or nitrogen gas. The atomic percentage of Sc or In in the first nucleation layer formed through the aforementioned process can be fixed. Alternatively, when reactive sputtering is performed using an Al target, an Sc target (or an In target), and ammonia gas or nitrogen gas to form a first nucleation layer on a substrate, the reactive sputtering percentage of the Sc target or In target may be gradually increased to gradually increase the atomic percentage of Sc or In in the first nucleation layer in a direction from the substrate toward the buffer layer, thereby forming a gradient layer. The gradual increase may be understood as multiple increasing trends, including a linear increase, a stepwise increase, a parabolic increase, etc. A thick first nucleation layer may be fabricated through a PVD or PLD process, and the thickness of the first nucleation layer may be controlled within 10 nm to 500 nm.

[0015] The first nucleation layer fabricated through PVD or PLD is made of a polycrystalline material (a polycrystalline material is composed of multiple columnar materials, with grain boundaries between the columnar materials, which form defects). Therefore, the first nucleation layer has many grain boundaries, poor crystal quality, and the crystals are mainly vertically aligned. Therefore, to improve the crystal quality of the nucleation layer, after the first nucleation layer is fabricated through the PVD or PLD process, a high-temperature annealing process can be performed on the first nucleation layer under the protection of an inert gas to improve the crystal quality of the material of the first nucleation layer. Alternatively, to improve the crystal quality of the nucleation layer, after the first nucleation layer is fabricated through the PVD or PLD process, a second nucleation layer can be fabricated through the MOVCD process. The second nucleation layer can be made of a quasi-monocrystalline material. In a possible implementation of the present application, the integrated circuit may further include a second nucleation layer positioned between the first nucleation layer and the buffer layer. The second nucleation layer is fabricated through an MOCVD process, resulting in fewer grain boundaries in the second nucleation layer than in the first nucleation layer. In other words, the second nucleation layer has fewer crystal defects and better crystal quality. Thus, when a buffer layer is epitaxially grown on the second nucleation layer, better crystal quality can be achieved.

[0016] To ensure that a second nucleation layer with good crystalline quality can be obtained, the material used for the second nucleation layer must be the same as the material used for the first nucleation layer. For example, after AlScN is deposited on a substrate as the first nucleation layer through a PVD or PLD process, AlScN can continue to grow as the second nucleation layer through an MOCVD process. In addition, the atomic percentages of Sc or In at the contacting surfaces of the first and second nucleation layers are preferably the same, so that the lattices of the first and second nucleation layers match perfectly and no new lattice defects appear. For example, if the atomic percentage of Sc in the first nucleation layer is 18%, the atomic percentage of Sc in the second nucleation layer is also 18%. In another example, if the atomic percentage of Sc in the first nucleation layer changes from 0% to 18%, the atomic percentage of Sc in the second nucleation layer is 18%. In addition, since the film layer grows slowly when the MOVCD process is used, the thickness of the second nucleation layer may be thin and controlled to be less than 100 nm, specifically, a few nm to a few tens of nm.

[0017] In a possible implementation of the present application, in order to achieve a higher surface density of the two-dimensional electron gas when the barrier layer thickness is small and to facilitate the application of radio frequency HEMT devices at high frequencies, the surface density of the two-dimensional electron gas formed using the barrier layer is 1e13 cm -2 Furthermore, the surface density of the two-dimensional electron gas formed using a barrier layer is 2e13cm -2 This further improves the surface density of the two-dimensional electron gas in the barrier layer.

[0018] In a possible implementation of the present application, the barrier layer may include AlScN material, AlInN material, AlN material, etc. These materials have good piezoelectric effects, which can increase the two-dimensional electron gas concentration in the barrier layer and effectively reduce the device short-channel effect caused by a reduced barrier layer thickness in the device. In addition, using AlScN or AlInN material as the barrier layer can further reduce the lattice mismatch between the channel layer and the barrier layer, improve the crystal quality, and obtain higher-quality epitaxially grown material, thereby improving the device performance and long-term reliability of the integrated circuit. Specifically, when AlScN or AlInN material is used as the barrier layer, the atomic percentage of Sc or In is the same as the atomic percentage of Sc or In in the first nucleation layer. The atomic percentage is usually less than 40%, preferably in the range of 15% to 20%, to reduce the lattice mismatch. The optimal atomic percentage of Sc is 18%, and the optimal atomic percentage of In is 17%.

[0019] According to a second aspect, the present application provides an integrated circuit including a substrate 1, a first nucleation layer disposed on the substrate, a buffer layer disposed on the first nucleation layer, a channel layer disposed on the buffer layer, a barrier layer disposed on the channel layer, and a source, a drain, and a gate disposed separately on the barrier layer. The buffer layer may include doped GaN or doped AlGaN, and the first nucleation layer may include AlScN material, AlInN material, etc. The doping material of the buffer layer may be Fe, C, etc., and the resistivity of the buffer layer may be improved by doping with Fe or C. When the first nucleation layer uses AlScN material, the Sc atoms in AlScN increase the atomic spacing between Al and N, increasing the lattice constant and achieving good lattice matching with GaN material, achieving minimal lattice mismatch, resulting in a dislocation density of the buffer layer of 1e8cm. -2 Less than or even 1e6cm -2Similarly, in the present application, when the first nucleation layer uses an AlInN material, the In atoms in the AlInN increase the atomic spacing between Al and N, increasing the lattice constant, which can achieve good lattice matching with the GaN material and minimize lattice mismatch. In addition, specifically, the percentage of Sc or In in the material of the first nucleation layer can be adjusted to achieve good lattice matching with the GaN material and minimize lattice mismatch, resulting in a dislocation density of the buffer layer of 1e8cm. -2 Less than or even 1e6cm -2 Because the lattice mismatch between the buffer layer and the first nucleation layer is reduced and the dislocation density of the buffer layer is reduced, the crystal quality can be improved and higher quality epitaxially grown material can be obtained, thereby improving the device performance and long-term reliability of the integrated circuit.

[0020] In possible implementations of the present application, the atomic percentage of Sc or In in the first nucleation layer is typically less than 40%, so the lattice mismatch between the first nucleation layer and the buffer layer can be less than 2%. In addition, as the percentage of Sc or In in the first nucleation layer gradually increases from 0%, the lattice mismatch with GaN gradually decreases.

[0021] In a possible implementation of the present application, the atomic percentage of Sc or In in the first nucleation layer can be in the range of 15% to 20%. Specifically, the atomic percentage of Sc in the first nucleation layer is 18.75%, i.e., Al. 0.8125 Sc 0.1875 When the atomic percentage of In in the first nucleation layer reaches 17%, the lattice of the AlScN material and the lattice of the GaN material perfectly matches, and the mismatch between the atoms is minimized. 0.83 In 0.17 At N, the lattice of the AlInN material matches perfectly with the lattice of the GaN material, resulting in the smallest mismatch between the atoms.

[0022] In a possible implementation of the present application, when the first nucleation layer is fabricated using AlScN or AlInN, the first nucleation layer can be fabricated by a PVD or PLD process. Compared to when AlN is fabricated as a nucleation layer through an MOCVD process, the first nucleation layer fabricated through PVD and PLD processes has lower substrate selectivity, i.e., the requirements for substrate quality are reduced, so that the growth of the subsequent channel layer material is substrate-independent. The first nucleation layer can be obtained by deposition on a substrate of slightly lower or normal quality. The obtained first nucleation layer can be used to directly grow doped GaN material as a buffer layer, and then high-quality GaN material can be epitaxially grown based on the buffer layer as the channel layer. Therefore, the substrate can be directly SiC or Si material, so that high-quality GaN epitaxial growth can also be performed on a Si substrate with a large lattice mismatch.

[0023] In a possible implementation of the present application, when the substrate uses a SiC material, the lattice constant of SiC is closer to that of AlN compared to when the first nucleation layer uses an AlScN material, an AlInN material, etc. Therefore, the atomic percentage of Sc or In at different positions of the first nucleation layer can be adjusted, specifically, the atomic percentage of Sc or In at the surface of the first nucleation layer in contact with the substrate is adjusted to be smaller than the atomic percentage of Sc or In at the surface of the first nucleation layer in contact with the buffer layer, so that the lattice constant of the surface of the first nucleation layer in contact with the substrate is smaller than the lattice constant of the surface of the first nucleation layer in contact with the buffer layer. In this way, the lattice constant of the surface of the first nucleation layer in contact with the substrate is closer to the lattice constant of SiC, resulting in a better lattice match at the contact interface between the first nucleation layer and the substrate; and the lattice constant of the surface of the first nucleation layer in contact with the buffer layer is closer to the lattice constant of the buffer layer, resulting in a better lattice match at the contact interface between the first nucleation layer and the buffer layer, reducing lattice defects in the first nucleation layer and the buffer layer and improving the crystal quality.

[0024] In a possible implementation of the present application, when the first nucleation layer uses a material such as AlScN, the atomic percentage of Sc in the first nucleation layer can vary from 0% to 18%, so the first nucleation layer is used as a gradient layer. In some gradient layers, the material of the surface in contact with the substrate is AlN to best match the lattice of SiC. The atomic percentage of Sc in the gradient layer gradually increases. In some gradient layers, the atomic percentage of Sc in the AlScN on the surface in contact with the buffer layer is the highest to best match the lattice of GaN. In some gradient layers, the material of the surface in contact with the buffer layer is AlInN to best match the lattice of SiC, so the first nucleation layer is used as a gradient layer. In some gradient layers, the material of the surface in contact with the substrate is AlN to best match the lattice of SiC. The atomic percentage of In in the graded layer gradually increases, and the atomic percentage of In in the AlInN on the surface in contact with the buffer layer is the largest due to the lattice match of GaN.

[0025] In a possible implementation of the present application, compared to using an MOCVD process to fabricate the first nucleation layer, using a PVD or PLD process to fabricate the first nucleation layer can result in a high deposition rate during the generation of the first nucleation layer, saving more than 20% production capacity and significantly reducing production costs. In addition, the PVD or PLD process can support substrates from 8 inches to 12 inches or larger. Specifically, to form the first nucleation layer on the substrate, direct sputtering can be performed using an AlScN or AlInN target, or reactive sputtering can be performed using an Al target, an Sc target (or an In target), and ammonia gas or nitrogen gas. The atomic percentage of Sc or In in the first nucleation layer formed through the aforementioned process can be fixed. Alternatively, when reactive sputtering is performed using an Al target, an Sc target (or an In target), and ammonia gas or nitrogen gas to form a first nucleation layer on a substrate, the reactive sputtering percentage of the Sc target or In target may be gradually increased to gradually increase the atomic percentage of Sc or In in the first nucleation layer in a direction from the substrate toward the buffer layer, thereby forming a gradient layer. The gradual increase may be understood as multiple increasing trends, including a linear increase, a stepwise increase, a parabolic increase, etc. A thick first nucleation layer may be fabricated through a PVD or PLD process, and the thickness of the first nucleation layer may be controlled within 10 nm to 500 nm.

[0026] The first nucleation layer fabricated through PVD or PLD is made of a polycrystalline material (a polycrystalline material is composed of multiple columnar materials, with grain boundaries between the columnar materials, which form defects). Therefore, the first nucleation layer has many grain boundaries, poor crystal quality, and the crystals are mainly vertically aligned. Therefore, to improve the crystal quality of the nucleation layer, after the first nucleation layer is fabricated through the PVD or PLD process, a high-temperature annealing process can be performed on the first nucleation layer under the protection of an inert gas to improve the crystal quality of the material of the first nucleation layer. Alternatively, to improve the crystal quality of the nucleation layer, after the first nucleation layer is fabricated through the PVD or PLD process, a second nucleation layer can be fabricated through the MOVCD process. The second nucleation layer can be made of a quasi-monocrystalline material. In a possible implementation of the present application, the integrated circuit may further include a second nucleation layer positioned between the first nucleation layer and the buffer layer. The second nucleation layer is fabricated through an MOCVD process, resulting in fewer grain boundaries in the second nucleation layer than in the first nucleation layer. In other words, the second nucleation layer has fewer crystal defects and better crystal quality. Thus, when a buffer layer is epitaxially grown on the second nucleation layer, better crystal quality can be achieved.

[0027] To ensure that a second nucleation layer with good crystalline quality can be obtained, the material used for the second nucleation layer must be the same as the material used for the first nucleation layer. For example, after AlScN is deposited on a substrate as the first nucleation layer through a PVD or PLD process, AlScN can continue to grow as the second nucleation layer through an MOCVD process. In addition, the atomic percentages of Sc or In at the contacting surfaces of the first and second nucleation layers are preferably the same, so that the lattices of the first and second nucleation layers match perfectly and no new lattice defects appear. For example, if the atomic percentage of Sc in the first nucleation layer is 18%, the atomic percentage of Sc in the second nucleation layer is also 18%. In another example, if the atomic percentage of Sc in the first nucleation layer changes from 0% to 18%, the atomic percentage of Sc in the second nucleation layer is 18%. In addition, since the film layer grows slowly when the MOVCD process is used, the thickness of the second nucleation layer may be thin and controlled to be less than 100 nm, specifically, a few nm to a few tens of nm.

[0028] In a possible implementation of the present application, in order to achieve a higher surface density of the two-dimensional electron gas when the barrier layer thickness is small and to facilitate the application of radio frequency HEMT devices at high frequencies, the surface density of the two-dimensional electron gas formed using the barrier layer is 1e13 cm -2 Furthermore, the surface density of the two-dimensional electron gas formed using a barrier layer is 2e13cm -2 This further improves the surface density of the two-dimensional electron gas in the barrier layer.

[0029] In a possible implementation of the present application, the barrier layer may include AlScN material, AlInN material, AlN material, etc. These materials have good piezoelectric effects, which can increase the two-dimensional electron gas concentration in the barrier layer and effectively reduce the device short-channel effect caused by a reduced barrier layer thickness in the device. In addition, using AlScN or AlInN material as the barrier layer can further reduce the lattice mismatch between the channel layer and the barrier layer, improve the crystal quality, and obtain higher-quality epitaxially grown material, thereby improving the device performance and long-term reliability of the integrated circuit. Specifically, when AlScN or AlInN material is used as the barrier layer, the atomic percentage of Sc or In is the same as the atomic percentage of Sc or In in the first nucleation layer. The atomic percentage is usually less than 40%, preferably in the range of 15% to 20%, to reduce the lattice mismatch. The optimal atomic percentage of Sc is 18%, and the optimal atomic percentage of In is 17%.

[0030] According to a third aspect, the present application provides a manufacturing method for the integrated circuit provided in either case of the first or second aspect, the method including the steps of forming a first nucleation layer on a substrate through a physical vapor deposition (PVD) process or a pulsed laser deposition (PLD) process, forming a buffer layer on the first nucleation layer through a metalorganic chemical vapor deposition (MOCVD) process, forming a channel layer on the buffer layer through a MOCVD process, forming a barrier layer on the channel layer through a MOCVD process or a molecular beam epitaxy (MBE) process, and separately forming a source, a drain, and a gate on the barrier layer.

[0031] Compared to the case where AlN is fabricated as a nucleation layer through MOCVD, the first nucleation layer fabricated through PVD and PLD processes has lower substrate selectivity, meaning the requirements for substrate quality are reduced, and as a result, the growth of the subsequent channel layer material is substrate-independent. The first nucleation layer can be obtained by deposition on a slightly lower-quality or normal-quality substrate. The obtained first nucleation layer can be used to directly grow doped GaN material as a buffer layer, and then high-quality GaN material can be epitaxially grown on the buffer layer as the channel layer. Therefore, SiC or Si material can be used directly as the substrate, and as a result, high-quality GaN epitaxial growth can be performed even on Si substrates with large lattice mismatches.

[0032] In addition, compared to using an MOCVD process to fabricate the first nucleation layer, using a PVD or PLD process to fabricate the first nucleation layer can result in a high deposition rate during the production of the first nucleation layer, saving more than 20% production capacity and significantly reducing production costs. In addition, the PVD or PLD process can support substrates from 8 inches to 12 inches or larger.

[0033] Specifically, in a possible implementation of the present application, to form a first nucleation layer on the substrate 1, direct sputtering may be performed using an AlScN or AlInN target, or reactive sputtering may be performed using an Al target, an Sc target (or an In target), and ammonia gas or nitrogen gas. The atomic percentage of Sc or In in the first nucleation layer formed through the aforementioned process may be fixed. Alternatively, when reactive sputtering is performed using an Al target, an Sc target (or an In target), and ammonia gas or nitrogen gas to form a first nucleation layer on the substrate, the reactive sputtering percentage of the Sc target or the In target may be gradually increased to gradually increase the atomic percentage of Sc or In in the first nucleation layer in the direction from the substrate to the buffer layer, forming a gradient layer. A thick first nucleation layer may be fabricated through a PVD or PLD process, and the thickness of the first nucleation layer may be controlled within 10 to 500 nm.

[0034] In a possible implementation of the present application, the first nucleation layer fabricated through PVD or PLD is made of a polycrystalline material, resulting in many grain boundaries, poor crystal quality, and crystals primarily oriented vertically. Therefore, to improve the crystal quality of the nucleation layer, a second nucleation layer can be fabricated through an MOVCD process after the first nucleation layer is fabricated through the PVD or PLD process. The second nucleation layer can be made of a quasi-monocrystalline material. The amount of grain boundaries in the second nucleation layer is less than that of the first nucleation layer. In other words, the second nucleation layer has fewer crystal defects and better crystal quality. In this way, better crystal quality can be achieved when a buffer layer is epitaxially grown on the second nucleation layer.

[0035] To ensure that a second nucleation layer with good crystalline quality can be obtained, the material used for the second nucleation layer needs to be the same as the material used for the first nucleation layer. For example, after AlScN is deposited on a substrate as the first nucleation layer through a PVD or PLD process, AlScN can continue to grow as the second nucleation layer through an MOCVD process. In addition, the atomic percentages of Sc or In at the contacting surfaces of the first and second nucleation layers are preferably the same, so that the lattices of the first and second nucleation layers match perfectly and no new lattice defects appear. For example, if the atomic percentage of Sc in the first nucleation layer is 18%, the atomic percentage of Sc in the second nucleation layer is also 18%. In another example, if the atomic percentage of Sc in the first nucleation layer gradually transitions from 0% to 18%, the atomic percentage of Sc in the second nucleation layer is 18%. In addition, since the film layer grows slowly when the MOVCD process is used, the thickness of the second nucleation layer may be thin and controlled to be less than 100 nm, specifically, a few nm to a few tens of nm.

[0036] In a possible implementation of the present application, after forming the first nucleation layer on the substrate, a high-temperature annealing process may be further performed on the first nucleation layer under the protection of an inert gas to improve the crystalline quality of the material of the first nucleation layer. Specifically, the annealing temperature may be controlled within 1500 to 1900 degrees Celsius, and preferably within 1600 to 1800 degrees Celsius. The annealing duration is within 1 to 5 hours, preferably within 2 to 3 hours. The inert gas may be argon gas or nitrogen gas.

[0037] According to a fourth aspect, there is provided an electronic device including a circuit board and an integrated circuit according to an implementation of the first or second aspect disposed on the circuit board.

[0038] According to a fifth aspect, there is provided a power amplifier, the power amplifier including a circuit board and an integrated circuit according to the implementation of the first or second aspect disposed on the circuit board.

[0039] For technical effects that can be achieved by any one of the third to fifth aspects, please refer to the description of the technical effects that can be achieved by any possible design of the first or second aspect, and the details will not be described again in this specification. [Brief explanation of the drawings]

[0040] [Figure 1a] FIG. 1 is a schematic diagram of a depletion mode HEMT device structure for radio frequency applications. [Figure 1b] 1 is a schematic diagram of an enhancement mode HEMT device structure for power application. [Figure 2] FIG. 1 is a schematic diagram of lattice and thermal mismatch in heteroepitaxial structures. [Figure 3a] FIG. 1 is a schematic diagram of a structure that adds a graded layer to a heteroepitaxial structure. [Figure 3b] FIG. 1 is a schematic diagram of a heteroepitaxial structure that adds a buffer layer. [Figure 4] 1 is a schematic diagram of a cross-sectional structure of an integrated circuit according to one embodiment of the present invention; [Figure 5a] FIG. 1 is a comparison diagram of lattice constants between different materials. [Figure 5b] FIG. 2 is a schematic diagram showing the relationship between the thickness of the first nucleation layer and the atomic percentage of Sc or In in the first nucleation layer. [Figure 5c] FIG. 10 is another schematic diagram of the relationship between the thickness of the first nucleation layer and the atomic percentage of Sc or In in the first nucleation layer. [Figure 5d] 1 is a schematic diagram of the structure of a first nucleation layer made of polycrystalline material. [Figure 6a] 2 is a schematic diagram of a cross-sectional structure of another integrated circuit according to an embodiment of the present invention. [Figure 6b]FIG. 2 is a schematic diagram of the relationship between the thickness of the nucleation layer and the atomic percentage of Sc or In in the nucleation layer. [Figure 6c] FIG. 10 is another schematic diagram of the relationship between the thickness of the nucleation layer and the atomic percentage of Sc or In in the nucleation layer. [Figure 7] 1 is a schematic flow chart of a manufacturing method for an integrated circuit according to an embodiment of the present application. [Figure 8] 8A-8C are schematic diagrams of the structure after completion of each step of the fabrication method provided in FIG. 7. [Figure 9] 4 is a schematic flow chart of another manufacturing method for an integrated circuit according to an embodiment of the present application. [Figure 10] 10A-10C are schematic diagrams of the structure after completion of each step of the fabrication method provided in FIG. 9. [Figure 11] 4 is a schematic flow chart of another manufacturing method for an integrated circuit according to an embodiment of the present application. [Figure 12] 12A-12C are schematic diagrams of the structure after completion of each step of the fabrication method provided in FIG. 11. DETAILED DESCRIPTION OF THE INVENTION

[0041] To make the objectives, technical solutions and advantages of the present application clearer, the following further describes the present application in detail with reference to the accompanying drawings.

[0042] GaN semiconductor materials have performance advantages such as a wide bandgap, high breakdown field strength, high polarization coefficient, high electron mobility, and high saturated electron drift velocity, and have great prospects for applications in the fields of power electronics and radio frequency. GaN-based HEMT devices achieve high electron mobility mainly by utilizing the two-dimensional electron gas generated by the polarization effect at the AlGaN / GaN heterojunction interface. These devices have advantages such as high voltage resistance, high power density, and fast processing speed.

[0043] The present application may be applied to the field of microelectronics, including microwave radio frequency devices, power electronic devices, etc., and may also be extended to optoelectronic devices or other fields of microelectronics. Microwave radio frequency devices mainly use GaN devices as power amplifiers. The function of the power amplifier is also applied to the active antenna units of base stations. (A The purpose of GaN devices is to amplify radio frequency signals in a power supply (power amplifier) ​​and then transmit the radio frequency signals through an antenna. Power electronic devices mainly use GaN devices as power switches, enabling fast charging for terminal products such as mobile phones, and functioning as switches for LIDAR.

[0044] See Figure 1a. HEMT devices for radio frequency (RF) applications, currently mainly depletion mode (D-Mode) HEMT devices, usually use semi-insulating SiC as the substrate. Then, AlN material is epitaxially grown as a nucleation layer, and finally electrodes are fabricated to obtain an RF HEMT device.

[0045] See Figure 1b. HEMT devices for power applications mainly use Si as the substrate material. A thick AlN material with a thickness of 50 to 300 nm is epitaxially grown on the Si material as a nucleation layer. Then, AlGaN material is epitaxially grown as a buffer layer, or an AlN / GaN superlattice is epitaxially grown as a buffer layer to buffer the lattice mismatch and thermal expansion coefficient mismatch between Si and nitride. Next, GaN material, AlGaN material, etc. is epitaxially grown, and a p-GaN layer is further fabricated on the AlGaN barrier layer to realize an enhancement mode (E-mode) HEMT.

[0046] See Figure 2. All currently mass-produced GaN-based HEMT devices use heterosubstrates, where GaN material is heteroepitaxially grown using MOCVD. RF HEMT devices typically use semi-insulating SiC as the substrate. The lattice mismatch between SiC and GaN is approximately 3.5%, and the thermal mismatch between GaN and SiC is 33.1%, which can lead to problems with dislocations and cracking in the epitaxial layer. These dislocation defects and other defects remain in the device, affecting its performance and long-term reliability. HEMT devices for power applications typically use Si as the substrate. The lattice mismatch between GaN and Si reaches 16.9%, and the thermal expansion coefficient mismatch (i.e., thermal mismatch) between GaN and Si reaches 56%. Therefore, epitaxial growth of GaN on Si substrates and GaN heterostructures faces severe challenges in terms of stress and defect control.

[0047] The difference in lattice constants of the epitaxial layer materials leads to a high density of dislocation defects at the interface between the substrate and the GaN epitaxial layer. During the epitaxial growth process, most dislocations penetrate the epitaxial layer, which severely affects the crystal quality of the epitaxial layer. In addition, the thermal expansion coefficients of the two layers do not match, which causes large internal stresses to accumulate throughout the epitaxial layer during the cooling process after the epitaxial layer is grown at high temperatures, resulting in warpage and cracks in the epitaxial layer. As the substrate size increases, the warpage and cracks become increasingly evident.

[0048] Currently, insertion layers and buffer layers are widely used to solve the stress problems that exist when GaN is grown heteroepitaxially on a substrate. See Figures 3a and 3b for the two mainstream stress adjustment solutions. This epitaxial structure is complex and requires excessively thick buffer or gradient layers. Additionally, cracks easily form on the edges of the epitaxially grown GaN layer, and the cracks extend continuously to the center.

[0049] The aforementioned issues pose significant challenges for epitaxy. If defects can be detected, the edge area usage can be reduced. If defects are not detected or intercepted, they can pose a risk to device reliability after the device is fabricated. In addition, the aforementioned issues pose significant challenges for future epitaxy of larger silicon substrates, such as 8-inch or 12-inch silicon substrates.

[0050] Therefore, the embodiments of the present application provide an integrated circuit, a manufacturing method thereof, a power amplifier, and an electronic device that can solve the above-mentioned problems. The integrated circuit, the manufacturing method thereof, the power amplifier, and the electronic device will be described in detail below with reference to specific accompanying drawings and embodiments.

[0051] The terms used in the following embodiments are merely for the purpose of describing particular embodiments and are not intended to limit the present application. As used in this specification and the appended claims of this application, the singular terms "one," "a," "the foregoing," "this," and "the one" are intended to include expressions such as "one or more," unless the context clearly dictates otherwise.

[0052] References to "one embodiment," "some embodiments," etc. described herein indicate that one or more embodiments of the present application include the particular feature, structure, or characteristic described with reference to the embodiment. Thus, statements such as "in one embodiment," "in some embodiments," "in some other embodiments," and "in other embodiments" appearing in various places herein do not necessarily refer to the same embodiment. Instead, these statements mean "one or more, but not all, embodiments," unless specifically emphasized otherwise. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless specifically stated otherwise.

[0053] 4 shows an example of a schematic diagram of a cross-sectional structure of an integrated circuit according to an embodiment of the present application. Please refer to FIG. 4. In this embodiment of the present application, the integrated circuit may include a substrate 1, a first nucleation layer 2 located on the substrate 1, a buffer layer 3 located on the first nucleation layer 2, a channel layer 4 located on the buffer layer 3, a barrier layer 5 located on the channel layer 4, and a source 6, a drain 7, and a gate 8 located separately on the barrier layer 5. The dislocation density of the buffer layer 3 is 1e8cm -2 is less than.

[0054] In the integrated circuit provided in this embodiment of the present application, the dislocation density of the buffer layer 3 is 1e8cm -2 Because the thickness is less than 100 nm, higher quality epitaxially grown material can be obtained, improving device performance and long-term reliability of integrated circuits.

[0055] Furthermore, in this embodiment of the present application, the dislocation density of the buffer layer 3 is 1e6 cm -2 The crystal quality can be further improved, and higher quality epitaxially grown material can be obtained, improving device performance and long-term reliability of integrated circuits.

[0056] In this embodiment of the present application, the lattice mismatch between the first nucleation layer 2 and the buffer layer 3 can be controlled to less than 2%, so that the crystal quality can be improved and higher quality epitaxial growth material can be obtained, improving the device performance and long-term reliability of the integrated circuit.

[0057] Specifically, in this embodiment of the present application, the integrated circuit comprises a high electron mobility transistor (H It may be an EMT.

[0058] Specifically, in this embodiment of the present application, the buffer layer 3 may include doped GaN or doped AlGaN, and the first nucleation layer 2 may include an AlScN material, an AlInN material, or the like. The doping material of the buffer layer 3 may be Fe, C, or the like, and the resistivity of the buffer layer 3 may be improved by doping with Fe or C. Below, we use an example in which the buffer layer 3 is made of GaN for explanation. Figure 5a shows an example of a comparison of the lattice constants of different materials. See Figure 5a. The lattice constant of AlN is smaller than that of GaN. In the prior art, AlN is used as a nucleation layer, and a lattice mismatch exists between AlN and GaN. Epitaxially grown GaN has lattice dislocations, which cause lattice defects and affect the crystal quality. In this application, when the first nucleation layer 2 is made of AlScN, the Sc atoms in AlScN increase the atomic spacing between Al and N, increasing the lattice constant and achieving a good lattice match with the GaN material, thereby achieving a minimal lattice mismatch. Similarly, in the present application, when the first nucleation layer 2 uses an AlInN material, the In atoms in the AlInN increase the atomic spacing between Al and N, increasing the lattice constant, which can achieve good lattice matching with the GaN material and minimize lattice mismatch. In addition, specifically, the percentage of Sc or In in the material of the first nucleation layer 2 can be adjusted to achieve good lattice matching with the GaN material and minimize lattice mismatch.

[0059] Specifically, in this embodiment of the present application, the atomic percentage of Sc or In in the first nucleation layer 2 is typically less than 40%, so that the lattice mismatch between the first nucleation layer 2 and the buffer layer 3 can be less than 2%. In addition, as the percentage of Sc or In in the first nucleation layer 2 gradually increases from 0%, the lattice mismatch with GaN gradually decreases. Furthermore, in this embodiment of the present application, the atomic percentage of Sc or In in the first nucleation layer 2 can be in the range of 15% to 20%. Preferably, in this embodiment of the present application, referring to FIG. 5a, the atomic percentage of Sc in the first nucleation layer 2 is 18.75%, i.e., Al 0.8125 Sc 0.1875When the atomic percentage of In in the first nucleation layer 2 reaches 17%, that is, Al 0.83 In 0.17 At N, the lattice of the AlInN material matches perfectly with the lattice of the GaN material, resulting in the smallest mismatch between the atoms.

[0060] In this embodiment of the present application, when the first nucleation layer 2 is manufactured using AlScN or AlInN, the first nucleation layer 2 is specifically formed by physical vapor deposition. (P VD) or pulsed laser deposition (P The first nucleation layer 2 can be fabricated through a PVD (photo-deposition) process. Compared with the case where AlN is fabricated as a nucleation layer through an MOCVD process, the first nucleation layer 2 fabricated through the PVD and PLD processes has lower selectivity on the substrate 1, i.e., the requirements for the quality of the substrate 1 are reduced, so that the subsequent growth of the material for the channel layer 4 does not depend on the substrate 1. The first nucleation layer 2 can be obtained by deposition on a slightly low-quality or normal-quality substrate 1 (this means that the defect requirements on the surface of the substrate 1 are not strict and macro-defects can be tolerated). The obtained first nucleation layer 2 can be used to directly grow a doped GaN material as the buffer layer 3, and then a high-quality GaN material can be epitaxially grown based on the buffer layer 3 as the channel layer 4. Therefore, the substrate 1 can be directly made of SiC or Si material, so that high-quality GaN epitaxial growth can also be performed on a Si substrate with a large lattice mismatch.

[0061] 5a. In another embodiment of the present application, when the substrate 1 uses a SiC material, the lattice constant of SiC is closer to that of AlN, compared with when the first nucleation layer 2 uses an AlScN material, an AlInN material, etc. Therefore, the atomic percentage of Sc or In at different positions of the first nucleation layer 2 can be adjusted, specifically, the atomic percentage of Sc or In at the surface of the first nucleation layer 2 in contact with the substrate 1 is adjusted to be smaller than the atomic percentage of Sc or In at the surface of the first nucleation layer 2 in contact with the buffer layer 3, so that the lattice constant of the surface of the first nucleation layer 2 in contact with the substrate 1 is smaller than the lattice constant of the surface of the first nucleation layer 2 in contact with the buffer layer 3. In this way, the lattice constant of the surface of the first nucleation layer 2 in contact with the substrate 1 is closer to the lattice constant of SiC, resulting in a better lattice match at the contact interface between the first nucleation layer 2 and the substrate 1, and the lattice constant of the surface of the first nucleation layer in contact with the buffer layer 3 is closer to the lattice constant of the buffer layer 3, resulting in a better lattice match at the contact interface between the first nucleation layer 2 and the buffer layer 3, reducing lattice defects in the first nucleation layer 2 and the buffer layer 3 and improving the crystal quality.

[0062] 5b and 5c show examples of schematic diagrams of the relationship between the thickness of the first nucleation layer and the atomic percentage of Sc or In in the first nucleation layer. See FIGS. 5b and 5c. In this embodiment of the present application, when the first nucleation layer 2 uses a material such as AlScN, the atomic percentage of Sc in the first nucleation layer 2 can vary from 0% to 18%, so the first nucleation layer 2 is used as a gradient layer. In the gradient layer, the material of the surface in contact with the substrate 1 is AlN to best match the lattice of SiC. The atomic percentage of Sc in the gradient layer gradually increases. The gradual increase can be understood as multiple increasing trends, including a linear increase, a stepwise increase as shown in FIG. 5b, and a parabolic increase as shown in FIG. 5c. In the gradient layer, the atomic percentage of Sc in AlScN on the surface in contact with the buffer layer 3 is the highest to best match the lattice of GaN. When the first nucleation layer 2 uses a material such as AlInN, the atomic percentage of In in the first nucleation layer 2 can vary from 0% to 17%, so the first nucleation layer 2 is used as a gradient layer. In the gradient layer, the material of the surface in contact with the substrate 1 is AlN to best match the lattice of SiC. The atomic percentage of In in the gradient layer gradually increases. The gradual increase can be understood as multiple increasing trends, including a linear increase, a stepwise increase as shown in FIG. 5b, and a parabolic increase as shown in FIG. 5c. In the gradient layer, the atomic percentage of In in the AlInN on the surface in contact with the buffer layer 3 is the highest to best match the lattice of GaN.

[0063] In this embodiment of the present application, compared to using an MOCVD process to fabricate the first nucleation layer 2, using a PVD or PLD process to fabricate the first nucleation layer 2 can result in a high deposition rate during the generation of the first nucleation layer 2, saving more than 20% production capacity and significantly reducing production costs. In addition, the PVD or PLD process can support substrates from 8 inches to 12 inches or larger. Specifically, to form the first nucleation layer 2 on the substrate 1, direct sputtering can be performed using an AlScN or AlInN target, or reactive sputtering can be performed using an Al target, an Sc target (or an In target), and ammonia gas or nitrogen gas. The atomic percentage of Sc or In in the first nucleation layer 2 formed through the aforementioned process can be fixed. Alternatively, when an Al target, an Sc target (or an In target), and ammonia gas or nitrogen gas are used to perform reactive sputtering to form the first nucleation layer 2 on the substrate 1, the reactive sputtering percentage of the Sc target or the In target may be gradually increased to gradually increase the atomic percentage of Sc or In in the first nucleation layer 2 in the direction from the substrate 1 toward the buffer layer 3, thereby forming a gradient layer. A thick first nucleation layer 2 may be fabricated through a PVD or PLD process, and the thickness of the first nucleation layer 2 may even be controlled within 10 nm to 500 nm.

[0064] FIG. 5d shows an example of a schematic diagram of the structure of a first nucleation layer made of a polycrystalline material. See FIG. 5d. Because the first nucleation layer 2 fabricated through PVD or PLD is made of a polycrystalline material (polycrystalline materials consist of multiple columnar materials, with grain boundaries between the columnar materials, which form defects), the first nucleation layer 2 has many grain boundaries, poor crystal quality, and the crystals are mainly vertically aligned. Therefore, to improve the crystal quality of the nucleation layer, after the first nucleation layer 2 is fabricated through the PVD or PLD process, a high-temperature annealing process can be performed on the first nucleation layer 2 under the protection of an inert gas to improve the crystal quality of the material of the first nucleation layer 2. Alternatively, to improve the crystal quality of the nucleation layer, a second nucleation layer can be fabricated through a MOVCD process after the first nucleation layer 2 is fabricated through the PVD or PLD process. The second nucleation layer can be made of a quasi-single-crystalline material. FIG. 6a shows an example of a schematic diagram of a cross-sectional structure of another integrated circuit according to an embodiment of the present application. See FIG. 6a. In another embodiment of the present application, the integrated circuit may further include a second nucleation layer 9 located between the first nucleation layer 2 and the buffer layer 3. The second nucleation layer 9 is fabricated through an MOCVD process, so that the amount of grain boundaries in the second nucleation layer 9 is smaller than the amount of grain boundaries in the first nucleation layer. In other words, the second nucleation layer 9 has fewer crystal defects and better crystal quality. In this way, better crystal quality can be obtained when the buffer layer 3 is epitaxially grown on the second nucleation layer 9.

[0065] 6b and 6c show examples of schematic diagrams of the relationship between the thickness of the nucleation layer and the atomic percentage of Sc or In in the nucleation layer. It is worth noting that the material used for the second nucleation layer 9 must be the same as the material used for the first nucleation layer 1 to ensure that the second nucleation layer 9 can be obtained with good crystal quality. For example, after AlScN is deposited on the substrate 1 as the first nucleation layer 2 through a PVD or PLD process, AlScN can continue to grow as the second nucleation layer 9 through an MOCVD process. In addition, the atomic percentages of Sc or In at the contacting surfaces of the first nucleation layer 2 and the second nucleation layer 9 are preferably the same, so that the lattices of the first nucleation layer 2 and the second nucleation layer 9 are perfectly matched and no new lattice defects appear. For example, if the atomic percentage of Sc in the first nucleation layer 2 is 18%, the atomic percentage of Sc in the second nucleation layer 9 is also 18%. 6b and 6c for another example. When the atomic percentage of Sc in the first nucleation layer 2 changes from 0% to 18%, the atomic percentage of Sc in the second nucleation layer 9 is 18%. In addition, because the film layer grows slowly when the MOVCD process is used, the thickness of the second nucleation layer 9 can be thin and is controlled to be less than 100 nm, specifically, several nm to several tens of nm.

[0066] In this embodiment of the present application, the channel layer 4 may include a GaN material. The buffer layer 3, the channel layer 4, and the barrier layer 5 may all be fabricated by an MOCVD process to obtain single-crystal materials. The thickness of the buffer layer 3 and the channel layer 4 may be less than 5 μm.

[0067] In this embodiment of the present application, in order to realize a higher surface density of the two-dimensional electron gas when the thickness of the barrier layer 5 is small and to facilitate the application of radio frequency HEMT devices at high frequencies, the surface density of the two-dimensional electron gas that can be formed using the barrier layer 5 is 1e13 cm -2 Furthermore, the surface density of the two-dimensional electron gas that can be formed using the barrier layer 5 is 2e13 cm -2This further improves the surface density of the two-dimensional electron gas in the barrier layer 5 .

[0068] In this embodiment of the present application, the barrier layer 5 may include an AlScN material, an AlInN material, an AlN material, or the like. These materials have a good piezoelectric effect, which can increase the two-dimensional electron gas concentration in the barrier layer 5 and effectively reduce the device short-channel effect caused by the reduced thickness of the barrier layer 5 in the device. In addition, the use of an AlScN or AlInN material as the barrier layer 5 can further reduce the lattice mismatch between the channel layer 4 and the barrier layer 5, improve the crystal quality, and obtain a higher-quality epitaxially grown material, thereby improving the device performance and long-term reliability of the integrated circuit. Specifically, when an AlScN or AlInN material is used as the barrier layer 5, the atomic percentage of Sc or In is the same as the atomic percentage of Sc or In in the first nucleation layer. The atomic percentage is usually less than 40%, preferably in the range of 15% to 20%, to reduce the lattice mismatch. The optimal atomic percentage of Sc is 18%, and the optimal atomic percentage of In is 17%.

[0069] To facilitate understanding of the integrated circuit provided in the embodiments of the present application, the following will describe in detail the manufacturing method thereof with reference to the accompanying drawings. Figure 7 shows an example of a schematic flowchart of the manufacturing method of the integrated circuit according to an embodiment of the present application. Figure 8 shows an example of a schematic diagram of the structure after each step of the manufacturing method provided in Figure 7 is completed. Please refer to Figures 7 and 8. The integrated circuit can be manufactured using the following manufacturing method, which includes the following steps:

[0070] S1: Form a first nucleation layer 2 on a substrate 1 through a PVD process or a PLD process. See Figure 8a.

[0071] Compared with the case where AlN is fabricated as a nucleation layer through an MOCVD process, the first nucleation layer 2 fabricated through PVD and PLD processes has lower selectivity on the substrate 1, i.e., the requirements for the quality of the substrate 1 are reduced, so that the subsequent growth of the material for the channel layer 4 does not depend on the substrate 1. The first nucleation layer 2 can be obtained by deposition on a substrate 1 of slightly lower or normal quality. The obtained first nucleation layer 2 can be used to directly grow a doped GaN material as a buffer layer 3, and then a high-quality GaN material can be epitaxially grown on the buffer layer 3 as the channel layer 4. Therefore, SiC or Si material can be directly used as the substrate 1, so that high-quality GaN epitaxial growth can also be performed on a Si substrate with a large lattice mismatch.

[0072] In addition, compared to using an MOCVD process to fabricate the first nucleation layer 2, using a PVD or PLD process to fabricate the first nucleation layer 2 can result in a high deposition rate during the production of the first nucleation layer 2, saving more than 20% production capacity and significantly reducing production costs. In addition, the PVD or PLD process can support substrates from 8 inches to 12 inches or larger.

[0073] Specifically, to form the first nucleation layer 2 on the substrate 1, direct sputtering can be performed using an AlScN or AlInN target, or reactive sputtering can be performed using an Al target, an Sc target (or an In target), and ammonia gas or nitrogen gas. The atomic percentage of Sc or In in the first nucleation layer 2 formed through the aforementioned process can be fixed. Alternatively, when reactive sputtering is performed using an Al target, an Sc target (or an In target), and ammonia gas or nitrogen gas to form the first nucleation layer 2 on the substrate 1, the reactive sputtering percentage of the Sc target or In target can be gradually increased to gradually increase the atomic percentage of Sc or In in the first nucleation layer 2 in the direction from the substrate 1 toward the buffer layer 3, forming a gradient layer. A thick first nucleation layer 2 can be fabricated through a PVD or PLD process, and the thickness of the first nucleation layer 2 can be controlled within 10 to 500 nm.

[0074] S2: Form a buffer layer 3 on the first nucleation layer 2 through an MOCVD process. See Figure 8b.

[0075] Specifically, doped GaN or doped AlGaN can be selected to form the buffer layer 3. The doping material for the buffer layer 3 can be Fe, C, or the like, and doping with Fe or C can improve the resistivity of the buffer layer 3. When the lattice of the material for the first nucleation layer 2 matches the lattice of the material for the buffer layer 3, dislocation defects and the like in the buffer layer 3 grown on the first nucleation layer 2 can be reduced, improving crystal quality and resulting in higher-quality epitaxially grown material, thereby improving the device performance and long-term reliability of integrated circuits. Specifically, the thickness of the buffer layer 3 fabricated through MOCVD can be controlled to less than 5 μm.

[0076] S3: Form a channel layer 4 on the buffer layer 3 through an MOCVD process. See Figure 8b.

[0077] Specifically, GaN material can be selected to form the channel layer 4. The thickness of the channel layer 4 fabricated through MOCVD can be controlled to be less than 5 μm.

[0078] S4: Form a barrier layer 5 on the channel layer 4 through an MOCVD process or a molecular beam epitaxy (MBE) process, see Figure 8c.

[0079] Specifically, AlScN material, AlInN material, AlN material, etc. may be selected to form the barrier layer 5. These materials have good piezoelectric effects, which can increase the two-dimensional electron gas concentration in the barrier layer 5 and effectively reduce the device short-channel effect caused by a reduction in the thickness of the barrier layer 5 in the device. In addition, by using AlScN or AlInN material as the barrier layer 5, the lattice mismatch between the channel layer 4 and the barrier layer 5 can be further reduced, the crystal quality can be improved, and a higher-quality epitaxially grown material can be obtained, thereby improving the device performance and long-term reliability of the integrated circuit.

[0080] S5: Separately form a source 6, a drain 7, and a gate 8 on the barrier layer 5. See FIG. 8d.

[0081] Figure 9 shows an example of a schematic flowchart of another method for manufacturing an integrated circuit according to an embodiment of the present application. Figure 10 shows an example of a schematic diagram of a structure after completing each step of the manufacturing method provided in Figure 9. Please refer to Figures 9 and 10. In another manufacturing method provided in the present application, after step S1 of forming a first nucleation layer on a substrate, the method may further include S11, i.e., forming a second nucleation layer on the first nucleation layer through an MOCVD process. Please refer to a1 in Figure 10.

[0082] Because the first nucleation layer 2 fabricated through PVD or PLD is made of a polycrystalline material, it has many grain boundaries, poor crystal quality, and the crystals are primarily vertically aligned. Therefore, to improve the crystal quality of the nucleation layer, a second nucleation layer 9 can be fabricated through an MOVCD process after the first nucleation layer 2 is fabricated through the PVD or PLD process. The second nucleation layer 9 can be made of a quasi-monocrystalline material. The amount of grain boundaries in the second nucleation layer 9 is less than that of the first nucleation layer. In other words, the second nucleation layer 9 has fewer crystal defects and better crystal quality. In this way, better crystal quality can be achieved when the buffer layer 3 is epitaxially grown on the second nucleation layer 9.

[0083] It is worth noting that the material used for the second nucleation layer 9 needs to be the same as the material used for the first nucleation layer 1 to ensure that a second nucleation layer 9 with good crystalline quality can be obtained. For example, after AlScN is deposited on the substrate 1 as the first nucleation layer 2 through a PVD or PLD process, AlScN can continue to grow as the second nucleation layer 9 through an MOCVD process. In addition, the atomic percentages of Sc or In at the contacting surfaces of the first nucleation layer 2 and the second nucleation layer 9 are preferably the same, so that the lattices of the first nucleation layer 2 and the second nucleation layer 9 are perfectly matched and no new lattice defects appear. For example, if the atomic percentage of Sc in the first nucleation layer 2 is 18%, the atomic percentage of Sc in the second nucleation layer 9 is also 18%. In another example, when the atomic percentage of Sc in the first nucleation layer 2 gradually transitions from 0% to 18%, the atomic percentage of Sc in the second nucleation layer 9 is 18%. In addition, because the film layer grows slowly when the MOVCD process is used, the thickness of the second nucleation layer 9 may be thin and is controlled to be less than 100 nm, specifically, several nm to several tens of nm.

[0084] FIG. 11 shows an example of a schematic flowchart of another method for manufacturing an integrated circuit according to an embodiment of the present application. FIG. 12 shows an example of a schematic diagram of a structure after completing each step of the manufacturing method provided in FIG. 11. For an optional solution, please refer to FIGS. 11 and 12. After step S1 of forming a first nucleation layer on a substrate, the method may further include step S12, namely, performing a high-temperature annealing process on the first nucleation layer 2 under the protection of an inert gas to improve the crystalline quality of the material of the first nucleation layer 2. See a2 in FIG. 12.

[0085] Specifically, the annealing temperature may be controlled within a range of 1500 to 1900° C., and preferably within a range of 1600 to 1800° C. The annealing duration is within a range of 1 to 5 hours, preferably within a range of 2 to 3 hours. The inert gas may be, specifically, argon gas or nitrogen gas.

[0086] An embodiment of the present application further provides an electronic device. The electronic device may include a circuit board and any integrated circuit provided in the above-mentioned embodiments of the present application. The integrated circuit is disposed on the circuit board. The problem-solving principle of the electronic device is similar to that of the above-mentioned integrated circuit. Therefore, for the implementation of the electronic device, please refer to the implementation of the above-mentioned integrated circuit, and the details will not be described again.

[0087] An embodiment of the present application further provides a power amplifier. The power amplifier may include a circuit board and any integrated circuit provided in the above-mentioned embodiments of the present application. The integrated circuit is disposed on the circuit board. The problem-solving principle of the power amplifier is similar to that of the above-mentioned integrated circuit. Therefore, for the implementation of the power amplifier, please refer to the implementation of the above-mentioned integrated circuit, and the details will not be described again.

[0088] Certainly, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application, and this application intends to cover such modifications and variations of this application as long as they fall within the scope of the claims of this application and their equivalents. [Explanation of symbols]

[0089] 1 board 2. First nucleation layer 3. Buffer layer 4 Channel Layer 5 Barrier Layer 6. Sauce 7. Drain 8 Gates 9 Second nucleation layer

Claims

1. 1. An integrated circuit comprising: A substrate; a first nucleation layer located on the substrate; a buffer layer located on the first nucleation layer; a channel layer located on the buffer layer; a barrier layer positioned on the channel layer; a source, a drain, and a gate, each of which is separately positioned on the barrier layer; Including, the dislocation density of the buffer layer is less than 1e6 cm The buffer layer comprises doped GaN or doped AlGaN, and the first nucleation layer comprises AlScN or AlInN.

2. 2. The integrated circuit of claim 1, wherein the lattice mismatch between the first nucleation layer and the buffer layer is less than 2%.

3. 2. The integrated circuit of claim 1, wherein the atomic percentage of Sc or In in said first nucleation layer is less than 40%.

4. 4. The integrated circuit of claim 3, wherein the atomic percentage of Sc or In in the first nucleation layer ranges from 15% to 20%.

5. 5. The integrated circuit of claim 4, wherein the atomic percentage of Sc in the first nucleation layer is 18.75% or the atomic percentage of In in the first nucleation layer is 17%.

6. 2. The integrated circuit of claim 1, wherein the atomic percentage of Sc or In at the surface of the first nucleation layer in contact with the substrate is less than the atomic percentage of Sc or In at the surface of the first nucleation layer in contact with the buffer layer.

7. 7. The integrated circuit of claim 6, wherein the atomic percentage of Sc in said first nucleation layer varies from 0% to 18% or the atomic percentage of In in said first nucleation layer varies from 0% to 17%.

8. 8. The integrated circuit of claim 1, further comprising a second nucleation layer located between the first nucleation layer and the buffer layer, wherein an amount of grain boundaries in the second nucleation layer is less than an amount of grain boundaries in the first nucleation layer.

9. The surface density of the two-dimensional electron gas formed using the barrier layer is 1e13 cm －２ 9. The integrated circuit of claim 1, further comprising:

10. The surface density of the two-dimensional electron gas formed using the barrier layer is 2e13 cm －２ The integrated circuit of claim 9 .

11. 11. The integrated circuit of claim 9 or 10, wherein the channel layer comprises GaN and the barrier layers comprise AlScN, AlInN, or AlN.

12. The integrated circuit of claim 1 , wherein the substrate comprises Si or SiC.

13. 13. The integrated circuit of claim 1, wherein the integrated circuit is a high electron mobility transistor.

14. 14. A method of manufacturing an integrated circuit according to any one of claims 1 to 13, comprising the steps of: forming a first nucleation layer on a substrate through a physical vapor deposition (PVD) process or a pulsed laser deposition (PLD) process; forming a buffer layer on the first nucleation layer through a metalorganic chemical vapor deposition (MOCVD) process; forming a channel layer on the buffer layer through the MOCVD process; forming a barrier layer on the channel layer through the MOCVD process or the molecular beam epitaxy (MBE) process; separately forming a source, a drain, and a gate on the barrier layer; A manufacturing method comprising:

15. After the step of forming a first nucleation layer on the substrate, the method further comprises: forming a second nucleation layer on the first nucleation layer through the MOCVD process; The method of claim 14 further comprising:

16. After the step of forming a first nucleation layer on the substrate, the method further comprises: performing a high temperature annealing process on the first nucleation layer under the protection of an inert gas; The method of claim 14 further comprising:

17. forming a first nucleation layer on a substrate; forming the first nucleation layer on the substrate by direct sputtering using an AlScN or AlInN target, reactive sputtering using an Al target, an Sc target, and ammonia gas or nitrogen gas, or reactive sputtering using an Al target, an In target, and ammonia gas or nitrogen gas; The method of any one of claims 14 to 16, comprising:

18. 18. The manufacturing method of claim 17, wherein when the Al target, the Sc target, and the ammonia gas or the nitrogen gas are used to perform reactive sputtering, or when the Al target, the In target, and the ammonia gas or the nitrogen gas are used to perform reactive sputtering to form the first nucleation layer on the substrate, a reactive sputtering percentage of the Sc target or the In target is gradually increased, so that the atomic percentage of Sc or In in the first nucleation layer gradually increases in a direction from the substrate toward the buffer layer.

19. An electronic device comprising a circuit board and an integrated circuit according to any one of claims 1 to 13 disposed on the circuit board.

20. A power amplifier comprising a circuit board and an integrated circuit according to any one of claims 1 to 13 arranged on the circuit board.

Images