Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device

Abstract

To provide a method for manufacturing a silicon carbide semiconductor device capable of reducing disturbance or damage at a SiO2 / SiC interface, uniformly nitriding the inside of a SiO2 film, and improving element characteristics, and the silicon nitride semiconductor device.SOLUTION: A gate insulation film forming step includes a step of performing first nitride heat treatment with a gas containing oxygen and nitrogen, a step of depositing an oxide film, and a step of performing second nitride heat treatment with a gas containing nitrogen monoxide and nitrogen in this order. At a processing start point, an amount of nitrogen in the first nitride heat treatment is greater than an amount of nitrogen in the second nitride heat treatment. At a processing end point, the amount of nitrogen in the second nitride heat treatment is greater than the amount of nitrogen in the first nitride heat treatment.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a next-generation semiconductor material that will replace silicon (Si). Compared to conventional semiconductor devices that use silicon carbide as the semiconductor material, semiconductor devices that use silicon carbide as the semiconductor material (hereinafter referred to as silicon carbide semiconductor devices) have various advantages, such as the ability to reduce the resistance of the device in the on-state to one-hundredth of that of conventional semiconductor devices that use silicon as the semiconductor material, and the ability to be used in higher temperature environments (over 200°C). This is due to the characteristics of the material itself, namely, that the band gap of silicon is about three times larger than that of silicon, and that the dielectric breakdown field strength is nearly one order of magnitude greater than that of silicon.

[0003] To date, commercially available silicon carbide semiconductor devices include Schottky barrier diodes (SBDs) and vertical MOSFETs (metal oxide semiconductor field effect transistors) with planar gate structures or trench gate structures.

[0004] The planar gate structure is a MOS gate structure in which a flat MOS gate is provided on the front surface of a semiconductor substrate. The trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on the front surface of a semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed along the sidewall of the trench in a direction perpendicular to the front surface of the semiconductor substrate. This allows for a higher density of unit cells (element constituent units) per unit area compared to a planar gate structure in which a channel is formed along the front surface of the semiconductor substrate, thereby increasing the current density per unit area, and is therefore advantageous in terms of cost.

[0005] The structure of a conventional silicon carbide semiconductor device will be described using a trench-type SiC-MOSFET as an example. + The front surface of the silicon carbide substrate 1 (see FIG. 1 for the reference numerals) is - A silicon carbide epitaxial layer 2 is deposited. - n type silicon carbide epitaxial layer 2 + On the surface side opposite to the silicon carbide substrate 1 side, an n-type heavily doped region 5 is provided. In the n-type heavily doped region 5, a second p + A mold base region 4 is optionally provided.

[0006] The MOS gate of the trench gate structure is made up of a p-type base layer 6, an n + Type source region 7, p + The semiconductor device is composed of a contact region 8, a trench 16, a gate insulating film 9, and a gate electrode 10. + The mold contact region 8 may not be provided.

[0007] In a MOS gate having a trench gate structure, a method for manufacturing a gate insulating film 9 involves first depositing an oxide film by a chemical reaction (chemical vapor deposition) such as thermal oxidation at a temperature of about 1000°C or high temperature oxidation (High Temperature Oxide: HTO) in an oxygen atmosphere.

[0008] In trench-type SiC-MOSFETs, the state of the interface between the oxide film (SiO2) and silicon carbide (SiC) affects device characteristics. Thermally oxidized films are excellent SiO2 films, but when SiC is oxidized, excess carbon (C) is generated, which has a negative effect on the SiO2 / SiC interface and causes deterioration of device characteristics. For this reason, deposited SiO2 films are sometimes used. However, deposited SiO2 films formed by, for example, plasma CVD (Chemical Vapor Deposition) or sputtering are not suitable for practical use because they do not have sufficient film density or insulating performance.

[0009] Furthermore, it is preferable that the thickness of the gate insulating film 9 is uniform throughout the trench 16, and deposited SiO2 films formed by plasma CVD or sputtering have problems such as different film thicknesses at the bottom and sidewalls of the trench 16, and even on the sidewalls they tend to be thicker closer to the opening of the trench 16. For this reason, SiO2 films deposited by HTO are usually used as the gate insulating film 9 for trench-type SiC-MOSFETs, as they have a uniform thickness and relatively good film quality.

[0010] Next, the oxide film is annealed. When formed by thermal oxidation, a heat treatment (POA (Post Oxidation Anneal) treatment) may be performed to reduce the interface state density at the interface between the oxide film and the semiconductor portion. When the oxide film is formed by a deposition method such as HTO, post-annealing is generally performed using a gas containing nitrogen (N2) after HTO formation to improve electrical characteristics (mobility, etc.). For example, NO annealing is performed at a temperature of 1300°C using 10% NO / N2 gas for about 30 minutes. This forms the gate insulating film 9.

[0011] However, when a silicon carbide substrate is thermally oxidized to form an oxide film, some of the carbon in the silicon carbide substrate cannot be sublimated and remains in the oxide film. In particular, the carbon remaining in the oxide film within a range of several nanometers from the interface between the silicon carbide substrate and the oxide film is thought to contribute to the generation of charge traps. Such charge traps are thought to cause fluctuations in the threshold voltage when a positive bias is applied to the gate electrode.

[0012] For this reason, a method is known in which thermal oxidation is performed in a nitrogen atmosphere containing nitric oxide (NO) gas before depositing an oxide film (see, for example, Patent Document 1 below). In this manufacturing method, first, NO annealing is performed at a temperature of 1300°C in 10% NO / N2 gas for about 30 minutes. Next, a deposition film is formed on the surface of the oxide film using a CVD method. The gate insulating film formed in this way has effectively suppressed carbon residue and effectively reduces charge traps in the oxide film.

[0013] Also known is a method that includes a nitriding step in which the surface of a silicon carbide substrate is passivated with nitrogen in a nitric oxide or dinitrogen monoxide gas atmosphere at a temperature of 900°C to 1450°C for a treatment time of 30 minutes to 6 hours, a step in which an insulating film is formed on the nitrided silicon carbide substrate surface by vapor phase growth, and a step in which the insulating film is heat-treated in a nitric oxide or dinitrogen monoxide gas atmosphere, and a nitriding step is performed before and after the formation of a gate insulating film (see, for example, Patent Document 2 below).

[0014] Also known is a method in which post-deposition annealing (PDA) is performed in a nitrogen atmosphere containing about 10% nitric oxide (90% N2 + 10% NO) (see, for example, Patent Document 3 below). [Prior art documents] [Patent documents]

[0015] [Patent Document 1] Japanese Patent Application Publication No. 2019-145570 [Patent Document 2] Patent No. 4549167 [Patent Document 3] Patent No. 6773198 Summary of the Invention [Problem to be solved by the invention]

[0016] However, while HTO can form a deposited SiO2 film, it introduces a gas containing oxygen (NO) into the source gas, which oxidizes the SiC for a moment at the beginning of deposition, causing a small amount of excess C (carbon clusters) to precipitate. When a gate insulating film is formed using HTO, the SiC in the interface region is oxidized very thinly, generating excess C at the SiO2 / SiC interface. Furthermore, the oxidation in this area causes crystal disorder at the SiO2 / SiC interface.

[0017] Although this varies somewhat depending on the HTO equipment and deposition conditions, it is generally impossible to completely prevent initial oxidation during film formation. In the conventional method of sequentially performing HTO and NO processes, the SiC surface is oxidized by approximately 2 nm during HTO deposition. Furthermore, the subsequent NO annealing process causes O to reach the interface, further oxidizing the SiC, increasing the amount of oxidation. Furthermore, analysis has shown that the process described in Reference 1, in which NO annealing is performed first and then NO / HTO, oxidizes the surface by approximately 5 nm during the initial NO annealing. In trench MOSFETs, the current flowing through the channel is thought to extend approximately 2–5 nm from the surface of the trench sidewall. While the initial oxidation during HTO deposition is approximately 2 nm, the initial NO annealing process results in approximately 5 nm of oxidation. This means that current flows through areas with crystal damage, affecting device performance. Therefore, to further improve device performance, it is important to prevent oxidation of the SiC on the trench sidewall where the channel will form. Since oxidation cannot be completely suppressed, minimizing excess C at the SiO2 / SiC interface and in the HTO film is essential for improving electrical characteristics.

[0018] Furthermore, since nitriding the interface to an appropriate amount is effective in improving characteristics, a manufacturing process that reduces nitrogen loss from the interface is important. When NO annealing is performed after HTO, the results in Figure 3, which will be explained below, show that nitrogen is lost near the oxide film surface on the opposite side of the HTO film from the SiC. As such, it is difficult to distribute nitrogen uniformly throughout the oxide film. In addition, the above-mentioned HTO / NO composition causes a phenomenon in which leakage current increases in the low electric field region during time-zero dielectric breakdown (TZDB) durability testing, posing a reliability problem.

[0019] In addition, in the conventional method of processing in the order of 10% NO / HTO / 10% NO, nitrogen is distributed uniformly in the HTO film, but the SiC interface is oxidized in the first NO anneal, which may increase the interface state at the SiO2 / SiC interface.

[0020] In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device that can reduce disturbance and damage to the SiO / SiC interface, uniformly nitride the SiO film, and improve device characteristics. [Means for solving the problem]

[0021] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. First, a first step is performed in which a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is formed on a front surface of a silicon carbide semiconductor substrate of a first conductivity type. Next, a second step is performed in which a second semiconductor layer of a second conductivity type is formed on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. Next, a third step is performed in which a first semiconductor region of a first conductivity type is selectively formed on a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. Next, a fourth step is performed in which a trench is formed through the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer. Next, a fifth step is performed in which a gate insulating film is formed inside the trench along the bottom and sidewalls of the trench. Next, a sixth step is performed in which a gate electrode is formed inside the trench and on the inside of the gate insulating film. Next, a seventh step is performed in which a first electrode is formed on surfaces of the first semiconductor region and the second semiconductor layer. Next, an eighth step is performed in which a second electrode is formed on the back surface of the silicon carbide semiconductor substrate. The fifth step includes a ninth step of performing a first nitridation heat treatment with a gas containing oxygen and nitrogen, a tenth step of depositing an oxide film after the ninth step, and an eleventh step of performing a second nitridation heat treatment with a gas containing nitric oxide and nitrogen after the tenth step, wherein the first nitridation heat treatment has a larger nitrogen content than the second nitridation heat treatment at the start of the treatment, and the second nitridation heat treatment has a larger nitrogen content than the first nitridation heat treatment at the end of the treatment.

[0022] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the first nitriding heat treatment is carried out using a gas containing 1 to 7% oxygen and the remaining 93 to 99% nitrogen.

[0023] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the second nitridation heat treatment is characterized in that at the start of the treatment, the gas is 10% nitric oxide and the remaining 90% is nitrogen, and the concentration of nitric oxide is gradually reduced until at the end of the treatment, the gas is 100% nitrogen.

[0024] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. A first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on a front surface of a silicon carbide semiconductor substrate of a first conductivity type. A second semiconductor layer of a second conductivity type is provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. A first semiconductor region of a first conductivity type is selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. A trench is provided that passes through the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer. A gate insulating film is provided inside the trench along a bottom and sidewalls of the trench. A gate electrode is provided inside the trench, inside the gate insulating film. A first electrode is provided on surfaces of the first semiconductor region and the second semiconductor layer. A second electrode is provided on a rear surface of the silicon carbide semiconductor substrate. The nitrogen concentration at the interface between the gate insulating film and the first semiconductor region and the second semiconductor layer is 1×10 20 atmos / cm 3 More than 1×10 21 atmos / cm 3 It has the following peaks: The mobility of silicon carbide semiconductor devices is 65cm 2 / V·s or more, and the threshold voltage is 5.2 V or more .

[0025] Further, in the silicon carbide semiconductor device according to the present invention, a concentration of nitrogen in the gate insulating film is 5×10 19atmos / cm 3 The present invention is characterized in that:

[0026] According to the above-described invention, by reducing the oxidizing partial pressure in the first nitridation heat treatment and suppressing additional oxidation at the interface in the second nitridation heat treatment, oxidation at the SiC interface is minimized, reducing damage (excess C, crystal disorder at the interface, etc.) caused by oxidation of SiC on the sidewalls of the trench where the channel is formed. Furthermore, by appropriately nitriding the interface between the gate insulating film and SiC, N can be uniformly distributed within the gate insulating film. This can improve device characteristics that deteriorate due to disorder or damage at the SiO2 / SiC interface. For example, it can improve threshold voltage without significantly reducing mobility. It can also reduce leakage current in the low electric field region during TZDB measurement. [Effects of the Invention]

[0027] According to the method for manufacturing a silicon carbide semiconductor device and the silicon carbide semiconductor device of the present invention, by changing the ratio of nitrogen gas to oxygen gas during annealing and reducing oxidation in the nitridation step, it is possible to reduce disturbance and damage to the SiO2 / SiC interface, achieve uniform nitridation within the SiO2 film, and improve device characteristics. [Brief explanation of the drawings]

[0028] [Figure 1] 1 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to an embodiment; [Figure 2] 1 is a flowchart showing a method for manufacturing a gate insulating film of a silicon carbide semiconductor device according to an embodiment. [Figure 3] 1 is a graph showing SIMS data of the vicinity of the gate insulating film formed by the conventional method and the method according to the embodiment. [Figure 4] 1 is a table showing threshold voltages and mobilities of silicon carbide semiconductor devices manufactured by conventional methods and methods according to the embodiment. [Figure 5] 10 is a graph showing a TZDB waveform of a silicon carbide semiconductor device manufactured by a conventional method. [Figure 6]10 is a graph showing a TZDB waveform of a silicon carbide semiconductor device manufactured by a method according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0029] Preferred embodiments of a silicon carbide semiconductor device and a method for manufacturing the same according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate higher and lower impurity concentrations than layers and regions without these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference symbols, and redundant explanations will be omitted. In this specification, in the notation of Miller indices, "-" refers to a bar attached to the index immediately following it, and adding "-" before an index indicates a negative index. It is preferable that the terms "same" or "equivalent" be used to include variations within 5% in consideration of variations in manufacturing.

[0030] (Embodiment) The semiconductor device according to the present invention is configured using a wide bandgap semiconductor. In the embodiment, a silicon carbide semiconductor device fabricated (manufactured) using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a trench MOSFET 70 as an example. Fig. 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the embodiment. Fig. 1 shows only the active region of the trench MOSFET 70 through which the main current flows.

[0031] As shown in FIG. 1, the silicon carbide semiconductor device according to the embodiment has n + A first main surface (front surface) of a silicon carbide substrate (silicon carbide semiconductor substrate of a first conductivity type) 1, for example, a (0001) surface (Si surface), is provided with an n - A silicon carbide epitaxial layer (first semiconductor layer of a first conductivity type) 2 is deposited on the silicon carbide epitaxial layer.

[0032] n +The silicon carbide substrate 1 is a silicon carbide single crystal substrate. - The silicon carbide epitaxial layer 2 is + The impurity concentration is lower than that of the silicon carbide substrate 1, and is, for example, a low-concentration n-type drift layer. - The n-type silicon carbide epitaxial layer 2 + An n-type heavily doped region 5 may be provided on the surface opposite to the silicon carbide substrate 1 side. + Lower n than silicon carbide substrate 1 - The n-type silicon carbide epitaxial layer 2 is a high-concentration n-type drift layer having a higher impurity concentration than the n-type silicon carbide epitaxial layer 2.

[0033] n - The n-type silicon carbide epitaxial layer 2 + On the surface opposite to the silicon carbide substrate 1 side, a p-type base layer (a second semiconductor layer of a second conductivity type) 6 is provided. + A silicon carbide substrate 1 and an n - The silicon carbide epitaxial layer 2, the n-type high concentration region 5, and the p-type base layer 6 are combined to form a silicon carbide semiconductor base (semiconductor substrate made of silicon carbide) 18.

[0034] n + A drain electrode serving as a back surface electrode 13 is provided on a second main surface (back surface, i.e., the back surface of the silicon carbide semiconductor base 18) of the silicon carbide substrate 1. A drain electrode pad (not shown) is provided on the surface of the back surface electrode 13.

[0035] A trench structure is formed on the first main surface side (p-type base layer 6 side) of the silicon carbide semiconductor substrate. Specifically, the trench 16 is formed between the n-type + The n-type heavily doped region 5 (or the n-type heavily doped region 5 when the n-type heavily doped region 5 is not provided) penetrates the p-type base layer 6 from the surface opposite to the silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor base). -The trench 16 has a silicon carbide epitaxial layer 2 (hereinafter simply referred to as (2)) extending therethrough. A gate insulating film 9 is formed on the bottom and sidewalls of the trench 16 along the inner wall thereof, and a gate electrode 10 is formed inside the gate insulating film 9 within the trench 16. The gate insulating film 9 insulates the gate electrode 10 from the n-type high concentration region 5 (2) and the p-type base layer 6. A portion of the gate electrode 10 may protrude from above the trench 16 (the side where the source electrode 12, described later, is provided) toward the source electrode 12. The gate insulating film 9 is preferably formed on an m-plane. For example, when a trench structure is formed, the sidewalls of the trench 16 are preferably m-planes.

[0036] n-type high concentration region 5(2) + The surface layer on the side opposite to the silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor base) has a first p + The n-type base region 3 is provided in the n-type high concentration region 5(2). + A mold base region 4 is provided. + The base region 4 is provided at a position facing the bottom of the trench 16 in the depth direction (the direction from the source electrode 12 to the back surface electrode 13). + The width of the mold base region 4 is equal to or wider than the width of the trench 16. The bottom of the trench 16 is the second p + The p-type base layer 6 and the second p-type base region 4 may be connected. + It may be located within the n-type high concentration region 5(2) sandwiched between the n-type base regions 4.

[0037] Also, n - In the silicon carbide epitaxial layer 2, a first p + The n-type high concentration region 5(2) has a peak impurity concentration higher than that of the n-type base region 3. + The mold region 17 is provided. + This refers to a position closer to the drain electrode 13 than the base region 3 .

[0038] Inside the p-type base layer 6, an n-type silicon carbide semiconductor substrate 18 is formed on the first main surface side. + A p-type source region (first semiconductor region of the first conductivity type) 7 is selectively provided. + The n-type contact region 8 may be selectively provided. + Type source region 7 and p + The mold contact regions 8 abut each other.

[0039] The interlayer insulating film 11 is provided on the entire first main surface side of the silicon carbide semiconductor substrate 18 so as to cover the gate electrode 10 embedded in the trench 16. The source electrode 12 is connected to the n-type semiconductor layer 14 via a contact hole opened in the interlayer insulating film 11. + The p-type source region 7 and the p-type base layer 6 are in contact with each other. + When the n-type contact region 8 is provided, the source electrode 12 is + Type source region 7 and p + The source electrode 12 is in contact with the gate electrode 10 through the interlayer insulating film 11. A source electrode pad (not shown) is provided on the source electrode 12. A barrier metal 14 may be provided between the source electrode 12 and the interlayer insulating film 11 to prevent diffusion of metal atoms from the source electrode 12 toward the gate electrode 10, for example.

[0040] (Method for manufacturing silicon carbide semiconductor device according to embodiment) Next, a method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. First, an n-type silicon carbide semiconductor device is formed. + A silicon carbide substrate 1 is prepared. + On the first main surface of the silicon carbide substrate 1, a lower n-type impurity, for example, a nitrogen atom (N), is doped and formed. - A silicon carbide epitaxial layer (not shown) is epitaxially grown to a thickness of, for example, about 30 μm.

[0041] Next, the bottom n -On the surface of the silicon carbide epitaxial layer, a mask (not shown) having a desired opening is formed by photolithography, for example, from an oxide film. Then, using this oxide film as a mask, n-type impurities, for example, nitrogen atoms, may be implanted by ion implantation. This results in the formation of a lower n - Inside the silicon carbide epitaxial layer, + A mold area 17 is formed.

[0042] Next, n + The mask used for ion implantation to form the silicon-doped region 17 is removed. Next, a mask for ion implantation having predetermined openings is formed using, for example, an oxide film by photolithography. Then, p-type impurities such as aluminum are implanted into the openings in the oxide film to form a lower first p-type region having a depth of about 0.5 μm. + A mold base region (not shown) and a second p + Forming the mold base region 4. + When the type region 17 is formed, n + n in type region 17 + On the surface opposite to the silicon carbide substrate 1, a lower first p + Let the type base region be n + It is formed so as to overlap the mold region 17 .

[0043] Next, a part of the ion implantation mask is removed, and n-type impurities such as nitrogen are ion-implanted into the opening. - A lower n-type heavily doped region (not shown) having a depth of, for example, about 0.5 μm may be formed in a part of the surface region of the silicon carbide epitaxial layer. The impurity concentration of the lower n-type heavily doped region is, for example, 1×10 17 / cm 3 Set it to a certain extent.

[0044] Next, the bottom n - On the surface of the silicon carbide epitaxial layer, an upper n-type layer is formed by doping n-type impurities such as nitrogen. - A silicon carbide epitaxial layer (not shown) is formed to a thickness of about 0.5 μm. - The impurity concentration of the silicon carbide epitaxial layer is 3×10 15 / cm 3The lower n - Silicon carbide epitaxial layer and top n - The combination of the silicon carbide epitaxial layer and the n-type silicon carbide epitaxial layer - This results in a silicon carbide epitaxial layer 2 .

[0045] Next, the upper n - An ion implantation mask having predetermined openings is formed on the surface of the silicon carbide epitaxial layer by photolithography, using, for example, an oxide film. Then, p-type impurities such as aluminum are implanted into the openings in the oxide film to form an upper first p-type impurity layer having a depth of about 0.5 μm. + The mold base region (not shown) is + The upper first p is formed so as to overlap the mold base region. + Mold base region and lower first p + The mold base region forms a continuous region, and the first p + This becomes the mold base region 3. + The impurity concentration of the base region is set to, for example, 5×10 18 / cm 3 Set it to about this extent.

[0046] Next, a part of the ion implantation mask is removed, and n-type impurities such as nitrogen are ion-implanted into the opening. - An upper n-type heavily doped region (not shown) having a depth of, for example, about 0.5 μm may be formed in a part of the surface region of the silicon carbide epitaxial layer 2. The impurity concentration of the upper n-type heavily doped region is, for example, 1×10 17 / cm 3 The upper n-type heavily doped region and the lower n-type heavily doped region are formed so that at least a portion of them are in contact with each other, forming the n-type heavily doped region 5. However, the n-type heavily doped region 5 may or may not be formed over the entire surface of the substrate.

[0047] Next, n - A p-type base layer 6 is formed by epitaxial growth on the surface of the silicon carbide epitaxial layer 2 to a thickness of about 1.1 μm. The impurity concentration of the p-type base layer 6 is 4×10 17 / cm 3After the p-type base layer 6 is formed by epitaxial growth, p-type impurities such as aluminum may be further ion-implanted into the p-type base layer 6.

[0048] Next, a predetermined region that constitutes a MOS gate is formed on the first main surface layer (surface layer of the p-type base layer 6) of the silicon carbide semiconductor substrate 18. Specifically, an ion implantation mask having a predetermined opening is formed on the surface of the p-type base layer 6 by photolithography, using, for example, an oxide film. N-type impurities such as nitrogen (N) and phosphorus (P) are ion-implanted into this opening, and n-type impurities are implanted into a portion of the surface of the p-type base layer 6. + Next, the n-type source region 7 is formed. + The ion implantation mask used for forming the p-type source region 7 is removed, and a new ion implantation mask having a predetermined opening is formed in the same manner. P-type impurities such as boron are ion-implanted into a portion of the surface of the p-type base layer 6, forming p + A contact region 8 may be formed. + The impurity concentration of the p-type contact region 8 is set to be higher than the impurity concentration of the p-type base layer 6.

[0049] Next, a heat treatment (activation annealing) is performed to activate the entire region formed by ion implantation. For example, the heat treatment (annealing) is performed in an inert gas atmosphere at about 1700° C., and the first p + Mold base region 3, second p + Type base region 4, n + Type source region 7, p + type contact region 8 and n + An activation process is carried out on the mold region 17. As described above, the ion implantation regions may be activated all at once by a single heat treatment, or activation may be carried out by performing a heat treatment each time an ion implantation is carried out.

[0050] Next, a trench forming mask having a predetermined opening is formed on the surface of the p-type base layer 6 by photolithography, using, for example, an oxide film. Next, a trench 16 is formed by dry etching, penetrating the p-type base layer 6 and reaching the n-type high concentration region 5(2). The bottom of the trench 16 is connected to the second p-type high concentration region 5(2) formed in the n-type high concentration region 5(2). + The trench formation mask may reach the mold base region 4. Next, the trench formation mask is removed. Next, the front surface of the silicon carbide semiconductor substrate 18 is subjected to, for example, RCA cleaning (wet cleaning using a strong acid and a strong base solution).

[0051] Next, n + A gate insulating film 9 is formed on the surface of the source region 7 and along the bottom and sidewall of the trench 16. A method for manufacturing the gate insulating film 9 according to the embodiment will be described in detail below. FIG. 2 is a flowchart showing a method for manufacturing the gate insulating film of the silicon carbide semiconductor device according to the embodiment. In the embodiment, the semiconductor layer (first p + a base region 3, an n-type high concentration region 5, a p-type base layer 6, and an n + The front surface of the source region 7) is defined as the m-plane.

[0052] First, the front surface of the silicon carbide layer is subjected to a first nitridation heat treatment using a gas containing O2 (oxygen) and N2 (nitrogen) (step S1: 9th process). The first nitridation heat treatment is performed at a temperature of 1200°C to 1300°C in a 1-7% O2 / remainder N2 gas (1-7% O2 and 93-99% N2, hereinafter the same) for 5 to 10 minutes. This nitrides and thermally oxidizes the front surface of the silicon carbide layer, forming a nitride film and an oxide film. By using a lower oxygen ratio than conventional methods for the first nitridation heat treatment, the amount of oxidation (film thickness) during nitridation and oxidation of the SiC trench sidewalls is minimized, minimizing damage to the SiC surface due to oxidation (excess carbon, crystal disorder at the interface, etc.). The oxide film formed by this thermal oxidation is a high-density, high-quality SiO2 film.

[0053] Next, an oxide film is deposited by HTO (Step S2: 10th process). HTO is performed by introducing dichlorosilane (DCS) and N2O at 800°C. Monosilane (SiH4) may be used instead of DCS. In this case, the temperature is raised to 600°C in the furnace and the chamber is evacuated to a vacuum over a period of about one hour. This forms an oxide film with a thickness of 60 nm to 80 nm.

[0054] Next, a second nitriding heat treatment is performed using a gas containing NO (nitric oxide) and N2 (step S3: 11th process). The second nitriding heat treatment begins at a temperature of 1300°C or higher but lower than 1330°C, with a 10% NO / 90% N2 gas mixture. The N2 concentration is gradually increased during annealing, and the treatment is finally completed with 100% N2 gas. This treatment is performed for 5 to 10 minutes. This 100% N2 concentration does not have to be strictly 100%, and may contain a very small amount of NO. Thus, in this embodiment, the first nitriding heat treatment has a higher nitrogen content at the start of treatment, and the second nitriding heat treatment has a higher nitrogen content at the end of treatment.

[0055] Because the HTO in step S2 removes N from the surface of the SiC / SiO2 nitrided in the first nitridation heat treatment, a second nitridation heat treatment is performed to deposit N again at the interface. By performing the second nitridation heat treatment at a higher temperature than the first nitridation heat treatment, the interface can be sufficiently nitrided again, and the interface between the gate insulating film 9 and SiC can be nitrided to an appropriate degree. To minimize additional oxidation at the SiC interface, it is preferable that the total heat treatment time for the first and second nitridation heat treatments be shorter than the time for nitridation heat treatment performed after conventional oxide film deposition. This results in the formation of the gate insulating film 9.

[0056] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the trench 16. This polycrystalline silicon layer is patterned by photolithography and left inside the trench 16 to form the gate electrode 10.

[0057] Next, for example, phosphorus glass is deposited to a thickness of about 1 μm to cover the gate insulating film 9 and the gate electrode 10, forming an interlayer insulating film 11. Next, a barrier metal 14 made of titanium (Ti) or titanium nitride (TiN) may be formed to cover the interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating film 9 are patterned by photolithography. + Type source region 7 and p + A contact hole is formed to expose the mold contact region 8. Thereafter, a heat treatment (reflow) is performed to flatten the interlayer insulating film 11.

[0058] Next, the interlayer insulating film 11 is selectively removed, and a nickel (Ni) or Ti film is formed on the surface of the silicon carbide semiconductor substrate 18. Next, the surface is protected and n + A Ni or Ti film is formed on the back surface of the silicon carbide substrate 1. Next, a heat treatment at about 1000° C. is performed to bond the front surface of the silicon carbide semiconductor base 18 and the n-type silicon carbide semiconductor base 18 to each other. + An ohmic electrode is formed on the surface side of the back surface of the silicon carbide substrate 1 .

[0059] Next, a conductive film that will become the source electrode 12 is provided on the interlayer insulating film 11 so as to contact the ohmic electrode portion formed in the contact hole, and n + Type source region 7 and p + The mold contact region 8 is brought into contact with the source electrode 12 .

[0060] Then, n + A back electrode 13 made of, for example, a nickel (Ni) film is formed on the second main surface of the silicon carbide substrate 1. After that, a heat treatment is performed at a temperature of, for example, about 970° C. to form an n + The silicon carbide substrate 1 and the back surface electrode 13 are ohmic-contacted.

[0061] Next, an electrode pad to become a source electrode pad (not shown) is deposited on the source electrode 12 on the front surface of the silicon carbide semiconductor substrate 18 and in the opening of the interlayer insulating film 11 by, for example, sputtering. The thickness of the portion of the electrode pad on the interlayer insulating film 11 may be, for example, 5 μm. The electrode pad may be made of, for example, aluminum containing 1% silicon (Al-Si). Next, the source electrode pad is selectively removed.

[0062] Next, a drain electrode pad (not shown) made of, for example, titanium (Ti), nickel (Ni), and gold (Au) is deposited in this order on the surface of back surface electrode 13. In this manner, the silicon carbide semiconductor device shown in FIG.

[0063] As described above, in this embodiment, the gate insulating film 9 is formed through three steps: a first nitridation heat treatment using a mixed gas of N2 and O2, oxide film deposition, and a second nitridation heat treatment in which the mixture ratio of NO and N2 is changed over time. By using a mixed gas of nitrogen and oxygen in the first nitridation heat treatment, the oxidizing partial pressure can be reduced as much as possible. By gradually reducing the concentration of nitric oxide from the beginning to the end of the second nitridation heat treatment, the initial NO diffuses nitrogen into the HTO, uniformly nitriding the HTO film, including the interface, while minimizing oxidation of the interface.

[0064] 3 is a graph showing SIMS data of the vicinity of the gate insulating film formed by the conventional method, the method according to the embodiment, and the method formed by annealing at 1250° C. in 100% nitrogen after HTO deposition. In FIG. 3, the vertical axis represents the nitrogen concentration, and the unit is atoms / cm. 3 The horizontal axis indicates the depth from the surface of the gate insulating film 9, and the unit is nm. Here, the area around the depth of 50 nm is the area between the gate insulating film 9 and the silicon carbide layer (the n-type high concentration region 5(2), the p-type base layer 6, the n + This forms the interface with the source region 7, etc.

[0065] As shown in Figure 3, in the gate insulating film formed by the conventional HTO film deposition / NO annealing sequence (thin line in Figure 3), the nitrogen concentration at the interface is 7 × 10 20atmos / cm 3 The results of SIMS analysis reveal that the N concentration is high at the interface, while it is low on the surface side of the HTO (opposite side of the SiC). Furthermore, in the gate insulating film formed by the HTO / N2 treatment sequence (dotted line in Figure 3), N is uniformly present in the SiO2. Meanwhile, the nitrogen concentration at the interface is lower than the concentration in the SiO2.

[0066] For this reason, in the embodiment, the second NO annealing is performed to increase the N concentration at the interface. Also, based on the results of HTO / N2, the N2 concentration is increased over time, and the N2 annealing is performed to increase the N concentration on the surface side of the HTO. As a result, in the embodiment (thick line in Figure 3), N is less likely to escape, and the N concentration in the HTO film is almost uniform in the depth direction, gradually increasing toward the surface, reaching 5 x 10 19 atmos / cm 3 The N concentration at the interface is 1×10 20 atmos / cm 3 More than 1×10 21 atmos / cm 3 The following peaks are observed. In the second nitriding heat treatment process, the initial concentration is 10% NO and 90% N2, but the N2 concentration increases over time, eventually reaching 100% N2. From the results of HTO / N2 (dotted line in Figure 3) in Figure 3, it can be seen that nitriding is not performed at the interface during N2 annealing, and therefore N2 does not reach the interface. For this reason, oxidation by NO is suppressed in this embodiment.

[0067] 4 is a table showing the threshold voltage and mobility of silicon carbide semiconductor devices manufactured by the conventional method and the method of the embodiment. As shown in FIG. 4, the silicon carbide semiconductor device of the embodiment has a mobility that is about 25% higher and a threshold voltage that is 44% higher than the conventional silicon carbide semiconductor device formed in the order of 10% NO annealing / HTO film formation / 10% NO annealing. In this way, the embodiment improves the trade-off relationship between mobility and threshold voltage.

[0068] FIG. 5 is a graph showing the TZDB waveform of a silicon carbide semiconductor device manufactured by a conventional method. FIG. 5 shows the TZDB waveform of a silicon carbide semiconductor device in which a gate insulating film is formed in the conventional order of HTO film formation / NO annealing. FIG. 6 is a graph showing the TZDB waveform of a silicon carbide semiconductor device manufactured by the method of the embodiment. In FIGS. 5 and 6, the vertical axis represents gate current Ig in A. The horizontal axis represents gate voltage Vg in V. As shown in FIGS. 5 and 6, the conventional TZDB waveform exhibits a phenomenon in which leakage current increases around 20V to 40V, but in the embodiment, the leakage current is reduced between 20V and 40V. In addition, in the embodiment, variation in the TZDB waveform is reduced.

[0069] As described above, according to the embodiment, by reducing the oxidizing partial pressure in the first nitridation heat treatment and suppressing additional oxidation of the interface in the second nitridation heat treatment, oxidation of the SiC interface can be minimized, reducing damage (excess C, crystal disorder at the interface, etc.) caused by oxidation of SiC on the sidewall of the trench where the channel is formed. Furthermore, by appropriately nitriding the interface between the gate insulating film and SiC, N can be uniformly distributed within the gate insulating film. This can improve device characteristics that deteriorate due to disorder or damage at the SiO2 / SiC interface. For example, it is possible to improve the threshold voltage without reducing mobility as much as possible. Furthermore, it is possible to reduce leakage current in the low electric field region during TZDB measurement.

[0070] The present invention can be modified in various ways without departing from the spirit of the present invention. In each of the above-described embodiments, for example, the dimensions of each component and the impurity concentration are variously set according to the required specifications. Furthermore, while each of the above-described embodiments has been described using silicon carbide as the wide bandgap semiconductor, the present invention can also be applied to wide bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). Furthermore, the present invention can also be applied to semiconductors other than wide bandgap semiconductors, such as silicon (Si) and germanium (Ge). Furthermore, while each of the embodiments describes the first conductivity type as n-type and the second conductivity type as p-type, the present invention is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0071] INDUSTRIAL APPLICABILITY As described above, the method for manufacturing a silicon carbide semiconductor device and the silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, automobile igniters, etc. [Explanation of symbols]

[0072] 1n + Silicon carbide substrate 2n - Silicon carbide epitaxial layer 3 1st p. + Type-based domain 4 2nd p. + Type-based domain 5 n-type high concentration region 6 p-type base layer 7n + Type Source Area 8 p + Mold contact area 9 Gate insulating film 10 gate electrode 11 Interlayer insulating film 12 Source electrode 13 Back electrode 14 Barrier Metal 16 Trench 17n + type area 18 Silicon carbide semiconductor substrate 70 Trench MOSFET

Claims

1. a first step of forming a first semiconductor layer of a first conductivity type on a front surface of a silicon carbide semiconductor substrate, the first semiconductor layer having an impurity concentration lower than that of the silicon carbide semiconductor substrate; a second step of forming a second semiconductor layer of a second conductivity type on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; a third step of selectively forming a first semiconductor region of a first conductivity type in a surface layer of the second semiconductor layer on a side opposite to the silicon carbide semiconductor substrate; a fourth step of forming a trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer; a fifth step of forming a gate insulating film inside the trench along the bottom and sidewalls of the trench; a sixth step of forming a gate electrode inside the trench and on the inner side of the gate insulating film; a seventh step of forming a first electrode on surfaces of the first semiconductor region and the second semiconductor layer; an eighth step of forming a second electrode on a back surface of the silicon carbide semiconductor substrate; Including, The fifth step is a ninth step of performing a first nitriding heat treatment using a gas containing oxygen and nitrogen; a tenth step of depositing an oxide film after the ninth step; an eleventh step of performing a second nitriding heat treatment using a gas containing nitric oxide and nitrogen after the tenth step; wherein at the start of the treatment, the first nitriding heat treatment has a larger amount of nitrogen than the second nitriding heat treatment, and at the end of the treatment, the second nitriding heat treatment has a larger amount of nitrogen than the first nitriding heat treatment.

2. 2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the first nitriding heat treatment is performed using a gas containing 1 to 7% oxygen and the remaining 93 to 99% nitrogen.

3. 3. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the second nitriding heat treatment starts with a gas that is 10% nitric oxide and 90% nitrogen, and gradually reduces the concentration of nitric oxide until the gas is 100% nitrogen at the end of the treatment.

4. a silicon carbide semiconductor substrate of a first conductivity type; a first semiconductor layer of a first conductivity type provided on a front surface of the silicon carbide semiconductor substrate and having a lower impurity concentration than the silicon carbide semiconductor substrate; a second semiconductor layer of a second conductivity type provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer on a side opposite to the silicon carbide semiconductor substrate; a trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer; a gate insulating film provided inside the trench along the bottom and sidewalls of the trench; a gate electrode provided inside the trench and on the inner side of the gate insulating film; a first electrode provided on the surfaces of the first semiconductor region and the second semiconductor layer; a second electrode provided on a back surface of the silicon carbide semiconductor substrate; Equipped with The concentration of nitrogen at the interface between the gate insulating film and the first semiconductor region and the second semiconductor layer is 1×10 20 atmospheres / cm 3 1x10 or more 21 atmospheres / cm 3 It has the following peaks: The mobility is 65 cm 2 / V·s or more, A silicon carbide semiconductor device having a threshold voltage of 5.2 V or more.

5. The concentration of nitrogen in the gate insulating film is 5×10 19 atmospheres / cm 3 5. The silicon carbide semiconductor device according to claim 4, wherein:

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