Semiconductor Devices

Abstract

To avoid a competition between a power supply line and a wiring of a power supply switch circuit in the case where the power supply line is formed by using a wiring layer that is close to a substrate.SOLUTION: A semiconductor device includes: first and second local wirings that are crossed to a plurality of fins of a transistor of a first power supply switching circuit, and are extended to a second direction; first and second power supply lines that are formed in a first wiring layer, and is extended to a first direction; a third power supply line connected to the first power supply line and a fourth power supply line connected to the second power supply line that are formed to a second wiring layer, and are extended to the second direction; a fifth power supply line that is formed to the first wiring layer, and is connected to a plurality of second local wirings; a first wiring that is formed to the second wiring layer, is connected to a fifth power supply line, is extended to the second direction, is overlapped to a transistor, and is not overlapped with the third and fourth power supply lines in a plan view; and a second wiring that is formed to a second wiring layer, is electrically connected to the third power supply line, is extended to the second direction, is overlapped with the transistor, and is not overlapped with the third and fourth power supply lines in the plan view.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] In order to reduce leakage current in a semiconductor device, a known technique is to provide a power switch circuit that turns on when a circuit block is operating between a power line and a virtual power line, which is the power line for each of a plurality of circuit blocks. For example, in order to increase the power supply capacity of the power switch circuit, the size of the transistors used in the power switch circuit is designed to be larger than the size of the cell transistors used in the logic circuits in the circuit blocks. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,141,336 [Patent Document 2] US Patent Application Publication No. 2019 / 0244900 [Patent Document 3] US Patent Application Publication No. 2019 / 0214377 [Patent Document 4] Japanese Patent Application Publication No. 2018-190760 [Patent Document 5] International Publication No. 2017 / 208887 Summary of the Invention [Problem to be solved by the invention]

[0004] As the transistor size increases, the layout size of the power switch circuit increases, and the power switch circuit no longer fits between the power wirings arranged at a predetermined pitch. In this case, the power switch circuit is arranged across the power wirings arranged at a predetermined pitch. In addition, in order to supply a sufficient power supply voltage to the circuit block that operates using the virtual power supply voltage, it is preferable that the virtual power line wired between the power switch circuit and the circuit block be formed using a metal wiring layer close to the semiconductor substrate.

[0005] However, when the virtual power line wired between the power switch circuit and the circuit block is formed using a metal wiring layer close to the semiconductor substrate, there is a risk that the wiring formed in the power switch circuit using the metal wiring layer close to the semiconductor substrate will compete with the virtual power line.

[0006] The present invention has been made in consideration of the above points, and aims to avoid conflict with wiring in a power switch circuit that is arranged in the same layer as the power line when the power line, such as a virtual power line, is formed using a metal wiring layer close to a semiconductor substrate. [Means for solving the problem]

[0007] In one aspect of the present invention, a semiconductor device includes a substrate; a plurality of fins formed on the substrate, extending in a first direction in a plan view, and arranged side by side in a second direction different from the first direction in a plan view; a plurality of first local wirings and a plurality of second local wirings formed on the plurality of fins, each extending in the second direction, and arranged alternately in the first direction; a plurality of gate electrodes formed on the plurality of fins, each extending in the second direction, and each arranged between the first local wirings and the second local wirings; a first power supply line formed in a first wiring layer above the second local wiring, extending in the first direction in a plan view, to which a first voltage is supplied, and electrically connected to the plurality of first local wirings; a second power supply line formed in the first wiring layer, extending in the first direction, and to which a second voltage is supplied; a third power supply line formed in a second wiring layer that is one wiring layer above the first wiring layer, extending in a second direction different from the first direction in a plan view, connected to the first power supply line, and to which the first voltage is supplied; and a third power supply line formed in the second wiring layer, extending in the second direction, and connected to the second local wirings. a fourth power supply line connected to a power supply line and supplied with the second voltage; a fifth power supply line formed in the first wiring layer, supplied with a third voltage, and electrically connected to the plurality of second local wirings; the plurality of gate electrodes; a plurality of source regions formed in the plurality of fins and connected to the plurality of second local wirings, respectively; and a plurality of drain regions formed in the plurality of fins and connected to the plurality of first local wirings, the transistor being positioned so as to overlap at least either the third power supply line or the fourth power supply line in a plan view; a first power supply switch circuit having the transistor; a first wiring formed in the second wiring layer, electrically connected to the fifth power supply line, extending in the second direction, overlapping with the transistor in a planar view, not overlapping with the third power supply line and the fourth power supply line in a planar view, and to which the third voltage is supplied; and a second wiring formed in the second wiring layer, electrically connected to the third power supply line, extending in the second direction, overlapping with the transistor in a planar view, not overlapping with the third power supply line and the fourth power supply line in a planar view, and to which the first voltage is supplied. [Effects of the Invention]

[0008] According to the disclosed technique, when the first power supply line is formed using a metal wiring layer close to the semiconductor substrate, it is possible to avoid competition between the first power supply line and the wiring in the power switch circuit. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 is a diagram illustrating an example of a layout of the semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of a power switch circuit in FIG. [Figure 3] 3 is a diagram showing an example of a layout of power supply wiring of the power switch circuit of FIG. 2. FIG. [Figure 4] FIG. 4 is a diagram showing a layout in which the wiring on the M1 layer and the vias between the M0 and M1 layers are removed from the layout of FIG. [Figure 5] FIG. 5 is a perspective view showing an example of the structure of the p-channel transistor of FIGS. 3 and 4. [Figure 6] FIG. 4 is a cross-sectional view taken along line Y1-Y1′ in FIG. 3. [Figure 7] FIG. 10 is a diagram showing an example of a layout of power supply wiring of a power switch circuit of a semiconductor device according to a second embodiment. [Figure 8] FIG. 10 is a diagram showing an example of a layout of power supply wiring of a power switch circuit of a semiconductor device according to a third embodiment. [Figure 9] FIG. 10 is a diagram showing an example of a layout of power supply wiring of a power switch circuit of a semiconductor device according to a fourth embodiment. [Figure 10] FIG. 13 is a diagram showing an example of a layout of a semiconductor device according to a fifth embodiment. [Figure 11] FIG. 13 is a diagram showing an example of a layout of a semiconductor device according to a sixth embodiment. [Figure 12] 12 is a diagram showing an example of the layout of power supply wiring of the power switch circuit PSW2 of FIG. 11. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment will be described with reference to the drawings.

[0011] (First embodiment) FIG. 1 shows an example of a layout of a semiconductor device according to the first embodiment. The semiconductor device 100 shown in FIG. 1 has, for example, at least one power domain PD. Within the power domain PD, a standard cell area SCA is provided in which a plurality of standard cells (not shown) are arranged. Although not limited to this, the transistors mounted on the semiconductor device 100 are finFETs. FinFETs will be described with reference to FIG. 5. The standard cell area SCA is an example of a first area in which a logic circuit can be arranged.

[0012] An end cap ECAP, indicated by a hatched pattern, is disposed around the standard cell area SCA. The end cap ECAP has a dummy gate electrode or a dummy transistor (not shown). In addition, in the standard cell area SCA, virtual power supply lines VVDD01b and ground lines VSS01c extending in the X direction (the horizontal direction in FIG. 1) are alternately disposed at intervals H1 in the Y direction (the vertical direction in FIG. 1). The X direction is an example of a first direction, and the Y direction is an example of a second direction intersecting the X direction.

[0013] Furthermore, in the standard cell area SCA, virtual power supply lines VVDD11b and ground lines VSS11c extending in the Y direction are alternately arranged at intervals W1 in the X direction. In Fig. 1, the virtual power supply lines VVDD01b and VVDD11b are indicated by solid lines, and the ground lines VSS01c and VSS11c are indicated by dashed lines.

[0014] For example, the virtual power supply line VVDD01b and ground line VSS01c extending in the X direction are formed using the M0 layer, which is the metal wiring layer closest to the semiconductor substrate. The virtual power supply line VVDD11b and ground line VSS11c extending in the Y direction are formed using the M1 layer, which is a metal wiring layer provided immediately above the M0 layer. The M0 layer is an example of a first wiring layer, and the M1 layer is an example of a second wiring layer. The virtual power supply line VVDD01b is an example of a first power supply line, and the ground line VSS01c is an example of a second power supply line. The virtual power supply line VVDD11b is an example of a third power supply line, and the ground line VSS11c is an example of a fourth power supply line.

[0015] When describing the power supply line VDD without distinguishing between wiring layers, etc., it is simply referred to as the power supply line VDD or wiring VDD. When describing the virtual power supply line VVDD without distinguishing between wiring layers, etc., it is simply referred to as the virtual power supply line VVDD or wiring VVDD. When describing the ground line VSS without distinguishing between wiring layers, etc., it is simply referred to as the ground line VSS or power supply line VSS.

[0016] The virtual power lines VVDD01b and VVDD11b, which extend in the X and Y directions, respectively, are connected to each other through vias at their intersections. Similarly, the ground lines VSS01c and VSS11c, which extend in the X and Y directions, respectively, are connected to each other through vias at their intersections. Furthermore, mesh-shaped virtual power lines VVDD and mesh-shaped ground lines VSS are provided in the standard cell area SCA. A power line VDD (not shown) that supplies power to the virtual power line VVDD is provided using multiple wiring layers above the M1 layer. The power line VDD is an example of a third power line.

[0017] In the standard cell area SCA, a plurality of power switch circuits PSW1 are arranged at intervals. For example, each power switch circuit PSW1 is designed to have a layout size that allows it to be arranged in an area surrounded by two virtual power lines VVDD01b extending in the X direction and two ground lines VSS11c extending in the Y direction.

[0018] In other words, each power switch circuit PSW1 is a double-height cell (two-height cell) arranged between two virtual power lines VVDD01b extending in the X direction, straddling one ground line VSS01c arranged between two virtual power lines VVDD01b extending in the X direction. Also, each power switch circuit PSW1 is arranged between two ground lines VSS11c extending in the Y direction, for example, straddling one virtual power line VVDD11b arranged between two ground lines VSS11c extending in the Y direction. Note that no standard cells are arranged in the area where the power switch circuit PSW1 is arranged.

[0019] By designing the power switch circuit PSW1 to be larger than the interval H1 and the interval W1, the ability of each power switch circuit PSW1 to supply the power supply voltage VVDD to the standard cells can be increased. However, if the size of the power switch circuit PSW1 in the X direction is designed to be larger than the interval W1, the power switch circuit PSW1 will overlap with the virtual power line VVDD11b or ground line VSS11c of the M1 layer, which extend in the Y direction in plan view. Similarly, if the size of the power switch circuit PSW1 in the Y direction is designed to be larger than the interval H1, the power switch circuit PSW1 will overlap with the ground line VSS01c or virtual power line VVDD01b of the M0 layer, which extend in the X direction in plan view.

[0020] As explained in Figure 3, the internal wiring of the power switch circuit PSW1 is formed using not only the M0 layer but also the M1 layer. For this reason, it is necessary to devise a layout so that the internal wiring of the M1 layer in the power switch circuit PSW1 does not compete with the power supply wiring VVDD11b of the M1 layer. In particular, when the wiring of the M1 layer in the power switch circuit PSW1 is connected to the source electrode and drain electrode of a transistor that are alternately arranged with the gate electrode in between, it is necessary to form the wiring of the M1 layer so as to avoid competition with the power supply wiring VVDD11b of the M1 layer. The layout innovations are explained in Figures 3 and 4.

[0021] 1, the power switch circuits PSW1 are arranged in the X direction at a pitch twice the wiring pitch of the virtual power lines VVDD01b (or ground lines VSS01c) arranged in the X direction. Also, the power switch circuits PSW1 are arranged in the Y direction at a pitch four times the wiring pitch of the virtual power lines VVDD11b (or ground lines VSS11c) arranged in the Y direction.

[0022] That is, the positions of the transistors (for example, the p-channel transistors PT shown in FIG. 3) that overlap with at least one of the virtual power supply line VVDD11b and the ground line VSS01c in plan view are the same among the multiple power supply switch circuits PSW1 arranged in the standard cell area SCA. Note that the power supply switch circuits PSW1 may be arranged at a pitch that is an integer multiple, such as three or six times, of the wiring pitch of the virtual power supply line VVDD (or the ground line VSS) in each of the X and Y directions.

[0023] By setting the arrangement pitch to an integer multiple, the positional relationship of the virtual power lines VVDD01b, 11b and the ground lines VSS01c, 11c relative to the power switch circuit PSW1 can be made the same in all power switch circuits PSW1. As a result, the layout data of the power switch circuits PSW1 that cross at least one of VVDD01b, 11b and the ground lines VSS01c, 11c can be made common, making it easier to design the layout of the power switch circuits PSW1.

[0024] Furthermore, the size of the power switch circuit PSW1 in the X direction is not limited to twice the interval W1. Similarly, the size of the power switch circuit PSW1 in the Y direction is not limited to twice the interval H1. Note that, although the power switch circuits PSW1 are arranged in a staggered pattern in FIG. 1, the arrangement pattern is not limited to that shown in FIG.

[0025] Fig. 2 shows an example of the power switch circuit PSW1 shown in Fig. 1. The power switch circuit PSW1 includes a p-channel transistor PT and a power switch control circuit PCNT1. Note that the p-channel transistor PT actually includes multiple transistors connected in parallel.

[0026] The source of the p-channel transistor PT is connected to, for example, a power supply line VDD to which an external power supply VDD is supplied, and the drain of the p-channel transistor is connected to a virtual power supply line VVDD of the standard cell. The gate electrode of the p-channel transistor PT is connected to the output of the power switch control circuit PCNT1. Note that the power switch circuit PSW1 may have an n-channel transistor instead of the p-channel transistor PT. In this case, the source of the n-channel transistor is connected to a ground line VSS, and the drain is connected to each logic circuit of the standard cell and to a virtual ground line that supplies a ground voltage.

[0027] The power switch control circuit PCNT1 is connected to the power supply line VDD and the ground line VSS to operate constantly, and operates based on the power control signal PCNT. When the power control signal PCNT indicates an active mode in which the circuits in the power domain PD operate, the power switch control circuit PCNT1 supplies the ground voltage VSS to the gate electrode of the p-channel transistor PT. This turns on the p-channel transistor PT, and the power supply line VDD and the virtual power supply line VVDD are connected to each other.

[0028] When the power control signal PCNT indicates the power-down mode, the power switch control circuit PCNT1 supplies the power supply voltage VDD to the gate electrode of the p-channel transistor PT. This turns off the p-channel transistor PT, cutting off the connection between the power supply line VDD and the virtual power supply line VVDD. In this way, the p-channel transistor PT operates based on the power control signal PCNT and functions as a power switch that connects the power supply line VDD to the virtual power supply line VVDD.

[0029] The p-channel transistor PT turns on during active mode and connects the power supply line VDD to the virtual power supply line VVDD. As a result, the standard cells in the power domain PD receive the power supply voltage VDD via the virtual power supply line VVDD during active mode and operate. On the other hand, the p-channel transistor PT turns off during power-down mode and cuts off the connection between the power supply line VDD and the virtual power supply line VVDD. As a result, the supply of the power supply voltage VDD to the standard cells in the power domain PD is stopped during power-down mode, and they stop operating.

[0030] Fig. 3 shows an example of the layout of power supply wiring for the power switch circuit PSW1 in Fig. 2. Note that in Fig. 3, the power switch control circuit PCNT1 in Fig. 2 is omitted.

[0031] Hereinafter, the virtual power lines VVDD01b and VVDD11b and the ground lines VSS01c and VSS11c, which are routed from outside the power switch circuit PSW1, will also be referred to as power lines VVDD and VSS. The virtual power lines VVDD02b and VVDD12b and the power lines VDD02a and VDD12a, which are enclosed within the power switch circuit PSW1, will also be referred to as lines VVDD02b, VVDD12b, VDD02a, and VDD12a, respectively. As described in Figure 1, the two power lines VVDD01b and one power line VSS01c extending in the X direction are formed using the M0 layer. The two power lines VSS11c and one power line VVDD11b extending in the Y direction are formed using the M1 layer.

[0032] The power switch circuit PSW1 has a plurality of p-channel transistors PT, each having a plurality of fins extending in the X direction and a plurality of gate electrodes G extending in the Y direction. The plurality of fins are arranged at intervals in the Y direction. The plurality of gate electrodes G are arranged at intervals in the X direction. Dummy gate electrodes DMYG are arranged on both sides in the X direction of the arrangement region of the plurality of gate electrodes G.

[0033] Each gate electrode G is the gate electrode of a p-channel transistor PT shown in Fig. 2, and is connected through a via to a signal line SIG formed in the M0 layer. The signal line SIG is connected to the output of the power switch control circuit PCNT1 shown in Fig. 2 through wiring, vias, etc. (not shown).

[0034] In the p-channel transistor PT, a source region S or a drain region D is formed between two adjacent gate electrodes G. The source regions S and the drain regions D are alternately formed with the gate electrode G sandwiched between them. Each source region S is electrically connected to a local wiring VDDLIa that extends in the Y direction on each source region S in the LI (local interconnect) layer. Each drain region D is electrically connected to a local wiring VVDDLIb that extends in the Y direction on each drain region D in the LI layer. The LI layer is a wiring layer provided between the semiconductor substrate and the M0 layer.

[0035] In a finFET, the source region S and the drain region D are each formed in a fin. Therefore, the local wiring VDDLIa is connected to the fin that functions as the source region S, and the local wiring VVDDLIb is connected to the fin that functions as the drain region D.

[0036] Local wiring VDDLIa extending in the Y direction in the LI layer is connected via a via to wiring VDD02a in the M0 layer extending in the X direction on the p-channel transistor PT, and is further connected via a via to wiring VDD12a in the M1 layer extending in the Y direction on the source region S. The wiring VDD12a in the M1 layer extending in the Y direction on the source region S is an example of a first wiring. Vias indicated by triangles in the figure represent both vias provided between the L1 layer and the M0 layer and vias provided between the M0 layer and the M1 layer, and are provided at positions that overlap in plan view.

[0037] By connecting the wiring VDD12a of the M1 layer to the local wiring VDDLIa of each source region S, the resistance of the source region S extending in the Y direction can be reduced and the supply of the power supply voltage VDD can be strengthened. Also, by connecting the local wiring VDDLIa to each other via the wiring VDD02a of the M0 layer, a sufficient power supply voltage VDD can be efficiently supplied to each source region S.

[0038] One or both of the wiring VDD02a in the M0 layer and the wiring VDD12a in the M1 layer are connected to a mesh-like power supply line VDD formed in a wiring layer above the M1 layer via vias (not shown). For example, the vias connecting the wiring VDD02a or the wiring VDD12a to the power supply line VDD may be formed in the same position as the vias indicated by the triangles on the source region S in a plan view. Alternatively, the vias connecting the wiring VDD02a to the power supply line VDD may be formed together with the wiring VDD12a in the M1 layer at a position extending further in the X direction from the wiring VDD02a in the M0 layer relative to FIG. 3, or may be formed at a position extending further in the Y direction from the wiring VDD12a in the M1 layer relative to FIG. 3.

[0039] The local wiring VVDDLIb extending in the Y direction on the LI layer is connected via a via to a wiring VVDD02b on the M0 layer extending in the X direction on the p-channel transistor PT, and is further connected via a via to a wiring VVDD12b on the M1 layer extending in the Y direction on the drain region D. The wiring VVDD12b on the M1 layer extending in the Y direction on the drain region D is an example of a second wiring.

[0040] By connecting the wiring VVDD12b in the M1 layer to the local wiring VVDDLIb of each drain region D, the resistance of the drain region D extending in the Y direction can be reduced and the supply of the power supply voltage VVDD can be strengthened. Also, by connecting the local wiring VVDDLIb to each other via the wiring VVDD02b in the M0 layer, a sufficient power supply voltage VVDD can be efficiently output from each drain region D.

[0041] 3, the power supply line VVDD11b in the M1 layer is formed on the source region S located in the center in the X direction of the p-channel transistor PT, for example. The power supply line VVDD11b in the M1 layer supplies the power supply voltage VVDD, which is supplied from each drain region D of the p-channel transistor PT via the local wiring VVDDLIb and the power supply line VVDD02b in the M0 layer, to the standard cell. Note that the power supply line VVDD11b in the M1 layer may be arranged in a location other than on the source region S.

[0042] By locating the power supply line VVDD11b of the M1 layer at the center of the p-channel transistor PT in the X direction, the difference in distance between the six drain regions D and the power supply line VVDD11b of the M1 layer can be reduced. This reduces the variation in parasitic resistance between each drain region D and the power supply line VVDD11b of the M1 layer, allowing the power supply voltage VVDD to be efficiently supplied to the standard cell. Note that the power supply line VVDD11b of the M1 layer is not limited to one line, and may be located in a group of multiple lines. In this case, the group of multiple power supply lines VVDD11b of the M1 layer may be located at the center of the p-channel transistor PT in the X direction.

[0043] On the other hand, to avoid contention with the power supply line VVDD11b of the M1 layer, the wiring VDD12a of the M1 layer is not formed on the source region S facing the power supply line VVDD11b of the M1 layer. However, the local wiring VDDLIa on the source region S facing the power supply line VVDD11b of the M1 layer is connected in sequence via vias to the wiring VDD02a of the M0 layer and the power supply line VDD12a of the M1 layer, which extend in the X direction, and is further connected to the power supply line VDD in layers above the M1 layer.

[0044] Therefore, even when the size of the power switch circuit PSW1 is large and the power line VVDD11b in the M1 layer is wired across the power switch circuit PSW1, the desired power supply voltage VDD can be supplied to the source region S located below the power line VVDD112b in the M1 layer. In other words, a sufficient power supply voltage VVDD can be supplied from the power switch circuit PSW1 to the standard cell without reducing the ability to supply the power supply voltage VDD to the power switch circuit PSW1.

[0045] Figure 4 shows the layout of Figure 3 excluding the wiring in the M1 layer and the vias between the M0 and M1 layers. The local wiring VDDLIa in the LI layer, which is electrically connected to each source region S, is connected via vias to two wirings VDD02a in the M0 layer extending in the X direction. The local wiring VVDDLIb in the LI layer, which is electrically connected to each drain region D, is connected via vias to two wirings VVDD02b in the M0 layer extending in the X direction. This allows the p-channel transistor PT to be formed while maintaining the repeating structure and repeating intervals of the source region S, gate electrode G, and drain region D, even when the power supply line VVDD11b (Figure 3) in the M1 layer is wired in the Y direction on the power switch circuit PSW1.

[0046] FIG. 5 shows an example of the structure of the p-channel transistor PT of FIGS. 3 and 4. The p-channel transistor PT has fins extending in the X direction provided on a semiconductor substrate and gate electrodes G extending in the Y direction across the fins. In the example of FIG. 5, the p-channel transistor PT has eight fins and ten gate electrodes G. A gate insulating film is formed between the fins and the gate electrodes G, and a channel of the p-channel transistor PT is formed in the surface portion of the fin covered with the gate insulating film. Note that the number of fins may be other than eight, and the number of gate electrodes G may be other than ten.

[0047] A source region S and a drain region D are provided on both sides of the gate electrode G in the fin. Although not shown, local wiring VDD and local wiring VVDD are provided in each source region and each drain region D, respectively, along the extension direction of the gate electrode G. Note that in FIG. 5, the source region S and the drain region D may be interchanged.

[0048] FIG. 6 shows a cross section taken along line Y1-Y1' in FIG. 3. The fin is formed in an isolation insulating film such as STI (Shallow Trench Isolation) formed on a semiconductor substrate. In the cross section shown in FIG. 6, the upper part of the fin protruding above the isolation insulating film is covered with a local interconnect VVDDLIb. In the cross section shown in FIG. 6, the local interconnect VVDDLIb is connected through vias to two power supply lines VVDD01b and VVDD02b formed in the M0 layer.

[0049] In the cross section shown in Figure 6, the wiring VVDD02b on the M0 layer is connected to the wiring VVDD12b formed on the M1 layer through a via. Each local wiring VVDDLIb is formed in the interlayer insulating film. In the interlayer insulating film on the local wiring VVDDLIb, each via, the power supply line VVDD01b on the M0 layer, wiring VDD02a, VVDD02b, the power supply line VSS01c, and the signal line SIG are formed. The power supply line VVDD12b on the M1 layer is formed in the interlayer insulating film on the M0 layer.

[0050] As described above, in this embodiment, even when the size of the power switch circuit PSW1 is large and the power line VVDD11b in the M1 layer is wired across the power switch circuit PSW1, it is possible to supply the desired power supply voltage VDD to the source region S located below the power line VVDD11b in the M1 layer. In other words, it is possible to supply a sufficient power supply voltage VVDD from the power switch circuit PSW1 to the standard cell without reducing the ability to supply the power supply voltage VDD to the power switch circuit PSW1.

[0051] Furthermore, even when the power supply line VVDD11b in the M1 layer is routed in the Y direction of the power switch circuit PSW1, the p-channel transistor PT can be formed while maintaining the repeating structure and repeating intervals of the source regions S, gate electrodes G, and drain regions D. In this case, for example, by locating the power supply line VVDD11b in the M1 layer at the center of the p-channel transistor PT in the X direction, the difference in distance between the six drain regions D and the power supply line VVDD11b in the M1 layer can be reduced. This reduces the variation in parasitic resistance between each drain region D and the power supply line VVDD11b in the M1 layer, allowing the power supply voltage VVDD to be supplied to the standard cell efficiently.

[0052] The layout pitch of the power switch circuits PSW1 is designed to be an integer multiple of the wiring pitch of the power line VSS01c or power line VSS11c, or the wiring pitch of the virtual power line VVDD01b or VVDD11b. This makes it possible to make the positional relationship of the virtual power lines VVDD01b, VVDD11b and the power lines VSS01c, VSS11c with respect to the power switch circuit PSW1 the same in all power switch circuits PSW1. As a result, it is possible to share the layout data of the power switch circuits PSW1 that cross at least one of the virtual power lines VVDD01b, VVDD11b and the power lines VSS01c, VSS11c, and this makes it easier to design the layout of the power switch circuits PSW1.

[0053] (Second embodiment) 7 shows an example of the layout of a power switch circuit of a semiconductor device according to the second embodiment. Elements similar to those in FIG. 3 are given the same reference numerals, and detailed description thereof will be omitted. The layout of the semiconductor device having the power switch circuit PSW1 shown in FIG. 7 is similar to the layout of the semiconductor device 100 shown in FIG. 1. That is, the semiconductor device having the power switch circuit PSW1 shown in FIG. 7 has a standard cell area SCA in which a plurality of standard cells are arranged in the power domain PD, and the power switch circuit PSW1 is arranged in the standard cell area SCA.

[0054] In this embodiment, the power supply line VVDD11b of the M1 layer, which is arranged along the Y direction in the central portion of the power switch circuit PSW1 in the X direction, is connected to the wiring VVDD02b of the M0 layer extending in the X direction through a via indicated by a diamond. As a result, the power supply voltage VVDD output from the drain region D of the p-channel transistor PT is supplied not only to the power supply line VVDD02b of the M0 layer extending in the X direction, but also to the power supply line VVDD11b of the M1 layer via the wiring VVDD02b of the M0 layer extending in the X direction. As a result, the ability to supply the power supply voltage VVDD to the standard cells can be improved compared to the power switch circuit PSW1 of FIG. 3. Note that the layout of FIG. 7, excluding the wiring of the M1 layer and the via between the M0 and M1 layers, is the same as that of FIG. 4.

[0055] As described above, this embodiment also achieves the same effects as the above-described embodiments. For example, even when the power supply line VVDD11b of the M1 layer is wired across the power switch circuit PSW1, a sufficient power supply voltage VVDD can be output from the power switch circuit PSW1 without reducing the ability to supply the power supply voltage VDD to the power switch circuit PSW1. Furthermore, in this embodiment, the power supply line VVDD11b of the M1 layer is connected to the wire VVDD02b of the M0 layer through a via, further improving the ability to supply the power supply voltage VVDD to the standard cells.

[0056] (Third embodiment) 8 shows an example of the layout of a power switch circuit of a semiconductor device according to the third embodiment. Elements similar to those in FIGS. 3 and 7 are designated by the same reference numerals, and detailed description thereof will be omitted. The layout of the semiconductor device having the power switch circuit PSW1 shown in FIG. 8 is similar to the layout of the semiconductor device 100 shown in FIG. 1. That is, the semiconductor device having the power switch circuit PSW1 shown in FIG. 8 has a standard cell area SCA in which a plurality of standard cells are arranged in the power domain PD, and the power switch circuit PSW1 is arranged in the standard cell area SCA.

[0057] In this embodiment, in addition to the power supply line VVDD11b in the M1 layer extending in the Y direction, a power supply line VSS11c in the M1 layer extending in the Y direction is wired on the p-channel transistor PT on the power switch circuit PSW1. In the M1 layer, the wire VVDD12b or the wire VDD12a is placed at a position that avoids the power supply line VSS11c on the p-channel transistor PT. The local wire VVDDLIb located below the power supply line VSS11c is connected to the wire VVDD02b extending in the X direction through a via. The wire VVDD02b is connected to the wire VVDD12b extending in the Y direction on the p-channel transistor PT.

[0058] The wiring VVDD12b is electrically connected to the power supply lines VVDD01b and VVDD11b. In other words, the local wiring VVDDLIb located below the power supply line VSS11c is electrically connected to the power supply lines VVDD01b and VVDD11b. The power supply line VSS01c is connected to the power supply line VSS11c on the p-channel transistor PT and to the power supply line VSS11c located at a position that does not overlap with the p-channel transistor PT in a planar view through a via that connects the M0 layer and the M1 layer.

[0059] For example, if the power switch circuit PSW1 becomes large-scale, multiple power supply lines or ground lines extending in the Y direction may be arranged to overlap the power switch circuit PSW1. In such a case, by providing an area in the power switch circuit PSW1 where the wiring VDD12a or the wiring VVDD12b is not arranged, as in this embodiment, it is possible to arrange an additional power supply line VSS11c in a position overlapping with the p-channel transistor PT of the power switch circuit PSW1.

[0060] In this embodiment, as in Fig. 7, the power supply line VVDD11b of the M1 layer, which is arranged in the center of the power switch circuit PSW1 in the X direction, is connected to the wiring VVDD02b of the M0 layer extending in the X direction through a via shown by a diamond. Note that the layout of Fig. 8, excluding the wiring of the M1 layer and the via between the M0 and M1 layers, is the same as Fig. 4.

[0061] As described above, this embodiment also provides the same effects as the above-described embodiments. Furthermore, in this embodiment, the power supply line VSS11c of the M1 layer is wired on the power switch circuit PSW1, so that the power supply resistance of the mesh-like power supply line VSS to which the power supply voltage VSS is supplied can be reduced. This improves the ability to extract the power supply voltage VSS from the standard cells via the power supply line VSS.

[0062] Furthermore, even when the power supply line VSS of the M1 layer is wired on the power switch circuit PSW1, the power supply voltage VVDD can be reliably supplied to the drain region D located below the power supply line VSS. As a result, the ability to extract the power supply voltage VSS can be improved without reducing the ability to supply the power supply voltage VVDD to the standard cells.

[0063] (Fourth embodiment) 9 shows an example of the layout of a power switch circuit of a semiconductor device according to the fourth embodiment. Elements similar to those in FIGS. 3, 7, and 8 are designated by the same reference numerals, and detailed description thereof will be omitted. The layout of the semiconductor device having the power switch circuit PSW1 shown in FIG. 9 is similar to the layout of the semiconductor device 100 shown in FIG. 1. That is, the semiconductor device having the power switch circuit PSW1 shown in FIG. 9 has a standard cell area SCA in which a plurality of standard cells are arranged in the power domain PD, and the power switch circuit PSW1 is arranged in the standard cell area SCA.

[0064] In this embodiment, in addition to the power supply line VVDD11b of the M1 layer that extends in the Y direction and is located in the center of the power supply switch circuit PSW1 in the X direction over the power supply switch circuit PSW1, another power supply line VVDD11b of the M1 layer that extends in the Y direction and a power supply line VSS11c of the M1 layer that extends in the Y direction are wired over the p-channel transistor PT. In the M1 layer, the wire VVDD12b or the wire VDD12a is arranged at a position that avoids the other power supply line VVDD11b and power supply line VSS11c over the p-channel transistor PT.

[0065] The local wiring VVDDLIb located below the power supply line VSS11c is connected to a wiring VVDD02b extending in the X direction through a via. The wiring VVDD02b is connected to a wiring VVDD12b extending in the Y direction above the p-channel transistor PT. The wiring VVDD12b is electrically connected to the power supply lines VVDD01b and VVDD11b. The local wiring VDDLIa located below another power supply line VVDD11b is connected to a wiring VDD02a extending in the X direction through a via. The wiring VDD02a is connected to a wiring VDD12a extending in the Y direction above the p-channel transistor PT. The power supply voltage VDD is supplied to the wiring VVDD12a through a wiring in a layer above the M1 layer, for example.

[0066] As in Figures 3 and 8, local wiring VDDLIa, which overlaps with power line VVDD11b or power line VSS11c of the M1 layer, is connected to wiring VDD02a of the M0 layer extending in the X direction via a via. Wiring VVDDLIb, which overlaps with power line VVDD11b or power line VSS11c of the M1 layer, is connected to wiring VVDD02b of the M0 layer extending in the X direction via a via, and wiring VVDD12b of the M1 layer extending in the Y direction via a via. Wiring VVDD12b is electrically connected to power lines VVDD01b and VVDD11b. The layout of Figure 9, excluding the wiring of the M1 layer and the vias between the M0 and M1 layers, is the same as that of Figure 4.

[0067] By wiring multiple power supply lines VVDD11b on the M1 layer above the power switch circuit PSW1, the power supply resistance of the mesh-like power supply lines to which the power supply voltage VVDD is supplied can be reduced. As a result, the supply capacity of the power supply voltage VVDD supplied to the standard cells via the power supply lines VVDD11b on the M1 layer can be improved compared to the power switch circuit PSW1 in Figure 3.

[0068] Furthermore, by routing the power supply line VVDD11b in the M1 layer over the p-channel transistor PT, the supply capability of the power supply voltage VVDD to the standard cells can be increased. Note that the larger the size of the power switch circuit PSW1 in the X direction, the more likely it is that the number of power supply lines VVDD11b and VSS11c in the M1 layer that cross over the power switch circuit PSW1 will increase. Even in this case, applying the layout technique shown in Figure 9 can improve the supply capability of the power supply voltage VVDD to the standard cells and the ability to extract the power supply voltage VSS from the standard cells.

[0069] 9, the power lines are arranged in the following order along the X direction: power line VSS11c, power line VVDD11b, power line VVDD11b, power line VSS11c, and power line VSS11c, but this is not limiting. For example, the power line VSS11c or a group of multiple power lines VSS11c and the power line VVDD11b or a group of multiple power lines VVDD11b may be arranged alternately along the X direction. This also applies to the third embodiment.

[0070] As described above, this embodiment also achieves the same effects as the above-described embodiments. Furthermore, in this embodiment, by wiring the multiple power supply lines VVDD of the M1 layer on the power switch circuit PSW1, the power supply resistance of the mesh-like power supply lines VVDD can be reduced. This makes it possible to improve the supply capacity of the power supply voltage VVDD supplied to the standard cells via the power supply lines VVDD of the M1 layer compared to the above-described embodiments. Furthermore, by wiring the power supply line VVDD11b of the M1 layer on the p-channel transistor PT, it is possible to further improve the supply capacity of the power supply voltage VVDD supplied to the standard cells.

[0071] (Fifth embodiment) FIG. 10 shows an example of a layout of a semiconductor device according to the fifth embodiment. Elements similar to those in FIG. 1 are assigned the same reference numerals, and detailed description thereof will be omitted. The semiconductor device 102 shown in FIG. 10 has, within a power domain PD, multiple peripheral areas PA in which large-sized random access memories (RAMs) 1 and small-sized RAMs 2 are respectively arranged around an end cap ECAP that surrounds a standard cell area SCA. RAMs 1 and RAMs 2 are examples of functional circuits having predetermined functions. The peripheral areas PA are an example of a second area.

[0072] In the standard cell area SCA, multiple power switch circuits PSW1 are arranged at intervals. As in Figure 1, each power switch circuit PSW1 is arranged in the X direction at a pitch twice the wiring pitch of the virtual power lines VVDD (or ground lines VSS) arranged in the X direction. Also, each power switch circuit PSW1 is arranged in the Y direction at a pitch four times the wiring pitch of the virtual power lines VVDD (or ground lines VSS) arranged in the Y direction.

[0073] However, in this embodiment, in the standard cell area SCA, a predetermined number of power switch circuits PSW1 are arranged at a pitch smaller than the above-mentioned predetermined pitch in the area close to RAM1. That is, in the standard cell area SCA, the arrangement frequency of power switch circuits PSW1 in the area adjacent to the peripheral area PA where RAM1 is arranged is higher than the arrangement frequency of power switch circuits PSW1 in other areas. By arranging the power switch circuit PSW1 near RAM1 in the standard cell area SCA, it is possible to improve the supply capability of the power supply voltage VVDD to RAM1 arranged in the power domain PD.

[0074] Even if no functional circuits such as RAM1 are arranged around the standard cell area SCA, the power switch circuits PSW1 may be arranged more frequently as in this embodiment. Specifically, for example, the power switch circuits PSW1 may be arranged more frequently in the corner areas of the standard cell area SCA than in the inner areas of the standard cell area SCA.

[0075] As described above, this embodiment also achieves the same effects as the above-described embodiments. Furthermore, in this embodiment, by changing the placement frequency of the power switch circuits PSW1 according to the required amount of power supply voltage VVDD, an appropriate power supply voltage VVDD can be supplied to a predetermined circuit. Furthermore, an appropriate power supply voltage VVDD can also be supplied to functional circuits such as RAM1 that are placed in the peripheral area PA outside the standard cell area SCA.

[0076] (Sixth embodiment) Figure 11 shows an example of the layout of a semiconductor device according to the sixth embodiment. Elements similar to those in Figures 1 and 10 are given the same reference numerals, and detailed description thereof will be omitted. In the semiconductor device 104 shown in Figure 11, a plurality of power switch circuits PSW2, each having a layout size smaller than that of the power switch circuit PSW1, are arranged at the end of the power domain PD on the RAM2 side in the X direction. The configuration other than the power switch circuit PSW2 is the same as that shown in Figure 10. The power switch circuit PSW2 is an example of a second power switch circuit.

[0077] The size of the power switch circuit PSW2 in the X direction is assumed to be equal to or less than one interval W1. Therefore, the power switch circuit PSW2 can be placed in a position where it does not overlap with the power supply lines VVDD11b and VSS11c extending in the Y direction in a plan view. Therefore, there is no contention between the wiring VVD12a and wiring VVDD12b in the M1 layer above the p-channel transistor PT and the power supply lines VVDD11b and VSS11c extending in the Y direction.

[0078] Furthermore, even if there is no space to place the power switch circuit PSW1 in the standard cell area SCA, the power switch circuit PSW2 can be placed near the RAM 2. In particular, the power switch circuit PSW2 can be placed in the peripheral part of the standard cell area SCA. As a result, for example, it is possible to improve the ability to supply the power voltage VVDD to the RAM 2 placed in the power domain PD.

[0079] FIG. 12 shows an example of the power supply wiring layout of the power switch circuit PSW2 of FIG. 11. The same elements as those in FIG. 3 are given the same reference numerals, and detailed description thereof will be omitted. Note that FIG. 12 does not show the power switch control circuit that generates the control voltage to be output to the signal line SIG connected to the gate electrode G of the power switch circuit PSW2. The function and operation of the power switch control circuit that controls the operation of the power switch circuit PSW2 are similar to the function and operation of the power switch control circuit PCNT1 shown in FIG. 2. Furthermore, in the example of FIG. 12, the power supply line VSS11c extending in the Y direction is wired on the left side, and the power supply line VVDD11b extending in the Y direction is wired on the right side, but this is not limiting.

[0080] The power switch circuit PSW2 has a plurality of p-channel transistors PT, each having eight fins extending in the X direction and four gate electrodes G extending in the Y direction. Dummy gate electrodes DMYG are arranged on both sides in the X direction of the arrangement area of ​​the four gate electrodes G.

[0081] The power switch circuit PSW2 is similar to the power switch circuit PSW1 of FIG. 3, except that a p-channel transistor PT having four gate electrodes G is arranged instead of the p-channel transistor PT having ten gate electrodes G. That is, in the p-channel transistor PT, the wiring and vias connected to the gate electrode G, source region S, and drain region D are the same as those in FIG. 3. The power switch circuit PSW2 is arranged so that its positional relationship with the power lines VVDD and VSS is the same. This allows the layout data of the power switch circuit PSW2 to be common, and makes it easier to design the layout of the power switch circuit PSW1.

[0082] As described above, this embodiment also provides the same effects as the above-described embodiments. Furthermore, in this embodiment, the power switch circuit PSW2 is smaller in size than the power switch circuit PSW1, so that the power switch circuit PSW2 can be placed in the peripheral portion of the standard cell area SCA where the power switch circuit PSW1 cannot be placed. As a result, for example, the ability to supply the power voltage VVDD to RAM2 placed in the power domain PD can be improved.

[0083] Although the above-described embodiment describes an example in which the power switch circuits PSW1 and PSW2 have finFETs, the present invention may also be applied to power switch circuits having planar transistors, nanowire transistors, nanosheet transistors, forksheet transistors, CFETs (Complementary FETs), vertical nanowire transistors, etc.

[0084] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form. [Explanation of symbols]

[0085] 100, 102, 104 Semiconductor device D drain region ECAP end cap G gate electrode H1 interval PA Surrounding Area PCNT Power control signal PCNT1 Power switch control circuit PD Power Domain PSW1, PSW2 power switch circuits PT p-channel transistor S source region SCA Standard Cell Area SIG signal line VDD power line VSS power wire (ground wire) VVDD virtual power line W1 spacing

Claims

1. A substrate; a plurality of fins formed on the substrate, extending in a first direction in a plan view, and arranged side by side in a second direction different from the first direction in a plan view; a plurality of first local wires and a plurality of second local wires formed on the plurality of fins, each extending in the second direction, and alternately arranged in the first direction; a plurality of gate electrodes formed on the plurality of fins, each extending in the second direction, and each disposed between the first local interconnect and the second local interconnect; a first power supply line formed in a first wiring layer above the first local wires and the second local wires, extending in the first direction in a plan view, supplied with a first voltage, and electrically connected to the plurality of first local wires; a second power supply line formed in the first wiring layer, extending in the first direction, and supplied with a second voltage; a third power supply line formed in a second wiring layer that is one wiring layer above the first wiring layer, extending in a second direction different from the first direction in a plan view, connected to the first power supply line, and supplied with the first voltage; a fourth power supply line formed in the second wiring layer, extending in the second direction, connected to the second power supply line, and supplied with the second voltage; a fifth power supply line formed in the first wiring layer, supplied with a third voltage, and electrically connected to the plurality of second local wirings; a transistor including the plurality of gate electrodes, a plurality of source regions formed in the plurality of fins and connected to the plurality of second local wirings, respectively, and a plurality of drain regions formed in the plurality of fins and connected to the plurality of first local wirings, the transistor being positioned so as to overlap at least one of the third power supply line and the fourth power supply line in a plan view; a first power switch circuit having the transistor; a first wiring formed in the second wiring layer, electrically connected to the fifth power supply line, extending in the second direction, overlapping with the transistor in a plan view, not overlapping with the third power supply line and the fourth power supply line in a plan view, and to which the third voltage is supplied; a second wiring formed in the second wiring layer, electrically connected to the third power supply line, extending in the second direction, overlapping the transistor in a plan view, not overlapping the third power supply line and the fourth power supply line in a plan view, and supplied with the first voltage; A semiconductor device having:

2. a third wiring formed in the first wiring layer, overlapping with the transistor in a plan view, extending in the first direction, and electrically connecting the plurality of first local wirings and the plurality of second wirings; a first via that overlaps the transistor in a plan view and connects the third power supply line and the third wiring; The semiconductor device according to claim 1 ,

3. the first wirings and the source regions are arranged to overlap each other in a plan view, 3. The semiconductor device according to claim 1, wherein the plurality of second wirings and the plurality of drain regions are arranged to overlap each other in a plan view.

4. a second via that overlaps the transistor in a plan view and connects the fourth power supply line and the second power supply line; 4. The semiconductor device according to claim 1, further comprising:

5. the third power supply line and the fourth power supply line are each provided in plural; a plurality of the first power switch circuits; the third power supply line and the fourth power supply line are repeatedly arranged at a first pitch in the first direction; The first power supply switch circuits have the transistors overlapping at least one of the third power supply line and the fourth power supply line in a plan view at the same positions.

5. The semiconductor device according to claim 1.

6. a first region including the first power supply line, the second power supply line, the third power supply line, the fourth power supply line, and the first power supply switch circuit, and in which a logic circuit is arranged; The first region has a portion where the first power supply switch circuits are arranged more frequently than other portions.

6. The semiconductor device according to claim 1.

7. a second region adjacent to the first region and having a functional circuit different from the logic circuit; The high-frequency portion is adjacent to the second region. The semiconductor device according to claim 6.

8. a second power supply switch circuit including a transistor that is disposed in the first region and does not overlap with the third power supply line and the fourth power supply line in a plan view; 8. The semiconductor device according to claim 6.

9. At least one of the third power supply line and the fourth power supply line overlapping the transistor in a plan view is located between a plurality of groups of the first wirings and the second wirings that are alternately arranged in the first direction.

9. The semiconductor device according to claim 1.

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