Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of improving a switching speed, and a method for manufacturing the same.SOLUTION: A semiconductor device includes: a first electrode; a first conductivity-type first semiconductor layer provided on the first electrode; a second conductivity-type pillar provided on the first semiconductor layer; a first conductivity-type pillar provided on the first semiconductor layer, and including a first conductivity-type low concentration layer and a first conductivity-type high concentration layer, the low concentration layer having an average value of impurity concentration lower than an average value of impurity concentration of the second conductivity-type pillar, the high concentration layer having an average value of impurity concentration higher than the average value of the impurity concentration of the second conductivity-type pillar; a second conductivity-type second semiconductor layer provided on the first conductivity-type pillar; a first conductivity-type third semiconductor layer provided on the second semiconductor layer; a second electrode connected to the second conductivity-type pillar and the third semiconductor layer; a third electrode; and an insulating film disposed between the second semiconductor layer and the third electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Power semiconductor devices using silicon carbide instead of silicon have been developed. Compared to silicon-based semiconductor devices, silicon carbide semiconductor devices can withstand stronger electric fields, improving the balance between breakdown voltage and on-resistance. Even in these semiconductor devices, there is a demand for improved switching speed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-129532 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments is to provide a semiconductor device capable of improving switching speed and a manufacturing method thereof. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor layer of a first conductivity type provided on the first electrode, a second conductivity type pillar of a second conductivity type provided on the first semiconductor layer, a first conductivity type pillar provided on the first semiconductor layer, the first conductivity type pillar having a low concentration layer of the first conductivity type and an average impurity concentration lower than the average impurity concentration of the second conductivity type pillar, and a high concentration layer of the first conductivity type and an average impurity concentration higher than the average impurity concentration of the second conductivity type pillar, a second semiconductor layer of a second conductivity type provided on the first conductivity type pillar, a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, a second electrode connected to the second conductivity type pillar and the third semiconductor layer, a third electrode, and an insulating film arranged between the second semiconductor layer and the third electrode.

[0006] a third semiconductor layer of the first conductivity type on the second semiconductor layer; a third semiconductor layer of the first conductivity type on the second semiconductor layer; a first electrode connected to the first semiconductor layer; a first electrode connected to the third portion and the third semiconductor layer; a second electrode connected to the third portion and the third semiconductor layer; a first electrode connected to the first semiconductor layer; a second electrode connected to the third portion and the third semiconductor layer;

[0007] a second epitaxial layer of a second conductivity type formed on the first epitaxial layer; a third semiconductor layer of a first conductivity type formed on the second semiconductor layer; a third electrode facing the second semiconductor layer via the insulating film; and a first electrode connected to the first semiconductor layer and a second electrode connected to the second epitaxial layer and the third semiconductor layer. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 2] FIG. 2(a) is a graph showing the nitrogen concentration profile of an n-type pillar, with the nitrogen concentration on the horizontal axis and the position along line A shown in FIG. 1 on the vertical axis. FIG. 2(b) is a graph showing the aluminum concentration profile of a p-type pillar, with the aluminum concentration on the horizontal axis and the position along line B shown in FIG. 1 on the vertical axis. [Figure 3] 3(a) to 3(d) are cross-sectional views showing the steps of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4(a) to 4(c) are cross-sectional views illustrating the steps of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view showing a semiconductor device according to a first modification of the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view showing a semiconductor device according to a second modification of the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view showing a semiconductor device according to a third modification of the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view showing a semiconductor device according to a fourth modification of the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 10] FIG. 10(a) is a graph showing the nitrogen concentration profile of the n-type pillar, with the nitrogen concentration on the horizontal axis and the position along line C shown in FIG. 9 on the vertical axis. FIG. 10(b) is a graph showing the aluminum concentration profile of the p-type pillar, with the aluminum concentration on the horizontal axis and the position along line D shown in FIG. 9 on the vertical axis. [Figure 11] 11(a) to 11(d) are cross-sectional views showing the steps of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 12] 12(a) to 12(c) are cross-sectional views showing the steps of the method for manufacturing the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] First Embodiment The first embodiment will be described below. FIG. 1 is a cross-sectional view showing a semiconductor device according to this embodiment. FIG. 2(a) is a graph showing the nitrogen concentration profile of an n-type pillar, with the nitrogen concentration on the horizontal axis and the position along line A shown in FIG. 1 on the vertical axis. FIG. 2(b) is a graph showing the aluminum concentration profile of a p-type pillar, with the aluminum concentration on the horizontal axis and the position along line B shown in FIG. 1 on the vertical axis. Note that the drawings are schematic and have been appropriately simplified. Furthermore, the dimensional ratios of the components in the drawings do not necessarily match exactly. The same applies to the other drawings described below.

[0010] 1, the semiconductor device 1 according to this embodiment is a trench-gate MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The semiconductor device 1 includes a drain electrode 10 (first electrode), a semiconductor portion 20, a source electrode 40 (second electrode), a gate electrode 50 (third electrode), and a gate insulating film 60 (insulating film).

[0011] Hereinafter, for convenience of explanation, this specification will adopt an XYZ Cartesian coordinate system. The direction connecting the drain electrode 10 and the source electrode 40 is referred to as the "Z direction," the direction in which the gate electrode 50 extends is referred to as the "Y direction," and the direction perpendicular to the Z direction and the Y direction is referred to as the "X direction." In addition, within the Z direction, the direction from the drain electrode 10 toward the source electrode 40 is also referred to as "up," and the opposite direction is also referred to as "down," but these expressions are also for convenience and are unrelated to the direction of gravity.

[0012] The drain electrode 10 and the source electrode 40 are plate-shaped and extend along the XY plane. The semiconductor portion 20 is disposed on the drain electrode 10. The source electrode 40 is disposed on the semiconductor portion 20. The gate electrode 50 is disposed inside the semiconductor portion 20. A plurality of gate electrodes 50 are provided and are arranged along the X direction. Each gate electrode 50 extends in the Y direction. Each gate electrode 50 is connected to a gate pad (not shown) provided on the semiconductor portion 20, and a voltage is applied from the outside. A gate insulating film 60 is disposed between the gate electrode 50 and the semiconductor portion 20, and insulates the gate electrode 50 from the semiconductor portion 20.

[0013] The semiconductor portion 20 includes silicon carbide (SiC) and is made of, for example, a single crystal of silicon carbide. Impurities that act as donors or acceptors are locally introduced into the semiconductor portion 20, making the conductivity type of each portion n-type or p-type. The donor impurity is, for example, nitrogen (N), and the acceptor impurity is, for example, aluminum (Al). The gate insulating film 60 includes silicon oxide (SiO). In this specification, the impurity that makes the semiconductor portion 20 a first conductivity type is also referred to as a "first conductivity type impurity," and the impurity that makes the semiconductor portion 20 a second conductivity type is also referred to as a "second conductivity type impurity." For example, when the first conductivity type is n-type, the first conductivity type impurity is a donor impurity, such as nitrogen. When the second conductivity type is p-type, the second conductivity type impurity is an acceptor impurity, such as aluminum.

[0014] The semiconductor portion 20 includes a drain layer 21, a drift layer 22, an n-type pillar 23 (a first conductivity type pillar), a p-type pillar 24 (a second conductivity type pillar), an n-type layer 25, a p-type layer 26, a base layer 27 (a second semiconductor layer), a source layer 28 (a third semiconductor layer), and a contact layer 29. For example, the conductivity type of the drain layer 21 is n + The conductivity type of the drift layer 22 is n - The conductivity type of the n-type pillars 23 as a whole is n-type. The conductivity type of the p-type pillars 24 is p-type. The conductivity type of the n-type layer 25 is n-type. The conductivity type of the p-type layer 26 is p-type. The conductivity type of the base layer 27 is p-type. The conductivity type of the source layer 28 is n-type. + The conductivity type of the contact layer 29 is p + It is a shape.

[0015] The superscript symbols attached to the letters "n" and "p" that represent the conductivity type indicate the relative level of impurity concentration. For n-type, the order of increasing impurity concentration is "n + ``shaped'', ``n-shaped'', ``n - The same applies to p-type. In this specification, "impurity concentration" refers to the effective impurity concentration that contributes to the conduction of a semiconductor, and when a region contains both impurities that act as donors and impurities that act as acceptors, it refers to the concentration excluding the offsetting amounts.

[0016] n + The drain layer 21 is disposed on the drain electrode 10, contacts the drain electrode 10, and is connected to the drain electrode 10. In this specification, "connection" refers to electrical connection. - The drift layer 22 having a shape similar to that of the drain layer 21 is disposed on the drain layer 21, contacts the drain layer 21, and is connected to the drain layer 21. The impurity concentration of the drift layer 22 is lower than the impurity concentration of the drain layer 21. The drain layer 21 and the drift layer 22 form a first semiconductor layer.

[0017] The n-type pillars 23 and p-type pillars 24 are disposed on the drift layer 22 and are in contact with the drift layer 22. A plurality of n-type pillars 23 and a plurality of p-type pillars 24 are provided. The plurality of n-type pillars 23 and the plurality of p-type pillars 24 form a superjunction (SJ) structure 30. Each n-type pillar 23 and each p-type pillar 24 is exposed on both the bottom surface and the top surface of the SJ structure 30.

[0018] 1, the shape of each n-type pillar 23 and each p-type pillar 24 is a plate extending along the YZ plane, and the n-type pillars 23 and p-type pillars 24 are arranged alternately along, for example, the X direction. As a result, a pn interface is formed at the contact surface between the n-type pillars 23 and the p-type pillars 24.

[0019] The arrangement of the n-type pillars 23 and the p-type pillars 24 in the SJ structure 30 is not limited to the above example. For example, the n-type pillars 23 and the p-type pillars 24 may be arranged alternately along the Y direction. Alternatively, the n-type pillars 23 and the p-type pillars 24 may have a columnar shape extending in the Z direction and be arranged in a staggered pattern as viewed from the Z direction. Furthermore, multiple columnar n-type pillars 23 extending in the Z direction may be arranged within a single lattice-shaped p-type pillar 24 as viewed from the Z direction, or multiple columnar p-type pillars 24 extending in the Z direction may be arranged within a single lattice-shaped n-type pillar 23 as viewed from the Z direction. However, in any arrangement, the amounts of donor impurities and acceptor impurities are approximately equal in the SJ structure 30 as a whole.

[0020] In the n-type pillar 23, the conductivity type is n - A low concentration layer 31 of a conductive type and a conductive type + The n-type pillars 23 have high-concentration layers 32 arranged alternately along the Z direction. The low-concentration layers 31 are arranged at the bottom of the n-type pillars 23, and the high-concentration layers 32 are arranged at the top of the n-type pillars 23. The average impurity concentration of the high-concentration layers 32 is higher than the average impurity concentration of the low-concentration layers 31.

[0021] 2(a), the nitrogen concentration profile along the Z direction is almost flat in the low-concentration layer 31, while there is one peak in the nitrogen concentration profile along the Z direction in the high-concentration layer 32. Therefore, the difference between the maximum and minimum values ​​of the nitrogen concentration in the low-concentration layer 31 is smaller than the difference between the maximum and minimum values ​​of the nitrogen concentration in the high-concentration layer 32.

[0022] 1, in the p-type pillar 24, a plurality of p-type layers 33 are arranged along the Z direction. Each p-type layer 33 corresponds to a pair of one low-concentration layer 31 and one high-concentration layer 32 adjacent to each other in the Z direction. The average impurity concentration of the p-type layer 33 is higher than the average impurity concentration of the low-concentration layers 31 of the n-type pillar 23, and lower than the average impurity concentration of the high-concentration layers 32 of the n-type pillar 23.

[0023] 2(b), there is one peak in the aluminum concentration profile along the Z direction in each p-type layer 33. However, because the amount of nitrogen contained in the n-type pillar 23 and the amount of aluminum contained in the p-type pillar 24 are approximately equal, the peak of the aluminum concentration in each p-type layer 33 is lower than the peak of the nitrogen concentration in the high-concentration layer 32 of the n-type pillar 23. The shapes of the peaks in the multiple p-type layers 33 that make up the p-type pillar 24 are similar to each other. Therefore, the difference between the maximum and minimum values ​​of the aluminum concentration in the p-type pillar 24 is greater than the difference between the maximum and minimum values ​​of the nitrogen concentration in the low-concentration layer 31 of the n-type pillar 23, but is smaller than the difference between the maximum and minimum values ​​of the nitrogen concentration in the high-concentration layer 32.

[0024] The average, maximum, and minimum values ​​of the impurity concentration of each layer can be determined, for example, by the following method: The impurity concentration is measured at 10 points arranged at equal intervals along the Z direction in the target layer, and the average value of the 10 measured values ​​is taken as the "average" impurity concentration of that layer, the maximum value of the 10 measured values ​​is taken as the "maximum" impurity concentration of that layer, and the minimum value of the 10 measured values ​​is taken as the "minimum" impurity concentration of that layer.

[0025] As shown in Figure 1, the n-type layer 25 is disposed on the n-type pillar 23. The p-type layer 26 is disposed on the p-type pillar 24. The p-type base layer 27 is disposed on the n-type layer 25 and the p-type layer 26, and is in contact with the n-type layer 25 and the p-type layer 26. + The source layer 28 is disposed on a portion of the base layer 27. The source layer 28 is in contact with the base layer 27. A plurality of source layers 28 are provided and are arranged along the X direction. Each source layer 28 extends in the Y direction. + A contact layer 29 having a shape similar to that of a semiconductor layer 21 is disposed on another part of the base layer 27. The contact layer 29 is in contact with the base layer 27 and the source layer 28. A plurality of contact layers 29 are provided and are arranged along the X direction. Each contact layer 29 extends in the Y direction.

[0026] The source electrode 40 is disposed on the source layer 28 and the contact layer 29, and is connected to the source layer 28 and the contact layer 29. The gate electrode 50 is disposed in the upper part of the n-type layer 25, inside the base layer 27, and inside the source layer 28. In other words, the gate electrode 50 penetrates the source layer 28 and the base layer 27 in the Z direction, and its lower end is located in the upper part of the n-type layer 25. The gate insulating film 60 covers the gate electrode 50 and is in contact with the gate electrode 50. The gate insulating film 60 is disposed between the n-type layer 25 and the gate electrode 50, between the base layer 27 and the gate electrode 50, and between the source layer 28 and the gate electrode 50.

[0027] However, the positional relationships among the n-type pillar 23, the p-type pillar 24, the n-type layer 25, the p-type layer 26, the base layer 27, the source layer 28, the contact layer 29, and the gate electrode 50 and the gate insulating film 60 are not limited to the above example. These positional relationships may be such that, when the p-type pillar 24 is connected to the source electrode 40 and a potential higher than the threshold is applied to the gate electrode 50, an inversion layer is formed in part of the base layer 27 and a current path is formed that connects the source layer 28 to the n-type pillar 23 via the inversion layer.

[0028] Next, a method for manufacturing the semiconductor device 1 according to this embodiment will be described. 3(a) to 3(d) and 4(a) to 4(c) are cross-sectional views showing the steps of the method for manufacturing a semiconductor device according to this embodiment.

[0029] First, it is made of silicon carbide and has n conductivity type. + This semiconductor substrate will become the drain layer 21 in the completed semiconductor device 1.

[0030] Next, as shown in FIG. 3(a), starting from the upper surface of the semiconductor substrate, a silicon carbide film having an n conductivity type is formed. - The epitaxial layer 71 having a shape similar to that of the epitaxial layer 71 is epitaxially grown on the semiconductor substrate. As a result, the epitaxial layer 71 is formed on the semiconductor substrate. The epitaxial layer 71 uniformly contains impurities, such as nitrogen, that act as donors.

[0031] Next, as shown in FIG. 3(b), impurities that will become acceptors, such as aluminum, are ion-implanted into portions 81 in the upper layer portion of the epitaxial layer 71. The portions 81 are portions that will become the lower portions of the p-type pillars 24. For example, multiple portions 81 are provided and are arranged along the X direction. Each portion 81 extends in the Y direction.

[0032] Next, as shown in FIG. 3(c), a donor impurity, for example, nitrogen, is ion-implanted into portion 82 in the upper layer portion of epitaxial layer 71. Portion 82 is in contact with portion 81 and is shallower than portion 81. Portion 82 is the portion that will become the lower portion of n-type pillar 23. For example, multiple portions 82 are provided and arranged along the X direction. Each portion 82 extends in the Y direction. In the Z direction, the upper surface of portion 82 is at approximately the same position as the upper surface of portion 81 and coincides with the upper surface of epitaxial layer 71. Meanwhile, the lower surface of portion 82 is higher than the lower surface of portion 81. Note that the order of the process shown in FIG. 3(b) and the process shown in FIG. 3(c) may be reversed.

[0033] Next, as shown in FIG. 3(d), starting from the upper surface of the epitaxial layer 71, a layer made of silicon carbide and having an n conductivity type is formed. - An epitaxial layer 72 having a shape similar to that of the epitaxial layer 71 is epitaxially grown on the epitaxial layer 71. In the epitaxial layer 72, impurities that act as donors, such as nitrogen, are uniformly contained.

[0034] Next, as shown in FIG. 4( a), an impurity that will serve as an acceptor, such as aluminum, is ion-implanted into portion 83 of epitaxial layer 72. Portion 83 is located directly above portion 81 and is in contact with portion 81. Next, an impurity that will serve as a donor, such as nitrogen, is ion-implanted into portion 84 of epitaxial layer 72. Portion 84 is located directly above portion 82 and is in contact with portion 83. Portion 84 is shallower than portion 83. Therefore, portion 84 is separated from portion 82. In the Z direction, the upper surface of portion 84 is substantially flush with the upper surface of portion 83 and coincides with the upper surface of epitaxial layer 72. Meanwhile, the lower surface of portion 84 is higher than the lower surface of portion 83. Note that the order of the step of introducing aluminum into portion 83 and the step of introducing nitrogen into portion 84 may be reversed.

[0035] Next, as shown in FIG. 4(b), starting from the upper surface of the epitaxial layer 72, a layer made of silicon carbide and having an n conductivity type is formed. - An epitaxial layer 73 having a shape similar to that of the epitaxial layer 72 is epitaxially grown on the epitaxial layer 72. The epitaxial layer 73 contains donor impurities, such as nitrogen, uniformly.

[0036] Next, as shown in FIG. 4( c), an impurity that will serve as an acceptor, such as aluminum, is ion-implanted into portion 85 of the epitaxial layer 73. Portion 85 is located directly above and in contact with portion 83. Next, an impurity that will serve as a donor, such as nitrogen, is ion-implanted into portion 86 of the epitaxial layer 73. Portion 86 is located directly above portion 84 and in contact with portion 85. Portion 86 is shallower than portion 85. Therefore, portion 86 is separated from portion 84. In the Z direction, the upper surface of portion 86 is substantially flush with the upper surface of portion 85 and coincides with the upper surface of the epitaxial layer 73. Meanwhile, the lower surface of portion 86 is higher than the lower surface of portion 85. The order of the step of introducing aluminum into portion 85 and the step of introducing nitrogen into portion 86 may be reversed.

[0037] Similarly, the following is made of silicon carbide and has n conductivity type. -The steps of forming an epitaxial layer of the same shape, doping an impurity that will act as an acceptor into a part of the epitaxial layer, and doping an impurity that will act as a donor into another part of the epitaxial layer may be repeated any number of times.

[0038] By activating the impurities introduced into each part, the epitaxial layer 71 except for the upper layer part becomes n - The n-type pillars 23 are formed by the p-type layers 33 arranged in a line along the Z direction. The n-type pillars 23 are formed by the p-type layers 33 arranged in a line along the Z direction. The n-type pillars 23 are formed by the portions of the epitaxial layers 71 to 73 located between the p-type pillars 23. The n-type pillars 23 are formed by the portions 82, 84, and 86 of the n-type pillars 23, which are formed by the high-concentration layers 32, and the remaining portions are formed by the low-concentration layers 31.

[0039] 1, an n-type layer 25 is formed on the portion 86 of the epitaxial layer 72, and a p-type layer 26 is formed on the portion 85. Next, a p-type base layer 27 is formed on the n-type layer 25 and the p-type layer 26. Next, an n-type base layer 27 is formed on the base layer 27. + The source layer 28 is formed in the shape of p + A contact layer 29 having a shape similar to that of the semiconductor portion 20 is formed.

[0040] Next, a trench 90 is formed in the upper surface of the semiconductor portion 20. For example, the trench 90 is formed in the region directly above the n-type pillar 23, and its lower end reaches into the n-type layer 25. Next, a gate insulating film 60 is formed on the inner surface of the trench 90. Next, a gate electrode 50 is formed in the trench 90 and on the inner surface of the gate insulating film 60. The gate electrode 50 faces the n-type layer 25, the base layer 27, and the source layer 28 via the gate insulating film 60.

[0041] Next, a drain electrode 10 is formed on the lower surface of the semiconductor substrate (drain layer 21), and a source electrode 40 is formed on the source layer 28 and the contact layer 29. The drain electrode 10 is connected to the drain layer 21, and is connected to the drift layer 22, the n-type pillar 23, and the n-type layer 25 via the drain layer 21. The source electrode 40 is connected to the source layer 28 and the contact layer 29, and is connected to the base layer 27, the p-type layer 26, and the p-type pillar 24 via the contact layer 29. In this manner, the semiconductor device 1 according to this embodiment is manufactured.

[0042] Next, the effects of this embodiment will be described. In the semiconductor device 1 according to this embodiment, the semiconductor portion 20 is made of silicon carbide, which allows it to withstand a stronger electric field in the off state than a semiconductor portion made of silicon. This allows for a reduced on-resistance while maintaining a predetermined breakdown voltage. Furthermore, because the semiconductor device 1 employs a superjunction structure, in the off state, a depletion layer generated at the interface between the n-type pillar 23 and the p-type pillar 24 expands and integrates in the X direction, depleting substantially the entire SJ structure 30. This allows for a higher breakdown voltage.

[0043] In the semiconductor device 1, the low-concentration layer 31 and the high-concentration layer 32 are provided in the n-type pillar 23, so the depletion layers bond more gently during turn-off. That is, the depletion layers spread more easily in the low-concentration layer 31 than in the high-concentration layer 32. Therefore, the depletion layers spreading from both sides of the n-type pillar 23 in the X direction first contact each other in the low-concentration layer 31, and then contact each other in the high-concentration layer 32. This reduces the change in capacitance between the drain electrode 10 and the source electrode 40 during turn-off, suppressing ringing in the output current, compared to when the depletion layers contact each other simultaneously. This reduces the time required for the ringing to converge, improving the switching speed of the semiconductor device 1.

[0044] On the other hand, the p-type pillars 24 have a more uniform impurity concentration profile along the Z direction than the n-type pillars 23. This allows a non-depleted region extending in the Z direction to be maintained for a long time within the p-type pillars 24 during turn-off, ensuring a path for the discharge of holes, which have lower mobility than electrons. This also improves the switching speed of the semiconductor device 1.

[0045] Furthermore, because the semiconductor device 1 uses silicon carbide as the semiconductor material, impurities are less likely to diffuse during ion implantation and activation. Therefore, the steps shown in Figures 3(a) to 4(c) form p-type pillars 24 with a relatively uniform impurity concentration distribution, while easily creating low-concentration layers 31 and high-concentration layers 32 in the n-type pillars 23. This makes it possible to manufacture the semiconductor device 1 while minimizing an increase in the number of steps.

[0046] Furthermore, in this embodiment, since the high concentration layer 32 and the p-type layer 33 are formed by ion implantation, the amount of introduced impurities can be controlled with higher precision than when they are formed by epitaxial growth.

[0047] Furthermore, when ion implantation is performed at the same acceleration voltage, aluminum is implanted deeper than nitrogen. Therefore, a relatively deep p-type layer 33 and a relatively shallow high-concentration layer 32 can be formed by ion implantation at the same acceleration voltage. In other words, in this embodiment, since it is not necessary to bring the high-concentration layers 32 adjacent in the Z direction into contact with each other, the p-type layer 33 can be formed as thick as possible depending on the performance of the ion implantation device used, and the number of ion implantations can be reduced. As a result, the manufacturing cost of the semiconductor device 1 can be reduced.

[0048] <First Modification of the First Embodiment> FIG. 5 is a cross-sectional view showing a semiconductor device according to this modification. As shown in Figure 5, the semiconductor device 1a of this modified example differs from the semiconductor device 1 of the first embodiment (see Figure 1) in that a high-concentration layer 32 is provided only at the top and bottom of the n-type pillar 23, and no high-concentration layer 32 is provided in the center in the Z direction.

[0049] The portion of the n-type pillar 23 that is not the high-concentration layer 32 is the low-concentration layer 31. In this modification, the amount of impurity in the n-type pillar 23 and the amount of impurity in the p-type pillar 24 are also approximately equal. This is also true for other modifications described later. Other than the above, the configuration, manufacturing method, and effects of this modification are the same as those of the first embodiment.

[0050] <Second Modification of the First Embodiment> FIG. 6 is a cross-sectional view showing a semiconductor device according to this modification. 6, the semiconductor device 1b according to this modification is different from the semiconductor device 1 according to the first embodiment (see FIG. 1) in that a high-concentration layer 32 is provided only on the upper part of the n-type pillar 23. Other configurations, manufacturing methods, and effects of this modification are the same as those of the first embodiment.

[0051] <Third Modification of the First Embodiment> FIG. 7 is a cross-sectional view showing a semiconductor device according to this modification. 7, the semiconductor device 1c according to this modification is different from the semiconductor device 1 according to the first embodiment (see FIG. 1) in that a high-concentration layer 32 is provided only in the center in the Z direction of the n-type pillar 23. Other configurations, manufacturing methods, and effects of this modification are the same as those of the first embodiment.

[0052] <Fourth Modification of the First Embodiment> FIG. 8 is a cross-sectional view showing a semiconductor device according to this modification. 8, the semiconductor device 1d according to this modification is different from the semiconductor device 1 according to the first embodiment (see FIG. 1) in that a high-concentration layer 32 is provided only in the lower part of the n-type pillar 23. Other configurations, manufacturing methods, and effects of this modification are the same as those of the first embodiment.

[0053] <Second embodiment> FIG. 9 is a cross-sectional view showing the semiconductor device according to this embodiment. FIG. 10(a) is a graph showing the nitrogen concentration profile of the n-type pillar, with the nitrogen concentration on the horizontal axis and the position along line C shown in FIG. 9 on the vertical axis. FIG. 10(b) is a graph showing the aluminum concentration profile of the p-type pillar, with the aluminum concentration on the horizontal axis and the position along line D shown in FIG. 9 on the vertical axis. In the following description, the same parts as those in the first embodiment will be omitted as appropriate.

[0054] 9, the semiconductor device 2 according to this embodiment differs from the semiconductor device 1 according to the first embodiment (see FIG. 1) in that each p-type pillar 24 does not have multiple p-type layers 33 but is formed continuously. Therefore, as shown in FIG. 10(b), the aluminum concentration profile along the Z direction in the p-type pillar 24 of the semiconductor device 2 is approximately uniform.

[0055] 9, in each n-type pillar 23 of the semiconductor device 2, low-concentration layers 31 and high-concentration layers 32 are alternately arranged along the Z direction, as in the first embodiment. Therefore, as shown in FIG. 10(a), the nitrogen concentration profile along the Z direction in the n-type pillar 23 of the semiconductor device 2 is uniform in the low-concentration layers 31, similar to the p-type pillars 24, but is non-uniform with a peak in the high-concentration layers 32.

[0056] Next, a method for manufacturing the semiconductor device 2 according to this embodiment will be described. 11(a) to 11(d) and 12(a) to 12(c) are cross-sectional views showing the steps of the method for manufacturing a semiconductor device according to this embodiment.

[0057] First, as in the first embodiment, the silicon carbide is used, and the conductivity type is n. + A semiconductor substrate having a shape is prepared. Next, as shown in FIG. 11(a), a silicon carbide film having an n-type conductivity is formed on the semiconductor substrate. - An epitaxial layer 71 having a shape similar to that of the epitaxial layer 71 is formed. Impurities that act as donors, such as nitrogen, are uniformly contained in the epitaxial layer 71. The same is true for epitaxial layers 72 and 73, which will be described later.

[0058] Next, as shown in FIG. 11(b), nitrogen ions are implanted into the upper layer portion 87 of the epitaxial layer 71. Next, as shown in FIG. 11(c), a silicon carbide film having an n-type conductivity is formed on the epitaxial layer 71. - An epitaxial layer 72 having a shape similar to that of the silicon nitride film is formed. Next, as shown in FIG. 11( d ), nitrogen ions are implanted into the upper layer portion 88 of the epitaxial layer 72 .

[0059] Next, as shown in FIG. 12(a), a silicon carbide film having an n-type conductivity is formed on the epitaxial layer 72. - Next, nitrogen ions are implanted into the upper portion 89 of the epitaxial layer 73.

[0060] Similarly, the following is made of silicon carbide and has n conductivity type. - The step of forming an epitaxial layer of this shape and the step of introducing an impurity to act as a donor into the upper layer portion of this epitaxial layer may be repeated any number of times.

[0061] 12(b), holes 74 are formed in the epitaxial layers 71 to 73. The holes 74 are made to penetrate the epitaxial layers 73 and 72 and reach the inside of the epitaxial layer 71.

[0062] 12(c), an epitaxial layer 75 made of silicon carbide and having a p-type conductivity is grown in the hole 74. The epitaxial layer 75 uniformly contains impurities that act as acceptors, such as aluminum.

[0063] By activating the impurities introduced into each portion, the epitaxial layer 75 becomes the p-type pillars 24. Furthermore, the portions of the epitaxial layers 71 to 73 located between the p-type pillars 24 become the n-type pillars 23. Of the n-type pillars 23, upper layer portions 87 to 89 each become the high-concentration layer 32, and the remaining portions become the low-concentration layer 31. The subsequent steps are the same as those in the first embodiment.

[0064] According to this embodiment, the impurity concentration of the p-pillars 24 can be made more uniform than in the first embodiment. This makes it possible to more reliably ensure a path for holes to be discharged during turn-off. Other configurations, manufacturing methods, and effects of this embodiment are the same as those of the first embodiment.

[0065] According to the above-described embodiment and its modifications, a semiconductor device capable of improving switching speed and a method for manufacturing the same can be realized.

[0066] Although several embodiments and variations thereof of the present invention have been described above, these embodiments and variations thereof are presented as examples and are not intended to limit the scope of the invention. These novel embodiments and variations thereof can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and variations thereof are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments and variations thereof can also be implemented in combination with each other. [Explanation of symbols]

[0067] 1, 1a, 1b, 1c, 1d, 2: semiconductor device 10: Drain electrode 20: Semiconductor part 21: Drain layer 22: Drift layer 23: n-type pillar 24: p-pillar 25:N-type layer 26:p-type layer 27: Base layer 28: Source layer 29: Contact layer 30: Superjunction (SJ) structure 31:Low concentration layer 32: High concentration layer 33:p-type layer 40: Source electrode 50: Gate electrode 60: Gate insulating film 71, 72, 73: Epitaxial layers 74: Hole 75: Epitaxial layer 81, 82, 83, 84, 85, 86: Part 87, 88, 89: Upper part 90: Trench

Claims

1. A first electrode; a first semiconductor layer of a first conductivity type provided on the first electrode; a second conductivity type pillar of a second conductivity type provided on the first semiconductor layer; a first conductivity type pillar provided on the first semiconductor layer, the first conductivity type pillar having a low concentration layer of a first conductivity type and an average value of an impurity concentration lower than the average value of the impurity concentration of the second conductivity type pillar, and a high concentration layer of the first conductivity type and an average value of an impurity concentration higher than the average value of the impurity concentration of the second conductivity type pillar; a second semiconductor layer of a second conductivity type provided on the first conductivity type pillar; a third semiconductor layer of the first conductivity type provided on the second semiconductor layer; a second electrode connected to the second conductivity type pillar and the third semiconductor layer; A third electrode; an insulating film disposed between the second semiconductor layer and the third electrode; Equipped with a difference between a maximum value and a minimum value of the impurity concentration of the low concentration layer is smaller than a difference between a maximum value and a minimum value of the impurity concentration of the high concentration layer; a difference between the maximum and minimum values ​​of the impurity concentration of the second conductivity type pillar is greater than a difference between the maximum and minimum values ​​of the impurity concentration of the low concentration layer and is smaller than a difference between the maximum and minimum values ​​of the impurity concentration of the high concentration layer.

2. A first electrode; a first semiconductor layer of a first conductivity type provided on the first electrode; a second conductivity type pillar of a second conductivity type provided on the first semiconductor layer; a first conductivity type pillar provided on the first semiconductor layer, the first conductivity type pillar having a low concentration layer of a first conductivity type and an average value of an impurity concentration lower than the average value of the impurity concentration of the second conductivity type pillar, and a high concentration layer of the first conductivity type and an average value of an impurity concentration higher than the average value of the impurity concentration of the second conductivity type pillar; a second semiconductor layer of a second conductivity type provided on the first conductivity type pillar; a third semiconductor layer of the first conductivity type provided on the second semiconductor layer; a second electrode connected to the second conductivity type pillar and the third semiconductor layer; A third electrode; an insulating film disposed between the second semiconductor layer and the third electrode; Equipped with a plurality of the low concentration layers and a plurality of the high concentration layers are provided, and the low concentration layers and the high concentration layers are alternately arranged along a first direction from the first electrode toward the second electrode; the second conductivity type pillar has a flat impurity concentration profile along the first direction; In each of the high concentration layers, the impurity concentration profile along the first direction has one peak.

3. The semiconductor device according to claim 1 , wherein the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the low concentration layer, the high concentration layer, and the second conductivity type pillar contain silicon carbide.

4. doping a second conductivity type impurity into a first portion of an upper layer portion of a first semiconductor layer of a first conductivity type and doping a first conductivity type impurity into a second portion of the upper layer portion that is shallower than the first portion; forming an epitaxial layer of a first conductivity type on the first semiconductor layer; doping a second conductivity type impurity into a third portion of the epitaxial layer in contact with the first portion, and doping a first conductivity type impurity into a fourth portion of the epitaxial layer shallower than the third portion; forming a second semiconductor layer of a second conductivity type on the epitaxial layer; forming a third semiconductor layer of a first conductivity type on the second semiconductor layer; forming an insulating film in contact with the second semiconductor layer; forming a third electrode facing the second semiconductor layer via the insulating film; forming a first electrode connected to the first semiconductor layer and a second electrode connected to the third portion and the third semiconductor layer; A method for manufacturing a semiconductor device comprising:

5. doping a first conductivity type impurity into an upper layer portion of a first conductivity type first semiconductor layer; forming a first epitaxial layer of a first conductivity type on the first semiconductor layer; doping an impurity of a first conductivity type into an upper layer portion of the first epitaxial layer; forming a hole that penetrates the first epitaxial layer and reaches the inside of the first semiconductor layer; forming a second epitaxial layer of a second conductivity type in the hole; forming a second semiconductor layer of a second conductivity type on the first epitaxial layer; forming a third semiconductor layer of a first conductivity type on the second semiconductor layer; forming an insulating film in contact with the second semiconductor layer; forming a third electrode facing the second semiconductor layer via the insulating film; forming a first electrode connected to the first semiconductor layer and a second electrode connected to the second epitaxial layer and the third semiconductor layer; A method for manufacturing a semiconductor device comprising:

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