Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device in which a resistance film and an MIM capacitive element can be arranged in one interlayer insulating film without increasing the thickness of the interlayer insulating film.SOLUTION: A semiconductor device includes an interlayer insulating film, a resistance film, a lower electrode film and an upper electrode film arranged in the interlayer insulating film. The interlayer insulating film includes a first layer, a second layer and a third layer. The resistance film and the lower electrode film are arranged on the first layer. The resistance film and the lower electrode film are formed of the same material. The upper electrode film is opposed to the lower electrode film with the second layer interposed therebetween. The third layer covers the resistance film, the lower electrode film and the upper electrode film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] For example, Japanese Patent Laid-Open No. 2011-155192 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 has a wiring layer, an interlayer insulating film, a metal resistive film, and a via plug. The interlayer insulating film has a first layer and a second layer. The first layer covers the wiring layer. The metal resistive film is disposed on the first layer. The second layer covers the metal resistive film. The via plug is electrically connected to the wiring layer by being embedded in a via hole formed in the first layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-155192 Summary of the Invention [Problem to be solved by the invention]

[0004] An MIM (Metal Insulator Metal) capacitor element has a lower electrode film and an upper electrode film arranged opposite the lower electrode film. If such an MIM capacitor element and the metal resistive film of the semiconductor device described in Patent Document 1 are arranged in a single interlayer insulating film, the thickness of the interlayer insulating film will increase. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0005] The semiconductor device of the present disclosure includes an interlayer insulating film, and a resistive film, a lower electrode film, and an upper electrode film disposed within the interlayer insulating film. The interlayer insulating film has a first layer, a second layer, and a third layer. The resistive film and the lower electrode film are disposed on the first layer. The resistive film and the lower electrode film are formed of the same material. The upper electrode film faces the lower electrode film with the second layer interposed therebetween. The third layer covers the resistive film, the lower electrode film, and the upper electrode film. [Effects of the Invention]

[0006] According to the semiconductor device of the present disclosure, it is possible to arrange a resistive film and an MIM capacitance element in one interlayer insulating film without increasing the thickness of the interlayer insulating film. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a cross-sectional view of the semiconductor device DEV. [Figure 2] 1 is a manufacturing process diagram of the semiconductor device DEV. [Figure 3] FIG. 10 is a cross-sectional view illustrating an interlayer insulating film forming step S1. [Figure 4] FIG. 10 is a cross-sectional view illustrating a first wiring layer forming step S2. [Figure 5] FIG. 10 is a cross-sectional view illustrating a first layer forming step S3. [Figure 6] FIG. 10 is a cross-sectional view illustrating a first via plug forming step S4. [Figure 7] FIG. 10 is a cross-sectional view illustrating a first film forming step S5. [Figure 8] FIG. 10 is a cross-sectional view illustrating a second layer forming step S6. [Figure 9] FIG. 10 is a cross-sectional view illustrating a second film forming step S7. [Figure 10] FIG. 10 is a cross-sectional view illustrating a second film patterning step S8. [Figure 11] FIG. 10 is a cross-sectional view illustrating a first film patterning step S9. [Figure 12] FIG. 10 is a cross-sectional view illustrating a third layer forming step S10. [Figure 13]FIG. 10 is a cross-sectional view illustrating a second via plug forming step S11. [Figure 14] FIG. 2 is a cross-sectional view of the semiconductor device DEV1. [Figure 15] 10A to 10C are manufacturing process diagrams of the semiconductor device DEV1. [Figure 16] FIG. 10 is a cross-sectional view illustrating a first wiring layer forming step S13. [Figure 17] FIG. 10 is a cross-sectional view illustrating a second layer forming step S14. [Figure 18] FIG. 10 is a cross-sectional view illustrating a first via plug forming step S15. [Figure 19] FIG. 10 is a cross-sectional view illustrating a resistive film forming step S16. [Figure 20] FIG. 10 is a cross-sectional view illustrating a third layer forming step S17. [Figure 21] FIG. 10 is a cross-sectional view illustrating a second via plug forming step S18. [Figure 22] FIG. 2 is a cross-sectional view of the semiconductor device DEV2. DETAILED DESCRIPTION OF THE INVENTION

[0008] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant description will not be repeated. The semiconductor device according to the embodiment is referred to as a semiconductor device DEV.

[0009] (Configuration of semiconductor device DEV) The configuration of the semiconductor device DEV will be described below.

[0010] 1 is a cross-sectional view of a semiconductor device DEV. As shown in Fig. 1, the semiconductor device DEV includes interlayer insulating films ILD1 and ILD2, wiring layers WL1 and WL2, via plugs VP1, VP2, VP3, and VP4, a resistive film RF, a lower electrode film LEF, and an upper electrode film UEF.

[0011] The interlayer insulating film ILD1 covers a wiring layer (not shown). The interlayer insulating film ILD1 is made of, for example, silicon oxide (SiO2). The wiring layer WL1 is disposed on the interlayer insulating film ILD1. The wiring layer WL1 is made of, for example, aluminum (Al) or an aluminum alloy. The wiring layer WL1 is a wiring layer used, for example, as semi-global wiring. That is, the thickness of the wiring layer WL1 is greater than the thickness of a wiring layer located below the interlayer insulating film ILD1, and the wiring pitch in the wiring layer WL1 is greater than the wiring pitch in a wiring layer located below the interlayer insulating film ILD1.

[0012] The interlayer insulating film ILD2 is made of, for example, silicon oxide, and has a first layer ILD2a, a second layer ILD2b, and a third layer ILD2c.

[0013] The first layer ILD2a is disposed on the interlayer insulating film ILD1 so as to cover the wiring layer WL1. Via holes VH1 and VH2 are formed in the first layer ILD2a. The via holes VH1 and VH2 penetrate the first layer ILD2a in the thickness direction. The wiring layer WL1 is exposed from the via holes VH1 and VH2.

[0014] The via plugs VP1 and VP2 are embedded in the via holes VH1 and VH2, respectively. The bottom ends of the via plugs VP1 and VP2 are electrically connected to the wiring layer WL1. The via plugs VP1 and VP2 are formed of, for example, tungsten (W).

[0015] The resistive film RF and the lower electrode film LEF are disposed on the first layer ILD2a. The resistive film RF is electrically connected to the upper end of the via plug VP1. The lower electrode film LEF is electrically connected to the upper end of the via plug VP2. As a result, the resistive film RF and the lower electrode film LEF are electrically connected to the wiring layer WL1. The resistive film RF and the lower electrode film LEF are formed of the same material. The resistive film RF and the lower electrode film LEF are formed of, for example, a metal material. This metal material contains at least one selected from the group consisting of, for example, silicon chromium (SiCr), silicon chromium doped with carbon (C) (SiCrC), nichrome (NiCr), and tantalum nitride (TaN).

[0016] The upper electrode film UEF is disposed on the lower electrode film LEF with the second layer ILD2b interposed therebetween. The lower electrode film LEF is formed of, for example, titanium nitride (TiN). The lower electrode film LEF, the upper electrode film UEF, and the second layer ILD2b constitute an MIM capacitance element. This MIM capacitance element is disposed in the interlayer insulating film ILD2. The thickness of the second layer ILD2b is smaller than the thickness of the first layer ILD2a and the thickness of the third layer ILD2c.

[0017] The third layer ILD2c covers the resistive film RF, the lower electrode film LEF, and the upper electrode film UEF. The second layer ILD2b is preferably interposed between the resistive film RF and the lower electrode film LEF and the third layer ILD2c. This makes it possible to prevent current leakage between the lower electrode film LEF and the upper electrode film UEF along the interface between the second layer ILD2b and the third layer ILD2c.

[0018] A via hole VH3 is formed in the third layer ILD2c. The via hole VH3 penetrates the third layer ILD2c in the thickness direction. The upper electrode film UEF is exposed from the via hole VH3. A via plug VP3 is embedded in the via hole VH3. The lower end of the via plug VP3 is electrically connected to the upper electrode film UEF. The via plug VP3 is made of, for example, tungsten.

[0019] A via hole VH4 is formed in the interlayer insulating film ILD2 (first layer ILD2a, second layer ILD2b, and third layer ILD2c). The via hole VH4 penetrates the interlayer insulating film ILD2 in the thickness direction. The wiring layer WL1 is exposed from the via hole VH4. A via plug VP4 is buried in the via hole VH4. The lower end of the via plug VP4 is electrically connected to the wiring layer WL1. The via plug VP4 is made of, for example, tungsten.

[0020] The wiring layer WL2 is disposed on the interlayer insulating film ILD2 (on the third layer ILD2c). The wiring layer WL2 is formed of, for example, aluminum or an aluminum alloy. The wiring layer WL2 is a wiring layer used, for example, as a global wiring. That is, the thickness of the wiring layer WL2 is greater than the thickness of the wiring layer WL1, and the wiring pitch in the wiring layer WL2 is greater than the wiring pitch in the wiring layer WL1. The wiring layer WL2 is electrically connected to the upper end of the via plug VP3. This electrically connects the wiring layer WL2 to the upper electrode film UEF. The wiring layer WL2 is connected to the upper end of the via plug VP4. This electrically connects the wiring layer WL2 to the wiring layer WL1.

[0021] The thickness of the interlayer insulating film ILD2 is defined as thickness T. Thickness T is preferably 650 nm or more. Thickness T is the thickness of the interlayer insulating film ILD2 between the wiring layer WL1 and the wiring layer WL2. The thickness of the resistive film RF and the thickness of the lower electrode film LEF are about 5 nm, and the thickness of the second layer ILD2b is about 50 nm. The thickness of the upper electrode film UEF is, for example, 50 nm or more and 80 nm or less.

[0022] (Method of manufacturing semiconductor device DEV) A method for manufacturing the semiconductor device DEV will be described below.

[0023] 2 is a manufacturing process diagram of the semiconductor device DEV. As shown in FIG. 2, the manufacturing method of the semiconductor device DEV includes an interlayer insulating film forming step S1, a first wiring layer forming step S2, a first layer forming step S3, a first via plug forming step S4, a first film forming step S5, a second layer forming step S6, a second film forming step S7, a second film patterning step S8, and a first film patterning step S9. The manufacturing method of the semiconductor device DEV further includes a third layer forming step S10, a second via plug forming step S11, and a second wiring layer forming step S12. Note that the structure below the interlayer insulating film ILD1 may be formed by a conventionally known method, and therefore will not be described here.

[0024] 3 is a cross-sectional view illustrating the interlayer insulating film forming step S1. In the interlayer insulating film forming step S1, an interlayer insulating film ILD1 is formed as shown in FIG. In the interlayer insulating film forming step S1, first, a constituent material of the interlayer insulating film ILD1 is deposited by, for example, CVD (Chemical Vapor Deposition). Second, the deposited constituent material of the interlayer insulating film ILD1 is planarized by, for example, CMP (Chemical Vapor Deposition).

[0025] FIG. 4 is a cross-sectional view illustrating the first wiring layer forming step S2. As shown in FIG. 4, in the first wiring layer forming step S2, a wiring layer WL1 is formed. In the first wiring layer forming step S2, first, a constituent material of the wiring layer WL1 is deposited on the interlayer insulating film ILD1 by, for example, sputtering. Second, a resist pattern is formed on the deposited constituent material of the wiring layer WL1. The resist pattern is formed by exposing and developing a photoresist. Third, the deposited constituent material of the wiring layer WL1 is patterned by dry etching using the resist pattern as a mask.

[0026] 5 is a cross-sectional view illustrating the first layer formation step S3. As shown in FIG. 5, in the first layer formation step S3, a first layer ILD2a is formed. In the first layer formation step S3, first, a constituent material of the first layer ILD2a is deposited on the interlayer insulating film ILD1 by, for example, CVD. Second, the deposited constituent material of the first layer ILD2a is planarized by, for example, CMP.

[0027] FIG. 6 is a cross-sectional view illustrating the first via plug formation step S4. In the first via plug formation step S4, as shown in FIG. 6, via plugs VP1 and VP2 are formed. In the first via plug formation step S4, first, via holes VH1 and VH2 are formed in the first layer ILD2a. The via holes VH1 and VH2 are formed by dry etching using a resist pattern formed on the first layer ILD2a as a mask. The resist pattern is formed by exposing and developing photoresist. Second, by, for example, CVD, the constituent materials of the via plugs VP1 and VP2 are respectively embedded in the via holes VH1 and VH2. Third, by, for example, CMP, the constituent materials of the via plugs VP1 and VP2 that protrude from the via holes VH1 and VH2 are removed.

[0028] FIG. 7 is a cross-sectional view illustrating the first film formation step S5. As shown in FIG. 7, in the first film formation step S5, a first film FF is formed on the first layer ILD2a. The first film FF is a film formed from the constituent material of the resistive film RF. The first film FF is formed by, for example, sputtering. FIG. 8 is a cross-sectional view illustrating the second layer formation step S6. As shown in FIG. 8, in the second layer formation step S6, a second layer ILD2b is formed on the first film FF. The second layer ILD2b is formed by, for example, CVD. FIG. 9 is a cross-sectional view illustrating the second film formation step S7. As shown in FIG. 9, in the second film formation step S7, a second film SF is formed. The second film SF is a film formed from the constituent material of the upper electrode film UEF. The second film SF is formed by, for example, sputtering.

[0029] 10 is a cross-sectional view illustrating the second film patterning step S8. As shown in FIG. 10, in the second film patterning step S8, the second film SF is patterned to form the upper electrode film UEF. In the second film patterning step S8, first, a resist pattern is formed on the second film SF. The resist pattern is formed by exposing and developing a photoresist. Second, the second film SF is patterned by dry etching using the resist pattern as a mask.

[0030] At this time, the second layer ILD2b below the second film SF that is not covered by the resist pattern is also etched, but it is preferable that this second layer ILD2b is not completely removed. That is, it is preferable that the second layer ILD2b still covers the first film FF even after the second film patterning step S8 is completed.

[0031] 11 is a cross-sectional view illustrating the first film patterning step S9. As shown in FIG. 11, in the first film patterning step S9, the first film FF is patterned to form a resistive film RF and a lower electrode film LEF. In the second film patterning step S8, first, a resist pattern is formed on the first film FF (more specifically, on the second layer ILD2b remaining after the etching in the second film patterning step S8). The resist pattern is formed by exposing and developing a photoresist. Second, the first film FF is patterned by dry etching using the resist pattern as a mask.

[0032] 12 is a cross-sectional view illustrating the third layer forming step S10. As shown in FIG. 12, in the third layer forming step S10, a third layer ILD2c is formed so as to cover the resistive film RF, the lower electrode film LEF, and the upper electrode film UEF. In the third layer forming step S10, first, a constituent material of the third layer ILD2c is deposited by, for example, CVD. Second, the deposited constituent material of the third layer ILD2c is planarized by, for example, CMP.

[0033] 13 is a cross-sectional view illustrating the second via plug formation step S11. As shown in FIG. 13, in the second via plug formation step S11, via plugs VP3 and VP4 are formed. In the second via plug formation step S11, first, a via hole VH3 is formed in the third layer ILD2c, and a via hole VH4 is formed in the interlayer insulating film ILD2. The via holes VH3 and VH4 are formed by dry etching using a resist pattern formed on the interlayer insulating film ILD2 as a mask. The resist pattern is formed by exposing and developing a photoresist.

[0034] Second, the constituent material of the via plug VP3 and the constituent material of the via plug VP4 are respectively filled into the via holes VH3 and VH4 by, for example, CVD. Third, the constituent material of the via plug VP3 that protrudes from the via hole VH3 and the constituent material of the via plug VP4 that protrudes from the via hole VH4 are removed by, for example, CMP.

[0035] In the second wiring layer formation step S12, the wiring layer WL2 is formed. In the second wiring layer formation step S12, first, a constituent material of the wiring layer WL2 is deposited on the interlayer insulating film ILD2 by, for example, sputtering. Second, a resist pattern is formed on the deposited constituent material of the wiring layer WL2. The resist pattern is formed by exposing and developing a photoresist. Third, the deposited constituent material of the wiring layer WL2 is patterned by dry etching using the resist pattern as a mask. As a result, the semiconductor device DEV having the structure shown in FIG. 1 is formed.

[0036] (Effects of semiconductor device DEV) The effects of the semiconductor device DEV will be described below in comparison with a semiconductor device according to Comparative Example 1 and a semiconductor device according to Comparative Example 2. The semiconductor device according to Comparative Example 1 is referred to as semiconductor device DEV1, and the semiconductor device according to Comparative Example 2 is referred to as semiconductor device DEV2.

[0037] 14 is a cross-sectional view of the semiconductor device DEV1. As shown in Fig. 14, the semiconductor device DEV1 includes interlayer insulating films ILD1 and ILD2, wiring layers WL1 and WL2, via plugs VP1, VP3, and VP4, a resistive film RF, and an upper electrode film UEF.

[0038] In the semiconductor device DEV1, the interlayer insulating film ILD2 has a first layer ILD2d, a second layer ILD2e, and a third layer ILD2f. In the semiconductor device DEV1, the upper electrode film UEF is disposed on the wiring layer WL1 with the first layer ILD2d interposed therebetween. That is, in the semiconductor device DEV1, the wiring layer WL1 functions as the lower electrode film of the MIM capacitance element. The second layer ILD2e covers the wiring layer WL1 and the upper electrode film UEF. The first layer ILD2d is interposed between the wiring layer WL1 and the second layer ILD2e.

[0039] In the semiconductor device DEV1, a resistive film RF is disposed on the second layer ILD2e. A via hole VH5 is formed in the first layer ILD2d and the second layer ILD2e. A via plug VP1 is embedded in the via hole VH5, thereby electrically connecting the resistive film RF and the wiring layer WL1. A third layer ILD2f covers the resistive film RF. A via hole VH6 is formed in the second layer ILD2e and the third layer ILD2f. A via plug VP3 is embedded in the via hole VH6, thereby electrically connecting the upper electrode film UEF and the wiring layer WL2.

[0040] Fig. 15 is a manufacturing process diagram of the semiconductor device DEV1. As shown in Fig. 15, the manufacturing method of the semiconductor device DEV1 includes an interlayer insulating film forming step S1, a first wiring layer forming step S13, a second layer forming step S14, a first via plug forming step S15, a resistive film forming step S16, a third layer forming step S17, a second via plug forming step S18, and a second wiring layer forming step S12.

[0041] FIG. 16 is a cross-sectional view illustrating the first wiring layer formation step S13. As shown in FIG. 16, in the first wiring layer formation step S13, a wiring layer WL1, a first layer ILD2d, and an upper electrode film UEF are formed. In the first wiring layer formation step S13, first, the constituent materials of the wiring layer WL1, the first layer ILD2d, and the upper electrode film UEF are sequentially deposited. Second, the constituent material of the upper electrode film UEF is patterned by dry etching using a resist pattern formed on the constituent material of the upper electrode film UEF as a mask, thereby forming the upper electrode film UEF. After the dry etching, the first layer ILD2d remains on the constituent material of the wiring layer WL1. Third, the constituent material of the wiring layer WL1 is patterned by dry etching using a resist pattern formed on the first layer ILD2d as a mask, thereby forming the wiring layer WL1.

[0042] FIG. 17 is a cross-sectional view illustrating the second layer formation step S14. As shown in FIG. 17, in the second layer formation step S14, a constituent material of the second layer ILD2e is deposited so as to cover the wiring layer WL1 and the upper electrode film UEF, and the deposited constituent material of the second layer ILD2e is planarized by CMP or the like to form the second layer ILD2e. FIG. 18 is a cross-sectional view illustrating the first via plug formation step S15. As shown in FIG. 18, in the first via plug formation step S15, a via hole VH5 is formed in the first layer ILD2d and the second layer ILD2e, and a via plug VP1 is embedded in the via hole VH5.

[0043] FIG. 19 is a cross-sectional view illustrating the resistive film forming step S16. As shown in FIG. 19, in the resistive film forming step S16, a resistive film RF is formed on the second layer ILD2e. The resistive film RF is formed by depositing a constituent material of the resistive film RF and patterning the deposited constituent material of the resistive film RF by dry etching using a resist pattern as a mask. FIG. 20 is a cross-sectional view illustrating the third layer forming step S17. In the third layer forming step S17, as shown in FIG. 20, a third layer ILD2f is formed to cover the resistive film RF.

[0044] 21 is a cross-sectional view illustrating the second via plug forming step S18. As shown in FIG. 21, in the second via plug forming step S18, first, a via hole VH5 is formed in the second layer ILD2e and the third layer ILD2f, and a via hole VH4 is formed in the interlayer insulating film ILD2. Second, a via plug VP3 and a via plug VP4 are embedded in the via holes VH5 and VH4, respectively. The second wiring layer forming step S12 is then performed, thereby forming the semiconductor device DEV1 having the structure shown in FIG. 14.

[0045] In the semiconductor device DEV1, when the constituent material of the via plug VP1 that protrudes from the via hole VH1 is removed by CMP or the like in the first via plug formation process S15, the second layer ILD2e is scraped off, and the upper electrode film UEF may be exposed from the second layer ILD2e or the upper electrode film UEF may disappear.

[0046] Furthermore, in the semiconductor device DEV1, in the resistive film formation step S16, the constituent material of the resistive film RF is patterned by dry etching. The constituent materials of the resistive film RF, such as silicon chrome, nichrome, and tantalum nitride, are difficult to dry etch (it is difficult to ensure a selectivity with silicon oxide, the constituent material of the interlayer insulating film ILD2, during dry etching). Therefore, when the constituent material of the resistive film RF is patterned, the second layer ILD2e is also significantly dug down. As a result, the upper electrode film UEF may be exposed, lost, or damaged.

[0047] To solve this problem, it is necessary to increase the thickness of the second layer ILD2e. In order to increase the thickness of the second layer ILD2e without increasing the thickness of the interlayer insulating film ILD2, it is necessary to decrease the thickness of the third layer ILD2f. However, if the thickness of the third layer ILD2f is decreased, the resistive film RF may be exposed or disappear from the third layer ILD2f when the constituent material of the via plug VP3 that protrudes from the via hole VH5 and the constituent material of the via plug VP4 that protrudes from the via hole VH4 are removed by CMP or the like in the second via plug formation step S18. Thus, in the semiconductor device DEV1, it is necessary to increase the thickness of the interlayer insulating film ILD2 to ensure the thickness of the second layer ILD2e and the thickness of the third layer ILD2f.

[0048] Increasing the thickness of the interlayer insulating film ILD2 changes the capacitance parameters, requiring redesign of the circuit IP. In addition, increasing the thickness of the interlayer insulating film ILD2 increases the width of the via plug VP4, so the wiring pitch in the wiring layer WL1 must also be increased accordingly.

[0049] On the other hand, in the semiconductor device DEV, the constituent material of the upper electrode film UEF is a material that is easily dry-etched, so even if the thickness of the second layer ILD2b is small, exposure of the lower electrode film LEF (first film FF) or damage to the lower electrode film LEF is unlikely to occur during dry etching in the second film patterning step S8. Therefore, in the semiconductor device DEV, the thickness of the third layer ILD2c can be ensured without increasing the thickness of the interlayer insulating film ILD2, and exposure or disappearance of the upper electrode film UEF can be prevented when the second via plug formation step S11 is performed. In this way, according to the semiconductor device DEV, it is possible to arrange an MIM capacitance element in the interlayer insulating film ILD2 without increasing the thickness of the interlayer insulating film ILD2.

[0050] 22 is a cross-sectional view of the semiconductor device DEV2. As shown in Fig. 22, the semiconductor device DEV2 includes interlayer insulating films ILD1 and ILD2, wiring layers WL1 and WL2, via plugs VP3, VP4, and VP5, a resistive film RF, and an upper electrode film UEF.

[0051] In the semiconductor device DEV2, the interlayer insulating film ILD2 has a first layer ILD2g and a second layer ILD2h. In the semiconductor device DEV2, the resistive film RF and the upper electrode film UEF are formed of the same material and are disposed on the first layer ILD2g. In the semiconductor device DEV2, the wiring layer WL1, the upper electrode film UEF, and the first layer ILD2g located between the wiring layer WL1 and the upper electrode film UEF constitute an MIM capacitance element. That is, in the semiconductor device DEV2, the wiring layer WL1 functions as a lower electrode film. The second layer ILD2h is disposed on the first layer ILD2g so as to cover the resistive film RF and the upper electrode film UEF.

[0052] In the semiconductor device DEV2, via holes VH7 and VH8 are formed in the second layer ILD2h. A via plug VP5 is embedded in the via hole VH7, thereby electrically connecting the resistive film RF and the wiring layer WL2. A via plug VP3 is embedded in the via hole VH8, thereby electrically connecting the upper electrode film UEF and the wiring layer WL2.

[0053] As described above, the material of the resistive film RF is a material that cannot have a large selectivity with respect to the material of the dry-etching interlayer insulating film ILD2. Therefore, in the semiconductor device DEV2, when the via holes VH7 and VH8 are formed by dry etching, the resistive film RF and the upper electrode film UEF, which is made of the same material as the resistive film RF, are also etched, and the via holes VH7 and VH8 may reach the resistive film RF and the upper electrode film UEF, respectively. As a result, the contact between the via plug VP7 and the resistive film RF and the contact between the via plug VP3 and the upper electrode film UEF becomes insufficient, resulting in increased contact resistance.

[0054] Furthermore, in the semiconductor device DEV2, the thickness of the first layer ILD2g constituting the dielectric film of the MIM capacitance element cannot be increased in order to ensure the characteristics of the MIM capacitance element, and therefore the wiring layer WL1 may be exposed by dry etching when forming the resistive film RF and the upper electrode film UEF, which may result in damage to the wiring layer WL1.

[0055] On the other hand, in the semiconductor device DEV, the upper electrode film UEF is formed of a material that easily ensures a selectivity with the constituent material (silicon oxide) of the interlayer insulating film ILD2 during dry etching, so the dry etching for forming the via hole VH3 is likely to stop at the upper electrode film UEF. Also, in the semiconductor device DEV, the upper electrode film UEF is not formed of the same material as the resistive film RF, so the contact resistance with the via plug VP3 is unlikely to increase. Furthermore, in the semiconductor device DEV, the first layer ILD2a does not constitute the dielectric film of the MIM capacitance element, so the thickness of the first layer ILD2a can be ensured, and even if the first layer ILD2a is dug down by dry etching when forming the resistive film RF and the lower electrode film LEF, the wiring layer WL1 is unlikely to be exposed.

[0056] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0057] DEV, DEV1, DEV2 semiconductor device, FF first film, ILD1 interlayer insulating film, ILD2 interlayer insulating film, ILD2a first layer, ILD2b second layer, ILD2c third layer, ILD2d first layer, ILD2e second layer, ILD2f third layer, ILD2g first layer, ILD2h second layer, LEF lower electrode film, RF resistive film, S1 interlayer insulating film forming step, S2 first wiring layer forming step, S3 first layer forming step, S4 first via plug forming step, S5 first film forming step, S6 second layer forming step, S7 second film forming step, S8 second film patterning step, S9 first film patterning step, S10 third layer forming step, S11 second via plug forming step, S12 second wiring layer forming step, S13 first wiring layer forming step, S14 second layer forming step, S15 First via plug formation process, S16 resistive film formation process, S17 third layer formation process, S18 second via plug formation process, SF second film, T thickness, UEF upper electrode film, VH1, VH2, VH3, VH4, VH5, VH6, VH7, VH8 via holes, VP1, VP2, VP3, VP4, VP5 via plugs, WL1, WL2 wiring layers.

Claims

1. an interlayer insulating film; a resistive film, a lower electrode film, and an upper electrode film disposed in the interlayer insulating film; the interlayer insulating film has a first layer, a second layer, and a third layer; the resistive film and the lower electrode film are disposed on the first layer, the resistive film and the lower electrode film are formed of the same material, the upper electrode film faces the lower electrode film with the second layer interposed therebetween, the third layer covers the resistive film, the lower electrode film, and the upper electrode film; a first wiring layer; a second wiring layer; a first via plug; a second via plug; the first layer covers the first wiring layer, the first via plug is formed in the first layer, the lower electrode film is electrically connected to the first wiring layer by the first via plug; the second wiring layer is disposed on the third layer, the second via plug is formed in the third layer, the upper electrode film is electrically connected to the second wiring layer by the second via plug; the resistive film is made of a metal material, The semiconductor device, wherein the metal material is silicon chromium doped with carbon.

2. 2. The semiconductor device according to claim 1, wherein said second layer is interposed between said third layer and said lower electrode film.

3. The semiconductor device according to claim 1 , wherein said resistive film and said lower electrode film are disposed spaced apart from each other.

4. 2. The semiconductor device according to claim 1, wherein said upper electrode film is made of titanium nitride.

5. 2. The semiconductor device according to claim 1, wherein said interlayer insulating film is made of silicon oxide.

6. 2. The semiconductor device according to claim 1, wherein said first wiring layer and said second wiring layer are made of aluminum or an aluminum alloy.

7. 2. The semiconductor device according to claim 1, wherein the thickness of said resistive film is the same as the thickness of said lower electrode film.

8. The semiconductor device according to claim 1 , wherein the thickness of said second layer is smaller than the thickness of said first layer and the thickness of said third layer.

9. 2. The semiconductor device according to claim 1, wherein said interlayer insulating film has a thickness of 650 nm or more.

10. 2. The semiconductor device according to claim 1, wherein said lower electrode film, said upper electrode film, and said second layer constitute an MIM capacitor.

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