Semiconductor device and power conversion device using the same

Abstract

To provide a semiconductor device capable of sufficiently suppressing high-frequency vibration caused by resonance between semiconductor chips which is generated due to mutual inductance of a plurality of bonding wires for connecting between a metal circuit pattern on an insulation substrate and the semiconductor chips, in a semiconductor device having a plurality of semiconductor chips connected in parallel.SOLUTION: A semiconductor device having a first semiconductor chip and a second semiconductor chip connected in parallel with each other, comprises: a first bonding wire connecting between a wiring pattern and the first semiconductor chip; a second bonding wire connecting between the wiring pattern and the second semiconductor chip; and a third bonding wire and a fourth bonding wire directly connecting between the first semiconductor chip and the second semiconductor chip. In a plan view of the semiconductor device, the third and fourth bonding wires cross each other.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present invention relates to the structure of a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor module having a plurality of semiconductor chips connected in parallel. [Background technology]

[0002] Today, power devices such as diodes and IGBTs (Insulated Gate Bipolar Transistors) play an important role in a wide range of fields, including electricity, transportation, communications, and home appliances. As key components used in power supplies and power conversion equipment, power devices have become increasingly diverse in type, with higher voltage resistance, larger capacity, and more powerful and functional.

[0003] Recently, in response to the trend toward inverter devices with expanding applications, there has been a demand for even greater capacity and performance.One method for achieving this is to use large-capacity semiconductor modules, in which multiple semiconductor chips such as diodes and IGBTs are placed on a single insulating substrate and connected in parallel to form a single module.

[0004] In a semiconductor module having multiple semiconductor chips connected in parallel as described above, depending on the operating conditions, vibrations due to resonance between the semiconductor chips can occur due to the mutual inductance of the multiple bonding wires connecting the metal circuit pattern on the insulating substrate to the semiconductor chips. For example, vibrations are likely to occur during reverse recovery of a diode or when an IGBT is turned off. High-frequency vibrations are also likely to occur when operating at low voltages and low temperatures. Vibrations due to resonance between semiconductor chips have a higher frequency than other vibrations, and they can propagate through space, posing a risk of interference with various communication devices and leading to power loss in the semiconductor module itself.

[0005] As background art in this technical field, there is, for example, technology such as that disclosed in Patent Document 1. Patent Document 1 discloses a power module in which a plurality of diodes D1 to D4 are arranged in a row so that the lengths of the Al wires L1 to L4 are the same, and Al wires L25 and L26 are added to connect the diodes D1 and D2, and the diodes D3 and D4, respectively, thereby shifting the frequency band of high-frequency vibration to a band that does not pose a practical problem, thereby reducing radiation noise (Figure 10 and paragraphs

[0024] -

[0028] of Patent Document 1). Furthermore, Patent Document 2 discloses a method for designing a semiconductor power module that does not oscillate when turned off by adjusting the wiring length or other factors to set values ​​of inductance L and capacitance C of the resonant circuit that do not establish oscillation conditions (see paragraph

[0043] of Patent Document 2, etc.). Furthermore, Patent Document 3 discloses a semiconductor switch device that suppresses current oscillations during turn-off by inserting a ferrite core, which is a high-frequency loss element, somewhere in the wiring path between the gate wiring branch point and the gate pad (see, for example, Figure 1 and paragraphs

[0029] and

[0049] of Patent Document 3). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-38803 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-229383 [Patent Document 3] Japanese Patent Application Laid-Open No. 2001-185679 Summary of the Invention [Problem to be solved by the invention]

[0007] However, although Patent Document 1 can shift the frequency band of high-frequency vibration to a band that does not pose a practical problem, it is believed that the effect of reducing high-frequency vibration between diodes is limited.

[0008] Furthermore, in the above-mentioned Patent Document 2, certain restrictions arise in the design of the module, such as the need to adjust the wiring length.

[0009] Furthermore, in the above-mentioned Patent Document 3, it is necessary to provide a ferrite core, which is a high-frequency loss element, on the substrate, which is disadvantageous in terms of miniaturization and cost of the semiconductor device.

[0010] Therefore, the object of the present invention is to provide a semiconductor device having a plurality of semiconductor chips connected in parallel, which can sufficiently suppress high-frequency vibrations caused by resonance between semiconductor chips due to the mutual inductance of a plurality of bonding wires connecting the semiconductor chips to a metal circuit pattern on an insulating substrate, and a power conversion device using the same. [Means for solving the problem]

[0011] In order to solve the above problem, the present invention provides a semiconductor device in which a first semiconductor chip and a second semiconductor chip are connected in parallel, the semiconductor device comprising: a first bonding wire connecting a wiring pattern to the first semiconductor chip; a second bonding wire connecting the wiring pattern to the second semiconductor chip; and a third bonding wire and a fourth bonding wire directly connecting the first semiconductor chip and the second semiconductor chip, wherein the third bonding wire and the fourth bonding wire intersect when the semiconductor device is viewed in a plane. [Effects of the Invention]

[0012] According to the present invention, it is possible to realize a semiconductor device having a plurality of semiconductor chips connected in parallel, which can sufficiently suppress high-frequency vibrations caused by resonance between the semiconductor chips due to the mutual inductance of a plurality of bonding wires connecting the semiconductor chips to a metal circuit pattern on an insulating substrate, and a power conversion device using the same.

[0013] This improves the reliability of the semiconductor device and reduces loss.

[0014] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. [Figure 2A] 1 is a plan view of a semiconductor device according to a first embodiment of the present invention. [Figure 2B] 2B is a diagram conceptually showing the mutual inductance of the bonding wires crossing each other in FIG. 2A. FIG. [Figure 3] FIG. 2C is a diagram showing a modification of FIGS. 2A and 2B. [Figure 4A] FIG. 10 is a diagram showing an example of conventional bonding wire connections. [Figure 4B] 1A and 1B are diagrams illustrating examples of bonding wire connections between semiconductor chips. [Figure 4C] 1A and 1B are diagrams illustrating examples of bonding wire connections between semiconductor chips. [Figure 4D] 1A and 1B are diagrams illustrating examples of bonding wire connections between semiconductor chips. [Figure 4E] 1A and 1B are diagrams illustrating examples of bonding wire connections between semiconductor chips. [Figure 4F] FIG. 10 is a diagram showing the relationship between the angle AOB of the bonding wire between the semiconductor chips and the mutual inductance IBC between the semiconductor chips. [Figure 5A] FIG. 10 is a plan view of a semiconductor chip according to a second embodiment of the present invention. [Figure 5B] FIG. 5B is a diagram showing a modification of FIG. 5A. [Figure 5C] FIG. 10 is a plan view of a semiconductor device according to a second embodiment of the present invention. [Figure 6A] FIG. 10 is a perspective view showing a state in which a conventional semiconductor device is mounted using bonding wires. [Figure 6B] FIG. 1 is a diagram conceptually illustrating a problem in a conventional semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and detailed description of overlapping parts will be omitted. [Example]

[0017] A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 4F, 6A and 6B.

[0018] FIG. 1 is a cross-sectional view of a semiconductor device according to this embodiment. FIGS. 2A and 2B are plan views of the semiconductor device according to this embodiment. FIG. 2A shows the bonding wire crossing angles A and B, which will be described below, and FIG. 2B conceptually illustrates the inductance interaction between the two bonding wires 8a and 8b in FIG. 2A. FIG. 3 is a diagram illustrating a modification of FIGS. 2A and 2B. FIGS. 4A to 4E are diagrams illustrating examples of bonding wire connections. FIG. 4F is a diagram illustrating the relationship between the bonding wire angle AOB between semiconductor chips and the mutual inductance IBC between semiconductor chips. Points A to E in FIG. 4F correspond to FIGS. 4A to 4E, respectively. FIGS. 6A and 6B illustrate the mounting state of a conventional semiconductor device using bonding wires and the problems associated with this mounting state, shown to facilitate understanding of the configuration of the present invention.

[0019] First, the configuration of a conventional semiconductor device and its problems will be described with reference to FIGS. 6A and 6B.

[0020] 6A, in a conventional semiconductor device, semiconductor chips 4a and 4b are mounted on a metal circuit pattern 6b formed on an insulating substrate (not shown). The semiconductor chips 4a and 4b are joined to the metal circuit pattern 6b with a joining material such as solder. Each pad electrode 15 of the semiconductor chips 4a and 4b is electrically connected to the metal circuit pattern 6a, which is also formed on the insulating substrate, by bonding wires 8a and 8b.

[0021] The semiconductor chips 4a and 4b are, for example, bipolar elements such as diodes and IGBTs. The pad electrode 15 is an anode pad in the case of a diode, and an emitter pad in the case of an IGBT.

[0022] As shown in Figures 6A and 6B, the bonding wires 8 connecting each pad electrode 15 of the semiconductor chips 4a, 4b to the metal circuit pattern 6a are generally arranged in a straight line connecting the semiconductor chips 4a, 4b and the metal circuit pattern 6a over the shortest distance so as to minimize electrical resistance, and are connected by wire bonding.

[0023] Conventional semiconductor devices are configured as described above, and as shown in FIG. 6B, a resonant loop is formed due to the interaction of the inductances of the bonding wires 8a and 8b closest to the adjacent semiconductor chips, causing high-frequency vibrations between the semiconductor chips 4a and 4b.

[0024] As described above, this high frequency vibration between the semiconductor chips 4a and 4b propagates through space and interferes with various communication devices, causing adverse effects, and also leading to power loss in the semiconductor device itself.

[0025] Next, the configuration and effects of the semiconductor device of this embodiment will be described with reference to FIGS. 1 to 4F.

[0026] As shown in FIG. 1, the semiconductor device of this embodiment is configured as a semiconductor module 1 having a plurality of semiconductor chips 4 connected in parallel.

[0027] As shown in FIG. 1, the semiconductor module 1 of this embodiment mainly comprises a plurality of insulating substrates 3 arranged on a single base plate 2 and a plurality of semiconductor chips 4 mounted on each of the plurality of insulating substrates 3.

[0028] A metal pattern 5 is formed on the lower surface of the insulating substrate 3, and the metal pattern 5 is joined to the base plate 2 by solder 7. A metal circuit pattern 6 is formed on the upper surface of the insulating substrate 3, and the semiconductor chip 4 is joined to the metal circuit pattern 6 by solder 7.

[0029] The semiconductor chips 4 are each connected by bonding wires 8 to the metal circuit patterns 6 on which no semiconductor chips 4 are mounted, and are further connected to the output terminals 13 and auxiliary terminals 14 via the metal circuit patterns 6.

[0030] The insulating substrate 3, the semiconductor chip 4, and the bonding wires 8 are covered with a resin case 9, and the case 9 is filled with an insulating resin (gel) 10, thereby forming the semiconductor module 1.

[0031] A heat sink 11 is connected via solder or grease 12 to the underside of the base plate 2, i.e., the surface opposite to the surface on which the insulating substrates 3 are arranged, and heat generated in conjunction with the operation of the semiconductor chips 4 is dissipated by heat exchange with the heat sink 11. The base plate 2 is a support member that supports the multiple insulating substrates 3, and also functions as a heat spreader (heat sink).

[0032] Here, in the semiconductor device of this embodiment, as shown in Figure 2A, in addition to the wiring using conventional bonding wires shown in Figure 6B, two bonding wires are further provided to connect the semiconductor chips 4a and 4b to each other, and the two bonding wires are arranged so that they cross each other when the semiconductor device is viewed in a plane.

[0033] In other words, the semiconductor device of this embodiment is a semiconductor device in which semiconductor chips 4a and 4b are connected in parallel, and is provided with a bonding wire that connects the metal circuit pattern 6a, which is a wiring pattern on the insulating substrate 3, to the semiconductor chip 4a, a bonding wire that connects the metal circuit pattern 6a to the semiconductor chip 4b, and bonding wires 8a and 8b that directly connect the semiconductor chips 4a and 4b, and is configured so that the bonding wire 8a and the bonding wire 8b intersect when the semiconductor device is viewed in a plane.

[0034] The two bonding wires that intersect with each other form an intersection angle A (or B). The intersection angle A is the angle in the arrangement direction of the semiconductor chips 4a and 4b, and the intersection angle B is the angle in the direction perpendicular to the arrangement direction of the semiconductor chips 4a and 4b. Therefore, A + B = 180°.

[0035] In this embodiment, the two bonding wires are arranged to cross each other so that the crossing angle A is 60° or more, and more preferably 90° or more.

[0036] By setting the crossing angle of the two intersecting bonding wires to 60° or more or 90° or more, the interaction of the inductances of the two bonding wires, as shown in Figure 2B, makes it possible to sufficiently suppress high-frequency vibrations due to resonance between the semiconductor chips 4a and 4b.

[0037] As shown in FIG. 3, by setting the crossing angle A of the two bonding wires that cross each other to about 90°, the mutual inductance between the bonding wires 8a and 8b can be made almost zero.

[0038] The intersection angle A will be described in more detail with reference to FIGS. 4A to 4F.

[0039] Fig. 4A shows wiring using the conventional bonding wire shown in Fig. 6B. As shown in Fig. 4B, when one bonding wire is added to directly connect the semiconductor chips 4a and 4b, the mutual inductance between the semiconductor chips 4a and 4b is reduced, but this may not be sufficient depending on the operating conditions of the semiconductor chips 4a and 4b.

[0040] Furthermore, as shown in Figure 4C, if two bonding wires that directly connect the semiconductor chips 4a and 4b are added without crossing each other, the mutual inductance between the semiconductor chips 4a and 4b can be reduced, but increasing the number of wires from one to two cannot halve the mutual inductance between the semiconductor chips 4a and 4b.

[0041] On the other hand, as shown in FIG. 4D, when the crossing angle A of the two bonding wires that cross each other is set to 60° or more, the mutual inductance between the semiconductor chips 4a and 4b can be more effectively suppressed.

[0042] Furthermore, as shown in FIG. 4E, when the intersection angle A is greater than 120°, the mutual inductance between the semiconductor chips 4a and 4b is stable and does not decrease any further.

[0043] From the above, it is preferable that the crossing angle A of two bonding wires that cross each other is 60° or more and 120° or less, and more preferably 90° or more and 120° or less. [Example]

[0044] Second Embodiment A semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 5A to 5C.

[0045] Fig. 5A is a plan view of a semiconductor chip of the semiconductor device of this embodiment, Fig. 5B is a diagram showing a modification of Fig. 5A, and Fig. 5C is a plan view of the semiconductor device of this embodiment.

[0046] In this embodiment, a more specific configuration example of the semiconductor device shown in FIG. 2A will be described.

[0047] When IGBTs are used for the semiconductor chips 4a and 4b, the semiconductor chip 4 has a configuration as shown in Fig. 5A. The semiconductor chip 4 has an emitter pad 16 and a gate pad 17 formed as pad electrodes 15, and terminations 18 for maintaining a breakdown voltage are provided around them.

[0048] When diodes are used for the semiconductor chips 4a and 4b, the semiconductor chip 4 has a configuration as shown in Fig. 5B. The semiconductor chip 4 has an anode pad 19 formed as a pad electrode 15, and a termination 18 for maintaining a breakdown voltage is provided around the anode pad 19.

[0049] Fig. 5C shows a configuration example using an IGBT. As shown in Fig. 5C, the semiconductor device of this embodiment includes an insulating substrate (reference numeral 3 in Fig. 1) on which semiconductor chips 4a and 4b are mounted, and a metal circuit pattern 6a is disposed on the insulating substrate 3 so as to extend along the arrangement direction of the semiconductor chips 4a and 4b. A bonding wire connecting the metal circuit pattern 6a to the semiconductor chip 4a and a bonding wire connecting the metal circuit pattern 6b to the semiconductor chip 4b are disposed approximately parallel to each other.

[0050] The metal circuit patterns 6a, 6b, 6c, and 6d are an emitter pattern, a collector pattern, an emitter auxiliary pattern, and a gate pattern, respectively.

[0051] In this embodiment, by specifying the crossing angle A of the two bonding wires that cross each other in the same manner as in embodiment 1, the interaction of the inductances of the two bonding wires can sufficiently suppress high-frequency vibrations due to resonance between the semiconductor chips 4a and 4b.

[0052] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0053] 1...Semiconductor module 2...Base plate (heat spreader) 3...Insulating substrate 4, 4a, 4b...Semiconductor chip 5...Metal pattern 6, 6a, 6b, 6c, 6d...Metal circuit patterns 7...Solder 8, 8a, 8b...Bonding wire 9…Case 10...Insulating resin (gel) 11...Heat sink 12...Grease 13...Output terminal 14...Auxiliary terminal 15...Pad electrode 16...Emitter pad 17...Gate pad 18...Termination 19...Anode pad A, B...Intersection angle AOB: Angle of bonding wire between semiconductor chips (A) IBC: Mutual inductance between semiconductor chips

Claims

1. In a semiconductor device in which a first semiconductor chip and a second semiconductor chip are connected in parallel, a first bonding wire connecting a wiring pattern and the first semiconductor chip; a second bonding wire connecting the wiring pattern and the second semiconductor chip; a third bonding wire and a fourth bonding wire that directly connect the first semiconductor chip and the second semiconductor chip; The semiconductor device is characterized in that, when the semiconductor device is viewed from above, the third bonding wire and the fourth bonding wire cross each other.

2. 2. The semiconductor device according to claim 1, 10. A semiconductor device comprising: a first semiconductor chip and a second semiconductor chip; a bonding wire and a bonding wire, the bonding wire and the bonding wire intersecting each other at an angle of 60 degrees or more in an arrangement direction of the first semiconductor chip and the second semiconductor chip;

3. 3. The semiconductor device according to claim 2, The semiconductor device is characterized in that the crossing angle is 90° or more.

4. 3. The semiconductor device according to claim 2, The semiconductor device is characterized in that the crossing angle is equal to or greater than 60° and equal to or less than 120°.

5. 4. The semiconductor device according to claim 3, The semiconductor device is characterized in that the crossing angle is equal to or greater than 90° and equal to or less than 120°.

6. 2. The semiconductor device according to claim 1, 1. A semiconductor device, wherein the first semiconductor chip and the second semiconductor chip are bipolar elements.

7. 2. The semiconductor device according to claim 1, an insulating substrate on which the first semiconductor chip and the second semiconductor chip are mounted; the wiring pattern is disposed on the insulating substrate so as to extend along an arrangement direction of the first semiconductor chip and the second semiconductor chip; The semiconductor device is characterized in that the first bonding wire and the second bonding wire are arranged substantially parallel to each other.

8. A power conversion device comprising the semiconductor device according to claim 1 .

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