Chip and method (chip supporting constant-time program control of nested loops)

Abstract

To provide a chip supporting constant time program control of a nested loop.SOLUTION: A chip comprises at least one arithmetic-logic computing unit and a controller operatively coupled to the at least one arithmetic-logic computing unit. The controller, according to a program configuration comprising at least one inner loop and at least one outer loop, causes the at least one arithmetic computing unit to execute a plurality of operations. A first loop counter is configured to count the number of executed iterations of the outer loop, and a second loop counter is configured to count the number of executed iterations of the inner loop. The controller, according to a first indication for indicating whether the first loop counter corresponds to a last iteration and a second indication for indicating whether the second loop counter corresponds to a last iteration, alternatively increments, resets, or maintains each of the first and second loop counters.SELECTED DRAWING: Figure 24

Description

[Technical Field]

[0001] Embodiments of the present disclosure relate to neural network processing, and more particularly to constant-time program control of nested loops. Summary of the Invention [Problem to be solved by the invention]

[0002] A chip is provided that supports constant-time program control of nested loops. [Means for solving the problem]

[0003] According to an embodiment of the present disclosure, a chip for calculating neural activity values ​​is provided. In various embodiments, the chip includes at least one arithmetic logic unit and a controller operably coupled to the at least one arithmetic logic unit. The controller is configured according to a program configuration, the program configuration including at least one inner loop and at least one outer loop. The controller is configured to cause the at least one arithmetic logic unit to perform a plurality of operations according to the program configuration. The controller is configured to maintain at least a first loop counter and a second loop counter, the first loop counter configured to count the number of executed iterations of the at least one outer loop, and the second loop counter configured to count the number of executed iterations of the at least one inner loop. The controller is configured to provide a first indicator indicating whether the first loop counter corresponds to the last iteration and a second indicator indicating whether the second loop counter corresponds to the last iteration. The controller is configured to alternatively increment, reset, or maintain each of the first and second loop counters according to the first and second indicators.

[0004] According to embodiments of the present disclosure, a method and computer program product are provided for constant-time program control of nested loops. In various embodiments, a controller is configured according to a program configuration, the program configuration including at least one inner loop and at least one outer loop. At least one arithmetic calculation unit executes a plurality of operations according to the program configuration. The controller maintains at least a first loop counter and a second loop counter, the first loop counter configured to count the number of executed iterations of the at least one outer loop, and the second loop counter configured to count the number of executed iterations of the at least one inner loop. The controller provides a first indicator indicating whether the first loop counter corresponds to the last iteration and a second indicator indicating whether the second loop counter corresponds to the last iteration. The second loop counter is alternatively incremented, reset, or maintained according to the first and second indicators. [Brief explanation of the drawings]

[0005] [Figure 1] 1 illustrates a neural core according to an embodiment of the present disclosure. [Figure 2] 1 illustrates an exemplary inference processing unit (IPU) according to an embodiment of the present disclosure. [Figure 3] 1 illustrates a multi-core inference processing unit (IPU) according to an embodiment of the present disclosure. [Figure 4] 1 illustrates a neural core and associated network according to an embodiment of the present disclosure. [Figure 5] 1 illustrates an exemplary loop and nested loops according to an embodiment of the present disclosure. [Figure 6] 1 illustrates another exemplary loop according to an embodiment of the present disclosure. [Figure 7] 1 illustrates an exemplary nested loop according to an embodiment of the present disclosure. [Figure 8] 1 illustrates an exemplary loop check condition according to an embodiment of the present disclosure. [Figure 9]1 illustrates an exemplary CPU loop instruction according to an embodiment of the present disclosure. [Figure 10] 1 illustrates an exemplary CPU loop instruction according to an embodiment of the present disclosure. [Figure 11] 1 illustrates an exemplary static loop unrolling technique according to an embodiment of the present disclosure. [Figure 12] 1 illustrates an exemplary loop merging technique according to an embodiment of the present disclosure. [Figure 13] 1 illustrates an exemplary loop counter according to an embodiment of the present disclosure. [Figure 14] 1 illustrates an exemplary parallel loop counter according to an embodiment of the present disclosure. [Figure 15A] 1 illustrates another exemplary parallel loop counter according to an embodiment of the present disclosure. [Figure 15B] 1 illustrates another exemplary parallel loop counter according to an embodiment of the present disclosure. [Figure 16] 1 illustrates an exemplary loop trace according to an embodiment of the present disclosure. [Figure 17] 1 illustrates another exemplary multiple loop counter according to an embodiment of the present disclosure. [Figure 18A] 1 illustrates nested counters for an exemplary parallel loop according to an embodiment of the present disclosure. [Figure 18B] 1 illustrates nested counters for an exemplary parallel loop according to an embodiment of the present disclosure. [Figure 19A] 3 illustrates an exemplary program counter and loop counter according to an embodiment of the present disclosure. [Figure 19B] 3 illustrates an exemplary program counter and loop counter according to an embodiment of the present disclosure. [Figure 20A] 1 illustrates an exemplary loop counter definition according to an embodiment of the present disclosure. [Figure 20B] 1 illustrates an exemplary loop counter definition according to an embodiment of the present disclosure. [Figure 21A] 1 illustrates an exemplary parallel loop without a program counter, according to an embodiment of the present disclosure. [Figure 21B] 1 illustrates an exemplary parallel loop without a program counter according to an embodiment of the present disclosure. [Figure 22] 1 illustrates an exemplary comparison of a parallel loop and a CPU loop according to an embodiment of the present disclosure. [Figure 23] 1 illustrates an exemplary loop reconfiguration according to an embodiment of the present disclosure. [Figure 24] 1 illustrates a method for constant-time program control of nested loops according to an embodiment of the present disclosure. [Figure 25] 1 illustrates a computing node according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0006] An artificial neuron is a mathematical function whose output is a nonlinear function of a linear combination of its inputs. Two neurons are connected where the output of one is an input to the other. A weight is a scalar value that encodes the strength of the connection between the output of one neuron and the input of another.

[0007] A neuron calculates an output, called an activation value, by applying a nonlinear activation function to a weighted sum of its inputs. A weighted sum is an intermediate result calculated by multiplying each input by its corresponding weight and accumulating the products. A partial sum is a weighted sum of a subset of the inputs. The weighted sum of all inputs can be calculated incrementally by accumulating one or more partial sums.

[0008] A neural network is a collection of one or more neurons. Neural networks are often divided into groups of neurons called layers. A layer is a collection of one or more neurons that all receive input from the same layer and all send output to the same layer, typically performing a similar function. An input layer is a layer that receives input from sources outside the neural network. An output layer is a layer that sends output to targets outside the neural network. All other layers are intermediate processing layers. A multilayer neural network is a neural network with more than one layer. A deep neural network is a multilayer neural network with many layers.

[0009] A tensor is a multidimensional array of numbers. A tensor block is a contiguous subarray of the elements of a tensor.

[0010] Each neural network layer is associated with a parameter tensor V, a weight tensor W, an input data tensor X, an output data tensor Y, and an intermediate data tensor Z. The parameter tensor contains all of the parameters that control the neuron activation function σ in the layer. The weight tensor contains all of the weights that connect inputs to the layer. The input data tensor contains all of the data that the layer consumes as input. The output data tensor contains all of the data that the layer computes as output. The intermediate data tensor contains any data that the layer generates as intermediate computations, such as partial sums.

[0011] The data tensors for a layer (input, output, and intermediate) can be three-dimensional, with the first two dimensions interpreted as encoding spatial location and the third dimension interpreted as encoding a different feature. For example, if the data tensor represents a color image, the first two dimensions encode the vertical and horizontal coordinates within the image, and the third dimension encodes the color at each location. Because every element of the input data tensor X can be connected to every neuron by a separate weight, the weight tensor W generally has six dimensions, concatenating the three dimensions of the input data tensor (input row a, input column b, input feature c) and the three dimensions of the output data tensor (output row i, output column j, output feature k). The intermediate data tensor Z has the same shape as the output data tensor Y. The parameter tensor V concatenates the three output data tensor dimensions with an additional dimension o that indexes the parameters of the activation function σ. In some embodiments, the activation function σ does not require any additional parameters, in which case no additional dimensions are required. However, in some embodiments, the activation function σ requires at least one additional parameter that appears in the additional dimension o.

[0012] The elements of the output data tensor Y of a layer can be calculated as in Equation 1, where the neuron activation function σ is composed of a vector of activation function parameters V[i,j,k,:], and the weighted sum Z[i,j,k] can be calculated as in Equation 2.

number

number

[0013] For simplicity of notation, we can refer to the weighted sum in Equation 2 as the output, which is equivalent to using a linear activation function Y[i,j,k]=σ(Z[i,j,k])=Z[i,j,k], with the understanding that the same description applies without loss of generality when different activation functions are used.

[0014] In various embodiments, the computation of the output data tensor as described above is decomposed into smaller problems, each of which can then be solved in parallel on one or more neural cores, or on one or more cores of a conventional multi-core system.

[0015] It will be understood from the above that neural networks are parallel structures. Neurons in a given layer receive elements x from one or more layers or other inputs. i Each neuron receives an input X with an element w i and a weight W with a weight b. In various embodiments, the weighted sum of the inputs is adjusted by a bias b, and the result is then passed to the nonlinear F(·). For example, the activation value of a single neuron can be calculated as y=F(b+Σx i w i ) can be expressed as

[0016] Because all neurons in a given layer receive input from the same layer and calculate their output independently, neuron activations can be calculated in parallel. This aspect of the neural network as a whole accelerates the overall computation by performing the computation on parallel distributed cores. Furthermore, vector operations can be calculated in parallel within each core. Even in the case of recurrent inputs, such as when a layer projects back onto itself, all neurons are still updated simultaneously. In effect, the recurrent connections are delayed to match subsequent inputs to the layer.

[0017] Referring now to FIG. 1, a neural core according to an embodiment of the present disclosure is shown. Neural core 100 is a tileable computational unit that computes one block of output tensors. Neural core 100 has M inputs and N outputs. In various embodiments, M=N. To compute an output tensor block, the neural core multiplies an M×1 input data tensor block 101 by an M×N weight tensor block 102 and accumulates the products into a weighted sum stored in an 1×N intermediate tensor block 103. An O×N parameter tensor block contains O parameters that specify each of the N neuron activation functions that are applied to the intermediate tensor blocks 103, producing a 1×N output tensor block 105.

[0018] Multiple neural cores can be tiled into a neural core array, which in some embodiments is two-dimensional.

[0019] A neural network model is a set of constants that collectively specify the entire computation performed by a neural network, including the graph of connections between neurons and the weight and activation function parameters for every neuron. Training is the process of modifying a neural network model to perform a desired function. Inference is the process of applying a neural network to inputs to generate outputs without modifying the neural network model.

[0020] An inference processing unit is a category of processor that performs neural network inference. A neural inference chip is a specific physical instance of an inference processing unit.

[0021] Referring now to FIG. 2, an exemplary inference processing unit (IPU) according to an embodiment of the present disclosure is shown. The IPU 200 includes a memory 201 for a neural network model. As described above, the neural network model may include synaptic weights for the neural network to be computed. The IPU 200 includes an activity memory 202, which may be temporary. The activity memory 202 may be divided into an input domain and an output domain and stores neuron activity values ​​for processing. The IPU 200 includes a neural computation unit 203 that loads the neural network model from the model memory 201. Input activity values ​​are provided from the activity memory 202 prior to each computation step. Output from the neural computation unit 203 is written back to the activity memory 202 for processing in the same or another neural computation unit.

[0022] In various embodiments, the micro-engines 204 are included in the IPU 200. In such embodiments, all operations within the IPU are directed by the micro-engines. As described below, various embodiments may provide a central micro-engine, distributed micro-engines, or both. A global micro-engine may be referred to as a chip micro-engine, while a local micro-engine may be referred to as a core micro-engine or local controller. In various embodiments, a micro-engine includes one or more micro-engines, microcontrollers, state machines, CPUs, or other controllers.

[0023] Referring to FIG. 3, a multi-core inference processing unit (IPU) according to an embodiment of the present disclosure is shown. The IPU 300 includes memory 301 for neural network models and instructions. In some embodiments, memory 301 is divided into a weight portion 311 and an instruction portion 312. As described above, the neural network model may include synaptic weights for the neural network to be calculated. The IPU 300 includes an activity value memory 302, which may be temporary. The activity value memory 302 may be divided into an input domain and an output domain and stores neuron activity values ​​for processing.

[0024] The IPU 300 includes an array 306 of neural cores 303. Each core 303 includes a computation unit 333 that operates to load a neural network model from the model memory 301 and perform vector computations. Each core also includes a local activation memory 332. Input activation values ​​are provided from the local activation memory 332 prior to each computation step. Output from the computation unit 333 is written back to the activity memory 332 for processing by the same or another computation unit.

[0025] IPU 300 includes one or more networks-on-chip (NoCs) 305. In some embodiments, a partial sum NoC 351 interconnects cores 303 and transmits partial sums between them. In some embodiments, a separate parameter distribution NoC 352 connects cores 303 to memory 301 for distributing weights and instructions to cores 303. It will be appreciated that various configurations of NoCs 351 and 352 are suitable for use with the present disclosure. For example, a broadcast network, a row broadcast network, a tree network, and a switched network may be used.

[0026] In various embodiments, a global micro-engine 304 is included in the IPU 300. In various embodiments, a local core controller 334 is included in each core 303. In such embodiments, the global micro-engine (chip micro-engine) and the local core controller (core micro-engine) cooperate to direct operations. Specifically, at 361, the global micro-engine 304 loads computational instructions from the instruction portion 312 of the model memory 301 into the core controller 334 on each core 303. At 362, the global micro-engine 304 loads parameters (e.g., neural network / synaptic weights) from the weight portion 311 of the model memory 301 into the neural computation unit 333 on each core 303. At 363, the local core controller 334 loads neural network activity data from the local activity memory 332 into the neural computation unit 333 on each core 303. As described above, activation values ​​are provided to neurons of a particular neural network defined by the model, and may come from the same or another neural computation unit, or may come from outside the system. At 364, the neural computation unit 333 performs a calculation when instructed by the local core controller 334 to generate an activation value for the output neuron. Specifically, the calculation involves applying input synaptic weights to the input activation value. It will be appreciated that various methods are available for performing such a calculation, including in silico dendrites and vector multiplication units. At 365, when instructed by the local core controller 334, the results of the calculation are stored in the local activity memory 332. As described above, these stages can be pipelined to provide efficient use of the neural computation units on each core. It will also be appreciated that inputs and outputs may be transferred from the local activity memory 332 to the global activity memory 302 depending on the requirements of a given neural network.

[0027] Thus, the present disclosure provides runtime control of operations in an inference processing unit (IPU). In some embodiments, the micro-engine is centralized (a single micro-engine). In some embodiments, the IPU computation is distributed (performed by an array of cores). In some embodiments, the runtime control of operations is hierarchical, involving both centralized and distributed micro-engines.

[0028] One or more microengines direct the execution of all operations in the IPU. Each microengine instruction corresponds to several sub-operations (e.g., address generation, load, calculation, store, etc.). Core microcode executes on the core microengines (e.g., 334). For local computation, the core microcode contains instructions to perform a complete single tensor operation, such as a convolution between a weight tensor and a data tensor. For distributed computation, the core microcode contains instructions to perform a single tensor operation on a subset (and partial sum) of the locally stored data tensors. Chip microcode executes on the chip microengines (e.g., 304). The microcode contains instructions to perform all of the tensor operations in the neural network.

[0029] Referring now to FIG. 4, an exemplary neural core and associated network is illustrated, according to an embodiment of the present disclosure. Core 401, which may be implemented as described with reference to FIG. 1, is interconnected with additional cores by networks 402...404. In this embodiment, network 402 is responsible for distributing weights and / or instructions, network 403 is responsible for distributing partial sums, and network 404 is responsible for distributing activation values. However, it will be understood that various embodiments of the present disclosure may combine these networks or further separate them into multiple additional networks.

[0030] Input activation values ​​(X) are distributed from off-core to core 401 via activation network 404 and into activation memory 405. Layer instructions are distributed from off-core to core 401 via weight / instruction network 402 and into instruction memory 406. Layer weights (W) and / or parameters are distributed from off-core to core 401 via weight / instruction network 402 and into weight memory 407 and / or parameter memory 408.

[0031] The weight matrix (W) is read from the weight memory 407 by a vector matrix multiply (VMM) unit 409. The activation vector (V) is read from the activation memory 405 by the vector matrix multiply (VMM) unit 409. The vector matrix multiply (VMM) unit 409 then performs a vector-matrix multiplication Z=X T The vector-vector unit 410 computes W and provides the result to the vector-vector unit 410. The vector-vector unit 410 reads additional partial sums from the partial sum memory 411 and receives additional partial sums from off-core via the partial sum network 403. The vector-vector unit 410 computes vector-vector operations from these source partial sums. For example, various partial sums may be summed in sequence. The resulting target partial sums may be written to the partial sum memory 411, sent off-core via the partial sum network 403, or fed back for further processing by the vector-vector unit 410, or a combination thereof.

[0032] After all calculations for a given layer's inputs are completed, the partial sum results from the vector-vector unit 410 are provided to the activation unit 412 for calculation of the output activation values. The activation vector (Y) is written to the activation memory 405. The layer's activation values ​​(including the results written to the activation memory) are redistributed from the activation memory 405 to the cores via the activation network 404. As each core receives the activation value, it writes it to its local activation memory. Once processing for a given frame is complete, the output activation value is read from the activation memory 405 and sent out of the core via the network 404.

[0033] Thus, in operation, a core control micro-engine (e.g., 413) coordinates the data movement and computation of the core. The micro-engine issues an activity memory address read operation to load an input activity value block into the vector-matrix multiplication unit. The micro-engine issues a weight memory address read operation to load a weight block into the vector-matrix multiplication unit. The micro-engine issues a calculation operation to the vector-matrix multiplication unit to cause the vector-matrix multiplication unit to calculate a partial sum block.

[0034] The microengine issues one or more of a partial sum read / write memory address operation, a vector calculation operation, or a partial sum communication operation to read partial sum data from a partial sum source, calculate using a partial sum arithmetic unit, or write the partial sum data to a partial sum target. Writing the partial sum data to a partial sum target can include communicating external to the core via a partial sum network interface or sending the partial sum data to an activated arithmetic unit.

[0035] The micro-engine issues an activation function calculation operation so that the activation function arithmetic unit calculates an output activation value block, and the micro-engine issues an activation value memory address write operation so that the output activation value block is written to the activation value memory via the activation value memory interface.

[0036] Thus, for a given core, various source, target, address type, computation type, and control components are defined.

[0037] The sources for the vector-vector unit 410 include the vector-matrix multiplication (VMM) unit 409, constants from the parameter memory 408, the partial sum memory 411, the partial sum result from the previous cycle (TGT partial sum), and the partial sum network 403.

[0038] The targets of the vector-vector unit 410 include a partial sum memory 411, the partial sum result for the subsequent cycle (SRC partial sum), an activation unit 412, and a partial sum network 403.

[0039] Thus, a given instruction may be a read or write from activation value memory 405, a read from weight memory 407, or a read or write from partial sum memory 411. Computational operations performed by the core include vector matrix multiplication by VMM unit 409, vector (partial sum) operations by vector-vector unit 410, and activation functions by activation unit 412.

[0040] Control operations include updating the program counter and the loop counter and / or sequence counter.

[0041] Thus, memory operations are issued to read weights from weight memory addresses, read parameters from parameter memory addresses, read activations from activation memory addresses, read partial sums from partial sum memory addresses, and write partial sums to partial sum memory addresses. Computation operations are issued to perform vector-matrix multiplication, vector-vector operations, and activation functions. Communication operations are issued to select vector-vector operands, route messages on the partial sum network, and select partial sum targets. Loops over layer outputs and loops over layer inputs are controlled by control operations that specify the micro-engine's program counter, loop counter, and sequence counter.

[0042] It will be appreciated that in order to accommodate a variety of program structures, it would be advantageous to provide a micro-engine that allows efficient program control of nested loops. Accordingly, the following discussion provides various exemplary embodiments of a suitable micro-engine.

[0043] Referring now to Figure 5, an exemplary loop 502 is presented, which is a program control structure that can repeat (or "iterate") the execution of a set of instructions (also called the "body" of the loop) multiple times. Also shown in Figure 5 is an exemplary nested loop 504, for example, when an (inner) loop is enclosed within another (outer) loop. In some embodiments, the nested loops can be represented as a tree 506, where each loop ("loop j" and "loop k") is a node whose parent ("loop i") is the innermost loop in which it is enclosed.

[0044] Loops are the core control structure of all modern computers and a key part of nearly every algorithm. Machine learning applications and deep convolutional neural networks, in particular, require the execution of vast numbers of arithmetic operations. These are controlled by complex code structures that contain multiple nested loops (in some implementations, loop nesting can be 10-16 loops deep). The overhead of looping itself is disproportionate. In fact, looping can require many more computation cycles than the actual arithmetic operations it drives, dramatically reducing operation utilization, thereby increasing power consumption and degrading performance. For example, in SIMD architectures, where utilization is a critical factor, every lost cycle in program control multiplied by the number of parallel SIMD operations per cycle results in significant computational losses. Therefore, there is a need, and the subject matter disclosed herein addresses, for highly efficient loop control methods and systems for central processing units (CPUs) and other processing units, including graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and other special-purpose processors. In some embodiments, the disclosed systems may be used in a variety of processors and controllers, including but not limited to CPUs, GPUs, FPGAs, neuromorphic processors, convolution processing units, inference engines, tensor processing units, etc.

[0045] Loops can be implemented in software using conditional branching, an example of which is shown in FIG. 6, where the loop index, or loop iterator, is denoted by “i.” An exemplary loop is shown in code block 602, and an exemplary conditional branch is shown in code block 604. Nested loops, as shown in code block 702, may result in serialized evaluation of the exit conditions. In the example shown in FIG. 7, each time “L2” finishes, “i” is incremented and the condition for “L1” is evaluated, as shown in code block 704. Thus, one or two loop conditions are evaluated prior to each evaluation of the loop body. According to one aspect of the present disclosure, utilization may indicate the ratio between the number of cycles used to process the body instructions and the total number of cycles (including loop initialization and branching). In general, the more nested loops are used, the more conditions must be evaluated, and the lower the utilization. In some embodiments, conditions implemented within loops may be checked before or after the loop body. An example of this is shown in Figure 8, where a loop repeats until its termination condition is met, and termination must be evaluated before or after each iteration, as shown in code block 802. If the termination condition is checked before the body executes, the loop can execute zero or more times. If the termination condition is checked after the body executes, the loop can execute one or more times, as shown in code block 804.

[0046] 9 shows an exemplary set of CPU loop instructions compiled into assembly code (e.g., using a POWER processor by IBM) that includes an outer "for" loop 906, an inner "for" loop 904, and a multiply-add operation 902. Updating the loop counter and checking the loop condition requires one or more cycles, and checking the conditions of multiple nested loops is performed sequentially, starting with the innermost loop and working outward. Thus, the more nested the loops, the longer it takes to update the loop, thereby reducing utilization. FIG. 10 shows another exemplary set of CPU loop instructions, with the multiply-add operation 1002 and loop control 1004 highlighted in bold.

[0047] Figure 11 illustrates an exemplary static loop unrolling technique in which a programmer analyzes a loop and translates iterations into a sequence of instructions to reduce loop overhead. This technique contrasts with dynamic unrolling, which is performed by a compiler. The illustrated example deletes 100 items from a collection, which can be achieved using a "for" loop that calls the function "delete(item_number)." If the loop overhead is significantly more resource-intensive than the overhead of a "delete(x)" loop, unwinding (or unrolling) can be used on selected portions of the program, as shown, for faster optimization. However, loop unrolling has several drawbacks, including an increase in program code size (which is exacerbated if the loop body contains function calls, especially if they are inlined). Unrolling can also cause increased instruction cache misses, which can adversely affect performance, and can make the code less readable unless performed transparently by an optimizing compiler. Aside from very small and simple code, unrolled loops containing branches are typically slower. Thus, when using a Very Large Instruction Word architecture, expansion may require additional program cache and / or program memory.

[0048] FIG. 12 illustrates an exemplary loop merging technique that replaces two (or more) nested loops, such as those shown in code block 1202, with a single loop, such as that shown in code block 1204, that executes the same total number of iterations. An advantage of this approach is that it reduces loop overhead. Instead of testing one or two conditions and applying one or two index updates, one test is performed per iteration, advancing one index. A disadvantage of this approach is that the index calculation based on the combined loop indexes can be complex and may require modular arithmetic. This becomes more complex as the number of loops being merged increases. Some hardware solutions, including some CPUs (e.g., the Intel 8086 microprocessor), have opcodes for implementing loop counters that use dedicated registers / counters, reducing the number of operations (or OPs) to one. However, these are only applicable to a single loop; therefore, nested loops require the use of other registers for generic operations. Indeed, even a single loop may still take one or two cycles per iteration, thus resulting in non-zero overhead. Figure 13 shows the instruction set reference for an exemplary 8086 microprocessor.

[0049] According to one aspect of the present disclosure, a configurable loop control circuit is provided that is configured first and then executed. The loop configuration can include the number of iterations, the start program counter address, and the end program counter address of the loop body code block. Such a configurable loop control circuit can support a large number of nested loops, and in an exemplary embodiment, includes circuitry to support 16 nested loops. This circuit can check the conditions of all nested loops in parallel, and the loop condition check circuitry is automatically triggered (e.g., without a LOOP OP or branch in the code), and all loop condition checks and counter updates are performed for all loops in a single clock cycle. This can be performed while the last instruction of the loop body is executing (thus incurring zero overhead).

[0050] 14-15 illustrate an exemplary embodiment of a parallel loop in hardware employing a single loop counter according to the present disclosure. As shown, code block 1402 and circuitry 1404 can be incorporated into a system having a program counter (PC) 1406 and a single loop counter 1408, implemented in hardware, where the first step involves configuring the loop counter circuit as follows:

number

[0051] FIG. 16 illustrates an exemplary embodiment of a loop trace in accordance with the disclosed subject matter. The illustrated example aims to execute CmdA, then CmdB five times, then CmdC, as shown. The loop counter circuit is configured as follows:

number

[0052] As shown in the cycle-by-cycle trace, first CmdA executes, then PC advances to 1. PC stays at 1 for four more cycles, executing CmdB four more times, during which LC advances four times. After the fifth iteration, LC is reset to 0, PC advances to 2, and executes CmdC.

[0053] 17 shows an exemplary embodiment of the present disclosure extended to multiple loop counters. When more than one loop is present in a program, the interaction between the two loop counters can be categorized into three cases 1701, 1702, and 1703, as shown and described below. 1. Disjoint Loops (1701): If two loops are not nested, their evaluations are performed in different cycles (e.g., different PC values) and are therefore independent of each other. Each loop counter can be implemented as a single loop in the same system. 2. Co-ending nested loops (1702): One loop is nested within another, and the last instruction of the nested loop body (T1=T) is also the last instruction of the outer loop body (T2=T). In this case, after performing an operation (op) with PC=T, one or more of the following can be performed: a) increment j, or b) reset j and increment i, or c) reset both i and j and exit the nested loop. The number of possible alternative actions at instruction T increases with the number of co-ending nested loops. 3. Non-co-ending nested loops (1703): one loop is nested within another, and the outer loop body contains at least one more instruction after the body of the inner loop finishes. As with non-intersecting loops, only one loop counter needs to be checked and updated in each of T1 and T2.

[0054] The circuitry provided herein addresses all three cases. Furthermore, it applies to any number of loops made up of any combination of these three cases, including any number of simultaneously terminating nested loops. Figure 18 shows an exemplary embodiment of the present disclosure for parallel loops in hardware with nested simultaneously terminating loop counters as shown in code blocks 1802 and 1805. Here, the system implements M loop counters, enumerated from 0 to M-1. This system handles all three cases defined in Figure 17, i.e., non-intersecting loops and nesting (simultaneous and non-simultaneous terminating). Without loss of generality, LC j and L.C. i and end simultaneously, and Loop LC j Loop LC i , then assume j>i. An exemplary embodiment of a logic circuit including a diagram of a program counter (PC) and a loop counter (LC) according to the present disclosure is shown in FIG. 19. In block 1805, for all loop counters i=0 to M-1, e i , l i and t i The values ​​of a are calculated independently and in parallel. i and r i The value of t from the loop counter of a higher index (perhaps an inner loop) i Finally, each of the loop counters, as well as the PC, is updated using the update rules in block 1805. These expressions are calculated each cycle. As a result, the PC will have a new value for the next cycle, and each of the loop counters will either retain its state, advance, or reset. This calculation is applicable to any configuration of loop counters.

[0055] In an exemplary embodiment, the loop counter is allowed to run forever unconditionally, represented as an infinite loop and indicated by the following binary flag: Inf i : True if this loop keeps repeating Also, one or more LCs may be inactive for a period of time, which is indicated by the valid bits below as active loop counters. Valid i : Valid bit. True if this loop counter is active.

[0056] According to one aspect of the present disclosure, the loop counter circuit can be implemented in a variety of ways. For example, instead of defining a Valid bit, a value of Count=0 can be specified to indicate that the loop counter is inactive. While a loop counter starting with an initial value of 0, a reset value of 0, and an increment value of 1 has been described, those skilled in the art will recognize that the loop counter configuration can be extended to additional fields. For purposes of illustration and not limitation, some examples include a specified initial value, application of a specified increment value, a count that increases or decreases based on the sign of a step value, and a termination criterion. If desired, these additional items can also include additional summing circuitry and signed comparators. Furthermore, error checking can be provided, and in some embodiments includes additional circuitry added to assert the validity of the configuration (the initial value must be lower than Count), operate to restore a defined mode of operation (e.g., replace an invalid initial value with zero), generate an error signal, or both.

[0057] 20 illustrates an exemplary embodiment of a loop counter definition including the flags described above. As illustrated, the loop counter (LC) definition includes a Valid bit and an Inf bit. Also, according to the present disclosure, the loop behavior of finite and infinite loops can be as follows:

number

[0058] 21 illustrates an exemplary embodiment of a program counter-less parallel loop according to the present disclosure. An advantage of the code shown in block 2102 and the circuitry shown in 2104 is that all nested loop counters share the same loop body, thereby providing a reduced, minimal implementation that does not require a program counter. For example, the body of a nested loop is one instruction (or one function call). Each time the loop body is executed, the loop counter is updated. The system is for M loop counters, here numbered from 0 to M-1, and the LC i denotes the i-th loop counter. Without loss of generality, LC j and L.C. i and end simultaneously, and Loop LC j Loop LC i If it is nested in LC, then assume j>i. i calculates a trigger for each loop body execution, as shown in block 2106.

[0059] 22 illustrates a comparison between parallel and CPU loops according to the present disclosure, showing example code blocks for a parallel loop 2202 and a CPU loop 2204. The parallel loop 2202 exhibits various attributes, including: Can be pre-configured with dedicated hardware Based on PC address Zero cycle overhead for loop iteration updates Multiple concurrently terminated nested loops can be updated simultaneously (while maintaining zero overhead) 100% utilization of calculation cycles regardless of the number of nested loops or loop length - Present specific implementation details Execute one or more times An exit condition is checked before incrementing (so the counter is not incremented after the last iteration) The number of nested loops is limited by the available LC circuits (e.g., 16 loop counters)

[0060] In contrast, the CPU loop 2204 includes the following attributes: - Programmed, it is part of the opcode in memory Flexible, data-driven loop conditions - Loop iteration update overhead is 1-5 cycles Simultaneously terminated nested loops are updated sequentially (the sum of the overhead of all update loops, not a constant). As the number of nested loops increases, utilization decreases, especially for short loops. Implementation details Execute one or more times The counter is incremented before checking the exit condition (the counter is incremented one more time after the last iteration) Unlimited number of nested loops

[0061] FIG. 23 illustrates an exemplary embodiment of loop restructuring according to the present disclosure. As illustrated, in some embodiments, a loop counter that is not currently counting (i.e., the program counter is not within the loop body) can be reconfigured to implement other loops in different parts of the program. For example, code block 2302 has three loops, where A and C are the bodies of the first and second nested loops, respectively. As shown in code block 2304, this code can be implemented using only two loop counters by reconfiguring the second loop counter to loop with PC=1 for N iterations and then to loop with PC=4 for K iterations. The restructuring takes time for each iteration of loop i. In some embodiments, the time can be reduced by performing the restructuring in parallel with the execution of instructions such as instruction B and instruction D.

[0062] Referring to FIG. 24, a method for calculating neural activity values ​​is shown. At 2401, a controller is configured according to a program configuration, the program configuration including at least one inner loop and at least one outer loop. At 2402, at least one arithmetic calculation unit executes a plurality of operations according to the program configuration. At 2403, the controller maintains at least a first loop counter and a second loop counter, the first loop counter configured to count the number of executed iterations of the at least one outer loop, and the second loop counter configured to count the number of executed iterations of the at least one inner loop. At 2404, the controller provides a first indicator indicating whether the first loop counter corresponds to the last iteration and a second indicator indicating whether the second loop counter corresponds to the last iteration. At 2405, the second loop counter is alternatively incremented, reset, or maintained according to the first and second indicators.

[0063] Referring now to Figure 25, a schematic of an example computing node is shown. Computing node 10 is merely one example of a suitable computing node and is not intended to suggest any limitation regarding the scope of use or functionality of the embodiments described herein. Nevertheless, computing node 10 may implement and / or perform any of the functions described above.

[0064] In computing node 10, computer system / server 12 is operable in numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, that may be suitable for use with computer system / server 12 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics devices, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices.

[0065] Computer system / server 12 may be described in the general context of computer system-executable instructions, such as program modules, executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. Computer system / server 12 may be practiced in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media, including memory storage devices.

[0066] 25, computer system / server 12 in computing node 10 is shown in the form of a general-purpose computing device. Components of computer system / server 12 may include, but are not limited to, one or more processors or processing units 16, system memory 28, and a bus 18 coupling various system components, including system memory 28, to processor 16.

[0067] Bus 18 represents any one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures, including, by way of example and not limitation, an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, a Peripheral Component Interconnect (PCI) bus, a Peripheral Component Interconnect Express (PCIe), and an Advanced Microcontroller Bus Architecture (AMBA).

[0068] In various embodiments, one or more inference processing units (not shown) are coupled to bus 18. In such embodiments, the IPU may receive data from or write data to memory 28 via bus 18. Similarly, the IPU may interact with other components via bus 18 as described herein.

[0069] Computer system / server 12 typically includes a variety of computer system-readable media, which can be any available media that can be accessed by computer system / server 12 and includes both volatile and nonvolatile media, removable and non-removable media.

[0070] System memory 28 may include computer system-readable media in the form of volatile memory, such as random access memory (RAM) 30 or cache memory 32, or both. Computer system / server 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 34 may be provided for reading from and writing to a non-removable, non-volatile magnetic medium (not shown, typically referred to as a "hard drive"). Although not shown, a magnetic disk drive may be provided for reading from and writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive may be provided for reading from and writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM, or other optical medium. In such cases, each may be connected to bus 18 by one or more data media interfaces. As further shown and described below, memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of embodiments of the present disclosure.

[0071] By way of example and not limitation, memory 28 may store a program / utility 40 having a set (at least one) of program modules 42, as well as an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data, or any combination thereof, may include an implementation of a networking environment. Program modules 42 generally perform the functions and / or methods of embodiments of the present invention described herein.

[0072] The computer system / server 12 may also communicate with one or more external devices 14, such as a keyboard, pointing device, display 24, etc., one or more devices that allow a user to interact with the computer system / server 12, or any device that allows the computer system / server 12 to communicate with one or more other computing devices (e.g., a network card, modem, etc.), or combinations thereof. Such communication may occur via an input / output (I / O) interface 22. Furthermore, the computer system / server 12 may also communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or combinations thereof, via a network adapter 20. As shown, the network adapter 20 communicates with other components of the computer system / server 12 via a bus 18. Although not shown, it is understood that other hardware and / or software components may be used with the computer system / server 12. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0073] The present disclosure may be a system, a method, or a computer program product, or a combination thereof, which may include a computer-readable storage medium or media having computer-readable program instructions thereon for causing a processor to perform aspects of the present invention.

[0074] A computer-readable storage medium may be any tangible device capable of holding and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, or semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanical coding devices such as punch cards or raised groove structures having instructions recorded thereon, and any suitable combination of the above. As used herein, computer-readable storage media is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses through fiber optic cable), or electrical signals sent through wires.

[0075] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device over a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network can include copper cables, optical fibers, wireless networks, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device.

[0076] The computer-readable program instructions for carrying out the operations of the present disclosure may be source or object code written in any combination of assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer readable program instructions to individualize the electronic circuitry by utilizing state information of the computer readable program instructions to implement aspects of the present disclosure.

[0077] Aspects of the present disclosure will be described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0078] These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, whereby the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for performing the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams. These computer program instructions can also be stored in a computer-readable medium that can direct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, whereby the instructions stored in the computer-readable medium can include an article of manufacture containing instructions that implement aspects of the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams.

[0079] The computer program instructions may be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to generate a computer-implemented process, whereby the instructions running on the computer, other programmable apparatus, or other device perform the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams.

[0080] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions shown in the blocks may occur in a different order than that shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or operations, or a combination of dedicated hardware and computer instructions.

[0081] STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT This invention was made with United States Government support under Contract No. FA8750-18-C-0015 awarded by the United States Air Force Office of Scientific Research. The United States Government has certain rights in this invention.

[0082] The descriptions of various embodiments of the present disclosure have been presented for illustrative purposes, but they are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications, or technical improvements over the art found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. at least one arithmetic logic unit; a controller operably coupled to the at least one arithmetic logic unit; A chip comprising: the controller is configured according to a program configuration, the program configuration including at least one inner loop and at least one outer loop including an infinite loop; the controller is configured to cause the at least one arithmetic logic unit to perform a plurality of operations in accordance with the program construct, the plurality of operations including operations associated with the at least one inner loop, and the controller is configured to cause the at least one arithmetic logic unit to perform the operations during a single clock cycle; the controller is configured to maintain at least a first loop counter and a second loop counter, the first loop counter configured to count the number of executed iterations of the infinite loop and the second loop counter configured to count the number of executed iterations of the at least one inner loop; the controller is configured to provide, during the single clock cycle, a first indicator indicating whether the first loop counter corresponds to a last iteration and a second indicator indicating whether the second loop counter corresponds to a last iteration; the controller is configured to alternatively increment or maintain the first loop counter during the single clock cycle according to the first index; the controller is configured to alternatively increment or reset the second loop counter during the single clock cycle according to the second index. Tips.

2. the controller is configured to maintain a program counter, the program counter indicating a current operation of the plurality of operations; the controller is configured to provide a third indicator indicating whether the current operation is a final operation of the inner loop. The chip of claim 1 .

3. the controller is configured to provide a fourth indication of whether the current operation is a final operation of the infinite loop. The chip of claim 2 .

4. the controller is configured to update the first and second loop counters and the program counter according to the first, second, third, or fourth indicator, or a combination thereof; The chip according to claim 3 .

5. The controller is configured to update the program counter when the second loop counter advances. The chip according to claim 4.

6. The controller is configured to update the first and second loop counters according to the program counter. The chip according to any one of claims 2 to 5.

7. the controller is configured to maintain an idle indicator for each of the first and second loop counters. The chip according to any one of claims 1 to 6.

8. the controller is configured to initialize the first or second loop counter to a predetermined value; The chip according to any one of claims 1 to 7.

9. the at least one inner loop or the at least one outer loop, or both, are bottom driven; The chip according to any one of claims 1 to 8.

10. the at least one inner loop or the at least one outer loop, or both, are top-driven; The chip according to any one of claims 1 to 9.

11. The chip of any one of claims 1 to 10, configured to calculate neural activity values.

12. further comprising a memory in communication with the controller; the controller is configured to receive the program configuration from the memory; The chip according to any one of claims 1 to 11.

13. the program construct includes at least one additional nested loop; the controller is configured to maintain an additional loop counter for each of the at least one additional nested loop. The chip according to any one of claims 1 to 12.

14. The chip of claim 1 , wherein the controller is configured to increment the first loop counter or to increment or decrement the second loop counter for each iteration.

15. configuring a controller according to a program construct, the program construct including at least one inner loop and at least one outer loop including an infinite loop; causing at least one arithmetic logic unit to perform a plurality of operations in accordance with the program construct, the plurality of operations including operations associated with the at least one inner loop, the controller being configured to cause the at least one arithmetic logic unit to perform the operations during a single clock cycle; maintaining, by the controller, at least a first loop counter and a second loop counter, the first loop counter configured to count the number of executed iterations of the infinite loop and the second loop counter configured to count the number of executed iterations of the at least one inner loop; providing, by the controller, during the single clock cycle, a first indicator indicating whether the first loop counter corresponds to a last iteration and a second indicator indicating whether the second loop counter corresponds to a last iteration; alternatively incrementing or maintaining the first loop counter during the single clock cycle according to the first index; alternatively incrementing or resetting the second loop counter during the single clock cycle according to the second index; A method comprising:

16. maintaining, by the controller, a program counter, the program counter indicating a current operation of the plurality of operations; providing, by the controller, a third indicator indicating whether the current operation is a final operation of the inner loop; 16. The method of claim 15, further comprising:

17. providing, by the controller, a fourth indicator indicating whether the current operation is a final operation of the infinite loop.

17. The method of claim 16.

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