Numeric conversion and scaling methods

Abstract

Instructions are provided for performing a transform operation and a scaling operation. Execution of the instructions includes transforming an input value in one format to provide a transformed result in another format. The transformed result is scaled to provide a scaled result. A result obtained from the scaled result is placed in a selected location. Additionally, instructions are provided for performing a scaling operation and a transform operation. Execution of the instructions includes scaling an input value in one format to provide a scaled result and transforming the scaled result from one format to provide a transformed result in another format. A result obtained from the transformed result is placed in a selected location.

Description

[Technical Field]

[0001] One or more aspects relate generally to facilitating processing within a computing environment, and more particularly to improving such processing. [Background technology]

[0002] Applications executing within computing environments provide many operations used by a wide variety of technologies, including, but not limited to, design, manufacturing, medical technology, automotive technology, computer processing, etc. These applications, written in programming languages ​​such as COBOL, often perform complex calculations in performing their operations. The calculations include, for example, power and / or exponential functions, and often require conversion of data from one format (e.g., binary-coded decimal) to another format (e.g., hexadecimal floating point) and vice versa.

[0003] For an application to perform a conversion from one format to another, various steps are performed. For example, to convert from binary-coded decimal to hexadecimal floating point, the application may include a step to convert the binary-coded decimal to an integer, which is then converted to hexadecimal floating point. To convert back to binary-coded decimal, the hexadecimal floating point number may be converted to an integer, which is then converted back to binary-coded decimal. Furthermore, each of these steps may include substeps, which can be time-consuming and impact the performance of the computing environment and the availability of computer resources. Summary of the Invention

[0004] Shortcomings of the prior art are overcome and additional advantages are achieved by providing a computer program product for facilitating processing within a computing environment. The computer program product includes one or more computer-readable storage media and program instructions collectively stored on the one or more computer-readable storage media for performing a method. The method includes executing the instructions to perform a conversion operation and a scaling operation. Executing the instructions includes converting an input value from one format to provide a converted result in another format, scaling the converted result to a scaled result, and placing a result obtained from the scaled result at a selected location.

[0005] By performing transformation and scaling operations using a single instruction, performance is improved and resource utilization is reduced. By performing transformation and scaling operations using a single designed instruction, certain tasks, such as transformation and scaling operations, can be performed much more efficiently than using a software paradigm. Transformation and scaling operations are performed much faster, reducing execution time and improving performance of the processor and / or the overall system.

[0006] In one example, one format is a hexadecimal floating point format and the other format is a decimal format. In one example, the decimal format is a binary coded decimal format.

[0007] In one example, scaling includes determining a scale factor and using the scale factor in scaling the transformed result to provide the scaled result. Determining the scale factor includes, for example, obtaining a scale value using an operand of the instruction and using the scale value to determine the scale factor. Using the scale factor includes multiplying the transformed result by the scale factor to obtain the scaled result.

[0008] Scaling, for example, isolates particular digits of a number to indicate selected positions within the number for truncation or rounding, for example.

[0009] In one example, the scaled result is rounded to provide a rounded result, where the rounding includes obtaining a rounding mode using a field of the instruction and rounding the scaled result to the rounded result based on the rounding mode.

[0010] In one example, the placing includes selecting a portion of the rounded result as the result and placing the result in the selected location.

[0011] In one example, the sign of the result is determined and the sign of the result is placed in a selected location, for example, a register specified using a field of the instruction.

[0012] In another aspect, a computer program product for facilitating processing in a computing environment is provided. The computer program product includes one or more computer-readable storage media and program instructions collectively stored on the one or more computer-readable storage media for performing a method. The method includes executing the instructions to perform scaling and conversion operations. Executing the instructions includes scaling input values ​​in one format to provide scaled results, converting the scaled results from one format to provide converted results in another format, and placing a result obtained from the converted results in a selected location.

[0013] By performing scaling and transformation operations using a single instruction, performance is improved and resource utilization is reduced. By performing scaling and transformation operations using a single designed instruction, certain tasks, such as scaling and transformation operations, can be performed much more efficiently than using a software paradigm. Scaling and transformation operations are performed much faster, reducing execution time and improving performance of the processor and / or the overall system.

[0014] In one example, executing the instruction further includes rounding a version of the converted result to provide a rounded result, where the rounded result is used to obtain the result.

[0015] By performing scaling, conversion, and rounding operations using a single instruction, performance is improved and resource utilization is reduced. By performing scaling, conversion, and rounding operations using a single designed instruction, certain tasks such as scaling, conversion, and rounding operations can be performed much more efficiently than using a software paradigm. Scaling, conversion, and rounding operations are performed much faster, reducing execution time and improving performance of the processor and / or the overall system.

[0016] As an example, the selected location is a register specified using a field of the instruction, and placing the result in the selected location includes determining a format of the result and placing the result in the register based on the format.

[0017] Computer-implemented methods and systems relating to one or more aspects are also described and claimed herein. Additionally, services relating to one or more aspects may also be described and claimed herein.

[0018] Additional features and advantages are realized by the techniques described herein. Other embodiments and aspects are described in detail herein and are considered a part of the claimed aspects.

[0019] One or more aspects are particularly pointed out and distinctly claimed as examples in the claims at the end of this specification. The foregoing, together with objects, features, and advantages of one or more aspects, will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0020] [Figure 1A] FIG. 1 illustrates an example computing environment for incorporating and using one or more aspects of the present invention. [Figure 1B] 1B illustrates further details of the processor of FIG. 1A in accordance with one or more aspects of the present invention. [Figure 2] FIG. 1 illustrates an example format for a Decimal Scale and Convert to Hexadecimal Floating Point instruction in accordance with one or more aspects of the present invention. [Figure 3] FIG. 2 illustrates an example of processing associated with executing decimal scaling and conversion to hexadecimal floating point instructions in accordance with one or more aspects of the present invention. [Figure 4] FIG. 2 illustrates an example of processing associated with the scaling operation of a decimal scaling and convert to hexadecimal floating point instruction in accordance with one or more aspects of the present invention. [Figure 5] FIG. 2 illustrates an example of processing logic for performing conversion operations of decimal scaling and convert to hexadecimal floating point instructions in accordance with one or more aspects of the present invention. [Figure 6] FIG. 2 illustrates an example of processing associated with the placement operation of a decimal scaling and conversion to hexadecimal floating point instruction in accordance with one or more aspects of the present invention. [Figure 7] FIG. 1 illustrates an example format for a Vector Convert Hexadecimal Floating Point to Scaled Decimal instruction in accordance with one or more aspects of the present invention. [Figure 8] FIG. 2 illustrates an example of processing associated with executing a hexadecimal floating-point to scaled decimal vector convert instruction in accordance with one or more aspects of the present invention. [Figure 9] FIG. 1 illustrates an example of processing logic for performing a conversion operation of a hexadecimal floating-point to scaled decimal vector convert instruction in accordance with one or more aspects of the present invention. [Figure 10] FIG. 1 illustrates an example of processing associated with the placement operation of a hexadecimal floating-point to scaled decimal vector conversion instruction in accordance with one or more aspects of the present invention. [Figure 11A] FIG. 1 illustrates an example of facilitating processing within a computing environment in accordance with one or more aspects of the present invention. [Figure 11B] FIG. 1 illustrates an example of facilitating processing within a computing environment in accordance with one or more aspects of the present invention. [Figure 11C] FIG. 1 illustrates another example of facilitating processing within a computing environment in accordance with one or more aspects of the present invention. [Figure 12A] FIG. 1 illustrates another example of a computing environment for incorporating and using one or more aspects of the present invention. [Figure 12B] FIG. 12B illustrates an example of further details of the memory of FIG. 12A in accordance with one or more aspects of the present invention. [Figure 12C] FIG. 12B illustrates another example of further details of the memory of FIG. 12A in accordance with one or more aspects of the present invention. [Figure 13A] FIG. 1 illustrates yet another example of a computing environment for incorporating and using one or more aspects of the present invention. [Figure 13B] FIG. 13B illustrates further details of the memory of FIG. 13A in accordance with one or more aspects of the present invention. [Figure 14] FIG. 1 illustrates one embodiment of a cloud computing environment in accordance with one or more aspects of the present invention. [Figure 15] FIG. 2 illustrates an example of an abstract model layer in accordance with one or more aspects of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] In accordance with an aspect of the present invention, capabilities are provided to facilitate processing within a computing environment. As one example, a single instruction (e.g., a single designed hardware machine instruction at a hardware / software interface) is provided to perform scaling and conversion operations. The instructions, referred to herein as decimal scaling and conversion to hexadecimal floating point instructions, are part of the instruction set architecture (ISA) of a general-purpose processor, dispatched by a program on a processor such as a general-purpose processor. (In another example, the instructions may be part of a special-purpose processor, such as a coprocessor configured for a specific function.)

[0022] As part of executing a single instruction (e.g., a decimal scale and convert to hexadecimal floating point instruction), various operations are performed, including scaling input data using a scale factor to provide scaled data, and converting the scaled data from one format (e.g., binary-coded decimal) to another format (e.g., hexadecimal floating point). Each of these operations is performed as part of executing the single instruction, improving system performance and reducing system resource usage.

[0023] In accordance with another aspect of the present invention, a single instruction (e.g., a single designed hardware machine instruction at a hardware / software interface) is provided to perform the conversion operation and subsequent scaling operation. The instruction, referred to herein as a hexadecimal floating-point to scaled decimal vector conversion instruction, is part of the instruction set architecture (ISA) of a general-purpose processor, dispatched by a program on a processor, such as a general-purpose processor. (In another example, the instruction may be part of a special-purpose processor, such as a coprocessor configured for a specific function.)

[0024] As part of executing a single instruction (e.g., a vector convert instruction from hexadecimal floating point to scaled decimal), various operations are performed, including converting input data from one format (e.g., hexadecimal floating point) to another format (e.g., binary-coded decimal) and scaling the converted data. Each of these operations is performed as part of executing the single instruction, improving system performance and reducing system resource usage.

[0025] In one example, the conversion is from binary-coded decimal to hexadecimal floating-point or from hexadecimal floating-point to binary-coded decimal, as shown. Binary-coded decimal is a binary encoding of decimal numbers, where each decimal digit is represented by a fixed number of bits (e.g., 4 or 8 bits). Hexadecimal floating-point is a format for encoding floating-point numbers. In one example, a hexadecimal floating-point number includes a sign bit, an exponent (e.g., 7 bits), and a fraction (e.g., 6, 14, or 28 digits). The exponent represents a signed exponent and is obtained, for example, by adding 64 to the exponent value. The exponent ranges from 0 to 127, which corresponds to an exponent range of, for example, -64 to +63. The magnitude of a hexadecimal floating-point number is the product of the fraction and the number 16 raised to the power of the exponent represented by the exponent. The number can be positive or negative depending on whether the sign bit is, for example, 0 or 1, respectively.

[0026] Hexadecimal floating-point numbers can be represented in several different formats, including short (e.g., 32 bits), long (e.g., 64 bits), and extended (e.g., 128 bits). In each format, the first bit (e.g., the first leftmost bit, bit 0) is a sign bit, the next selected number of bits (e.g., 7 bits) are an exponent, and in the short and long formats, the remaining bits are a fraction containing, e.g., 6 or 14 hexadecimal digits, respectively. In the extended format, the fraction is, e.g., 28 digits, and an extended hexadecimal floating-point number consists of two long-format numbers, called the high-order and low-order parts. The high-order part is an arbitrary long hexadecimal floating-point number. The high-order fraction includes, for example, the leftmost 14 hexadecimal digits of the 28-digit fraction, and the low-order fraction includes, for example, the rightmost 14 hexadecimal digits of the 28-digit fraction. The high-order exponent and sign are those of the extended hexadecimal floating-point number; the low-order sign and exponent of the extended operand are ignored.

[0027] One embodiment of a computing environment for incorporating and using one or more aspects of the present invention is described with reference to FIG. 1A. As an example, the computing environment is based on the z / Architecture® hardware architecture provided by International Business Machines Corporation (Armonk, New York). One embodiment of the z / Architecture hardware architecture is described in the publication “z / Architecture Principles of Operation,” IBM Publication No. SA22-7832-12, Thirteenth Edition, September 2019, which is incorporated herein by reference in its entirety. However, the z / Architecture hardware architecture is only one exemplary architecture, and other architectures or types of computing environments of International Business Machines Corporation or other entities or both may include and / or use one or more aspects of the present invention. z / Architecture and IBM are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction.

[0028] 1A, computing environment 100 includes a computer system 102, shown, for example, in the form of a general-purpose computing device. Computer system 102 may include, but is not limited to, one or more processors or processing units 104 (e.g., central processing units (CPUs)), memory 106 (e.g., also referred to as system memory, main memory, primary storage, central storage, or storage), and one or more input / output (I / O) interfaces 108, coupled together via one or more buses or other connections 110 or both.

[0029] Bus 110 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures, including, by way of example only, Industry Standard Architecture (ISA), MicroChannel Architecture (MCA), Enhanced ISA (EISA), Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnects (PCI).

[0030] The memory 106 may include a cache 112, such as a shared cache, which may be coupled to a local cache 114 of the processor 104, for example. Additionally, the memory 106 may include one or more programs or applications 116 and at least one operating system 118. An exemplary operating system includes the z / OS® operating system offered by International Business Machines Corporation (Armonk, New York). z / OS is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Other operating systems offered by International Business Machines Corporation and / or other entities may also be used. The memory 106 may include one or more computer-readable program instructions 120 configured to perform functions of embodiments of aspects of the present invention.

[0031] The computer system 102 may communicate with one or more external devices 130, such as a user terminal, a tape drive, a pointing device, a display, and one or more data storage devices 134, for example, via the I / O interface 108. The data storage devices 134 may store one or more programs 136, one or more computer-readable program instructions 138, or data, or a combination thereof. The computer-readable program instructions may be configured to perform the functions of embodiments of aspects of the present invention.

[0032] The computer system 102 may communicate, for example, via the I / O interface 108, with a network interface 132 that enables the computer system 102 to communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or a combination thereof, to facilitate communication with other computing devices or systems.

[0033] Computer system 102 may include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, computer system 102 may include and / or be coupled to non-removable, non-volatile magnetic media (typically referred to as a "hard drive"), a magnetic disk drive for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), and / or an optical disk drive for reading from or writing to removable, non-volatile optical disks, such as CD-ROMs, DVD-ROMs, or other optical media. It should be understood that other hardware and / or software components may be used with computer system 102, including, but not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0034] Computer system 102 can operate in numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, that may be suitable for use with computer system 102 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, microcomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of these systems or devices.

[0035] In one example, a processor (e.g., processor 104) includes multiple functional components used to execute instructions. As shown in FIG. 1B , these functional components include, for example, an instruction fetch component 150 for fetching instructions to be executed, an instruction decode unit 152 for decoding the fetched instructions and obtaining operands for the decoded instructions, one or more instruction execution components 154 for executing the decoded instructions, a memory access component 156 for accessing memory to execute the instructions, if necessary, and a writeback component 158 ​​for providing results of the executed instructions. One or more of the components may access and / or use one or more registers 160 in instruction processing. Additionally, one or more of the components may include or have access to at least a portion of one or more other components used in performing scaling and / or conversion operations of, for example, a decimal scaling and conversion to hexadecimal floating point instruction or a hexadecimal floating point to scaled decimal vector conversion instruction (or other processing that may employ one or more aspects of the present invention) as described herein in accordance with one or more aspects of the present invention. The one or more other components may include, for example, scaling component / conversion component (or one or more other components) 170.

[0036] In accordance with an aspect of the present invention, instructions, referred to herein as decimal scaling and conversion to hexadecimal floating point instructions, are provided to perform at least scaling and conversion operations to convert a number from one format (e.g., a decimal number such as a signed packed decimal number) to another format (e.g., a hexadecimal floating point) as part of executing an instruction.

[0037] One embodiment of a decimal scaling and conversion to hexadecimal floating point instruction used to perform the scaling and conversion operations is described with reference to FIG. 2. The instructions, in one example, are executed using a general-purpose processor (e.g., processor 104). In the description herein, specific locations of fields, specific fields, and / or specific sizes are indicated (e.g., specific bytes and / or bits). However, other locations, fields, and / or sizes may be provided. Furthermore, while setting bits to specific values ​​(e.g., 1 or 0) may be specified, this is merely an example. Bits may be set to different values, such as opposite or different values, in other examples. Many variations are possible.

[0038] In one example, the decimal scaling and conversion to hexadecimal floating point instructions have a VRR-b format that indicates vector registers and register operations along with an extended operation code (opcode). The decimal scaling and conversion to hexadecimal floating point instructions are part of a vector function, for example, that provides fixed-size vectors containing, for example, 1 to 16 elements. Each vector contains data that is operated on by the vector instructions defined in this function. In one embodiment, when a vector consists of multiple elements, each element is processed in parallel with the other elements. In one example, completion of the instruction does not occur until processing of all elements is complete. In other embodiments, the elements are processed partially in parallel, sequentially, or both.

[0039] In one embodiment, there are 32 vector registers, and other types of registers can be mapped to the vector register quadrants. For example, a register file, which is an array of processor registers within a central processing unit (e.g., processor 104), may contain 32 vector registers, each 128 bits in length. Sixteen floating-point registers, each 64 bits in length, can overlap the vector registers. Thus, as an example, if floating-point register 2 is modified, vector register 2 is also modified. Other mappings of other types of registers are possible.

[0040] For example, vector data may appear in storage in the same left-to-right order as other data formats: bits of the data format numbered 0-7 form the byte in the leftmost (lowest numbered) byte position in storage, bits 8-15 form the byte in the next consecutive position, etc. In yet another example, vector data may appear in storage in a different order, such as right-to-left.

[0041] As shown in FIG. 2, in one example, a decimal scaling and conversion to hexadecimal floating point instruction 200 includes multiple fields, which may have subscript numbers associated with them. The subscript numbers associated with fields of the instruction indicate the operand to which the field applies. For example, the subscript number 1 associated with vector register V1 indicates that the register specified using V1 contains the first operand, and so on. The length of a register operand is one register, e.g., 128 bits.

[0042] In one embodiment, the decimal scaling and conversion to hexadecimal floating point instruction 200 includes operation code (opcode) fields 202a, 202b (e.g., bits 0-7 and 40-47) that indicate a scaling and conversion operation where the input data is, for example, a decimal number (e.g., a signed packed decimal number, such as a binary coded decimal number including 31 digits and a sign) and the output is, for example, a hexadecimal floating point value; a first vector register (V1) field 202b that is used to specify a first vector register; The vector registers include a first mask (M5) field 210 (e.g., bits 24-27), a second mask (M4) field 212 (e.g., bits 32-35), and a register extension bit (RXB) field 214 (e.g., bits 36-39), each of which is described below. In one embodiment, each field is separate and independent of one another, although in other embodiments, two or more fields may be combined. More information regarding these fields is described below.

[0043] In one embodiment, the vector register (V1) field 204 is used to indicate the vector register that stores the first operand. The first operand is the result obtained by scaling and converting a decimal value to a hexadecimal floating-point value. The second operand is contained in a vector register specified using the vector register (V2) field 206 and is, for example, a signed packed decimal number (e.g., a binary-coded decimal number containing 31 digits and a sign), which is scaled using an unsigned integer contained in the third operand contained in a vector register specified using the vector register (V3) field 208.

[0044] In one example, each of the vector register fields 204, 206, and 208 is used in conjunction with the RXB field 214 to specify a vector register. For example, the RXB field 214 contains the most significant bit of the operand specified by the vector register. Bits of the register specification not specified by the instruction are reserved and are set to 0. The most significant bit is, for example, concatenated to the left of the 4-bit register specification of the vector register field to create a 5-bit vector register specification.

[0045] In one example, the RXB field includes four bits (eg, bits 0-3), each defined as follows: 0 - The most significant bit of the instruction's first vector register specification (e.g., bits 8 through 11). 1 - The most significant bit of the instruction's second vector register specification (e.g., bits 12-15), if present. 2 - The most significant bit of the instruction's third vector register specification (e.g., bits 16-19), if present. 3 - The most significant bit of the instruction's fourth vector register specification (e.g., bits 32-35), if present. Each bit is set to 0 or 1 depending on the register number, e.g., by an assembler. For example, for registers 0-15, the bit is set to 0, for registers 16-31, the bit is set to 1, etc.

[0046] In one embodiment, each RXB bit is an extension bit for a particular position in an instruction containing one or more vector registers. For example, bit 0 of RXB is the extension bit for positions 8-11, assigned to, for example, V1, and so on. Specifically, for vector registers, registers containing operands are specified using a 4-bit field in the register field, for example, with the corresponding register extension bit (RXB) added as the most significant bit. For example, if the 4-bit field is 0110 and the extension bit is 0, then the 5-bit field 00110 indicates register number 6. In a further embodiment, the RXB field includes additional bits, so that two or more bits per vector or position are used as extensions.

[0047] In one example, the size of the first operand is selected by a floating-point format control specified, for example, in the M4 field 212. The M4 field specifies the hexadecimal floating-point format of operand 1. If a reserved value for the M4 field is specified, a specification exception is recognized. Example values ​​for the M4 field include, for example:

[0048] M 4 floating point format

[0049] 0~1 Reserve

[0050] 2 Short form

[0051] 3 long format

[0052] 4 Extended Format

[0053] 5~15 spare

[0054] Although particular values ​​and formats are provided as examples, more values ​​and / or formats, fewer values ​​and / or formats, or other values ​​and / or formats, or combinations thereof, may be used.

[0055] In one example, the M5 field 210 is used to specify the rounding mode. The scaled and converted result is rounded by a rounding technique as specified by the rounding mode control in the M5 field, e.g., bit 3 of the 4-bit M5 field. When this control (e.g., bit) is, e.g., 0, the normalized result obtained from the converted result is truncated to form the result. When this control is, e.g., 1, the normalized result is rounded to the nearest value away from 0. The normalized result includes, e.g., 29, 15, or 7 most significant hexadecimal digits of the scaled and converted result, including, in one example, one guard digit on the right, for the extended, long, and short formats, respectively. (The guard digit may improve the precision of the final result because it is involved in certain operations that occur during normalization, including, e.g., addition, subtraction, comparison, and left shift.) A 1 is added to the leftmost bit of the guard digit of the normalized result, the carry is propagated to the left, and the guard digit is removed to generate the fractional part of the result.

[0056] In one embodiment of the Decimal Scale and Convert to Hexadecimal Floating-Point instruction, the second operand is scaled and converted to a hexadecimal floating-point number using the unsigned integer at a selected position (e.g., byte element 7) of the third operand. The second operand is multiplied by a scale factor equal to, for example, 10 to the power of byte element 7 of the third operand. The scaled result is converted, for example, to a hexadecimal floating-point value. The size of the first operand is selected by the floating-point format control in the M4 field. The scaled and converted result (e.g., the normalized and converted result) is rounded using the rounding technique specified in the M5 field. Based on the rounding mode control specified in M5, the result obtained by rounding the normalized and converted result is placed into the entire vector register specified by the first operand, for all formats, for example, by placing the result in the element counting from 0 in the vector and placing 0 in all other elements.

[0057] The sign of the result is equal to the sign code of the second operand, except when the second operand is zero, in which case the result is coerced to a positive true zero, which is a hexadecimal floating-point number with a zero exponent and a zero fraction.

[0058] In one example, the digits and sign of the second operand are checked for validity. If the validity check fails, a general operand data exception is recognized.

[0059] Further details of one embodiment of a process based on execution of decimal scaling and conversion to hexadecimal floating point instructions in accordance with one or more aspects of the present invention are described with reference to Figures 3-6. In one example, a processor, such as general processor 104, is used to execute the instructions. As an example, processor hardware is used to execute the instructions. The hardware may be within or coupled to the processor for the purpose of receiving instructions from the processor, which may, for example, retrieve, decode, and set the instructions for execution on the hardware. Other variations are possible.

[0060] 3, initially, an instruction, such as a decimal scaling and conversion to hexadecimal floating-point instruction, is obtained (e.g., fetched, received, provided, etc.) (300) and executed (310). This execution includes, for example, obtaining a second operand and a third operand of the instruction (312). The second operand may be, for example, a signed packed decimal number obtained from a location (e.g., a vector register) specified by the instruction (e.g., using the V2 field 206), and the third operand may include, for example, an unsigned integer obtained from a location (e.g., a vector register) specified by the instruction (e.g., using the V3 field 208). In one example, the unsigned integer is located in byte element 7 of the third operand.

[0061] The second operand (e.g., a signed packed decimal obtained using V2) is scaled using the unsigned integer in, e.g., byte element 7 of the third operand (e.g., obtained using V3) to obtain a scaled result (314).

[0062] The scaled result in one format (e.g., a decimal number such as a signed packed decimal number, also known as a binary-coded decimal number) is converted (316) to a converted result in another format. For example, the scaled decimal number is converted to a hexadecimal floating-point number. As described herein, a result obtained from the converted result is placed (320) in the location of the first operand (e.g., a register specified using V1). Further details regarding scaling, conversion, and placing are described with reference to FIGS. 4-6.

[0063] Referring first to FIG. 4, one embodiment for performing scaling of a second operand (314 in FIG. 3) is described. In one example, a value, called a scale value, of a selected portion (e.g., byte element 7) of the third operand (stored in a vector register specified using V3) is obtained (400). A determination is made as to whether the value is valid (410). For example, a determination is made as to whether the value has a predetermined relationship to a preselected value (e.g., is the value less than a preselected value, such as 8, as an example). If the value is invalid, processing terminates, e.g., with an error. However, if the value is valid, processing proceeds by determining a scale factor using the value. For example, the scale factor is equal to 10 raised to the value (415). The second operand is multiplied by the scale factor to obtain a scaled result (420). In one example, because the second operand is a signed packed decimal number, scaling by a power of 10 is equivalent to shifting digits to the left. Scaling facilitates the conversion of signed packed decimal numbers to hexadecimal floating-point numbers, for example, by isolating certain digits of the number to indicate selected positions within the number for truncation or rounding, for example.

[0064] The scaled result, which is in one format (e.g., decimal format), is then converted to a converted result, which is in another format (e.g., hexadecimal floating point format) (316 in FIG. 3). This conversion can be performed using a number of techniques. In one example, to convert a decimal number to a hexadecimal number, the following is performed:

[0065] Divide a decimal number by 16 to get the quotient and remainder.

[0066] The remainder multiplied by 16 becomes the first hexadecimal digit starting from the rightmost digit.

[0067] Divide the quotient by 16 to get another quotient and remainder.

[0068] This process is repeated, starting with 16 times the remainder, until the quotient is zero.

[0069] While the above technique is used to convert decimal numbers to hexadecimal numbers, other techniques may be used. In one example, hardware logic is used to improve the speed at which the process is performed and facilitate the conversion.

[0070] One example of hardware logic used to perform the conversion is described with reference to FIG. 5. Referring to FIG. 5, in one example, a binary-coded decimal number 500 is input to the logic. First, up to four binary-coded decimal digits are selected 510, starting with the leftmost digit of the binary-coded decimal number. The selected digits are input to a counter tree 520, which multiplies each digit using a redundant form of the digit and an equation. In one example, this multiplication is performed by shifting the number, with each multiplication by a power of 2 resulting in a shift of the number.

[0071] One example of an equation used by a counter tree is as follows: Initially, (X'+Y') is set to 0 and represents the value resulting from the previous loop in the counter tree, and A, B, C, and D are the digits of the binary coded decimal (BCD) number.

[0072] New total = X+Y=(X'+Y')*10000+A*1000+B*100+C*10+D

[0073] =(X'+Y')*(2 13 +2 11 -2 8 +2 4 )

[0074] +A*(2 9 +2 8 +2 7 +2 6 +2 5 +2 3 )

[0075] +B*(2 6 +2 5 +2 2 )

[0076] +C*(2 3 +2 1 )

[0077] +D

[0078] Processing loops within the counter tree until all digits of the BCD number have been processed. The output of counter tree 520 is input to 2:1 adder 530, which provides an intermediate converted result (e.g., an intermediate hexadecimal floating-point number) in non-redundant format. The output of adder 530 is input to hex normalize, update exponent logic 540, which is used to normalize the output of the adder and update the exponent to provide a hexadecimal floating-point number. For example, normalization involves shifting all leading zero digits to the right of the radix point to the left, removing those digits, and decreasing the exponent by one per shift.

[0079] One specific example of the above process for an 8-digit BCD number is described herein. In the following example, Z is used, which is implementation independent, because the actual values ​​of X and Y are implementation specific (e.g., X and Y can be different values ​​but still have the same total). Thus, Z=X+Y, Z'=X'+Y', and Z' is initialized to 0. Furthermore, in this example, BCD=32610423, and therefore, initially A=3, B=2, C=6, and D=1.

[0080] formula Hexadecimal Value

[0081] Z=0*(2 13 +2 11 -2 8 +2 4 ) Z=x0

[0082] +3*(2 9 +2 8 +2 7 +2 6 +2 5 +2 3 ) +xBB8

[0083] +2*(2 6 +2 5 +2 2 ) +xC8

[0084] +6*(2 3 +2 1 ) +x3C

[0085] +1 +x1

[0086] Z=0+3000+200+60+1=3261 Z=xCBD

[0087] Next, A=0, B=4, C=2, D=3.

[0088] Z=3261*(2 13 +2 11 -2 8 +2 4 ) Z=1F196D0

[0089] +0*(2 9 +2 8 +2 7 +2 6 +2 5 +2 3 ) +x0

[0090] +4*(2 6 +2 5 +2 2 ) +x190

[0091] +2*(2 3 +2 1 ) +x14

[0092] +3 +x3

[0093] Z=32610000+400+20+3=32610423 Z=x1F19877

[0094] The hexadecimal floating-point number (also referred to herein as the converted result) is used in obtaining a result, which is placed in the first operand position, such as a register specified using V1 (320 in FIG. 3), as described with reference to FIG. 6. In one embodiment, a selected rounding mode is determined (600). For example, a rounding mode indicator specified by M5 is obtained and used to determine the rounding mode. The converted result (e.g., a version of the converted result) is then rounded based on the specified rounding mode to obtain a result (602). For example, if this control (e.g., bit) is, for example, 0, the normalized result obtained from the converted result is truncated to form the result. If this control is, for example, 1, the normalized result is rounded to the nearest value away from 0. The normalized result includes, for example, 29, 15, or 7 most significant hexadecimal digits of the scaled and converted result, including one guard digit on the right, for the extended, long, and short formats, respectively. A 1 is added to the leftmost bit of the guard digit of the normalized result, the carry is propagated left, and the guard digit is removed to produce the mantissa of the result.

[0095] In one example, the sign of the result is also determined 604. For example, the sign of the result is equal to the sign code of the second operand, except when the second operand is zero, in which case the result is forced to be a positive true zero. A true zero is a hexadecimal floating-point number with a zero exponent and a zero fraction.

[0096] Further, in one example, the format of the first operand is determined (606). For example, the value stored in the M4 field is retrieved to determine the selected format. The result (e.g., the scaled, converted, normalized, and rounded hexadecimal floating-point result) and sign are placed (608) in selected locations (e.g., registers specified using V1) based on the selected format. For example, for each of the formats, the result is placed, for example, starting with the element counted from 0 in the vector, and placing 0 in all other elements, so that the result and sign are placed throughout the vector register specified by the first operand.

[0097] Although various fields and registers of the decimal scaling and conversion to hexadecimal floating point instructions have been described, one or more aspects of the present invention may use other more or fewer fields and / or registers, or other sized fields and / or registers, or combinations thereof, etc. Many variations are possible. For example, implicit registers may be used in place of explicitly specified registers and / or fields of the instruction, or explicitly specified registers and / or fields may be used in place of implicit registers and / or fields, or combinations thereof. Other variations are also possible.

[0098] As described herein, in one aspect, a single instruction (e.g., a single designed machine instruction at a hardware / software interface (e.g., a decimal scale and convert to hexadecimal floating-point instruction)) is provided to scale a decimal number to provide a scaled decimal number and convert the scaled decimal number to a hexadecimal floating-point number. Furthermore, in one embodiment, the single instruction can round the converted result (e.g., a version of the converted result, such as a normalized converted result) based on a selected rounding mode, or format the result based on a selected format of multiple possible formats, or both. The instruction can, for example, be a hardware instruction defined in an instruction set architecture (ISA) that directly converts a value in one format (e.g., decimal) to a value in another format (e.g., hexadecimal floating-point). This conversion is, for example, a direct conversion from decimal to hexadecimal floating point, rather than a conversion from decimal to integer and then from integer to hexadecimal floating point. This is faster and more efficient than, for example, a program that performs a binary-coded decimal multiplication or shift, converts the binary-coded decimal to an integer, and then converts the integer to hexadecimal floating point. The program complexity associated with performing scaling and conversion operations is reduced. Furthermore, the performance of the operation (and therefore the processor) is improved. Hardware instruction execution reduces execution time and improves performance.

[0099] By performing, for example, scaling and conversion (and optionally rounding and / or other operations) using a single instruction rather than multiple instructions, performance is improved by not requiring multiple passes through a hardware / software interface. Furthermore, by performing operations as part of a single instruction, the operations do not require updating registers in the processor's register file (i.e., the array of processor registers used to store data between memory and functional units (e.g., floating-point processing units)) before completing the operation, and remain within the processing unit (e.g., floating-point processing unit) performing the operation. This improves execution time and reduces processor resource usage.

[0100] In a further aspect, hexadecimal floating-point values ​​are converted to decimal values ​​(e.g., binary-coded decimal values). To provide this conversion, in one example, a single designed machine instruction, referred to herein as a hexadecimal floating-point to scaled decimal vector conversion instruction, is used. This single instruction, as part of executing an instruction, at least converts a value from one format (e.g., hexadecimal floating-point) to a converted result in another format (e.g., a decimal number such as binary-coded decimal) and scales the converted result to provide a scaled result (e.g., a scaled decimal value).

[0101] One embodiment of a hexadecimal floating-point to scaled decimal vector conversion instruction used to perform at least the conversion and scaling operations is described with reference to FIG. 7 . The instruction, in one example, is executed using a general-purpose processor (e.g., processor 104). In the description herein, specific locations of fields, specific fields, and / or specific sizes are indicated (e.g., specific bytes and / or bits). However, other locations, fields, and / or sizes may be provided. Furthermore, while setting bits to specific values ​​(e.g., 1 or 0) may be specified, this is merely an example. Bits may be set to different values, such as opposite or different values, in other examples. Many variations are possible.

[0102] In one example, a hexadecimal floating-point to scaled decimal vector conversion instruction has a VRR-j format that indicates vector registers and register operations along with an extended operation code (opcode). This instruction is part of, for example, a vector function, as described herein.

[0103] As shown in FIG. 7, in one example, a hexadecimal floating-point to scaled decimal vector convert instruction 700 includes multiple fields, which may have subscript numbers associated with them. The subscript numbers associated with fields of the instruction indicate the operand to which the field applies. For example, a subscript number 1 associated with vector register V1 indicates that the register specified using V1 contains the first operand, and so on. The length of the register operand is one register, e.g., 128 bits.

[0104] In one embodiment, the hexadecimal floating-point to scaled decimal vector conversion instruction 700 includes operation code (opcode) fields 702a, 702b (e.g., bits 0-7 and 40-47) indicating a conversion and scaling operation where the input data is, e.g., a hexadecimal floating-point number and the output is, e.g., a decimal number (e.g., a binary-coded decimal), a first vector register (V1) field 704 (e.g., bits 8-11) used to specify a first vector register, a second vector register (V2) field 706 (e.g., bits 12-15) used to specify a second vector register, a third vector register (V3) field 708 (e.g., bits 16-19) used to specify a third vector register, a mask (M4) field 710 (e.g., bits 24-27), and a register extension bits (RXB) field 712 (e.g., bits 36-39), each of which is described below. In one embodiment, each field is separate and independent of one another, but in other embodiments, two or more fields may be combined. More information regarding these fields is described below.

[0105] In one embodiment, the vector register (V1) field 704 is used to indicate a vector register that stores a first operand. The first operand is the result of converting a hexadecimal floating-point value to a decimal value, scaling the decimal value to provide a scaled result, and using the scaled result to obtain a result. The second operand is contained in a vector register specified using the vector register (V2) field 706 and is, for example, an extended-precision hexadecimal floating-point number. The extended-precision hexadecimal floating-point number is converted to a binary-coded decimal number, and this binary-coded decimal number is scaled using an unsigned integer contained in a third operand contained in a vector register specified using the vector register (V3) field 708. In one example, each of the vector register fields 704, 706, and 708 is used in conjunction with the RXB field 712 to specify a vector register, as described herein.

[0106] In one example, the M4 field 710 is used to specify the rounding mode. The converted and scaled result is rounded by a rounding technique as specified by the rounding mode modifier in the M4 field, e.g., bit 3 of the 4-bit M4 field. If this control (e.g., bit) is, e.g., 0, the scaled result is truncated to form the result. If this bit is, e.g., 1, the scaled result is rounded to the nearest value away from 0.

[0107] In execution of one embodiment of the hexadecimal floating-point to scaled decimal vector convert instruction, a second operand (e.g., an extended-precision hexadecimal floating-point number) is converted to a converted result (e.g., a binary-coded decimal number), the converted result is scaled to provide a scaled result, and the scaled result is, for example, rounded to obtain a result (e.g., a decimal integer).

[0108] Further details of one embodiment of a process based on execution of a hexadecimal floating-point to scaled decimal vector conversion instruction in accordance with one or more aspects of the present invention are described with reference to FIGS. 8-10. In one example, a processor, such as general processor 104, is used to execute the instructions. As an example, processor hardware is used to execute the instructions. The hardware may be within or coupled to the processor for the purpose of receiving instructions from the processor, which may, for example, retrieve, decode, and set the instructions for execution on the hardware. Other variations are possible.

[0109] 8, initially, an instruction, such as a hexadecimal floating-point to scaled decimal vector conversion instruction, is obtained (e.g., fetched, received, provided, etc.) (800) and executed (810). This execution includes, for example, obtaining a second operand and a third operand of the instruction (812). The second operand may be, for example, an extended-precision hexadecimal floating-point number obtained from a location (e.g., a vector register) specified by the instruction (e.g., using the V2 field 706), and the third operand may include, for example, an unsigned integer obtained from a location (e.g., a vector register) specified by the instruction (e.g., using the V3 field 708). In one example, the unsigned integer is located in byte element 7 of the third operand.

[0110] The second operand, which is in one format (e.g., an extended-precision hexadecimal floating-point number obtained using V2), is converted (814) to another format (e.g., a binary-coded decimal number), referred to herein as a converted result. The converted result is scaled (816) using the unsigned integer in, e.g., byte element 7 of the third operand (e.g., obtained using V3) to obtain a scaled result. The scaled result is rounded based on the rounding mode specified in the M4 field 710 to obtain a rounded result (e.g., a decimal integer) (818). The result obtained from the rounded result is placed (820) in the location of the first operand (e.g., in the vector register specified using V1). Further details regarding conversion, scaling, and placement are described below.

[0111] As shown, a second operand in one format (e.g., an extended-precision hexadecimal floating-point number obtained using V2) is converted to another format (e.g., a binary-coded decimal number) called the converted result (814 in Figure 8). This conversion may be performed using multiple techniques. In one example, this conversion involves converting a hexadecimal number to a decimal number. To perform such a conversion, in one example, the decimal equivalent of each hexadecimal digit is multiplied by a power of 16, starting with 0 in the rightmost hexadecimal digit and increasing by 1 for each subsequent digit. For example, to convert the hexadecimal number ABC to decimal, C=12 is multiplied by 16. 0 is multiplied (12x1=12), B=11 to 16 1 is multiplied (11x16=176), A=10 is multiplied by 16 2 (10x256=2560). The results of each multiplication are then added together: 12+176+2560=2748, etc. Thus, the hexadecimal number ABC is equal to 2748 in decimal.

[0112] Additionally, if a fractional part is present, in one example, the fractional part is converted to a decimal number as follows: The decimal equivalent of each hexadecimal digit in the fractional part is multiplied by a negative power of 16, starting with -1 for the leftmost hexadecimal digit after the period and increasing by 1 for each subsequent digit. For example, to convert the hexadecimal number .DEF to a decimal number, multiply D=13 by 16. -1 is multiplied (13 x 0.0625 = 0.8125), E = 14 to 16 -2 is multiplied (14 x 0.00390625 = 0.0546875), F = 15 to 16 -3 (15 x 0.0000244140625 = 0.87084960937). The results of each multiplication are then added together: 0.8125 + 0.0546875 + 0.87084960937 = 0.87084960937, etc. Thus, the hexadecimal number .DEF is equal to 0.87084960937 in decimal.

[0113] In one example, an integer value (e.g., 2748) is combined with a fractional value (0.87084960937) to result in 2748.87084960937, the decimal equivalent of xABC.DEF.

[0114] While the above technique is used to convert hexadecimal to decimal, other techniques may be used. In one example, hardware logic is used to improve the speed at which the process is performed and facilitate the conversion.

[0115] One example of hardware logic used to perform the conversion is described with reference to Figure 9. A specific example is shown to facilitate understanding of the hardware logic, but this is only an example and is not intended to be limiting in any way.

[0116] Referring to Figure 9, in one example, a hexadecimal floating point number (HFP) 900 is input to the logic. As a specific example, the input hexadecimal floating point number is ABC.DEF. First, the hexadecimal floating point number is split 910 into a hexadecimal floating point fractional portion 912 (e.g., .DEF) and a hexadecimal floating point integer portion (e.g., ABC) 914. The fractional portion 912 and a selected value (e.g., decimal 10) are then added together to form a hexadecimal floating point integer portion 914. 8 =x5F5E100) is input to counter tree 920. The counter tree multiplies x5F5E100 by the fractional part's redundant form of the fractional part and provides the result. The output of counter tree 920 is input to 2:1 adder 922, which provides a non-redundant product including the integer part and the fractional part. For example, if the output of adder 922 is 530CFA0F00, this value is input to split logic 910, which splits the value into an integer part 530CFA0 and a fractional part F00, and the process repeats.

[0117] The integer portion 914 (e.g., ABC) is input to the hexadecimal-to-decimal conversion logic 930 with a shift amount of 5 (e.g., 00000ABC). In one example, starting with the most significant digit, two hexadecimal digits are converted to binary-coded decimal per cycle; converting eight hexadecimal digits requires four loops. For example, for the integer portion, S=0, H(i,i+1)=>A, the previous accumulated sum is passed through eight binary-coded decimal doublers (2x) to multiply by, for example, 256. The converted hexadecimal digit is then summed with the old sum * 256 (S' = S * 256 + A, i = i + 2). Converting eight hexadecimal digits requires four loops.

[0118] As shown, the output of hex to decimal conversion logic 930 and up to eight decimal digits 934 from the previous loop are input to adder 932 (e.g., a 2:1 adder). For the particular example given, the output of adder 932 after the second loop is 2748.87084960. The final output of the adder is input to final shift and round logic 936. In one example, 10 5 There is a scaling and rounding function by . So ABC.DEF in hexadecimal is converted to binary coded decimal of 274887085 (10 5 Scaling and rounding by 2748.87084960 = 274887085).

[0119] In summary, for a 6 digit hex number such as ABC.DEF and a shift amount of 5, the logic performs the following:

[0120] ABC converted to BCD => 2748

[0121] DEF to 10 8 =5F5E100 multiplied =>530CFA0.F00

[0122] 530CFA0 converted to BCD => 87084960

[0123] 2748*10 8 +87084960=274887084960

[0124] In one example, 10 8 When multiplying, the original base point is maintained, so 10 -8 Multiply by 10 8 Cancels the multiplication by .

[0125] 2748.87084960 and 10 5 Scaling and rounding by = 274887085.

[0126] In one example, after converting the hexadecimal number to binary-coded decimal, the converted result is scaled (816 in FIG. 8). For example, as described with reference to FIG. 4, a value, called a scale value, of a selected portion (e.g., byte element 7) of the third operand (stored in a vector register specified using V3) is obtained (400). A determination is made as to whether the value is valid (410). For example, a determination is made as to whether the value has a predetermined relationship to a preselected value (e.g., is the value less than a preselected value, such as 32, as an example). If the value is invalid, processing terminates, e.g., with an error. However, if the value is valid, processing proceeds by determining a scale factor using the value. For example, the scale factor is equal to 10 raised to the value power (415). The second operand is multiplied by the scale factor to obtain a scaled result (420). In one example, scaling by a power of 10 is equivalent to a shift operation. Scaling facilitates the conversion of extended precision hexadecimal floating point numbers, for example, by allowing more digits to be converted when the result is a decimal number.

[0127] In one example, the converted and scaled value is rounded to obtain a rounded result (818 in FIG. 8). For example, the scaled result is rounded by a rounding technique as specified by a rounding mode modifier in the M4 field, e.g., bit 3 of the 4-bit M4 field 710. If this control (e.g., bit) is, e.g., 0, the scaled result is truncated to form the result. If this control is, e.g., 1, the scaled result is rounded to the nearest value away from 0. A result is obtained from the rounded result. For example, a selected portion of the rounded result is selected as the result (e.g., a decimal number, such as a 32-digit signed packed decimal number), and this result is placed in the first operand position (820 in FIG. 8).

[0128] Further details regarding one embodiment of the arrangement are described with reference to Figure 10. In one embodiment, a portion of the rounded result (e.g., the rightmost 31 digits of the decimal integer, ignoring overflow) is selected as the decimal integer result (1000). Additionally, in one example, the sign of the result is determined (1002). For example, the sign of the result is equal to the sign of the second operand, even if the second operand is negative zero. The result and sign are placed in the position of the first operand (1004).

[0129] Although various fields and registers of the hexadecimal floating-point to scaled decimal vector convert instruction have been described, one or more aspects of the present invention may use other more or fewer fields and / or registers, other sized fields and / or registers, or combinations thereof, etc. Many variations are possible. For example, implicit registers may be used in place of the explicitly specified registers and / or fields of the instruction, or explicitly specified registers and / or fields may be used in place of the implicit registers and / or fields, or combinations thereof. Other variations are also possible.

[0130] As described herein, in one aspect, a single instruction (e.g., a single designed machine instruction at a hardware / software interface (e.g., a hexadecimal floating-point to scaled decimal vector conversion instruction)) is provided to convert a hexadecimal floating-point number to a decimal number and scale the decimal number to provide a scaled decimal number. Furthermore, in one embodiment, the single instruction can also round the converted and scaled result based on a selected rounding mode. The instruction is, for example, a hardware instruction defined in an instruction set architecture (ISA) that directly converts a value in one format (e.g., a hexadecimal floating-point number) to a value in another format (e.g., a decimal number). This conversion is performed by a program directly, for example, from a hexadecimal floating-point number to a decimal number, rather than converting from a hexadecimal floating-point number to an integer and from an integer to a decimal number. This results in faster and more efficient processing, and reduced program complexity associated with performing the conversion and scaling operations. Furthermore, the performance of the operation (and therefore the processor) is improved: hardware instruction execution reduces execution time and improves performance.

[0131] By performing, for example, conversion and scaling operations (and optionally, rounding) using a single instruction rather than multiple instructions, performance is improved by not requiring multiple passes through a hardware / software interface. Furthermore, by performing operations as part of a single instruction, the operations remain within the processing unit (e.g., floating-point processing unit) performing the operations, rather than requiring updates to registers in the processor's register file (i.e., the array of processor registers used to store data between memory and functional units (e.g., floating-point processing unit)) before completing the operation. This improves execution time and reduces processor resource usage.

[0132] One or more aspects of the present invention are closely related to computer technology and facilitate processing within a computer and improve its performance. Using a single designed machine instruction for at least performing scaling of a decimal number (e.g., a binary-coded decimal number) to obtain a scaled decimal number, converting the scaled decimal number to a hexadecimal floating-point number, and optionally performing rounding improves performance within a computing environment by reducing complexity, reducing resource usage, and increasing processing speed. Furthermore, using a single designed machine instruction for converting a hexadecimal floating-point number to a decimal number (e.g., a binary-coded decimal number) and scaling the decimal number to obtain a scaled decimal number (and, in one embodiment, rounding the result and / or performing other operations) improves performance within a computing environment by reducing complexity, reducing resource usage, and increasing processing speed. The data and / or instructions may be used in many technical fields, such as computer processing, medical processing, design, automotive technology, and manufacturing. Achieving optimization in the conversion of data improves these technical fields by reducing execution time.

[0133] Further details of embodiments that facilitate processing within a computing environment as it relates to one or more aspects of the present invention are described with reference to FIGS. 11A-11C.

[0134] 11A, in one embodiment, instructions for performing conversion and scaling operations are executed 1100. Executing the instructions includes converting input values ​​from one format to provide a converted result in another format 1102, scaling the converted values ​​to provide a scaled result 1104, and placing a result obtained from the scaled result in a selected location 1106.

[0135] By performing transformation and scaling operations using a single instruction, performance is improved and resource utilization is reduced. By performing transformation and scaling operations using a single designed instruction, certain tasks, such as transformation and scaling operations, can be performed much more efficiently than using a software paradigm. Transformation and scaling operations are performed much faster, reducing execution time and improving performance of the processor and / or the overall system.

[0136] In one example, one format is a hexadecimal floating point format and the other format is a decimal format 1108. In one example, the decimal format is a binary coded decimal format 1110.

[0137] In one example, scaling includes determining a scale factor (1112) and using the scale factor in scaling the transformed result to provide a scaled result (1114). Determining the scale factor includes, for example, obtaining a scale value using an operand of the instruction (1116) and determining a scale factor using the scale value (1118). Using the scale factor includes multiplying the transformed result by the scale factor to obtain a scaled result (1120).

[0138] Scaling, for example, isolates particular digits of a number to indicate selected positions within the number for truncation or rounding, for example.

[0139] In one example, referring to 11B, the executing further includes rounding the scaled result to provide a rounded result (1130). For example, the rounding includes obtaining a rounding mode using a field of the instruction (1132) and rounding the scaled result to a rounded result based on the rounding mode (1134).

[0140] By performing at least the conversion, scaling, and rounding operations using a single instruction, performance is improved and resource utilization is reduced. By performing the conversion, scaling, and rounding operations using a single designed instruction, certain tasks, such as conversion, scaling, and rounding operations, can be performed much more efficiently than using a software paradigm. The conversion, scaling, and rounding operations are performed much faster, reducing execution time and improving the performance of the processor and / or the overall system.

[0141] In one example, the placing includes selecting a portion of the rounded result as a result (1136) and placing the result in a selected location (1138). In one example, the sign of the result is determined (1140) and the sign of the result is placed in a selected location (1142). The selected location includes, for example, a register specified using a field of the instruction (1144).

[0142] 11C , in one embodiment, instructions for performing scaling and conversion operations are executed 1150. Executing the instructions includes, for example, scaling input values ​​in one format to provide a scaled result 1152, converting the scaled result from one format to provide a converted result in another format 1154, and placing a result obtained from the converted result in a selected location 1156.

[0143] By performing at least the scaling and transformation operations using a single instruction, performance is improved and resource utilization is reduced. By performing the scaling and transformation operations using a single designed instruction, certain tasks, such as scaling and transformation operations, can be performed much more efficiently than using a software paradigm. The scaling and transformation operations are performed much faster, reducing execution time and improving performance of the processor and / or the overall system.

[0144] In one example, executing the instruction further includes rounding a version of the converted result to provide a rounded result (1160), and the result is obtained using the rounded result (1162).

[0145] By performing at least scaling, conversion, and rounding operations using a single instruction, performance is improved and resource utilization is reduced. By performing scaling, conversion, and rounding operations using a single designed instruction, certain tasks, such as scaling, conversion, and rounding operations, can be performed much more efficiently than using a software paradigm. Scaling, conversion, and rounding operations are performed much faster, reducing execution time and improving performance of the processor and / or the overall system.

[0146] As an example, the selected location is a register specified using a field of the instruction (1170), and placing the result in the selected location includes determining a format of the result (1172) and placing the result in the register based on the format (1174).

[0147] Other variations and embodiments are possible.

[0148] Aspects of the present invention may be employed by many types of computing environments. Another example of a computing environment for incorporating and using one or more aspects of the present invention is described with reference to FIG. 12A. As an example, the computing environment of FIG. 12A is based on the z / Architecture® hardware architecture offered by International Business Machines Corporation (Armonk, New York). However, the z / Architecture hardware architecture is only one exemplary architecture. Additionally, computing environments may be based on other architectures, including, but not limited to, the Intel® x86 architecture, other architectures from International Business Machines Corporation, or architectures from other companies, or combinations thereof. Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

[0149] In one example, computing environment 10 includes a central electronics complex (CEC) 11. Central electronics complex 11 includes multiple components, such as, for example, memory 12 (also called system memory, main memory, primary storage, central storage, or storage) coupled to one or more processors (also called central processing units (CPUs)) 13 and an input / output (I / O) subsystem 14.

[0150] I / O subsystem 14 may be part of or separate from the central electronics complex. I / O subsystem 14 directs the flow of information between main memory 12 and input / output control unit 15 and input / output (I / O) devices 16 coupled to the central electronics complex.

[0151] Many types of I / O devices may be used. One particular type is a data storage device 17. The data storage device 17 may store one or more programs 18, one or more computer-readable program instructions 19, or data, or a combination thereof. The computer-readable program instructions may be configured to perform the functions of embodiments of aspects of the present invention.

[0152] Central electronics complex 11 can include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, central electronics complex 11 can include and / or be coupled to non-removable, non-volatile magnetic media (typically referred to as "hard drives"), magnetic disk drives for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), and / or optical disk drives for reading from and writing to removable, non-volatile optical disks such as CD-ROMs, DVD-ROMs, or other optical media. It should be understood that other hardware and / or software components can be used in conjunction with central electronics complex 11, including, but not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0153] Additionally, central electronics complex 11 can operate in numerous other general purpose or special purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, suitable for use with central electronics complex 11 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of these systems or devices.

[0154] In one or more embodiments, central electronics complex 11 provides support for logical partitioning and / or virtualization. In one embodiment, as shown in FIG. 12B , memory 12 includes, for example, one or more logical partitions 20, a hypervisor 21 that manages the logical partitions, and processor firmware 22. One example of hypervisor 21 is the Processor Resource / System Manager (PR / SM™) offered by International Business Machines Corporation (Armonk, New York). As used herein, firmware includes, for example, processor microcode. Firmware includes, for example, hardware-level instructions and / or data structures used in implementing higher-level machine code. In one embodiment, firmware includes proprietary code that controls operating system access to the system's hardware, typically provided as microcode containing trusted software or microcode specific to the underlying hardware. PR / SM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0155] Each logical partition 20 can function as a separate system. That is, each logical partition can be reset independently, run a guest operating system 23, such as the z / OS® operating system provided by International Business Machines Corporation (Armonk, New York), or other control code 24, such as coupling facility control code (CFCC), and operate with different programs 25. An operating system or application program running within a logical partition appears to have access to the entire system, but in fact, only a portion of it is available. While the z / OS operating system is provided as an example, other operating systems provided by International Business Machines Corporation, other companies, or both, may be used in accordance with one or more aspects of the present invention.

[0156] Memory 12 is coupled to CPU 13 (FIG. 12A), which is a physical processor resource that is assigned to a logical partition. For example, logical partition 20 includes one or more logical processors, each of which represents all or a portion of physical processor resource 13 that is dynamically assigned to the logical partition.

[0157] In yet another embodiment, the central electronics complex provides support for virtual machines (which may or may not support logical partitioning). As shown in FIG. 12C, memory 12 of central electronics complex 11 includes, for example, one or more virtual machines 26, a virtual machine manager (e.g., hypervisor 27) that manages the virtual machines, and processor firmware 28. One example of hypervisor 27 is the z / VM® hypervisor offered by International Business Machines Corporation (Armonk, New York). A hypervisor may be referred to as a host. z / VM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0158] The central electronics complex's virtual machine support allows multiple virtual machines 26 to be run, each running a different program 29 and a guest operating system 30, such as the Linux® operating system. Each virtual machine 26 can function as a separate system; that is, each virtual machine can be reset independently, run a guest operating system, and run different programs. An operating system or application program running within a virtual machine appears to have access to the entire system, but in fact only a portion of it is available. While z / VM and Linux are provided as examples, other virtual machine managers and / or operating systems may be used in accordance with one or more aspects of the present invention. The registered trademark Linux® is used pursuant to a sublicense from the Linux Foundation (an exclusive licensee of Linus Torvalds, owner of the trademark worldwide).

[0159] Another embodiment of a computing environment for incorporating and using one or more aspects of the present invention is described with reference to FIG. 13A. In this example, computing environment 36 includes a native central processing unit (CPU) 37, memory 38, and one or more input / output devices and / or interfaces 39, coupled together, for example, via one or more buses 40 or other connections. By way of example, computing environment 36 may include a PowerPC® processor offered by International Business Machines Corporation (Armonk, New York), an HP Superdome with an Intel® Itanium® II processor offered by Hewlett-Packard Company (Palo Alto, California), or other machines based on architectures offered by International Business Machines Corporation, Hewlett-Packard Company, Intel Corporation, Oracle Corporation, or other companies, or combinations thereof. PowerPC is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Itanium is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

[0160] The native central processing unit 37 includes one or more native registers 41, such as one or more general purpose registers and / or one or more special purpose registers that are used during processing within the environment. These registers contain information that represents the state of the environment at any particular point in time.

[0161] Additionally, native central processing unit 37 executes instructions and code stored in memory 38. In one particular example, central processing unit executes emulator code 42 stored in memory 38. This code enables a computing environment configured with one architecture to emulate another architecture. For example, emulator code 42 enables machines based on architectures other than the z / Architecture hardware architecture (e.g., PowerPC processors, HP Superdome servers, etc.) to emulate the z / Architecture hardware architecture and execute software and instructions developed based on the z / Architecture hardware architecture.

[0162] Further details related to emulator code 42 are described with reference to FIG. 13B . Guest instructions 43 stored in memory 38 include software instructions (e.g., interrelated to machine instructions) developed to execute on an architecture other than that of native CPU 37. For example, guest instructions 43 are designed to execute on a processor based on the z / Architecture hardware architecture, but are instead emulated on native CPU 37, which may be, for example, an Intel Itanium II processor. In one example, emulator code 42 includes an instruction fetch routine 44 for retrieving one or more guest instructions 43 from memory 38 and, optionally, providing local buffering of the retrieved instructions. Emulator code 42 also includes an instruction conversion routine 45 for determining the type of the retrieved guest instruction and for converting the guest instruction into one or more corresponding native instructions 46. This conversion includes, for example, identifying a function performed by the guest instruction and selecting a native instruction to perform this function.

[0163] Additionally, emulator code 42 includes an emulation control routine 47 for causing execution of native instructions. Emulation control routine 47 may cause native CPU 37 to execute a routine of native instructions that emulates one or more already-fetched guest instructions, and upon completion of such execution, return control to an instruction fetch routine to emulate the fetch of the next guest instruction or group of guest instructions. Execution of native instructions 46 may include reading data from memory 38 into registers, storing data from registers back to memory, or performing any type of arithmetic or logical operation as determined by a translation routine.

[0164] For example, each routine is implemented in software that is stored in memory and executed by native central processing unit 37. In other examples, one or more of the routines or operations are implemented in firmware, hardware, software, or some combination thereof. The emulated processor's registers may be emulated using the native CPU's registers 41 or by using locations in memory 38. In embodiments, guest instructions 43, native instructions 46, and emulator code 42 may reside in the same memory or may be distributed among different memory devices.

[0165] Exemplary instructions that are emulated are the decimal scaling and conversion to hexadecimal floating point and hexadecimal floating point to scaled decimal vector conversion instructions described herein, in accordance with one or more aspects of the present invention.

[0166] The computing environments described above are only examples of computing environments that may be used. Other environments may be used, including, but not limited to, non-partitioned, partitioned, cloud, or emulated environments, or combinations thereof, and embodiments are not limited to any one environment. Although various examples of computing environments are described herein, one or more aspects of the present invention may be used with many types of environments. The computing environments provided herein are only examples.

[0167] Each computing environment can be configured to include one or more aspects of the present invention.

[0168] One or more aspects may relate to cloud computing.

[0169] Although this disclosure includes detailed descriptions of cloud computing, it should be understood that implementation of the teachings presented herein is not limited to cloud computing environments. Embodiments of the present invention may be implemented in conjunction with any other type of computing environment now known or later developed.

[0170] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computational resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) and for rapidly provisioning and releasing these resources with minimal administrative effort or interaction with a service provider. This cloud model may include at least five characteristics, at least three service models, and at least four deployment models.

[0171] The features are as follows:

[0172] On-demand self-service: Cloud customers can unilaterally and automatically provision computing power, such as server time and network storage, as needed, without the need for human interaction with the service provider.

[0173] Wide network access: Cloud capabilities are available over the network and can be accessed using standard mechanisms, facilitating usage by heterogeneous thin- or thick-client platforms (e.g., mobile phones, laptops, and PDAs).

[0174] Resource Pool: The provider's computing resources are pooled and offered to multiple consumers using a multi-tenant model. Various physical and virtual resources are dynamically allocated and reallocated according to demand. There is a sense of location independence; consumers typically have no control or knowledge regarding the exact location of the resources offered, although at a higher level of abstraction, they may be able to specify a location (e.g., country, state, or data center).

[0175] Rapid Elasticity: Cloud capacity can be quickly and elastically provisioned, in some cases automatically, to scale out quickly, and quickly released to scale in quickly. Capacity available for provisioning often appears to consumers as unlimited, available for purchase in any quantity at any time.

[0176] Metered Services: Cloud systems leverage metering capabilities to automatically control and optimize resource usage at an abstraction level appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of the services used.

[0177] The service model is as follows:

[0178] SaaS (Software as a Service): The consumer is provided with the ability to use the provider's applications running on a cloud infrastructure. Those applications can be accessed from a variety of client devices through thin-client interfaces such as web browsers (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or individual application features, except for the possibility of setting limited user-specific application configuration settings.

[0179] PaaS (Platform as a Service): The ability offered to a consumer is to deploy applications they create or acquire, written using programming languages ​​and tools supported by the provider, onto a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, or storage, but does have control over the deployed applications and, in some cases, the configuration of the application hosting environment.

[0180] Infrastructure as a Service (IaaS): The capability provided to a consumer is the provisioning of processing, storage, network, and other basic computing resources, upon which the consumer can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but has control over the operating system, storage, deployed applications, and in some cases, limited control over selected network components (e.g., host firewalls).

[0181] The deployment model is as follows:

[0182] Private Cloud: This cloud infrastructure is operated solely for the organization, can be managed by the organization or a third party, and can reside on-premise or off-premise.

[0183] Community Cloud: This cloud infrastructure is shared by multiple organizations to support a specific community with shared interests (e.g., mission, security requirements, policy, and compliance considerations). It can be managed by these organizations or a third party and can reside on-premises or off-premises.

[0184] Public cloud: This cloud infrastructure is available for use by the general public or large industry organizations and is owned by an organization that sells cloud services.

[0185] Hybrid cloud: This cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain distinct but are joined together by standardized or proprietary technologies that allow for data and application portability (e.g., cloud bursting to balance load between clouds).

[0186] A cloud computing environment is a service-oriented environment that emphasizes statelessness, loose coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that contains a network of interconnected nodes.

[0187] Referring now to FIG. 14 , an exemplary cloud computing environment 50 is illustrated. As illustrated, the cloud computing environment 50 includes one or more cloud computing nodes 52 with which local computing devices used by cloud consumers (e.g., a personal digital assistant (PDA) or mobile phone 54A, a desktop computer 54B, a laptop computer 54C, and / or an automobile computer system 54N) can communicate. The nodes 52 may communicate with each other. The nodes 52 may be physically or virtually grouped in one or more networks (not shown), such as a private cloud, community cloud, public cloud, or hybrid cloud, or combinations thereof, as previously described herein. This enables the cloud computing environment 50 to provide an infrastructure, platform, and / or SaaS that does not require cloud consumers to maintain resources on their local computing devices. The types of computing devices 54A-N shown in FIG. 14 are intended to be illustrative only, and it is understood that computing node 52 and cloud computing environment 50 can communicate with any type of computer-controlled device via any type of network and / or network-addressable connection (e.g., a connection using a web browser).

[0188] Referring now to Figure 15, there is shown a set of functional abstraction layers provided by cloud computing environment 50 (Figure 14). It should be understood in advance that the components, layers, and functions shown in Figure 15 are intended to be illustrative only, and that embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0189] Hardware and software layer 60 includes hardware and software components. Examples of hardware components include mainframe 61, RISC (Reduced Instruction Set Computer) architecture-based server 62, server 63, blade server 64, storage device 65, and network and network components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0190] The virtualization layer 70 comprises an abstraction layer capable of providing virtual entities such as virtual servers 71, virtual storage 72, virtual networks including virtual private networks 73, virtual applications and operating systems 74, and virtual clients 75.

[0191] By way of example, the management layer 80 may provide the following functions: Resource provisioning 81 dynamically procures computing and other resources used to execute tasks within the cloud computing environment; Metering and pricing 82 tracks costs as resources are utilized within the cloud computing environment and sends bills or invoices for the utilization of those resources; by way of example, those resources may include application software licenses; Security verifies the identity of cloud users and tasks and protects data and other resources; User portal 83 provides users and system administrators with access to the cloud computing environment; Service level management 84 allocates and manages cloud computing resources to meet required service levels; and Service Level Agreement (SLA) planning and execution 85 proactively prepares and procures cloud computing resources in accordance with SLAs in anticipation of future demand.

[0192] The Workload Layer 90 provides examples of functionality available in a cloud computing environment. Examples of workloads and functionality provided by this layer include mapping and navigation 91, software development and lifecycle management 92, virtual classroom education delivery 93, data analytics processing 94, transaction processing 95, and scaling and / or transformation (and rounding) 96.

[0193] Aspects of the invention may be systems, methods, and / or computer program products, at any possible level of technical detail of integration. The computer program product may include a computer-readable storage medium containing computer-readable program instructions for causing a processor to perform aspects of the invention.

[0194] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device, such as, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves on which instructions are recorded, and any suitable combination thereof. As used herein, computer-readable storage media should not be construed as being ephemeral signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through fiber optic cable), or electrical signals transmitted over wires.

[0195] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device over a network (e.g., the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof). This network may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage on a computer-readable storage medium within each computing / processing device.

[0196] Computer-readable program instructions for carrying out the operations of the present invention may be source or object code written in any combination of one or more programming languages, including assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or object-oriented programming languages ​​such as Smalltalk®, C++, and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer and on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, to carry out aspects of the present invention, electronic circuitry including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions to customize the electronic circuitry by utilizing state information of the computer-readable program instructions.

[0197] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, are implemented by computer-readable program instructions.

[0198] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to create a machine, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may be stored on a computer-readable storage medium and capable of directing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored comprises an article of manufacture containing instructions for performing aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0199] Computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams, thereby causing a series of operable steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process.

[0200] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, comprising one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions shown in the blocks may occur in an order different from that shown in the figures. For example, two blocks shown in succession may actually be realized as a single step, executed concurrently, executed substantially concurrently in a partially or fully overlapping manner in time, or executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks included in the block diagrams and / or flowchart diagrams, are implemented by a special-purpose hardware-based system that performs the specified function or operation or executes a combination of special-purpose hardware and computer instructions.

[0201] Additionally, one or more aspects may be provided, offered, deployed, managed, serviced, etc. by a service provider that offers management of a customer's environment. For example, a service provider may create, maintain, support, etc., computer code and / or computer infrastructure that implements one or more aspects for one or more customers. In return, the service provider may receive payments from the customer, for example, under a subscription and / or fee agreement. Additionally or alternatively, the service provider may receive payments from the sale of advertising content to one or more third parties.

[0202] In one aspect, an application may be deployed to perform one or more embodiments. As one example, deploying an application includes providing a computer infrastructure that functions to perform one or more embodiments.

[0203] As a further aspect, a computing infrastructure may be deployed that includes integrating computer readable code into a computing system, where the code in combination with the computing system is capable of executing one or more embodiments.

[0204] In yet another aspect, a process for integrating a computing infrastructure may be provided, comprising integrating computer-readable code into a computer system comprising a computer-readable medium, the computer-readable medium including one or more embodiments, the code in combination with the computer system being capable of executing one or more embodiments.

[0205] Although various embodiments have been described above, they are merely examples. For example, computing environments of other architectures may be used to incorporate and / or use one or more aspects. Furthermore, different instructions or operations may be used. Furthermore, different types of registers and / or different registers may be used. Many variations are possible.

[0206] Various embodiments are described herein. Furthermore, many variations are possible without departing from the spirit of the embodiments of the present invention. It should be noted that each embodiment or feature described herein and variations thereof can be combined with any other embodiment or feature unless specifically inconsistent.

[0207] Additionally, other types of computing environments may be beneficial and may be used. By way of example, a data processing system may be used that includes at least two processors coupled directly or indirectly via a system bus to memory elements suitable for storing and / or executing program code. These memory elements may include, for example, local memory used during the actual execution of the program code, bulk storage, and cache memory for temporarily storing at least some program code to reduce the number of times the code must be retrieved from bulk storage during execution.

[0208] Input / output or I / O devices (including but not limited to keyboards, displays, pointing devices, DASDs, tapes, CDs, DVDs, thumb drives, and other storage media) may be coupled to the system either directly or through intervening I / O controllers. Network adapters may also be coupled to the system to enable the data processing system to be coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems, and Ethernet cards are just a few of the types of network adapters available.

[0209] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used herein, indicate the presence of stated features, integers, steps, operations, elements, or components, or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof, or combinations thereof.

[0210] Corresponding structures, materials, acts, and equivalents of all means or steps and functional elements within the scope of the claims below are intended to include any structure, material, or acts for performing a function in combination with other claimed elements, if any, when specifically claimed. The description of one or more embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed forms. Many modifications and variations will be apparent to those skilled in the art. The embodiments have been chosen and described to best explain various aspects and practical applications, and to enable others skilled in the art to appreciate various embodiments with various modifications as may be suited to the particular use contemplated.

Claims

1. 1. A computer program product for facilitating processing within a computing environment, said computer program product comprising: one or more computer-readable storage media; and program instructions collectively stored on the one or more computer-readable storage media, the program instructions causing a computer to: causing instructions to be executed to perform a conversion operation and a scaling operation, said causing said instructions to be executed Converting input values ​​from one format and providing the converted results in another format; scaling the transformed result to provide a scaled result; and and placing the result obtained from the scaled result at a selected location.

2. 2. The computer program product of claim 1, wherein the one format is a hexadecimal floating point format and the other format is a decimal format.

3. 3. The computer program product of claim 2, wherein the decimal number format is a binary-coded decimal number format.

4. The scaling step comprises: determining a scale factor; and using the scale factor in scaling the transformed result to provide the scaled result.

5. determining the scale factor obtaining a scale value using an operand of said instruction; determining the scale factor using the scale value; 5. The computer program product of claim 4, wherein said using said scale factor comprises multiplying said transformed result by said scale factor to obtain said scaled result.

6. 6. The computer program product of claim 1, wherein said executing said instructions further comprises rounding said scaled result to provide a rounded result.

7. The rounding step comprises: obtaining a rounding mode using a field of said instruction; and rounding the scaled result to the rounded result based on the rounding mode.

8. The placing selecting a portion of the rounded result as the result; and placing the result in the selected location.

9. said executing said instructions determining the sign of the result; and placing the sign of the result in the selected location.

10. 10. A computer program product as claimed in any preceding claim, wherein the selected location comprises a register specified using a field of the instruction.

11. 1. A computer system for facilitating processing within a computing environment, said computer system comprising: Memory and a processor in communication with the memory, the computer system configured to perform a method, the method comprising: executing instructions to perform a transforming operation and a scaling operation, wherein said executing said instructions comprises: Converting input values ​​from one format and providing the converted results in another format; scaling the transformed result to provide a scaled result; and and placing the result obtained from the scaled result at a selected location.

12. The scaling step comprises: determining a scale factor; and using the scale factor in scaling the transformed result to provide the scaled result.

13. 13. The computer system of claim 11 or 12, wherein said executing said instructions further comprises rounding said scaled result to provide a rounded result.

14. The rounding step comprises: obtaining a rounding mode using a field of said instruction; and rounding the scaled result to the rounded result based on the rounding mode.

15. The placing selecting a portion of the rounded result as the result; and placing the result in the selected location.

16. 1. A method for facilitating processing in a computing environment by processing information in a computer, said method comprising: executing instructions to perform a transforming operation and a scaling operation, wherein said executing said instructions comprises: Converting input values ​​from one format and providing the converted results in another format; scaling the transformed result to provide a scaled result; and and placing a result obtained from the scaled result at a selected location.

17. The scaling step comprises: determining a scale factor; 17. The method of claim 16, further comprising using the scale factor in scaling the transformed result to provide the scaled result.

18. 18. The method of claim 16 or 17, wherein said executing said instruction further comprises rounding said scaled result to provide a rounded result.

19. The rounding step comprises: obtaining a rounding mode using a field of said instruction; and rounding the scaled result to the rounded result based on the rounding mode.

20. The placing selecting a portion of the rounded result as the result; and placing the result at the selected location.

21. 1. A computer program product for facilitating processing within a computing environment, said computer program product comprising: one or more computer-readable storage media; and program instructions collectively stored on the one or more computer-readable storage media, the program instructions causing a computer to: causing instructions to be executed to perform scaling and transformation operations, said causing said instructions to be executed Scaling input values ​​in one format to provide a scaled result; converting the scaled result from the one format to provide a converted result in another format; placing the result obtained from the transformed result at a selected location; The computer program product, wherein said one format is a decimal format and said other format is a hexadecimal floating point format.

22. 22. The computer program product of claim 21, wherein the decimal number format is a binary-coded decimal number format.

23. 23. A computer program product according to any one of claims 21 to 22, wherein said executing said instructions further comprises rounding a version of the converted result to provide a rounded result, wherein said result is obtained using said rounded result.

24. the selected location is a register specified using a field of the instruction, and placing the result in the selected location; determining a format of the result; and placing the result in the register based on the format.

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