Adaptive nonlinearity identification and compensation using orthogonal functions in mixed-signal circuits.

Abstract

To improve the performance of adaptive nonlinearity identification and a compensation technique.SOLUTION: A feedback divider in a mixed-signal circuit is modulated by a frequency control word that controls a delta-sigma modulator. An accumulated quantization error from the delta-sigma modulator is compared with a residual error in the circuit for gain calibration to adjust a linearity error by a least mean square (LMS) correlator. The upper bits of the accumulated quantization error access a lookup table to find the two outputs of the compensation function between which the lower bits of the accumulated quantization error are interpolated. The interpolated result is an adjustment that is subtracted from the loop to compensate for a nonlinearity error. A set of orthogonal kernels is generated from the accumulated quantization error and calibrated using another LMS correlator and inversely transformed to produce an update to the nonlinear compensation function in the lookup table. The kernel may be a Walsh-Hadamard (WH) and the inverse transformer may be an inverse WH transformer.SELECTED DRAWING: Figure 2B

Description

[Technical Field]

[0001] FIELD OF THE INVENTION [Para 1] The present invention relates to mixed-signal integrated circuits (ICs), and more particularly to building block nonlinearity identification and compensation for mixed-signal ICs. [Background technology]

[0002] Background of the Invention [Para 2] The ever-increasing data rates of wired and wireless communication systems impose stringent performance requirements on their mixed-signal IC subsystems. In particular, there is a great demand for high-resolution data converters at higher sampling rates and high-performance frequency synthesizers with stringent phase noise and spurious performance requirements. Delta-sigma (ΔΣ) digital-to-analog converters (DACs) utilize noise shaping and high oversampling ratios to achieve high resolution (on the order of 20 bits) that cannot be easily achieved using conventional DACs.

[0003] [Para 3] Similarly, ΔΣ fractional-N phase-locked loops (FN-PLLs) utilize noise shaping and high oversampling ratios to achieve very fine (on the order of 20 bits) frequency synthesis capabilities. In both of these examples, the ΔΣ noise-shaping modulator reduces the word length (m) of its digital input signal x[k] to a few bits (1–6), and the resulting large amount of quantization noise is shaped to high frequencies to make in-band noise negligible. Out-of-band quantization noise is suppressed by a dedicated low-pass filter in the case of a ΔΣ DAC or by loop dynamics in the case of a ΔΣ FN-PLL.

[0004] [Para 4] In practice, the nonlinearity of the circuit building blocks imposes a bottleneck for realizing high-performance ΔΣ DACs and ΔΣ FN-PLLs. The nonlinearity causes shaped out-of-band noise to fold intermodulation products into the baseband, limiting the spurious-free dynamic range (SFDR) and signal-to-noise-plus-distortion ratio (SNDR) of ΔΣ DACs and the phase noise and spurious performance of ΔΣ FN-PLLs.

[0005] Impact of nonlinearity on ΔΣ quantization noise rejection [Para 5] Delta-sigma DACs using 1-bit DAC units inherently offer high linearity, but at the cost of large quantization errors. As a result, achieving a high in-band signal-to-noise ratio (SNR) requires a very large oversampling ratio. Therefore, their use is typically limited to low-bandwidth applications such as audio and sensor interfaces. Using multi-bit DACs effectively reduces the amount of quantization noise and significantly relaxes the oversampling ratio required to achieve high bandwidth. However, this comes at the cost of high sensitivity to mismatch between DAC unit cells.

[0006] [Para 6] To improve matching between DAC unit cells, thermometer coding is recommended. As the number of bits in a DAC increases, the DAC implementation is usually segmented into two smaller DACs: an m1-bit coarse DAC and an m2-bit fine DAC to obtain a better tradeoff between linearity and area. The original modulator output x0[k] contains shaped noise, while the divided coarse x1[k] and fine x2[k] signals contain unshaped noise and distortion. The outputs of DAC1 and DAC2 are then multiplied by an appropriate gain ratio.

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[0007] [Para 7] The segmented ΔΣ DAC architecture can use quantization noise cancellation (QNC) techniques to overcome this limitation. By requantizing the original modulator output x0[k] using a second ΔΣ modulator to drive DAC1, the coarse DAC1 control x1[k] therefore includes noise-shaped components in addition to the signal. Because signal x2[k] is the difference between the ΔΣ modulator input and output, it represents only the shaped quantization noise and does not include any signal components. As a result, any spectral leakage due to an inappropriate gain ratio results only in a noise-shaped signal that contributes little in-band energy.

[0008] [Para 8] Similarly, QNC techniques can be used to improve the performance and increase the bandwidth of a ΔΣ fractional-N phase-locked loop (FN-PLL). FIG. 1 shows a prior art analog FN-PLL. A phase-frequency detector and charge pump (PFD / CP) 102 compares a reference clock REF with a divided clock DIV to control a charge pump that charges a loop filter 104 to generate a control voltage Vc that controls the frequency generated by a voltage-controlled oscillator (VCO) 106. The output OUT of VCO 106 is fed back to a multi-modulus divider (MMD) 108 to generate the divided clock DIV. MMD 108 may be a ΔΣ fractional divider in the feedback path. VCO 106 divides the frequency F OUT =(N DIV +α DIV )F REF where N DIV is a positive integer, and α DIV is a decimal value between 0 and 1, and F REFis the frequency of the reference clock signal REF. The fractional-N operation is achieved by dithering the feedback multi-modulus divider MMD 108 using a delta-sigma modulator 110. Here, the dithered signal x DIV The average of [k] is the desired fractional coefficient α DIV The ΔΣ fractional divider MMD 108 is similar to a digital-to-frequency converter, in which case its shaped frequency quantization noise can be removed similarly to the case of a ΔΣ-DAC. Here, the quantization noise removal path ΔΣ QNC 120 includes a summer 112, a digital accumulator 114 for frequency-to-phase conversion, and a current DAC 116 for removing quantization noise at the charge pump output using a summer 118. In practice, gain mismatch between the DAC 116 and the signal path through the PFD / CP 102 results in imperfect QNC.

[0009] [Para 9] Fractional divider quantization noise affects both analog and digital FN-PLLs in the same way. QNC techniques for digital FN-PLLs may use a time-to-digital converter (TDC) and a digital-to-time converter (DTC). Although the cancellation gain path can be accurately calibrated using least mean square (LMS) techniques, each of the PFD / CP signal and DAC noise cancellation paths has different nonlinear characteristics, i.e., p CP (x) and p DAC (x), respectively. The nonlinearities of these blocks can significantly limit the overall phase noise and spurious performance of the FN-PLL. Similarly, the coarse and fine DACs in the segmented ΔΣ-DAC architecture have different nonlinear characteristics, i.e., P DAC1 (x) and P DAC2 (x), which can severely degrade the SNDR and SFDR of the overall DAC.

[0010] [Para 10] Nonlinearities in the signal path or noise cancellation path impose a bottleneck for achieving high-performance ΔΣ DACs and ΔΣ FN-PLLs. Nonlinearities cause shaped noise and tones in the high-frequency region of the multibit spectrum to fold intermodulation products into the baseband. In-band distortion products cannot be easily removed by simple linear filters. Reducing the system bandwidth may or may not significantly improve the SNDR and SFDR of the ΔΣ DAC and the phase noise and spurious performance of the ΔΣ FN-PLL. In this case, it is the nonlinearities, not the quantization noise, that limit the system performance. Summary of the Invention [Problem to be solved by the invention]

[0011] [Para 11] What is desired is an adaptive nonlinearity identification and compensation technique that can be utilized in data converter, PLL, and frequency synthesizer implementations to achieve improved performance. An adaptive nonlinearity identification and compensation circuit is desired that is useful for a variety of analog / mixed-signal / RF integrated circuit (IC) building blocks, including those for clock generators, clock and data recovery (CDR), phase interpolators, voltage / current amplifiers, transimpedance amplifiers (TIAs), and power amplifiers (PAs). [Brief explanation of the drawings]

[0012] BRIEF DESCRIPTION OF THE DRAWINGS [Figure 1] [Para 12] shows a prior art analog FN-PLL. [Figure 2A] [Para 13] Identify and estimate the integral nonlinearity (INL) error function. [Figure 2B] [Para 13] Identify and estimate the integral nonlinearity (INL) error function. [Figure 3] [Para 14] A block diagram of an adaptive INL identification and compensation scheme using the LMS method is shown. [Figure 4][Para 15] A graph of the block pulse set of the kernel. [Figure 5] [Para 16] Simulation results for an LMS embodiment of the nonlinearity identification and compensation circuit are presented. [Figure 6] [Para 17] FIG. 6 is a graph illustrating simulated settling behavior of compensation coefficients for the LMS embodiment of FIGS. 4-5. [Figure 7] [Para 18] A graph showing an example of a Haar kernel. [Figure 8] [Para 19] An example of a Walsh-Hadamard (WH) kernel set is shown. [Figure 9] [Para 20] Simulation results of LMS adaptation for nonlinearity identification and compensation using the Walsh-Hadamard (WH) kernel set are presented. [Figure 10] [Para 21] FIG. 10 is a graph illustrating simulated settling behavior of compensation coefficients for the LMS embodiment of FIGS. 8-9 using the Walsh-Hadamard (WH) kernel set. [Figure 11] [Para 22] An example of a triangular Walsh-Hadamard (TWH) kernel set is presented. [Figure 12] [Para 23] Simulation results of LMS adaptation for nonlinearity identification and compensation using a triangular Walsh-Hadamard (TWH) kernel set are presented. [Figure 13] [Para 24] FIG. 13 is a graph illustrating simulated settling behavior of compensation coefficients for the LMS embodiment of FIGS. 11-12 using the Triangular Walsh-Hadamard (TWH) kernel set. [Figure 14] [Para 25] Block diagram of adaptive INL identification and compensation using a constant piecewise kernel with LMS correlation and interpolation. [Figure 15] [Para 26] Simulation results of the LMS adaptation of the nonlinearity identification and compensation of Figure 14 using the Walsh-Hadamard (WH) kernel set and interpolation for N=8 are shown. [Figure 16][Para 27] Simulation results of the LMS adaptation of the nonlinearity identification and compensation of Figure 14 using the Walsh-Hadamard (WH) kernel set and interpolation for N=16 are shown. [Figure 17] [Para 28] Simulation results of the LMS adaptation of the nonlinearity identification and compensation of Figure 14 using the Walsh-Hadamard (WH) kernel set and interpolation for N = 32 are shown. [Figure 18] [Para 29] presents a digital FN-PLL with TDC-based "digital domain" ΔΣ quantization noise cancellation and adaptive TDC INL identification and compensation. [Figure 19] [Para 30] Block diagram of another digital FN-PLL architecture in which ΔΣ quantization noise rejection and adaptive INL identification and compensation are performed in the “time domain” using a digital-to-time converter (DTC). [Figure 20] [Para 31] Block diagram of another digital FN-PLL architecture in which ΔΣ quantization noise cancellation is performed in the “time domain” while INL identification and compensation is in the “digital domain.” DETAILED DESCRIPTION OF THE INVENTION

[0013] Detailed Description [Para 32] The present invention relates to improvements in mixed-signal circuits. The following description is presented to enable any person skilled in the art to make and use the invention as provided in connection with a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Thus, the present invention is not intended to be limited to the particular embodiment shown and described, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0014] [Para 33] The present inventors propose a method and apparatus for identifying and compensating for nonlinearities in precision analog and mixed-signal building blocks such as ΔΣ DACs and ΔΣ FN-PLLs. In general, any arbitrary memoryless nonlinearity of a given circuit block can be described as a function p(x) of its input signal x, where x is a function of the closed domain x∈[-x p ,+x p ]. In the context of a DAC, the input is a discrete-time digital signal x[k], and the nonlinearity function p(x) represents the DAC integral nonlinearity (INL). This INL function primarily defines the deviation of the DAC from its ideal linear behavior. For a perfectly linear DAC, p(x) = 0 for any input x.

[0015] [Para 34] Figures 2A-2B illustrate the identification and estimation of integral nonlinearity (INL) error functions. Figure 2A is a graph showing an example of a best-fit linear INL function p(x) for a DAC. Conceptually, if we can accurately identify the undesired nonlinear function p(x), we can compensate for it based on an approximated composite compensation function q(x) as shown in Figure 2B. Compensation Signal

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[0016] [Para 35] INL discrimination and compensation 140 is performed by using the output e of adder 136. R It also includes an adaptive INL estimator 138 that uses [k] along with the input signal x[k] to estimate the error and accordingly control the q(x) function generator 134. The INL function p(x) generator 132 represents the deviation from a linear output due to a mixed-signal component such as a DAC.

[0017] [Para 36] In practice, the nonlinearity function p(x) can vary significantly with supply and temperature variations. Therefore, techniques for describing the compensation function using factory adjustments or start-up calibrations may not be sufficient. For example, temperature may change as the system heats up after initial calibration. The goal here is to adaptively synthesize a nonlinearity compensation function q(x) to accurately and robustly remove the effect of the INL function p(x) across process, supply, and temperature (PVT) variations. To achieve this goal, our nonlinearity identification and compensation scheme detects residual errors after compensation and adaptively constructs the compensation function q(x). The complexity of constructing such an adaptive nonlinearity identification and compensation system can be reduced by how we construct the compensation function and how we adapt its coefficients. This construction method can be coupled with our model for representing the nonlinearity function p(x).

[0018] Expression of nonlinearity [Para 37] Continuous static nonlinearities are usually expressed using an Nth-order power series given by

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[0019] [Para 38] Where, c i represents the real-valued polynomial coefficients. i The coefficients can be estimated using cross-correlation techniques, but this is prohibitively expensive in terms of hardware implementation, especially as the polynomial order increases. In practice, the implementation of this type of polynomial modeling and estimation technique is limited to only a few (2 or 3) terms.

[0020] [Para 39] Alternatively, we consider a closed domain x∈[-x p ,+x p ], we define any arbitrary unknown static nonlinear function p(x) defined over i It is expressed as a linear combination of the complete set of (x).

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[0021] [Para 40] Where, c i denotes the i-th coefficient of the corresponding kernel. The orthogonal series method offers some interesting advantages over the power series method, allowing for a much simpler yet accurate implementation of the compensation scheme as will be shown later. This is based on the orthogonality property of the underlying kernel. The kernel φ i (x) is in the interval -x if they satisfy the following equation: p ≦x≦+x p are said to be orthogonal within

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[0022] [Para 41] where A is a constant. If the range of x is a discrete set (i.e., quantized with M levels or digitally represented from -M / 2 to +M / 2-1), then the complete set of orthogonal kernels consists of a finite number, M, of kernels.

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[0023] [Para 42] For the remainder of this disclosure, we treat x as a discrete-time signal with discrete amplitude (M values). Without loss of generality, all subsequent equations and analysis are valid and readily applied when x has continuous amplitude (M → ∞).

[0024] [Para 43] The compensation function q(x) is similarly represented by an orthogonal kernel. In practice, only a limited number (N≦M) of kernels can be used in the implementation of q(x).

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[0025] [Para 44] Where:

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[0026] Optimal Compensation Coefficient [Para 45] R (x)=p(x)-q(x) represents the residual compensation error due to the imperfect representation, which is the least squares

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[0027] [Para 46]

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[0028] [Para 47] {k1,k2,...,k L Let} denote the L distinct discrete-time instances. Then, using vector notation, we can write the input, output, compensation and error signals as 1×L vectors as follows:

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[0029] [Para 48] where T is the transpose operator. Similarly, we consider the coefficient

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[0030] [Para 49] Then, the compensation and error vector can be expressed as follows:

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[0031] [Para 50] We define the cost function ε to be minimized as: ε=E R T E R (17)

[0032] [Para 51] At this time,

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[0033] [Para 52] The inventors have determined that the error minimization process is the autocorrelation matrix product Φ T It can be clearly seen that the autocorrelation matrix product Φ depends mainly on Φ. Due to the uniformly distributed input vector X and the orthogonality of the kernel (see equation (5)), T Φ can be simplified to the identity matrix I times a constant A.

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[0034] [Para 53] At this time, the optimal

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[0035] [Para 54] In standard form, the optimal compensation coefficients to minimize the MSE are

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[0036] [Para 55] In other words, the optimal compensation coefficient

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[0037] Adaptive nonlinearity compensation using LMS techniques. [Para 56] Orthogonality promotes avoiding the prohibitively expensive matrix inversion operation (Φ T Φ) -1 . However, in practice, the inventor may not have the signal y[k] readily available in digital form, so it is not obvious to find the optimal compensation coefficients in the background state by calculating Φ T Y. Alternatively, the inventor can use the compensated residual error signal e R [k] to adaptively construct the compensation function q(x). In some cases, it may be better to iteratively search for the optimal solution using the steepest descent method. Starting from the initial guess

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[0038] [Para 57] Here, μ is the step size parameter. The error signal in Equation (5) can be expressed as follows using the kernel

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[0039] [Para 58] The second error term is due to the incomplete kernel representation (i.e., N < M). Due to kernel orthogonality (see Equation (5)), the non-orthogonal terms will be averaged, and the expected value Φ T E R can be approximately simplified to the following formula

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[0040] [Para 59] This is the compensation coefficient

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[0041] [Para 60] LMS is R [k] and x i This is valid when both [k] are zero-mean signals (i.e., have no DC component).

[0042] [Para 61] Figure 3 shows a block diagram of an adaptive INL identification and compensation scheme using the LMS method. The function p(x) generator 132 represents the nonlinearity error generated by an m-bit DAC, and the range of x is M=2. m The cancellation signal generated by INL identification and compensation 140 is assumed to be a discrete set having levels.

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[0043] [Para 62] INL identification and compensation 140 has N paths. The first path, for N=1, has kernel block 141 which generates x1[k], which is multiplied by multiplier 171 to produce a residual error e R [k] and accumulated in accumulator 181.

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[0044] [Para 63] An input signal x[k] is passed through N kernel blocks 141, 142, ... 144 to obtain x i [k]=φ i (x[k]), which is then scaled by the corresponding coefficients using multipliers 151, 152, ... 154 and integrated to produce the cancellation signal

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[0045] Orthogonal kernel selection [Para 64] Conceptually, any complete orthogonal kernel set can be used to represent p(x) and construct q(x). In practice, a finite number, N, of kernels are used. The choice of kernel set can have a decisive impact on the compensation MSE. Increasing N equivalently results in finer granularity in the input signal x to the kernel. Proper choice of kernel set is crucial to practically realizing the compensation function in an efficient manner while ensuring a small MSE that meets the target specifications.

[0046] [Para 65] For example, the most famous orthogonal representation, the Fourier series, uses sine and cosine kernels. In practice, implementations of sine and cosine kernels can result in prohibitively complex implementations and can produce very large MSEs when N<<M. Other non-sinusoidal representations can be categorized as polynomial kernels and piecewise kernels. Classical orthogonal polynomial kernels, such as Laguerre polynomials, Hermite polynomials, and Jacobi polynomials (including Legendre, Chebyshev, and Gegenbauer polynomials), are difficult to implement in practice due to the many multiplication and accumulation operations involved.

[0047] [Para 66] Piecewise kernels, on the other hand, can lead to much simpler implementations. The simplest piecewise kernel set is based on block-pulse functions. The block-pulse (BP) N kernel set can be defined using the following equation:

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[0048] [Para 67] where i = 1, 2, ..., N. Figure 4 is a graph of a block pulse set of kernels. In the example of Figure 4, N = 8 for the BP orthogonal kernel set. There are eight non-overlapping pulse trains for the input x range of -512 to +512, labeled φ1 [LSB] to φ8 [LSB].

[0049] [Para 68] In a discrete sense, the BP kernel can be represented by the identity matrix I. Figure 5 shows simulation results for an LMS implementation of the nonlinearity discrimination and compensation circuit. The simulation is for a 10-bit DAC with a fifth-order INL characteristic p(x) with a random standard deviation of 0.1 LSB using the BP kernel set in Figure 4. The difference e(x) = p(x) - q(x) represents the residual error resulting from the limited number of kernels (N = 8 << M = 1024) used in constructing q(x). It can be clearly seen how q(x), curve 188, is constructed from separate segments each representing a block pulse. The compensation coefficient represents the weight given to each block pulse to minimize the MSE, which is the average of this corresponding segment of p(x) along curve 186. Curve 190 shows that the error e(x) varies from approximately +4 to -7, except for an initial excursion to +10 near -512. The root mean square (RMS) of this error e(x) at steady state is approximately 2.50 LSB.

[0050] [Para 69] Figure 6 is a graph showing the simulated settling behavior of the compensation coefficients for the LMS embodiment of Figures 4-5. There are N=8 kernels that generate the 8 block pulses of Figure 4 and the error function e(x) of Figure 5. Curves 192, 194, 196, 198, 200, 202, 204, and 206 represent the optimal compensation coefficients.

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[0051] [Para 70] The reduced complexity of the BP kernel allows the number of kernels to be increased in practice up to N=16 or N=32. With N=16, the RMS error can be reduced to 1.29 LSB. However, the BP kernel has a major drawback: the LMS adaptation of the BP kernel is R[k] may be sensitive to any offset or flicker noise added to the signal. This is because all BP kernels and the correspondingly generated x i [k] signal has a DC component, and LMS is R [k] and x i This is valid when both [k] are zero-mean signals (i.e., have no DC component) (see Equation (27)). To overcome this limitation, a constant piecewise kernel using a Haar function can be used, where only one kernel carries the DC component. The Haar function has three possible states: 0 and ±a, where a is set to normalize the amplitude of each kernel to satisfy Equation (5).

[0052] [Para 71] Figure 7 is a graph showing an example of a Haar kernel. This orthogonal Haar kernel set has N=8 kernels labeled φ1[LSB] through φ8[LSB] for an input x range of -512 to +512. The first kernel φ1[LSB] establishes the DC component, while the other seven kernels have both high +a and low -a segments. The final six kernels have high, low, and zero segments, and all seven kernels φ2[LSB] through φ8[LSB] average to 0 across the entire range.

[0053] [Para 72] Walsh functions can also be used to construct a set of constant-partition kernels, where only one kernel carries the DC component. Walsh functions use only two possible states, ±1, to form a complete orthonormal set. It has a striking similarity to the sine-cosine function, primarily regarding their zero-crossing pattern. In the discrete sense, Walsh kernels are represented by an N × N matrix of Walsh-Hadamard (WH) codes. In general, the WH matrix WH(n0) can be generated using the following recurrence relation:

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[0054] [Para 73] where WH(0)=1 and n=log2N.

[0055] [Para 74] Figure 8 shows an example of a Walsh-Hadamard (WH) kernel set. This orthogonal set of kernels is arranged in natural order and has N=8. The set consists of N / 2 even kernels (φ1 [LSB], φ4 [LSB], φ6 [LSB], and φ7 [LSB]) and N / 2 odd kernels (kernels φ2 [LSB], φ3 [LSB], φ5 [LSB], and φ8 [LSB]). The DC component is set by the first kernel φ1 [LSB]. This even-odd feature can be exploited to represent and appropriately compensate for nonlinearities using only odd kernels in differential systems where even-order distortions and nonlinearities are inherently suppressed.

[0056] [Para 75] Figure 9 shows simulation results of LMS adaptation for nonlinearity identification and compensation using the Walsh-Hadamard (WH) kernel set. The simulation is for a 10-bit DAC with a fifth-order INL characteristic p(x) with a random standard deviation of 0.1 LSB using the WH kernel set of Figure 8. The difference between e(x) = p(x) - q(x) represents the residual error resulting from the limited number of kernels (N = 8 << M = 1024) used in constructing q(x). In this case, q(x), curve 214, is constructed by a weighted sum of different kernels that simulate segments of p(x) along curve 212.

[0057] [Para 76] Curve 216 shows that the error e(x) varies from about +4 to -7, except for an initial excursion to +10 near -512. The root mean square (RMS) of this error e(x) at steady state is about 2.50 LSB.

[0058] [Para 77] Figure 10 is a graph showing simulated settling behavior of compensation coefficients for the LMS embodiment of Figures 8-9 using a Walsh-Hadamard (WH) kernel set. There are N=8 kernels that generate the 8 block pulses of Figure 8 and the error function e(x) of Figure 9. Curves 222, 224, 226, 228, 230, 232, 234, and 236 represent the optimal compensation coefficients.

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[0059] [Para 78] Similar to the BP kernel, the reduced complexity of the WH kernel allows the number of kernels to be increased practically to N=16 or N=32. With N=16, the RMS error can be reduced to 1.29 LSB. However, the residual error may still be large and not meet the target compensation accuracy.

[0060] Triangulation kernel [Para 79] To improve compensation, we modify the WH kernel to be a set of linear piecewise kernels that use triangular waveforms as opposed to the rectangular waveforms of the WH kernel. We call the new set Triangular Walsh-Hadamard (TWH).

[0061] [Para 80] Compared to the prior art piecewise linear approach using simplex canonical piecewise linear (SCPWL) functions, the proposed TWH representation provides a more accurate and simpler representation. In contrast to the fixed segments of the kernel described above, the proposed THW linear piecewise representation significantly improves compensation accuracy because now each segment can be represented by a linear function, resulting in a significantly reduced RMS error. The TWH kernel provides a very simple implementation of sine / cosine-like kernels.

[0062] [Para 81] Figure 11 shows an example of a triangular Walsh-Hadamard (TWH) kernel set. This orthogonal set of kernels is arranged in natural order and has N=8. The set consists of N / 2 even kernels (φ1 [LSB], φ4 [LSB], φ6 [LSB], and φ7 [LSB]) and N / 2 odd kernels (kernels φ2 [LSB], φ3 [LSB], φ5 [LSB], and φ8 [LSB]). The DC component is set by the first kernel φ1 [LSB]. This even-odd feature can be exploited to represent and appropriately compensate for nonlinearities using only odd kernels in differential systems where even-order distortions and nonlinearities are inherently suppressed.

[0063] [Para 82] Figure 12 shows simulation results of LMS adaptation for nonlinearity identification and compensation using a triangular Walsh-Hadamard (TWH) kernel set. The simulation is for a 10-bit DAC with a fifth-order INL characteristic p(x) with a random standard deviation of 0.1 LSB using the triangular Walsh-Hadamard (TWH) kernel set of Figure 11. The difference between e(x) = p(x) - q(x) represents the residual error resulting from the limited number of kernels (N = 8 << M = 1024) used in constructing q(x). In this case, q(x), curve 244, is constructed by a weighted sum of different kernels that simulate segments of p(x) along curve 242.

[0064] [Para 83] Curve 246 shows that the error e(x) fluctuates from approximately +2 to -2, and there is no longer an initial excursion to a high value near -512, as seen in Figures 5 and 9 using the other kernels. The root mean square (RMS) of this error e(x) at steady state is approximately 0.65 LSB. For N=8, using TWH provides more than a four-fold improvement over WH. Curve 246 is much flatter and shows much lower error than error curve 190 in Figure 5 and curve 216 in Figure 9. The error is dramatically reduced using our TWH kernel compared to the WH and BP kernels.

[0065] [Para 84] Figure 13 is a graph showing simulated settling behavior of compensation coefficients for the LMS embodiment of Figures 11-12 using a triangular Walsh-Hadamard (TWH) kernel set. There are N=8 kernels that generate the 8 block pulses of Figure 11 and the error function e(x) of Figure 12. Curves 252, 254, 256, 258, 260, 262, 264, and 266 represent the optimal compensation coefficients.

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[0066] Constant Piecewise Kernel with Interpolation [Para 85] Our linear piecewise kernel, the triangular Walsh-Hadamard (TWH), significantly reduces the compensation MSE compared to piecewise kernels such as BP and WH. However, the TWH kernel has scalability issues because as the number of kernels increases, the implementation complexity of the TWH kernel grows rapidly with many accumulation and multiplication operations. Therefore, in practice, increasing the number of THW kernels beyond N=8 may become inefficient. To overcome this tradeoff between compensation accuracy and implementation complexity, we utilize significantly simpler constant piecewise kernels such as BP, Haar, or WH in addition to linear interpolation to achieve the same compensation accuracy as TWH but with a much simpler and more scalable implementation.

[0067] [Para 86] Figure 14 is a block diagram of adaptive INL identification and compensation using LMS correlation and interpolation with a constant piecewise kernel. The compensation signal y[k] is obtained by passing the input signal x[k] directly to the kernel.

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[0068] [Para 87] The interpolation process smooths the final compensation function q(x). The compensation function builder 312 LUT To construct (x) directly and track PVT variations, matrix inversion and dot product operations can be used to periodically update LUT 314. Because tracking the PVT is a slow process, matrix inversion and LUT updates can be performed at a rate much slower than the input sample rate by adding decimation filters 301, 302, ... 304 onto the outputs of accumulators 291, 292, ... 294 in LMS correlator 320.

[0069] [Para 88] For the BP kernel, the kernel matrix is ​​the identity matrix. This means that its inverse is also the identity matrix, and therefore the coefficients q LUT (x) can be expressed directly. For the WH kernel, the coefficients are expressed as

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[0070] [Para 89] The function p(x) generator 132 represents the nonlinearity error generated by the m-bit DAC, and the range of x is M=2 m The cancellation signal generated by INL identification and compensation 322 is assumed to be a discrete set having levels.

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[0071] [Para 90] INL identification and compensation 322 has N paths. The first path, for N=1, has kernel block 271 generating x1[k], which is multiplied by multiplier 281 to produce residual error e R Multiplied by [k]. Multiplier output e LMS1[k] is accumulated by accumulator 291, decimated by decimation filter 301, and provided as the first input to compensation function builder 312

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[0072] [Para 91] The input signal x[k] is passed through N kernel blocks 271, 272, ... 274 in the kernel 318 to obtain x i [k]=φ i (x[k]), which is then multiplied by multipliers 281, 282, ... 284 to produce a kernel signal of the residual error e R [k], accumulated by accumulators 291, 292, ... 294, decimated by decimation filters 301, 302, ... 304, and input to compensation function builder 312. LUT 314 is updated by compensation function builder 312 to perform PVT adjustment for LUT interpolation, and the cancellation signal

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[0073] [Para 92] Figure 15 shows simulation results for the LMS adaptation of the nonlinearity identification and compensation of Figure 14 using a Walsh-Hadamard (WH) kernel set and interpolation. The simulation is for a 10-bit DAC with a 5th-order INL characteristic p(x) with a random standard deviation of 0.1 LSB using a WH kernel set (N=8) and interpolation.

[0074] [Para 93] As shown in Figure 14, using interpolation and updating of LUT 314, q(x), curve 334, is constructed from the nonlinear error function p(x), shown as curve 332. Curve 334 closely follows curve 332, and therefore q(x) is close to p(x), resulting in a small error, curve 336.

[0075] [Para 94] Curve 336 shows that the error e(x) varies from approximately +2 to -3. The RMS of the steady-state error e(x), curve 336, is approximately 0.66 LSB. This is approximately a four-fold improvement in compensation accuracy compared to the WH without interpolation, and approximately the same compensation accuracy as the TWH (N=8).

[0076] [Para 95] Figure 16 shows simulation results of the LMS adaptation of the nonlinearity identification and compensation of Figure 14 using a Walsh-Hadamard (WH) kernel set and interpolation for N = 16. Curves 342 and 344 match more closely, causing error curve 346 to stay closer to zero. With N = 16, the RMS error can be reduced to 0.19 LSB, which is approximately a 5x improvement in compensation accuracy compared to WH without interpolation.

[0077] [Para 96] Figure 17 shows simulation results of the LMS adaptation of the nonlinearity discrimination and compensation of Figure 14 using a Walsh-Hadamard (WH) kernel set and interpolation for N = 32. Curves 352 and 354 match more closely, causing error curve 356 to become nearly flat. With N = 32, the RMS error can be reduced to 0.11 LSB, which is very close to the limit of 0.1 LSB random variation in p(x).

[0078] Applicable [Para 97] In this section, we present some examples of applications for the proposed adaptive INL identification and compensation technique.

[0079] [Para 98] Figure 18 shows a digital FN-PLL with TDC-based "digital domain" ΔΣ quantization noise cancellation and adaptive TDC INL identification and compensation. A time-to-digital converter (TDC) 362 measures the time difference between a reference clock REF and a divided feedback clock DIV. A multi-modulus divider (MMD) 108 generates the divided feedback clock DIV using dithering.

[0080] [Para 99] TDC 362 is a digital word TDC [k]. Digital loop filter 364 digitally filters the output of TDC 362 after subtraction of the error term by summers 368, 370. Digital loop filter 364 outputs a multi-bit digital control word D that drives digitally controlled oscillator (DCO) 366 towards phase and frequency lock within the loop. C Generate [k].

[0081] [Para 100] Using the digital ΔΣ modulator 110, an m1-bit x[k] is generated by truncating an m-bit (m>m1) frequency control word x[k]. DIV Dithering the MMD 108 with [k] produces a fractional-N operation. Adder 112 subtracts the frequency control word x[k] from the output of the ΔΣ modulator 110 to produce m bits of quantization error that are accumulated by accumulator 114.

[0082] [Para 101] Output of accumulator 114 e TDC [k] is applied to gain calibrator 376, which generates the gain adjustment y that is subtracted from the PLL loop by summer 368. G The gain calibrator 376 uses the LMS correlator 372 to generate the cumulative quantization error e TDC [k] is the input to the digital loop filter 364, and the residual error e R [k], and the output of the LMS correlator 372 is multiplied by a multiplier 374 to obtain the accumulated quantization error e TDC [k] is multiplied and the gain is adjusted by y. G Generate [k].

[0083] [Para 102] INL identification and compensation 322 also determines the cumulative quantization error e TDC[k] from accumulator 114. Kernel 318, LMS correlator 320, and compensation function builder 312 operate on the input from accumulator 114 to generate updates to entries in LUT 314, as shown and described above for FIG. 14. The input from accumulator 114 is split into MSB and LSB sections, with the MSB applied as an address input to LUT 314, while the LSB controls interpolator 316 to interpolate between two consecutive entries in LUT 314. Interpolator 316 generates an interpolated adjustment y that is subtracted from the PLL loop by adder 370. INL Generate [k].

[0084] [Para 103] Both the LMS correlator 320 in the INL identification and compensation 322 and the LMS correlator 372 in the gain calibrator 376 calculate the residual error e input to the digital loop filter 364. R [k]. The output OUT of the DCO 366 is fed back to the multi-modulus divider (MMD) 108 to generate the divided clock DIV. The MMD 108 may be a ΔΣ fractional divider in the feedback path. The DCO 366 receives the frequency F OUT =(N DIV +α DIV )F REF where N DIV is a positive integer, and α DIV is a decimal value between 0 and 1, and F REF is the frequency of the reference clock signal REF. The fractional-N operation is achieved by dithering the feedback multi-modulus divider MMD 108 using a delta-sigma modulator 110. Here, the dithered signal x DIV The average of [k] is the desired fractional coefficient α DIV Corresponds to.

[0085] [Para 104] The m2-bit quantization error is filtered by the low-pass filtering characteristics of the PLL. However, it is well known that PLLs face conflicting bandwidth trade-offs. For example, DCO phase noise suppression requires a large bandwidth, while effective suppression of ΔΣ quantization noise error requires a low bandwidth. Considering these trade-offs, the impact of ΔΣ quantization noise error on output phase noise is reduced by removing it at the output of the TDC. The effectiveness of this approach depends heavily on the gain and nonlinearity characteristics of the TDC.

[0086] [Para 105] While gain calibration using LMS correlation techniques has been reported in the prior art, it is insufficient to adequately suppress ΔΣ quantization noise errors to the levels mandated by many applications. The dynamic range of the TDC 362 must be at least as large as one DCO period when the fractional divider is dithered by a first-order ΔΣ modulator, and several DCO periods for higher-order ΔΣ modulators. Increasing the dynamic range of the TDC severely degrades its linearity performance. The nonlinearity identification and compensation circuit of Figure 18 accurately estimates and compensates for the nonlinearity in the TDC's output, significantly improving the accuracy of ΔΣ quantization noise rejection.

[0087] [Para 106] Figure 19 is a block diagram of another digital FN-PLL architecture in which ΔΣ quantization noise cancellation is performed in the "time domain" using a digital-to-time converter (DTC). A main DTC 382 and a compensation DTC in the feedback path. C 384 is used to remove quantization noise at the output of fractional divider MMD 108, thereby significantly reducing the dynamic range requirements of TDC 362. The DTC gain is calibrated using LMS correlation techniques by gain calibrator 376 and subtracted from the loop by DTC 382. Similarly, INL compensation is performed by INL identification and compensation 322, and the compensated DTC CThe interpolated adjustment y is subtracted from the PLL loop by 384 INL [k]. The components and functions of INL identification and compensation 322, gain calibrator 376 and delta-sigma modulator 110 are as described above for FIG.

[0088] [Para 107] DTC 382 and DTC C 384 can be any digitally controlled delay element such as a digitally controlled delay line, a voltage controlled delay line with a DAC, a phase rotator, a phase interpolator, a multiphase generator with a phase selector, a multiphase delay locked loop (DLL) with programmable delay, or a phase selector.

[0089] [Para 108] However, the effectiveness of this approach is also limited by the nonlinearity of the DTC. This embodiment of the adaptive DTC INL identification and compensation scheme utilizes narrow range linear compensation (DTC C ) to compensate for DTC INL in the "time domain". As a result, it greatly improves the ΔΣ quantization noise rejection accuracy, thereby enabling ultra-low noise and spurs at the combiner output.

[0090] [Para 109] Figure 20 is a block diagram of another digital FN-PLL architecture where ΔΣ quantization noise cancellation is performed in the "time domain" while INL identification and compensation is in the "digital domain". In this hybrid embodiment, INL identification and compensation 322 is performed by interpolator 316, which provides an interpolated adjustment y that is subtracted from the PLL loop by adder 370. INL Generate the interpolated adjusted y INL [k] is a multi-bit digital value, as is the input to the digital loop filter 364 and the input to the DCO 366. INL compensation is performed in the "digital domain" at the output of the TDC. INL identification and compensation 322 operates as described in FIG. 18.

[0091] [Para 110] Gain calibrator 376 is connected as described in Figure 19. The DTC gain is calibrated by gain calibrator 376 using LMS correlation techniques and subtracted from the loop by DTC 382. This gain calibration is subtracted from the PLL loop after conversion to the "time domain" by DTC 382.

[0092] Alternative Embodiments [Para 111] Several other embodiments are also contemplated by the inventors. For example, many types and configurations of analog detectors, filters, oscillators, adders, DACs and digital processors, functional units, logic gates and logic structures are possible. Various encodings, conversions and modifications to data and signals may be performed at different stages and for various reasons. Functional units, blocks and other components may be shared and used for several purposes. Various initialization and start-up procedures or circuits or power-down circuits and routines could be added.

[0093] [Para 112] Some embodiments disclosed herein are applicable to any ΔΣ FN-PLL, such as analog, digital, or hybrid. FN-PLLs can be used for frequency synthesis, phase modulation and demodulation, clock generation, clock and data recovery, jitter attenuator, and phase synchronization. The output clock OUT can be encoded with data for transmission. Some embodiments presented in this disclosure are particularly suitable for applications with stringent phase noise and spurious performance requirements.

[0094] [Para 113] Error correction or adjustment can be added to the loop in the time domain or the digital domain, or a combination such as that shown in FIG. 20. Various conversions between domains are possible. Compensation can occur in the time, digital, voltage, or current domains, as well as at various locations within a PLL or other loop, network, or circuit. Function p(x) generator 132 has been described as representing the nonlinear error generated by an m-bit DAC. However, the error can also be generated by a DTC (Digital-to-Time Converter) or PI (Phase Interpolator), where the input signal is in digital form and the output is in voltage, time, phase, or other signal form. Generally, similar concepts and techniques can be applied to other analog circuits, such as an ADC (Analog-to-Digital Converter). However, modifications can be added because the ADC input signal is analog and not digital. Thus, kernel blocks 141, 142, .. 144 then represent x i [k] processes an analog input signal (voltage, time, phase, etc.) to generate a signal. By using a constant division kernel such as BP, Haar, or WH, this implementation can still use a simple comparator. This can be a great advantage when using our approach of constant division and interpolation in ADCs and other mixed-signal or analog circuits.

[0095] [Para 114] DTCs 382, ​​384 can be any digitally controlled delay element, such as a digitally controlled delay line, a phase rotator, or a phase interpolator. TDC 362 can compare the phases of REF and DIV to generate a multi-bit digital value directly, or it can use a charge pump to generate an analog voltage that is then converted to a digital value by an ADC.

[0096] [Para 115] Depending on the function, a digital signal processor (DSP) may be used. A DSP may be part of a larger system controlled by a central processing unit (CPU), which may have a microprocessor controlling the DSP, signal processing blocks, circuits, or other additional enhancements, such as a pipeline for processing signals. The CPU can execute instructions stored in memory to perform operations. Inputs, outputs, and intermediate results may be stored in one or more memories. Data signals converted to digital values ​​may be stored in memory for processing by the CPU or DSP, which may use lookup tables or dedicated processors or data pipelines to perform value accumulation, modulation, kernel operations, LMS correlation, compensation function builders, fast iWHT, interpolation, multiplication, and addition / subtraction. General-purpose programmable DSPs may be used for prototyping and development, after which faster DSPs with dedicated hardware may be used for production. Application-specific or custom DSP blocks and other hardware may be used for some or all components, while more general-purpose DSPs may be used for other components, particularly blocks where speed is not critical. Field programmable gate arrays (FPGAs) or other semi-custom blocks may also be used initially for prototypes or later for production devices. The invention may also be implemented using application specific integrated circuit (ASIC) designs or other implementations. Mixed-signal ICs may be used, including PLL and DSP blocks for gain calibration and INL identification and compensation. Devices may be digitally reprogrammable to support various operation modes, initialization, testing, digital signals of different bit widths, different operation speeds, clock speeds, division factors for feedback dividers, etc.

[0097] [Para 116] Many embodiments of the nonlinearity identification and compensation techniques described herein are generally applicable to many analog / mixed-signal / RF integrated circuit (IC) building blocks, including, but not limited to, clock generators, clock and data recovery (CDR), phase interpolators, voltage / current amplifiers, transimpedance amplifiers (TIAs), and power amplifiers (PAs).

[0098] [Para 117] Additional components such as resistors, capacitors, inductors, transistors, extra buffering, etc. may be added at various nodes, and parasitic components may also be present. Enabling and disabling the circuit could be achieved with additional transistors or in other ways. Pass gate transistors or transmission gates could be added for isolation. Filters could be added. While a fast iWHT process has been described, other inverse transforms could be substituted or modified. For example, fast Fourier transforms and inverse Fourier transforms could be used, particularly during the design and prototyping stages, and later reduced in complexity for iWHT.

[0099] [Para 118] Kernel coefficients

number

[0100] [Para 119] In another alternative, TDC 362 includes a charge pump and an analog-to-digital converter (ADC). In this alternative, TDC 362 measures the time or phase difference between the rising edges of clocks REF and DIV and activates the charge pump to charge or discharge a capacitor within TDC 362. The capacitor voltage is then converted by the ADC to a digital value that is input to loop filter 364 or one of summers 368 and 370.

[0101] [Para 120] In yet another embodiment, the TDC 362 can be the PFD / CP 102 without the capacitor or ADC. The loop filter 364 then converts the capacitor voltage V C is the digital control value D for controlling the oscillation frequency of the DCO 366. C It could be an analog capacitor (loop filter 104) with an ADC that converts to [k]. Other combinations and variations are possible.

[0102] [Para 121] Although least mean squares (LMS) has been described, other steepest gradient methods such as recursive least squares (RLS) and modifications of LMS, RLS, or other methods may be substituted.

[0103] [Para 122] Although separate subtractors 368, 370 in series are shown, the subtractors can be in series, or both adjustments can be summed first, and then only the sum of the adjustments is subtracted in a single subtractor within the PLL loop.

[0104] [Para 123] Kernel φ i (x) is in the interval -x if they satisfy the following equation: p ≦x≦+x p are said to be orthogonal within

number

[0105] [Para 124] The + and - inputs to adder 112 may be reversed.

[0106] [Para 125] The orthogonal kernel generator may generate a complete or incomplete set of orthogonal kernels. The orthogonal kernel generator may generate polynomial kernels, linear piecewise kernels, or constant piecewise kernels. Polynomial kernels may include Laguerre polynomials, Hermite polynomials, and Jacobi polynomials such as Legendre, Chebyshev, and Gegenbauer polynomials. Constant piecewise kernels may include block pulse (BP), Haar, and Walsh-Hadamard (WH) kernels. The WH kernel set includes one kernel with a non-zero constant DC bias, while the other WH kernels have a net zero DC bias over the range of the input signal and can each have only two output values. The linear piecewise kernel includes the triangular Walsh-Hadamard (TWH) kernel. The TWH kernel set includes one kernel with a constant DC bias, while the other TWH kernels have a net zero DC bias over the range of the input signal.

[0107] [Para 126] The Background of the Invention section may contain background information related to the problem or environment of the present invention, rather than describing prior art by others. Therefore, the inclusion of material in the Background section is not an admission of prior art by the applicant.

[0108] [Para 127] Any method or process described herein is machine-implemented or computer-implemented and intended to be performed by a machine, computer, or other device, and not intended to be performed solely by a human without the assistance of such a machine. The tangible results produced may include a report or other machine-generated display on a display device such as a computer monitor, projection device, sound generating device, and related media device, as well as hardcopy printout generated by the machine. Computer control of another machine is another tangible result.

[0109] [Para 128] Any advantages and benefits described above may not apply to all embodiments of the present invention. When the word "means" is recited in a claim element, Applicant intends that the claim element fall within the sixth paragraph of 35 U.S.C. § 112. Often, one or more word labels precede the word "means." The one or more words preceding the word "means" are labels intended to facilitate reference to the claim element and are not intended to convey structural limitations. Such means-plus-function claims are intended to encompass not only the structures described herein and their structural equivalents for performing a function, but also equivalent structures. For example, nails and screws have different structures, but are equivalent structures because they both perform a fastening function. Claims without the word "means" are not intended to fall within the sixth paragraph of 35 U.S.C. § 112. The signal is typically an electronic signal, but may also be an optical signal, such as may be carried through fiber optic lines.

[0110] [Para 129] The foregoing description of embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the present invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

1. 1. An integrated circuit (IC), comprising: a mixed signal circuit p(x) (132) that generates a non-linear error in generating an output in response to an input signal x[k]; a nonlinearity error subtractor (136) for subtracting a nonlinearity compensation signal from an internal signal in the mixed signal circuit to compensate for the nonlinearity error and generate a residual error; an integral nonlinearity (INL) discrimination and compensation circuit (322) that receives the input signal and generates the nonlinearity compensation signal; The INL identification and compensation circuit (322) includes: a lookup table (314) for storing an INL compensation result, the INL compensation result being a pre-calculated result of a compensation function acting on the input signal; an interpolator (316) that receives two INL compensation results read from the lookup table (314) in response to n most significant bits (MSBs) of the m-bit input signal x[k], and that uses (m-n) least significant bits (LSBs) of the input signal to interpolate between the two INL compensation results read from the lookup table (314) to generate a nonlinearity compensation signal, where (m-n) has a minimum value of 1; a quadrature kernel generator that receives the input signal and generates a plurality of quadrature kernel signals from the input signal; a minimum mean square error correlator configured to adjust the nonlinearity compensation signal to compensate for changes in the nonlinearity error due to temperature and supply voltage variations, the error correlator having a plurality of paths, each path in the plurality of paths configured to minimum mean square correlate the residual error with a quadrature kernel signal in the plurality of quadrature kernels generated by the quadrature kernel generator, the error correlator generating adaptive coefficients using the plurality of paths; a compensation function constructor (312) that receives the adaptation coefficients from the error correlator and performs an inverse transform to generate an updated compensation function, the updated compensation function being used to generate an updated result that overwrites the INL compensation result in the lookup table (314); Including, An integrated circuit (IC) whereby INL errors in the mixed-signal circuit are identified and adaptively compensated for by subtracting the nonlinearity compensation signal.

2. further comprising preset coefficients for input to said compensation function constructor (312); when the preset coefficients are input to the compensation function constructor (312), the compensation function constructor (312) uses the preset coefficients instead of the adaptive coefficients to generate the updated compensation function; the error correlator is operated to generate the adaptive coefficients periodically, when the residual error exceeds a threshold, or when temperature or supply voltage variations occur; 2. The IC of claim 1, whereby the preset coefficients and the adaptive coefficients are used at different times to generate the INL compensation result that is written into the lookup table (314).

3. the orthogonal kernel generator generates a plurality of Walsh-Hadamard (WH) kernels; a first one of the WH kernels has a constant non-zero DC bias for all values ​​of the input signal; Other WH kernels have a net zero DC bias over the range of the input signal and each have at least two states; Temperature and supply voltage variations cause changes in the non-linearity error; The IC of claim 1 , wherein the error correlator adjusts the nonlinearity compensation signal to compensate for changes in the nonlinearity error caused by the temperature and supply voltage variations.

4. The error correlator a plurality of multipliers (281, 282, 284) each receiving the nonlinearity error; a plurality of accumulators (291, 292, 294); a plurality of decimation filters (301, 302, 304); a plurality of paths through the error correlator, each path having a path kernel in the plurality of orthogonal kernels generated by the orthogonal kernel generator, the path kernel being multiplied by the nonlinear error by a path multiplier in the plurality of multipliers (281, 282, 284) to generate a path product, the path products being accumulated by path accumulators in the plurality of accumulators (291, 292, 294) to generate accumulated path values, the accumulated path values ​​being decimated by a path decimation filter in the plurality of decimation filters (301, 302, 304) to generate an adaptation coefficient in the plurality of adaptation coefficients; further comprising the error correlator is a least mean squares (LMS) correlator (320); The IC of claim 1 , whereby each of the plurality of orthogonal kernels has a corresponding path in the plurality of paths through the error correlator.

5. The mixed signal circuit comprises: an oscillator (366) that produces an output having a frequency determined by a control input to said oscillator (366); a feedback divider for dividing the frequency of said output in response to a divisor input signal to generate a feedback clock; a phase detector for comparing the feedback clock with a reference clock to generate a phase difference; and a loop filter (364) coupled between the phase detector and the oscillator (366), the residual error being sampled from an input to the loop filter (364), the loop filter (364) generating the control input to the oscillator; a delta-sigma modulator (110) that receives a modulator control word and generates the divisor input signal to the feedback divider; a modulator subtractor that generates the difference between the modulator control word and the divisor input signal; and a modulator accumulator (114) for accumulating the differences produced by the modulator subtractor to produce the input signal; further comprising The feedback divider is a multi-modulus divider (MMD) (108), and the mixed signal circuit has a frequency F ＯＵＴ = (N ＤＩＶ +α ＤＩＶ ) F ＲＥＦ a fractional-N PLL that generates an output from the oscillator having ＤＩＶ is a positive integer, and α ＤＩＶ is a decimal value between 0 and 1 corresponding to the mean of the dithering, and F ＯＵＴ is the frequency of the output, and F ＲＥＦ 2. The IC of claim 1, wherein: is the frequency of the reference clock.

6. the phase detector generates a digital value for the phase difference; the loop filter is a digital filter; the control input to the oscillator carries a digital value generated by the loop filter; The IC of claim 5 , wherein the oscillator is a digitally controlled oscillator (DCO).

7. a gain calibrator having a second error correlator (372) that correlates the input signal with the residual error to generate gain calibration coefficients; a gain adjustment multiplier (374) that multiplies the input signal by the gain calibration factor to generate a gain adjusted phase control signal; a second subtractor (368) that subtracts the gain-adjusted phase control signal from a second internal signal within the mixed signal circuit to remove fractional divider phase quantization noise; The IC of claim 5 further comprising:

8. the nonlinearity error subtractor is a digital subtractor coupled between the phase detector and the loop filter; 8. The IC of claim 7, wherein the second subtractor (368) is a digital subtractor and is coupled in series with the nonlinear error subtractor.

9. the nonlinearity error subtractor is a first digital-to-time converter (384) that converts the nonlinearity compensation signal from a digital value to a time adjustment to be applied to the feedback clock; the second subtractor is a second digital-to-time converter (382) that converts the gain adjusted phase control signal from a digital value to a time adjustment to be applied to the second internal signal; 8. The IC of claim 7, wherein the first digital-to-time converter and the second digital-to-time converter are in series between the feedback divider and the phase detector.

10. the nonlinearity error subtractor is a digital subtractor (370) coupled between the phase detector and the loop filter; the second subtractor is a digital-to-time converter (382) that converts the gain adjusted phase control signal from a digital value to a time adjustment that is applied to the second internal signal; the digital-to-time converter (382) is coupled between the feedback divider and the phase detector; 8. The IC of claim 7, wherein the digital-to-time converter (382) is a digitally controlled delay element, a digitally controlled delay line, a voltage controlled delay line with a digital-to-analog converter (DAC), a phase rotator, a phase interpolator, a multiphase generator with a phase selector, a multiphase delay locked loop (DLL) with programmable delay, or a phase selector.

11. 1. A fractional-N phase-locked loop (PLL) with non-linear error correction, comprising: a time-to-digital converter (TDC) (362) that receives a reference clock and a feedback clock and generates a TDC output, the TDC output being a digital value of the phase difference detected by the TDC between the reference clock and the feedback clock; a loop filter (364) that receives the residual error signal and generates the oscillator control signal by applying a digital filter to the residual error signal; an oscillator (366) controlled by the oscillator control signal and generating an output clock having a frequency determined by the oscillator control signal; a feedback divider that divides the output clock by a divisor to generate a divided clock; a modulator that generates a modulating signal to the feedback divider, the modulating signal dithering the divisor of the feedback divider to divide the output clock by an effective divisor having both an integer portion and a fractional portion, the fractional portion being between 0 and 1; a modulation accumulator (114) for accumulating differences in the modulated signal to generate a phase control signal that is the accumulated quantization error of the modulator; a gain calibrator receiving the residual error signal and the phase control signal, the gain calibrator minimizing the error and generating a gain adjustment; a gain subtractor that subtracts the gain adjustment from a first signal in the PLL to remove fractional divider phase quantization noise; 2. The integrated circuit (IC) of claim 1, wherein the phase control signal is an input signal to the integrated circuit, an internal signal of the integrated circuit is a second signal within the PLL for compensating for nonlinearity errors not compensated for by the gain adjustment, and the updated compensation function operates on a range of values ​​of the phase control signal to produce the updated result; A fractional-N phase-locked loop (PLL) comprising:

12. 12. The fractional-N phase-locked loop (PLL) with non-linear error correction of claim 11, wherein the plurality of orthogonal kernels comprises Walsh-Hadamard (WH) kernels.

13. the gain subtractor and the nonlinearity error subtractor each subtract from the TDC output to generate the residual error signal to the loop filter (364); 13. The fractional-N phase-locked loop (PLL) with non-linear error correction of claim 12, wherein the divided clock is the feedback clock.

14. the nonlinearity error subtractor includes a first digital-to-time converter (DTC) coupled between the divided clock and the feedback clock, the first digital-to-time converter (DTC) converting a nonlinearity compensation signal from a digital signal to a time delay that is added to the divided clock to generate the feedback clock; the gain subtractor includes a second digital-to-time converter (DTC) also coupled between the divided clock and the feedback clock and in series with the first DTC, the second DTC converting the gain adjustment from a digital signal to a time delay that is added to the divided clock to generate the feedback clock; 13. The fractional-N phase-locked loop (PLL) with non-linear error correction of claim 12, wherein the TDC output is connected to the residual error signal to the loop filter.

15. the nonlinearity error subtractor is coupled between the TDC output and the loop filter (364), the nonlinearity error subtractor subtracting a nonlinearity compensation signal from the TDC output to generate the residual error signal to the loop filter (364), the TDC output being the second signal; 13. The fractional-N phase-locked loop (PLL) with nonlinear error correction of claim 12, wherein the gain subtractor includes a digital-to-time converter (DTC) coupled between the divided clock and the feedback clock, the DTC converting the gain adjustment from a digital signal to a time delay that is added to the divided clock to generate the feedback clock.

16. The gain subtractor and the nonlinear error subtractor are a pre-adder that adds the gain adjustment to a nonlinearity compensation signal to generate a composite adjustment; a first digital-to-time converter (DTC) coupled between the divided clock and the feedback clock, the first digital-to-time converter (DTC) converting the composite adjustment from a digital signal to a time delay that is added to the divided clock to generate the feedback clock; Both include 13. The fractional-N phase-locked loop (PLL) with non-linear error correction of claim 12, wherein the first signal and the second signal in the PLL are the same signal.

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