Semiconductor processing equipment and semiconductor processing system

Abstract

The present invention relates to A semiconductor processing apparatus includes a lower cavity having a first support area for supporting a wafer, an upper cavity having a second support area, a temperature control module attached close to the upper cavity and / or the lower cavity, and a first passage formed in an edge area of ​​the first support area or the second support area. When the upper cavity and the lower cavity are combined, a wafer is placed between the first support area and the second support area. The temperature control module adjusts its own temperature to adjust the temperature of the upper cavity and / or the lower cavity. A first space is formed by the first passage, and one or more chemical fluids flow in the first space to etch the edge area of ​​the wafer. The temperature control module adjusts the temperature of the upper cavity and / or the lower cavity to adjust the etch width of the wafer edge. The present invention thus allows fine adjustment of the etch width of the wafer edge.

Description

[Technical Field]

[0001] The present invention is in the field of surface processing of semiconductor wafers or similar components, and more particularly relates to semiconductor processing equipment and systems. [Background technology]

[0002] During semiconductor manufacturing, semiconductor wafers undergo various processes to meet the high standards of the semiconductor industry. During the semiconductor wafer manufacturing process, the wafer edges must be uniform, flat, free of damage, and smooth. Due to the requirements for uniform wafer edges and precise etching of the wafer edges, improvements to the semiconductor wafer manufacturing process are needed.

[0003] FIG. 1a is a plan view showing the structure of a semiconductor wafer 100. The semiconductor wafer 100 includes an underlayer 101 and a thin film layer 102 deposited on the underlayer 101. FIG. 1b is a cross-sectional view showing the AA cross section of FIG. 1a. Measurement points 1 through 8 in FIG. 1a are locations where certain values ​​of the semiconductor wafer are measured. As shown in FIG. 1b, the corrosion width refers to the difference between the radius of the underlayer 101 and the radius of the thin film layer 102. The corrosion widths at measurement points 1 through 8 are approximately the same. The smaller the difference between the maximum and minimum corrosion widths, the better the corrosion uniformity. For example, if the edge width is designed to be 0.7 mm, the difference between the maximum and minimum corrosion widths must be less than 0.1 mm. Failure to meet this requirement could result in uneven edge widths. A difference between the maximum and minimum corrosion widths exceeding 0.1 mm could affect subsequent processing. This can affect the performance of the integrated circuit chip and reduce the yield of the manufactured chips.

[0004] Wet processing methods for semiconductor wafers have the advantages of simple principles, good process variability, and low costs. Conventional wet etching methods for treating the edge of a semiconductor wafer include various methods, such as polishing the edge area of ​​the semiconductor wafer, rotating the semiconductor wafer, and removing a thin film layer on an underlying layer using mechanical friction and chemical etching. Because polishing methods can damage the remaining thin film and the underlying layer, they are typically used in semiconductor wafer manufacturing, which requires low precision. Damage to the edge of the semiconductor wafer can cause the wafer to move during processing, resulting in the wafer being discarded. Another commonly used method is vacuum suction. In vacuum suction, the wafer is suctioned by a vacuum suction unit. When suctioning the wafer by the vacuum suction unit, the desired portion of the thin film that does not need to be removed is covered by the vacuum suction unit, while the desired portion of the thin film that needs to be removed is exposed outside the vacuum suction unit. Next, the vacuum suction unit and wafer are immersed in a chemical corrosion solution to remove the desired portion of the thin film exposed outside the vacuum suction unit. However, using the vacuum suction method can result in uneven corrosion due to the inability to remove the thin film smoothly. Another commonly used method is thin film bonding. In this method, the desired portion of the thin film to be removed is protected with a high-purity anticorrosive plastic, such as PTFE or PE. The exposed portion is then etched by either injecting a chemical corrosion gas or immersing it in a chemical corrosion solution. When using the thin film bonding method, the center of the pre-cut thin film and the center of the wafer underside cannot be easily aligned, resulting in uneven corrosion. The thin film bonding method requires multiple steps and equipment, such as a thin film bonding device, a wet corrosion device, a cleaning device, and a thin film removal device. To address these issues, a spraying method has been proposed. The spraying method precisely sprays the etching liquid onto the peripheral area of ​​the rotating wafer using a designated nozzle, allowing for precise, uniform, and flat corrosion without damage.Although the spraying method can improve the corrosion effect, it places high requirements on the design and components of the equipment, which increases the cost of the equipment, and also places high requirements on the process, which increases the processing cost.

[0005] Many materials have a certain coefficient of thermal expansion. In semiconductor wafer edge processing equipment made of a material with a large coefficient of thermal expansion, the width of corrosion at the edge of the wafer may vary during manufacturing or use due to differences in temperature between manufacturing and use, changes in temperature during transportation, or other unexpected factors.

[0006] Due to different processes and manufacturer needs, the width of the wafer edge corrosion must be different. For example, the width of the wafer edge corrosion can be 0.5 mm, 0.6 mm, or 0.3 mm. To meet the different needs of different processes and manufacturers, various semiconductor wafer edge processing equipment with different corrosion sizes can be manufactured, but this method is not feasible because it would significantly increase manufacturing costs.

[0007] Therefore, it is necessary to propose a new type of semiconductor wafer edge processing device that can solve the above problems. Summary of the Invention [Problem to be solved by the invention]

[0008] SUMMARY OF THE INVENTION The object of the present invention is to provide a new semiconductor processing apparatus and system for solving the problems of the prior art and for properly controlling the erosion width of the edge of a semiconductor wafer. [Means for solving the problem]

[0009] To achieve the above object, a first embodiment of the present invention provides a semiconductor processing apparatus. The semiconductor processing apparatus includes a lower cavity having a first support area for supporting a wafer, an upper cavity having a second support area, a temperature control module mounted adjacent to the upper cavity and / or the lower cavity, and a first passage formed in the peripheral area of ​​the first support area or the second support area. When the upper cavity and the lower cavity are joined, the wafer is placed between the first support area and the second support area. The temperature control module adjusts its own temperature to adjust the temperature of the upper cavity and / or the lower cavity. The first passage defines a first space, and one or more chemical fluids can flow within the first space to etch the peripheral area of ​​the wafer. By adjusting the temperature of the upper cavity and / or the lower cavity with the temperature control module, the heating expansion and cooling contraction of the upper cavity and / or the lower cavity can be adjusted, and the position of the edge area of ​​the first support area and / or the second support area can be fine-tuned, and the width of the edge area of ​​the wafer inserted into the first space can be adjusted to suitably adjust the corrosion width of the edge of the wafer.

[0010] In a second embodiment of the present invention, there is further provided a semiconductor processing system, comprising: the semiconductor processing device; and a material storage device coupled to the semiconductor processing device, wherein the material storage device stores one or more chemical fluids and allows the one or more chemical fluids to flow between the semiconductor processing device and the material storage device.

[0011] By using embodiments of the present invention in semiconductor wafer processing, the edge surface of the wafer can be etched evenly and accurately, and the effect of temperature changes on the accuracy of etching of the wafer edge can be reduced.

[0012] In comparison with the prior art, the embodiments of the present invention can provide various inventive advantages.

[0013] The temperature control module of the present invention can adjust the size of the upper and / or lower cavities and adjust the corrosion width of the edge of the wafer by appropriately adjusting the temperature of the upper and / or lower cavities.

[0014] The features, forms, and advantages of the present invention can be understood in detail by carefully reading the following examples and drawings of the present invention. When it is said that the present invention includes a combination of one or more features or elements, it is true that the present invention includes a combination of one or more features or elements, even if the combination of one or more features or elements is explicitly or implicitly described in the examples of the present invention, or is not described in the examples of the present invention. The application of the present invention must be read as a whole. Although separable features or elements are described in the examples of the present invention, unless otherwise specified, the embodiments of the present invention consist of a combination thereof.

[0015] It should be noted that the purpose of the above summary of the invention is to provide a basic understanding of the subject matter of the present invention by outlining an outline of the embodiments of the present invention. The above embodiments are merely illustrative of the present invention and are not intended to limit the scope or gist of the present invention. The following specific embodiments and drawings of the present invention will allow easy understanding of the features, aspects, and effects of the embodiments of the present invention. In other words, the principles of the present invention will be described in detail with reference to the drawings and embodiments of the present invention. [Brief explanation of the drawings]

[0016] The present invention can be readily understood by reference to the following drawings and detailed description, in which like reference numerals refer to like structures. [Figure 1a] FIG. 2 is a bottom view showing the structure of a semiconductor wafer. [Figure 1b] FIG. 1b is a cross-sectional view showing the AA section of FIG. [Figure 2a] 1 is a cross-sectional view showing a semiconductor processing apparatus 200 according to an embodiment of the present invention. [Figure 2b] FIG. 2b is an enlarged view of part A of FIG. 2a. [Figure 2c] FIG. 2b is an enlarged view of part B of FIG. [Figure 2d] FIG. 2c is an enlarged view showing part C of FIG. [Figure 2e] 2b is a bottom view of the upper cavity 220 of the semiconductor processing apparatus 200 of FIG. 2a. [Figure 2f] 2b is a plan view showing the lower cavity 210 of the semiconductor processing apparatus 200 of FIG. 2a. [Figure 3a] 1 is a cross-sectional view showing a semiconductor processing apparatus 300 according to an embodiment of the present invention. [Figure 3b] FIG. 3b is an enlarged view showing part D of FIG. 3a. [Figure 3c] 3b is an enlarged view showing part D of FIG. 3a where a protrusion 342 is provided. [Figure 3d] 3b is a bottom view of the upper cavity 320 of the semiconductor processing apparatus 300 of FIG. 3a. [Figure 3e] 3b is a plan view showing the lower cavity 310 of the semiconductor processing apparatus 300 of FIG. 3a. [Figure 4a] 1 is a cross-sectional view showing a semiconductor processing apparatus 400 according to an embodiment of the present invention. [Figure 4b] FIG. 4b is an enlarged view showing part E of FIG. 4a. [Figure 4c] FIG. 4B is an enlarged view of part F in FIG. [Figure 4d] 4b is a top view of the upper cavity 420 of the semiconductor processing apparatus 400 of FIG. 4a. [Figure 4e] 4b is a plan view of the lower cavity 410 of the semiconductor processing apparatus 400 of FIG. 4a. [Figure 5] 5 illustrates a semiconductor processing system 500 according to an example of the present invention, including semiconductor processing equipment and material storage equipment. [Figure 6] 1 illustrates an exemplary method for processing an edge area of ​​a semiconductor wafer in a semiconductor processing apparatus according to an embodiment of the present invention. [Figure 7] 1 is a diagram showing the structure of one embodiment of a semiconductor processing apparatus capable of fine-tuning the etching width of the edge of a semiconductor wafer according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are merely some of the embodiments of the present invention and do not represent all embodiments of the present invention. The embodiments of the present invention may include not only the following embodiments but also various other embodiments. The purpose of providing the following embodiments is to explain the details of the present invention in detail and to allow those skilled in the art to understand the details of the present invention in detail. For example, unless otherwise specified, terms such as "first," "second," etc. do not imply an order of the details. Although a component is described as being above another component, it may be below the other component (due to a different viewing direction) (unless otherwise specified), and vice versa. Furthermore, although a component is described as being on the left side, it may be on the right side (due to a different viewing direction), and vice versa. Unless otherwise specified, the same reference numeral always represents the same component.

[0018] 1a and 1b are diagrams illustrating the structure of a semiconductor wafer 100. FIG. 1a is a bottom view illustrating the structure of the semiconductor wafer 100, and FIG. 1b is a cross-sectional view illustrating the AA cross section of FIG. 1a. As shown in FIGS. 1a and 1b, the semiconductor wafer 100 includes an underlayer 101 and a thin film layer 102 laminated on the upper surface of the underlayer 101, and a portion of the underlayer 101 may be covered by the thin film layer 102. In another embodiment, the entire underlayer 101 may be covered by the thin film layer 102. In another embodiment, both sides of the surface of the underlayer 101 may be covered by the thin film layer 102.

[0019] In this embodiment, the semiconductor wafer is processed to remove the thin film layer 102 on the underlayer 101. As shown in FIGS. 1a and 1b, the radius of the thin film layer 102 is smaller than the radius of the underlayer 101, and the corrosion width refers to the difference between the radius of the thin film layer 102 and the radius of the underlayer 101. Measurement points 1 through 8 in FIG. 1a are locations where certain values ​​on the semiconductor wafer are measured. The corrosion widths at measurement points 1 through 8 are approximately the same, and the smaller the difference between the maximum and minimum corrosion widths, the better the corrosion uniformity. For example, when the edge width is designed to be 0.7 mm, the difference between the maximum and minimum corrosion widths should be 0.1 mm or less. In this embodiment, part or all of the thin film layer 102 covering both sides of the surface of the underlayer 101 is removed. The corrosion widths on each side of the underlayer 101 can be the same or different.

[0020] 2a to 2f, which are diagrams illustrating the structure of a semiconductor processing apparatus 200 according to an embodiment of the present invention. Fig. 2a is a cross-sectional view illustrating the semiconductor processing apparatus 200, Fig. 2b is an enlarged view illustrating part A of Fig. 2a, Fig. 2c is an enlarged view illustrating part B of Fig. 2b (through holes are omitted), Fig. 2d is an enlarged view illustrating part C of Fig. 2c, Fig. 2e is a bottom view illustrating an upper cavity 220 of the semiconductor processing apparatus 200 of Fig. 2a, and Fig. 2f is a plan view illustrating a lower cavity 210 of the semiconductor processing apparatus 200 of Fig. 2a.

[0021] 1 and 2, the semiconductor processing apparatus 200 includes a lower cavity 210 having a first support area 212 formed therein. The first support area 212 can support a wafer 100. As shown in FIG. 2a, the first support area 212 has an upper surface facing the wafer 100. The wafer 100 can be mounted on the upper surface of the first support area 212. In an embodiment of the present invention, the semiconductor processing apparatus 200 includes an upper cavity 220 having a second support area 222 formed therein. As shown in FIG. 2a, the second support area 222 has a lower surface facing the wafer 100. When the upper cavity 220 and the lower cavity 210 are coupled together, the wafer 100 is mounted between the first support area 212 and the second support area 222. The upper cavity 220 can move between two positions with the lower cavity 210 as its origin. When the upper cavity 220 is in the first position, the wafer 100 can be loaded onto or removed from the first support area 212. As shown in Figure 2a, when the upper cavity 220 is in the second position, the upper cavity 220 and the lower cavity 210 are coupled together, and the wafer 100 can be processed by being secured between the upper surface of the first support area 212 and the lower surface of the second support area 222.

[0022] In one embodiment or a combination of embodiments of the present invention, referring to FIGS. 2a-2c, a semiconductor processing apparatus 200 includes a first passage 230 formed at an edge region of the first support area 212 or the second support area 222. The first passage 230 forms a first space 232, and one or more chemical fluids can be injected into the first space 232 to etch the edge region of the wafer 100. Referring to FIGS. 2a-2c, the first passage 230 forms a peripheral region of the second support part 222 of the upper cavity 220. The first passage 230 is formed on the lower surface of the upper cavity 220, and one side opening of the first passage 230 faces the wafer 100. In this embodiment, the first passage 230 forms a first space 232, and one or more chemical fluids can be injected into the first space 232 to etch the edge region of the wafer 100. 2a to 2c, the first space 232 is formed by the first passage 230 and the inner surface of the wafer 100. In this embodiment, the first passage 230 is formed in an annular shape and surrounds the peripheral region of the wafer 100. The entire peripheral region of the wafer 100 is contained within the first space 232. In another embodiment, the first passage 230 is formed in an arc shape with an included angle of less than 360°, so that the peripheral region of the wafer 100 is contained within a predetermined area of ​​the first space 232. One or more chemical fluids can flow through the arc portion of the first space 232 to etch the peripheral region of the wafer 100.

[0023] 2a to 2c, in a semiconductor processing apparatus 200 according to one embodiment or a combination of embodiments of the present invention, the upper cavity 220 includes a protrusion 240 that abuts against the edge of the wafer 100. The protrusion 240 can be in direct contact with and abut against the edge of the wafer 100. Referring to FIG. 2a, the central axis XX of the wafer 100 is perpendicular to the upper surface of the wafer 100, and the central axis X'-X' of the second support area 222 is perpendicular to the lower surface of the second support area 222. The protrusion 240 allows the central axis XX of the wafer 100 and the central axis X'-X' of the second support area 222 to overlap. When the upper cavity 220 is located at the first position, the wafer 100 is placed on the first support area 212. The central axis XX of the wafer 100 and the central axis X'-X' of the second support area 222 do not necessarily have to overlap. When the upper cavity 220 moves from the first position to the second position, the protrusion 240 contacts the edge of the wafer 100 and then abuts against the edge of the wafer 100, thereby moving the wafer 100 on the upper surface of the first support area 212. When the upper cavity 220 is located at the second position, the wafer 100 is fixed on the upper surface of the first support area 212, and the central axis XX of the wafer 100 and the central axis X'-X' of the second support area 222 can be aligned parallel to each other, or the central axis XX of the wafer 100 and the central axis X'-X' of the second support area 222 can overlap.

[0024] In the semiconductor processing apparatus 200 according to one embodiment or a combination of embodiments of the present invention, the protrusion 240 is adjacent to the second support area 222 and extends in a direction toward the lower cavity 210. Referring to FIGS. 2a and 2b, the protrusion 240 is connected to the second support area 222. When the upper cavity 220 is located in the second position, the protrusion 240 extends to the lower cavity 210. Referring to FIGS. 2a and 2b, in this embodiment, the protrusion 240 is located near the first passage 230. Referring to FIG. 2a, the central axis XX of the wafer 100 is perpendicular to the upper surface of the wafer 100, the central axis X'-X' of the second support area 222 is perpendicular to the lower surface of the second support area 222, and the upper surface of the wafer 100 is parallel to the lower surface of the second support area 222. In an embodiment of the present invention, when the upper cavity 220 is located in the second position, a portion of the upper surface of the wafer 100 overlaps with the lower surface of the second support area 222, and the central axis XX of the wafer 100 overlaps with the central axis X'-X' of the second support area 222.

[0025] In the semiconductor processing apparatus 200 according to one or more embodiments of the present invention, the protrusion 240 may be a closed loop surrounding the wafer 100. Referring to FIG. 2A, the protrusion 240 includes a closed loop. The closed loop surrounds the peripheral region of the wafer 100. The protrusion 240 abuts against the peripheral region of the wafer 100, thereby allowing the central axis XX of the wafer 100 and the central axis X'-X' of the second support region 222 to overlap. In another embodiment, the closed loop has an arc shape with an included angle of 360° or less, and a predetermined portion of the closed loop may abut against the peripheral region of the wafer 100. The protrusion 240 may be formed so that the central axis XX of the wafer 100 and the central axis X'-X' of the second support region 222 are parallel to each other or overlap each other. In another embodiment, the protrusion 240 may be an open loop.

[0026] In the semiconductor processing apparatus 200 according to one or more embodiments of the present invention, the protrusion 240 includes an interior angle facing the central axis X'-X' of the second support area 222. Referring to FIG. 2c, the protrusion 240 includes an interior surface 242, and the included angle α is between the interior surface 242 and a first reference direction Y-Y. The first reference direction Y-Y is parallel to the lower surface of the second support area 222. The included angle α ranges from 20° to 90°. As shown in FIGS. 2b and 2c, the interior angle is formed by the interior surface 242 of the protrusion 240 and the inner surface of the first passage 230 and faces the central axis X'-X' of the second support area 222. In this embodiment, the interior angle abuts the peripheral area of ​​the wafer 100. 2b, when the upper cavity 220 moves from the first position to the second position, the interior corner of the protrusion 240 comes into contact with the edge of the wafer 100 and then abuts against the edge of the wafer 100, thereby moving the wafer 100. When the upper cavity 220 is located at the second position, the wafer 100 is fixed on the upper surface of the first support area 212, and the central axis XX of the wafer 100 and the central axis X'-X' of the second support area 222 are aligned parallel to each other, or the central axis XX of the wafer 100 and the central axis X'-X' of the second support area 222 overlap.

[0027] In the semiconductor processing apparatus 200 according to one or a combination of embodiments of the present invention, a first tank 250 is formed in the peripheral region 214 of the lower cavity 210, and one or more chemical fluids can flow within a first tank space 252 formed by the first tank 250. Referring to Figures 2a, 2b, and 2f, the first tank 250 is formed in the peripheral region 214 of the lower cavity 210 and is adjacent to the first support region 212 of the lower cavity 210. The first tank space 252 is formed by the first tank 250, and one or more chemical fluids can flow from the first space 232 of the first passage 230 to the first tank space 252.

[0028] In the semiconductor processing apparatus 200 according to one or more embodiments of the present invention, a passage 260 is located between the upper cavity 220 and the lower cavity 210. Referring to FIGS. 2B and 2F, the lower cavity 210 has a first upper surface 262 located between the first support area 212 and the first tank 250. The passage 260 is located between the first upper surface 262 of the lower cavity 210 and the inner surface 242 of the protrusion 240. The passage 260 connects the first space 232 and the first tank space 252, allowing one or more chemical fluids to flow from the first space 232 to the first tank space 252 through the passage 260. In some embodiments of the present invention, the passage 260 is blocked by the protrusion 240, thereby preventing one or more chemical fluids from flowing from the first space 232 to the first tank space 252. In another embodiment, the passageway 260 may be blocked by the first support area 212, thereby preventing one or more chemical fluids from flowing from the first volume 232 to the first reservoir volume 252.

[0029] In a semiconductor processing apparatus 200 according to one or a combination of embodiments of the present invention, as shown in FIGS. 2A to 2C, the first passage 230 is located in the peripheral region of the second support region 222. The upper cavity 220 includes a first through-hole 270, through which one or more chemical fluids can flow between the first space 232 and the outside of the semiconductor processing apparatus 200. The first through-hole 270 passes through the upper cavity 220 from the outside of the semiconductor processing apparatus 200 and is then connected in communication with the first space 232. In this embodiment, the one or more chemical fluids can flow between the first space 232 and the outside of the semiconductor processing apparatus 200 through the first through-hole 270. In other embodiments, the upper cavity 220 may include two or more through-holes similar to the first through-hole 270 (e.g., the other first through-hole 272 in FIGS. 2A and 2E). In this embodiment, at least one first through-hole (e.g., first through-hole 270) can be used as an inlet, and another first through-hole (e.g., another first through-hole 272) can be used as an outlet. The first space 232 can be connected to the outside via the first through-hole 270 and the other first through-hole 272. In this embodiment, one or more chemical fluids can flow from the outside of the semiconductor processing device 200 to the first space 232 of the first passage 230 via the first through-hole 270, and can flow from the first space 232 to the outside of the semiconductor processing device 200 via the other first through-hole 272.

[0030] In the semiconductor processing apparatus 200 according to one or a combination of embodiments of the present invention, the second passage 280 is formed in the peripheral region of the first support region 212, and one or more chemical fluids can be injected into the second space 282 of the second passage 280 to etch the peripheral region of the wafer 100. Referring to FIGS. 2a to 2c, the second passage 280 is formed in the peripheral region of the first support region 212 of the lower cavity 210. Referring to FIGS. 2a to 2c, the second passage 280 is formed on the upper surface of the lower cavity 210, and one side opening of the second passage 280 faces the wafer 100. In this embodiment, the second passage 280 forms a second space 282, and one or more chemical fluids can be injected into the second space 282 to etch the peripheral region of the wafer 100. Referring to FIGS. 2a to 2c, the second space 282 can be formed by the inner surface of the second passage 280 and the wafer 100. In one embodiment of the present invention, the second passage 280 is annular and surrounds the peripheral region of the wafer 100. In another embodiment, the second passage 280 is arc-shaped with an included angle of less than 360°, so that the peripheral region of the wafer 100 is exposed to a predetermined region of the second space 282. In this case, one or more chemical fluids can flow through the arc portion of the second space 282 to etch the peripheral region of the wafer 100. In another embodiment of the present invention, the shape of the second passage 280 and the shape of the first passage 230 can be similarly designed. The second passage 280 is adjacent to the first upper surface 262 and is located between the first support region 212 and the first tank 250. The passage 260 is located between the first upper surface 262 of the lower cavity 210 and the inner surface 242 of the upper cavity 220. When the passage 260 is formed, one or more chemical fluids can flow from the second space 282 to the first tank space 252 through the passage 260. In some embodiments, the passage 260 may be blocked by the protrusion 240, thereby preventing one or more chemical fluids from flowing from the second space 282 to the first reservoir space 252. In other embodiments, the passage 260 may be blocked by the first support area 212, thereby preventing one or more chemical fluids from flowing from the second space 282 to the first reservoir space 252.

[0031] In the semiconductor processing apparatus 200 according to one or more embodiments of the present invention, the second through-hole 290 is formed in the lower cavity 210, thereby allowing one or more chemical fluids to flow between the second space 282 and the outside of the semiconductor processing apparatus 200. Referring to FIGS. 2A and 2B, the second through-hole 290 passes through the lower cavity 210 from the outside of the semiconductor processing apparatus 200 and then communicates with the second space 282 of the second passage 280. In some embodiments of the present invention, the one or more chemical fluids can flow between the second space 282 and the outside of the semiconductor processing apparatus 200 through the second through-hole 290. In other embodiments, the one or more chemical fluids can flow from the outside of the semiconductor processing apparatus 200 to the second space 282 of the second passage 280 through the second through-hole 290, and can also flow from the second space 282 of the second passage 280 to the first tank space 252 of the first tank 250 through the passage 260. In another embodiment, the lower cavity 210 may further include one or more second through-holes similar to the second through-hole 290 (e.g., may further include another second through-hole 292 in FIG. 2a ). In this case, at least one second through-hole (e.g., the second through-hole 290) may be used as an inlet, and another first through-hole (e.g., the other second through-hole 292) may be used as an outlet, and the second space 282 may be connected in communication with the outside via the second through-hole 290 and the other second through-hole 292. In this embodiment, one or more chemical fluids may flow from the outside of the semiconductor processing device 200 to the second space 282 of the second passage 280 via the second through-hole 290, and from the second space 282 to the outside of the semiconductor processing device 200 via the other second through-hole 292. In another embodiment, one or more chemical fluids can flow from the outside of the semiconductor processing device 200 to the second space 282 of the second passage 280 through the second through-hole 290 and the other second through-hole 292, and can flow from the second space 282 of the second passage 280 to the first tank space 252 of the first tank 250 through the passage 260.

[0032] 3a to 3e, which are diagrams illustrating the structure of a semiconductor processing apparatus 300 according to an embodiment of the present invention, Fig. 3a is a cross-sectional view illustrating the semiconductor processing apparatus 300 according to an embodiment of the present invention, Fig. 3b is an enlarged view illustrating portion D of Fig. 3a, Fig. 3c is an enlarged view illustrating portion D of Fig. 3a with a protrusion 342, Fig. 3d is a bottom view illustrating an upper cavity 320 of the semiconductor processing apparatus 300 of Fig. 3a, and Fig. 3e is a plan view illustrating a lower cavity 310 of the semiconductor processing apparatus 300 of Fig. 3a.

[0033] In an embodiment of the present invention, referring to FIGS. 3a to 3e, a semiconductor processing apparatus 300 includes a lower cavity 310 in which a first support area 312 is formed. The structures of the lower cavity 310 and the first support area 312 may refer to the structures of the lower cavity 210 and the first support area 212 shown in FIGS. 2a to 2f. The semiconductor processing apparatus 300 includes an upper cavity 320 in which a second support area 322 is formed. The structures of the upper cavity 320 and the second support area 322 may refer to the structures of the upper cavity 220 and the second support area 222 shown in FIGS. 2a to 2f. As described above, when the upper cavity 320 and the lower cavity 310 are coupled together, the wafer 100 is fixed between the first support area 312 and the second support area 322. The semiconductor processing apparatus 300 includes a first passage 330 formed by the peripheral area of ​​the first support area 312 or the second support area 322. The structure of the first passage 330 may refer to the structure of the first passage 230 shown in FIGS. 2a to 2f. The first passage 330 is formed in the peripheral region of the second support region 322 of the upper cavity 320. The first passage 330 forms a first space 332, and one or more chemical fluids can be injected into the first space 332 to etch the peripheral region of the wafer 100. The structure of the first space 332 may refer to the structure of the first space 232 shown in FIGS. 2a to 2f. In an embodiment of the present invention, the first space 332 of the first passage 330 may be formed by the inner surface of the first passage 330, the lower cavity 310, and the wafer 100. Since all or a portion of the peripheral region of the wafer 100 is exposed in the first space 332 of the first passage 330, it can be etched with one or more chemical fluids.

[0034] In a semiconductor processing apparatus 300 according to one or a combination of embodiments of the present invention, as shown in FIGS. 3a to 3d, the upper cavity 320 includes a protrusion 340, which abuts against the edge of the wafer 100, thereby allowing the central axis XX of the wafer 100 to overlap with the central axis X'-X' of the second support area 322. The structure of the protrusion 340 can refer to the structure of the protrusion 240 shown in FIGS. 2a to 2e. In this embodiment of the present invention, the protrusion 340 includes a plurality of protrusions 342 that are evenly arranged around the periphery of the wafer 100 and abut against the edge area of ​​the wafer 100. The protrusions 342 extend from the protrusion 340 into the first space 332 of the first passage 330. As shown in FIGS. 3c and 3d, the protrusion 340 may include four protrusions (e.g., protrusions 342a to 342d). Each protrusion 342 includes an inner surface 344, and the included angle β between the inner surface 344 and the reference direction Y-Y is 20° to 90°. The inner surface 344 faces the edge of the wafer 100. The reference direction Y-Y is parallel to the upper surface of the wafer 100 or perpendicular to the central axis X'-X' of the second support area 322. For example, in FIG. 3c, the protrusion 342a includes an inner surface 344a, and the included angle β between the inner surface 344a and the reference direction Y-Y is β. The inner surface 344a abuts against the edge of the wafer 100, thereby moving the wafer 100 so that the central axis XX of the wafer 100 and the central axis X'-X' of the second support area 322 overlap. The protrusion 340 may include multiple protrusions 342. For example, in one embodiment of the present invention, the protrusion 340 includes six protrusions 342. In other embodiments, the protrusion 340 may include eight protrusions 342 or the protrusion 340 may include twelve protrusions 342 .

[0035] 3a to 3c, in a semiconductor processing apparatus 300 according to one or a combination of embodiments of the present invention, a first tank 350 is formed in a peripheral region 314 of a lower cavity 310, and one or more chemical fluids can flow within a first tank space 352 defined by the first tank 350. The first tank 350, the peripheral region 314 of the lower cavity 310, and the first tank space 352 of the first tank 350 may refer to the first tank 250, the peripheral region 214 of the lower cavity 210, and the first tank space 252 of the first tank 250, respectively, shown in FIGS. 2a to 2f. In this embodiment of the present invention, a passage 360 ​​is formed between the upper cavity 320 and the lower cavity 310, and the passage 360 ​​connects the first space 332 and the first tank space 352, allowing one or more chemical fluids to flow from the first space 332 to the first tank space 352 through the passage 360. The structure of the passage 360 ​​can refer to the structure of the passage 260 shown in Figures 2a to 2f. In the embodiment of the present invention, the passage 360 ​​is located between the protrusion 340 and the first upper surface 362 of the lower cavity 310. As shown in Figures 3a to 3c and 3e, the first upper surface 362 is close to the first support area 312 and is located between the first support area 312 and the first tank 350.

[0036] In the semiconductor processing apparatus 300 according to one embodiment or a combination of embodiments of the present invention, as shown in FIGS. 3a, 3b, and 3d, the upper cavity 320 includes a first through-hole 370, through which one or more chemical fluids can flow between the first space 332 and the outside of the semiconductor processing apparatus 300. The structure of the first through-hole 370 may refer to the structure of the first through-hole 270 shown in FIGS. 2a to 2e. In the present embodiment, the upper cavity 320 may further include one or more first through-holes similar to the first through-hole 370 (e.g., the first through-hole 372 in FIGS. 3a and 3d). The arrangement of the one or more first through-holes may refer to the arrangement of the one or more first through-holes shown in FIGS. 2a and 2e.

[0037] 3a, 3b, and 3e, in a semiconductor processing apparatus 300 according to one or more embodiments of the present invention, the lower cavity 310 includes a second through-hole 380. As shown in FIGS. 3a and 3b, the second passage 380 allows one or more chemical fluids to flow between the first space 332 and the outside of the semiconductor processing apparatus 300. The second through-hole 380 passes through the lower cavity 310 from the outside of the semiconductor processing apparatus 300 and is then connected to the first space 332 in communication. In this embodiment, one or more chemical fluids can flow from the outside of the semiconductor processing apparatus 300 to the first space 332 through the second through-hole 380, and can flow from the first space 332 to the first tank space 352 of the first tank 350 through the passage 360. In an embodiment of the present invention, one or more chemical fluids can flow from the outside of the semiconductor processing apparatus 300 to the first space 332 through the first passage 330 via the first through-hole 370, from the first space 332 to the first tank space 352 via the passage 360, and then to the outside of the semiconductor processing apparatus 300 via the second through-hole 380.

[0038] In the semiconductor processing apparatus 300 according to one or a combination of embodiments of the present invention, the second tank 390 is formed in the peripheral region 324 of the upper cavity 320 and is located above the first tank 350. Referring to FIGS. 3a to 3d, the second tank 390 is formed in the peripheral region 324 of the upper cavity 320 and is adjacent to the protrusion 340. One or more chemical fluids can flow within the second tank space formed by the second tank 390. The opening of the second tank 390 faces the lower cavity 310. Since the second tank 390 is located above the first tank 350, the first tank space 352 of the first tank 350 and the second tank space of the second tank 390 can be connected in communication with each other. The structure of the second tank 390 can be designed similarly to the structure of the first tank 350. As shown in FIGS. 3d and 3e, the first tank 350 and the second tank 390 are formed in an annular shape. The first and second tanks 350 and 390 may also be designed to have an arc shape with an included angle of less than 360°.

[0039] In the semiconductor processing apparatus 300 according to one embodiment or a combination of embodiments of the present invention, as shown in FIGS. 3a to 3c, a resilient element 392 may be installed between the first tank 350 and the second tank 390. In some embodiments of the present invention, the resilient element 392 may be installed in the first tank space 352 or the second tank space. In some embodiments of the present invention, the resilient element 392 may be installed in the first tank space 352 and the second tank space. In some embodiments of the present invention, the resilient element 392 may prevent one or more chemical fluids from flowing from the first space 332 to the first tank space 352. As shown in FIGS. 3a to 3c, the width of the resilient element 392 is greater than the widths of the first tank 350 and the second tank 390. The inner surface of the first tank 350 and / or the inner surface of the second tank 390 may contact the resilient element 392 to prevent one or more chemical fluids from flowing from the first space 332 to the first tank space 352.

[0040] In the semiconductor processing apparatus 300 according to one or a combination of embodiments of the present invention, the elastic component 392 can be an O-ring.

[0041] 4a to 4e, which are diagrams illustrating a structure of a semiconductor processing apparatus 400 according to an embodiment of the present invention, Fig. 4a is a cross-sectional view illustrating the semiconductor processing apparatus 400 according to an embodiment of the present invention, Fig. 4b is an enlarged view illustrating a portion E of Fig. 4a, Fig. 4c is an enlarged view illustrating a portion F of Fig. 4b, Fig. 4d is a plan view illustrating an upper cavity 420 of the semiconductor processing apparatus 400 of Fig. 4a, and Fig. 4e is a plan view illustrating a lower cavity 410 of the semiconductor processing apparatus 400 of Fig. 4a.

[0042] 4a to 4e, a semiconductor processing apparatus 400 according to an embodiment of the present invention includes a lower cavity 410 in which a first support area 412 is formed. The structures of the lower cavity 410 and the first support area 412 may refer to the structures of the lower cavity 210 and the first support area 212 shown in FIGS. 2a to 2f. The semiconductor processing apparatus 400 includes an upper cavity 420 in which a second support area 422 is formed. The structures of the upper cavity 420 and the second support area 422 may refer to the structures of the upper cavity 220 and the second support area 222 shown in FIGS. 2a to 2f. The semiconductor processing apparatus 400 includes a first passage 430 formed in a peripheral area of ​​the first support area 412. The structure of the first passage 430 may refer to the structure of the first passage 230 shown in FIGS. 2a to 2f. 4a to 4c and 4e, a first passage 430 is formed in the peripheral region of the first support region 412 of the lower cavity 410, and one or more chemical fluids can be injected into a first space 432 formed by the first passage 430 to etch the peripheral region of the wafer 100. The first space 432 of the first passage 430 can also be formed by the inner surface of the first passage 430 and the wafer 100. Since all or a portion of the peripheral region of the wafer 100 is accommodated within the first space 432 of the first passage 430, all or a portion of the peripheral region of the wafer 100 can be etched with one or a plurality of chemical fluids.

[0043] In a semiconductor processing apparatus 400 according to one embodiment or a combination of embodiments of the present invention, as shown in FIGS. 4a to 4d, the upper cavity 420 includes a protrusion 440, which abuts against the edge of the wafer 100, thereby allowing the central axis XX of the wafer 100 to overlap with the central axis X'-X' of the second support area 422. The structure of the protrusion 440 may refer to the structure of the protrusion 240 shown in FIGS. 2a to 2e. In this embodiment, the protrusion 440 faces the lower cavity 410 and is located near the lower surface 424 of the second support area 422. In this embodiment, the protrusion 440 includes a plurality of protrusions that are evenly arranged around the periphery of the wafer 100 and abut against the edge area of ​​the wafer 100. The structure of the protrusions may refer to the structure of the protrusions 342 shown in FIGS. 3a to 3d.

[0044] In a semiconductor processing apparatus 400 according to one embodiment or a combination of embodiments of the present invention, the protrusion 440 includes an inner surface 442 that is inclined relative to the central axis X'-X' of the second support area 422, and the inner surface 442 abuts against the peripheral area of ​​the wafer 100. Referring to FIGS. 4a to 4d, the inner surface 442 faces the wafer 100 and abuts against the peripheral area of ​​the wafer 100. The inner surface 442 is inclined relative to the reference axis ZZ, and the included angle between the inner surface 442 and the reference axis ZZ is γ. The included angle γ ranges from 20° to 90°. The reference axis ZZ is parallel to the central axis X'-X' of the second support area 422. In an embodiment of the present invention, the inner surface 442 of the protrusion 440 contacts the peripheral region of the wafer 100 and abuts against the peripheral region of the wafer 100, thereby allowing the central axis XX of the wafer 100 to overlap with the central axis X'-X' of the second support region 422. In an embodiment of the present invention, the inner surface 442 of the protrusion 440 abuts against the wafer 100, thereby allowing the wafer 100 to move so that the central axis XX of the wafer 100 overlaps with the central axis X'-X' of the second support region 422.

[0045] In a semiconductor processing apparatus 400 according to one or a combination of embodiments of the present invention, referring to FIGS. 4a, 4b, and 4e, a first tank 450 is formed in the peripheral region 414 of the lower cavity 410, and one or more chemical fluids can flow within a first tank space 452 formed in the first tank 450. The first tank 450, the peripheral region 414 of the lower cavity 410, and the first tank space 452 of the first tank 450 may refer to the first tank 250, the peripheral region 214 of the lower cavity 210, and the first tank space 252 of the first tank 250 shown in FIGS. 2a to 2f. In this embodiment of the present invention, a passage 460 is located between the upper cavity 420 and the lower cavity 410. The passage 460 connects the first space 432 and the first tank space 452, allowing one or more chemical fluids to flow from the first space 432 to the first tank space 452 through the passage 460. The structure of the passage 460 can refer to the structure of the passage 260 shown in Figures 2a to 2f. In an embodiment of the present invention, as shown in Figure 4c, the passage 460 is located between the wafer 100 and the first upper surface 462 of the lower cavity 410. As shown in Figures 4c and 4e, the first upper surface 462 is located between the first passage 430 and the first tank 450.

[0046] 4a to 4c and 4e, in a semiconductor processing apparatus 400 according to one embodiment or a combination of embodiments of the present invention, the lower cavity 410 includes a first through-hole 470, through which one or more chemical fluids can flow between the first space 432 and the outside of the semiconductor processing apparatus 400. The structure of the first through-hole 470 may refer to the structure of the first through-hole 270 shown in FIGS. 2a to 2e. In an embodiment of the present invention, the lower cavity 410 may further include one or more first through-holes similar to the first through-hole 470 (e.g., the first through-hole 472 in FIGS. 4a and 4e). The arrangement of the one or more first through-holes may refer to the arrangement of the one or more first through-holes shown in FIGS. 2a and 2e.

[0047] In a semiconductor processing apparatus 400 according to one or a combination of embodiments of the present invention, referring to FIGS. 4a, 4b, and 4e, a second passage 480 is located in the peripheral region of the first support region 412, and one or more chemical fluids can be injected into the second space 482 of the second passage 480 to etch the peripheral region of the wafer 100. The structure of the second passage 480 can refer to the structure of the second passage 280 shown in FIGS. 2b, 2c, and 2f. In this embodiment, the first passage 430 and the second passage 480 are connected by a passage 484, so that one or more chemical fluids can flow between the first space 432 of the first passage 430 and the second space 482 of the second passage 480. Referring to FIGS. 4b and 4c, the passage 484 connecting the first passage 430 and the second passage 480 is formed in the wafer 100 and the first support region 412 of the lower cavity 410. One or more chemical fluids can flow between the first space 432 and the second space 482 through the passage 484. In some embodiments of the present invention, one or more chemical fluids can flow from the second space 482 through the passage 484, the first space 432, and the passage 460, and then into the first reservoir space 452.

[0048] 4a, 4b, and 4e, in a semiconductor processing apparatus 400 according to one or a combination of embodiments of the present invention, a second through-hole 490 is formed in a lower cavity 410, thereby allowing one or more chemical fluids to flow between a second space 482 and the outside of the semiconductor processing apparatus 400. The structure of the second through-hole 490 may refer to the structure of the second through-hole 290 shown in FIGS. 2a to 2c. In some embodiments of the present invention, the lower cavity 410 may further include one or more second through-holes similar to the second through-hole 490 (e.g., second through-hole 492 in FIGS. 4a and 4e). The arrangement of the one or more second through-holes may refer to the arrangement of the one or more second through-holes shown in FIG. 2a.

[0049] In the present invention, the use of protrusions improves the accuracy and uniformity of etching the wafer's edge area, and by appropriately selecting the components of the chemical fluid used for etching and controlling the flow rate of the chemical fluid and the contact time between the chemical fluid and the wafer's edge, a flat surface can be formed on the wafer's underlayer, making subsequent wafer processing easier and reducing wafer processing costs. That is, the present invention can accurately select the surface of the wafer's edge that needs to be processed, and in particular, accurately control the etching area of ​​the wafer's edge.

[0050] In the above embodiment, the protrusion is formed on the upper cavity, but in other embodiments, the protrusion can be formed on the lower cavity. Also, a positioning structure can be formed on the upper cavity and / or the lower cavity, and the positioning structure can abut the outer periphery of the wafer edge, thereby overlapping the central axis of the wafer with the central axis of the second support section.

[0051] FIG. 5 illustrates a semiconductor processing system 500 according to an embodiment of the present invention, which includes a semiconductor processing device 510 and a material storage device 520. The semiconductor processing device 510 may refer to any one of the semiconductor processing devices 200, 300, and 400 shown in FIGS. 2a-2f, 3a-3e, and 4a-4e, respectively. The semiconductor processing device 510 includes a lower cavity having a first support area for supporting a wafer and an upper cavity having a second support area. The wafer is fixed between the first and second support areas by coupling the upper and lower cavities. A first passage is located in the peripheral area of ​​the first or second support area, and one or more chemical fluids can be injected into the first space to etch the peripheral area of ​​the wafer. In this embodiment, the upper cavity includes a protrusion that abuts against the edge of the wafer, thereby allowing the central axis of the wafer to overlap with the central axis of the second support area. The material storage device 520 is coupled to the semiconductor processing device 510. The material storage device 520 stores one or more chemical fluids and allows the one or more chemical fluids to flow between the semiconductor processing device 510 and the material storage device 520. In an embodiment of the present invention, the one or more chemical fluids may be H3PO4, HF, HCl, HNO3, H2O2, or a combination thereof.

[0052] In a semiconductor processing system 500 according to one or a combination of embodiments of the present invention, the protrusion is adjacent to the second support area and extends in a direction toward the lower cavity. The central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support area is perpendicular to the lower surface of the upper cavity, and the upper surface of the wafer is parallel to the lower surface of the second support area. In an embodiment of the present invention, the protrusion includes a closed loop surrounding the wafer, and the protrusion evenly abuts the peripheral area of ​​the wafer, allowing the central axis of the wafer and the central axis of the second support area to overlap.

[0053] In a semiconductor processing system 500 according to one or a combination of embodiments of the present invention, the convex portion is adjacent to the second support area and extends in a direction toward the lower cavity. The central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support area is perpendicular to the lower surface of the upper cavity, and the upper surface of the wafer is parallel to the lower surface of the second support area. In an embodiment of the present invention, the convex portion includes a plurality of protrusions arranged in a ring shape around the wafer, and the plurality of protrusions evenly abut the peripheral area of ​​the wafer.

[0054] In a semiconductor processing system 500 according to one or a combination of embodiments of the present invention, a first tank is formed in the peripheral region of the lower cavity, and one or more chemical fluids can flow within the first tank space defined by the first tank. In some embodiments of the present invention, a passage is formed between the upper cavity and the lower cavity, connecting the first space and the first tank space, allowing one or more chemical fluids to flow from the first space to the first tank space through the passage. In some embodiments of the present invention, a second tank is formed in the peripheral region of the upper cavity, and the second tank is located above the first tank. In some embodiments of the present invention, an elastic element is attached between the first tank and the second tank, and the elastic element can prevent the one or more chemical fluids from flowing from the first space to the first tank space.

[0055] In a semiconductor processing system 500 according to one or a combination of embodiments of the present invention, the semiconductor processing system 500 includes a controller 530. The controller 530 can communicate with and control the semiconductor processing equipment 510 and the material storage equipment 520. For example, the controller 530 can control the movement of the upper cavity between a first position where a wafer is loaded or unloaded and a second position where the upper cavity and the lower cavity are coupled to process the wafer. The controller 530 can also control the flow rate and flow direction of one or more chemical fluids. The controller 530 can detect the flow rate, flow direction, and state of the one or more chemical fluids and any malfunctions of the semiconductor processing equipment 510. In an embodiment of the present invention, the controller can include a PLC, a control unit, a sensor, and a storage device (e.g., a memory, a hard disk drive, an SSD, etc.).

[0056] 6 illustrates an exemplary method 600 for processing an edge region of a semiconductor wafer 100 using semiconductor processing equipment according to an embodiment of the present invention. The method may use any one of semiconductor processing equipment 200, semiconductor processing equipment 300, semiconductor processing equipment 400, or semiconductor processing equipment 500 shown in FIGS. 2a-2f, 3a-3e, 4a-4e, and 5, respectively.

[0057] In step 602 of FIG. 6 according to an embodiment of the present invention, the semiconductor processing equipment 200 (semiconductor processing equipment 300, semiconductor processing equipment 400, or semiconductor processing equipment 500) places the transferred wafer on the first support area of ​​the lower cavity. In step 604, the semiconductor processing equipment couples the upper and lower cavities to fix the wafer between the first and second support areas of the upper cavity. In step 606, a first passage is formed in the peripheral area of ​​the first support area or the second support area, and a first space is formed by the first passage. In step 608, the semiconductor processing equipment abuts a protrusion against the peripheral area of ​​the wafer, thereby overlapping the central axis of the wafer with the central axis of the second support area. In step 610, the semiconductor processing equipment injects one or more chemical fluids into the first space to etch the peripheral area of ​​the wafer.

[0058] In step 602 of method 600 according to one embodiment or a combination of embodiments of the present invention, a wafer is transferred by a wafer transfer device onto a first support area of ​​a lower cavity of semiconductor processing apparatus 200 (semiconductor processing apparatus 300, semiconductor processing apparatus 400, or semiconductor processing apparatus 500). The upper surface of the first support area faces the wafer. When the wafer transfer device transfers the wafer onto the upper surface of the first support area, a portion of the lower surface of the wafer is covered by the upper surface of the first support area. In an embodiment of the present invention, when the upper cavity of semiconductor processing apparatus 200 (semiconductor processing apparatus 300, semiconductor processing apparatus 400, or semiconductor processing apparatus 500) is located at the first position, a wafer can be loaded onto or removed from the first support area. That is, the wafer can be transferred from the wafer transfer device onto the upper surface of the first support area.

[0059] In step 604 of method 600 according to one embodiment or a combination of embodiments of the present invention, the semiconductor processing apparatus 200 (semiconductor processing apparatus 300, semiconductor processing apparatus 400, or semiconductor processing apparatus 500) couples the upper and lower cavities to fix the wafer between the first and second support areas of the upper cavity. When the upper cavity is located in the second position, the coupling of the upper and lower cavities fixes the wafer between the first and second support areas, thereby allowing the peripheral area of ​​the wafer to be processed. The upper cavity includes a second support area facing the lower surface of the wafer. Coupling the upper and lower cavities fixes the wafer between the first and second support areas. That is, the wafer can be fixed between the lower surface of the first support area and the upper surface of the second support area.

[0060] In step 606 of method 600 according to one or a combination of embodiments of the present invention, a first passage is formed in the peripheral region of the first support region or the second support region. The first passage may also be formed on the lower surface of the upper cavity. The opening of the first passage faces the wafer. In some embodiments of the present invention, the first passage forms a first space, in which the peripheral region of the wafer can be processed. For example, the peripheral region of the wafer can be etched by injecting one or more chemical fluids into the first space. In some embodiments of the present invention, the first passage may be designed as a closed loop. In some embodiments of the present invention, the first passage may also be designed as a circle. The semiconductor processing device 200 (semiconductor processing device 300, semiconductor processing device 400, or semiconductor processing device 500) or a wafer transfer device can feed all or part of the peripheral region of the wafer into the first space for processing. In some embodiments of the present invention, the first passage may be formed as an arc with an included angle of 360° or less. The semiconductor processing apparatus 200 (semiconductor processing apparatus 300, semiconductor processing apparatus 400, or semiconductor processing apparatus 500) or the wafer transfer apparatus transfers a portion of the peripheral area of ​​the wafer into the first space for processing.

[0061] In step 608 of method 600 according to one or a combination of embodiments of the present invention, a protrusion is formed in the upper or lower cavity of the semiconductor processing apparatus 200 (semiconductor processing apparatus 300, semiconductor processing apparatus 400, or semiconductor processing apparatus 500). The semiconductor processing apparatus can abut the protrusion against the peripheral area of ​​the wafer. When the upper cavity moves from the first position to the second position, the protrusion contacts the edge of the wafer. The protrusion then abuts the edge of the wafer, thereby moving the wafer on the upper surface of the first support area of ​​the lower cavity. When the upper and lower cavities are coupled, the wafer is fixed on the upper surface of the first support area, and the central axis XX of the wafer and the central axis X'-X' of the second support area are aligned parallel to each other. The distance between the central axis XX of the wafer and the central axis X'-X' of the second support area is 0 mm to 0.1 mm. In an embodiment of the present invention, the protrusion is adjacent to the second support area and extends toward the lower cavity. In an embodiment of the present invention, the protrusion is located near the first passageway.

[0062] In one embodiment of the present invention, the protrusion includes an interior angle that faces the central axis X'-X' of the second support region. The interior angle is formed by the inner surface of the protrusion and the inner surface of the first passage, and faces the central axis X'-X' of the second support region. In one embodiment of the present invention, the interior angle abuts the edge region of the wafer. When the upper cavity moves from the first position to the second position, the interior angle of the protrusion can contact the edge of the wafer and then abut against the edge of the wafer, thereby moving the wafer. In another embodiment, the inner surface of the protrusion can contact the edge of the wafer and then abut against the edge of the wafer, thereby moving the wafer.

[0063] In step 610 of method 600 according to one or a combination of embodiments of the present invention, the semiconductor processing apparatus 200 (semiconductor processing apparatus 300, semiconductor processing apparatus 400, or semiconductor processing apparatus 500) etches the peripheral area of ​​the wafer by injecting one or more chemical fluids into the first space. The one or more chemical fluids flow around the edge of the wafer in the first space, thereby etch the peripheral area of ​​the wafer exposed in the first space. In one embodiment of the present invention, the semiconductor processing apparatus includes a through-hole that communicates between the first space and the outside of the semiconductor processing apparatus. The one or more chemical fluids can flow into the first space through the through-hole. In another embodiment of the present invention, the semiconductor processing apparatus includes two through-holes that communicate with the first space and the outside of the semiconductor processing apparatus, respectively. The two through-holes are spaced apart by a predetermined distance, and one or more chemical fluids can flow into the first space through one through-hole and flow out of the first space to the outside of the semiconductor processing device through the other through-hole.

[0064] As described in the prior art, many materials have a certain coefficient of thermal expansion. Semiconductor wafer edge processing equipment made of materials with a certain coefficient of thermal expansion may experience variations in the width of the wafer's edge corrosion during manufacturing or use due to differences in temperature between manufacturing and use, temperature changes during transportation, or other unforeseen factors. Furthermore, different wafer edge corrosion widths may be required depending on the process and manufacturer's needs. For example, the wafer edge corrosion width may be 0.5 mm, 0.6 mm, or 0.3 mm. While it is possible to manufacture various semiconductor wafer edge processing equipment with different specifications to meet the various process and manufacturer needs, this method is not feasible due to the significant increase in manufacturing costs.

[0065] To solve the above problems, the present invention provides a semiconductor processing apparatus that can finely adjust the etching width of the wafer edge. As shown in Figure 7, Figure 7 is a diagram showing the structure of one embodiment of the semiconductor processing apparatus that can finely adjust the etching width of the wafer edge of the present invention.

[0066] The semiconductor processing apparatus of FIG. 7 has a similar structure to that of FIG. 3A, except that the semiconductor processing apparatus of FIG. 7 further includes a temperature control module 810 mounted adjacent to the upper cavity 320 and a temperature control module 810 mounted adjacent to the lower cavity 310. The temperature control module 810 adjusts its own temperature to control the temperatures of the upper cavity 320 and the lower cavity 310. By adjusting the temperatures of the upper cavity 320 and the lower cavity 310, the temperature control module 810 can adjust the expansion and contraction of the upper cavity 320 and the lower cavity 310 when heated and cooled, and can also fine-tune the position of the edge region of the first support area and / or the second support area. That is, by adjusting the width at which the edge region of the wafer 100 is inserted into the first space 332, the width of the edge corrosion of the wafer 100 can be tailored. Specifically, when the upper cavity 320 and the lower cavity 310 expand, causing the edges of the first and / or second support regions to expand outward, the width by which the edge region of the wafer 100 is inserted into the first space 332 decreases. This reduces the width of the edge corrosion of the wafer 100. Conversely, when the upper cavity 320 and the lower cavity 310 contract, causing the edges of the first and / or second support regions to contract inward, the width by which the edge region of the wafer 100 is inserted into the first space 332 increases. This increases the width of the edge corrosion of the wafer 100. Note that the expansion and contraction are relative terms. Similarly, the temperature control module 810 can be installed in the semiconductor processing equipment of FIGS. 2a and 4a.

[0067] The temperature control module 810 installed in the semiconductor processing equipment allows the temperature of the upper cavity and the temperature of the lower cavity to be appropriately adjusted. Adjusting the temperature of the temperature control module 810 prevents small changes in the size of the upper and lower cavities due to changes in environmental temperature or other factors, and actively adjusts the edge corrosion width of the wafer. This avoids using a single semiconductor processing equipment for various wafers with different edge corrosion widths and manufacturing different semiconductor processing equipment to achieve different corrosion widths. Furthermore, even if the edge corrosion width of the wafer processed in the semiconductor processing equipment does not meet a preset requirement, the temperature of the temperature control module 810 can be adjusted to ensure that the edge corrosion width of the wafer meets the preset requirement.

[0068] In an embodiment of the present invention, the temperature control module 810 includes a temperature control element 811 and a heat conduction element 812, the heat conduction element 812 is installed between the temperature control element 811 and the upper cavity 320, and the temperature control element 811 includes a plurality of electric heating units. The temperature of the temperature control element 811 is controlled by controlling the power of the electric heating units, and the heat conduction element 812 transfers heat to the upper cavity 320 to adjust the temperatures of the upper cavity 320 and the lower cavity 310. The electric heating units may be, for example, electric heating resistance wires.

[0069] The temperature control module 810, the upper cavity 320, and the lower cavity 310 may be designed to have a separable structure. In this case, the temperature control module 810, the upper cavity 320, and the lower cavity 310 may be integrally assembled by a connecting module. The temperature control module 810, the upper cavity 320, and the lower cavity 310 may also be integrally molded. In other embodiments, the temperature control module 810 may be attached only to the lower side of the lower cavity 310 or only to the upper side of the upper cavity 320.

[0070] By installing the temperature control module 810 in a semiconductor processing apparatus, the requirements for manufacturing, transporting, and assembling the semiconductor processing apparatus can be significantly reduced. In addition, the erosion width of the wafer edge can be controlled, thereby increasing the range of use of the semiconductor processing apparatus.

[0071] Although specific embodiments of the present invention have been described above, these embodiments are merely illustrative of the present invention and are not intended to limit the present invention. The scope of the present invention is defined by the claims and their equivalents.

[0072] In this specification, the term "one embodiment" or "embodiment" means that a feature, structure, or characteristic of the embodiment is included in at least one embodiment of the present invention. When the term "in one embodiment" appears in various places in this specification, it does not refer exclusively to the same embodiment, nor does it refer exclusively to the only embodiment or to a specific embodiment that excludes other embodiments. In this specification, the terms "multiple" and "plural" refer to two or more items. In this specification, the term "and / or" refers to a relationship of "and" or "or." In this specification, terms such as "first," "second," "third," and "fourth" are used to distinguish between different items and are not intended to limit the order of the items. In this specification, each term describes a specific item, but does not limit it.

[0073] When a person skilled in the art implements various modifications and other embodiments of the present invention, it is assumed that the person skilled in the art has common knowledge and some basic data in the art. It should be noted that the present invention is not limited to the above-described embodiments of the present invention, and may further include other embodiments within the scope of the present invention. Although elements and functions according to certain embodiments have been described above with reference to the above-described embodiments and certain drawings, it is understood that other elements and functions included in the claims of the present application are also included in the present invention. The claims of the present application may include not only the elements and features explicitly described above, but also other elements, features, and combinations thereof that are different from them. Certain terms are used in this specification, but they are intended to describe the present invention and not to limit the present invention.

Claims

1. The wafer processing apparatus includes a lower cavity in which a first support area for supporting a wafer is formed, an upper cavity having a second support area, a temperature control module attached so as to be close to the upper cavity and / or the lower cavity, and a first passage formed in a peripheral area of ​​the first support area or the second support area, When the upper cavity and the lower cavity are joined, the wafer is mounted between the first support area and the second support area; a temperature control module for controlling the temperature of the upper cavity and / or the lower cavity by controlling its own temperature; the first passage defines a first space, and one or more chemical fluids flow within the first space to etch the edge area of ​​the wafer; The temperature control module adjusts the temperature of the upper cavity and / or the lower cavity to adjust the heating expansion and cooling contraction of the upper cavity and / or the lower cavity, and also fine-tunes the position of the edge area of ​​the first support area and / or the second support area, and adjusts the width of the edge area of ​​the wafer inserted into the first space to suitably adjust the etching width of the edge of the wafer.

2. 2. The semiconductor processing apparatus of claim 1, wherein the upper cavity and / or the lower cavity includes a positioning structure that abuts against the outer periphery of the wafer edge, thereby overlapping the central axis of the wafer with the central axis of the second support area.

3. 3. The semiconductor processing apparatus of claim 2, wherein the positioning structure is formed on the upper cavity, the positioning structure being a convex portion, and the convex portion abuts against the outer periphery of the edge of the wafer, thereby overlapping the central axis of the wafer with the central axis of the second support area.

4. the protrusion on the upper cavity is adjacent to the second support area and extends in a direction toward the lower cavity, the central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support area is perpendicular to the lower surface of the upper cavity, and the upper surface of the wafer is parallel to the lower surface of the second support area; 4. The semiconductor processing apparatus of claim 3, wherein the convex portion includes a curved portion formed in a ring shape surrounding the outer periphery of the wafer, and the convex portion evenly abuts against the outer periphery of the edge of the wafer, so that the central axis of the wafer and the central axis of the second support area overlap.

5. 4. The semiconductor processing apparatus according to claim 3, wherein the convex portion includes a plurality of protruding portions, the plurality of protruding portions being arranged in a ring shape around the periphery of the wafer and evenly abutting against the outer periphery of the wafer's edge.

6. the protrusion includes an inner surface that is inclined to form a predetermined angle with a central axis of the second support section, the inner surface evenly abutting the outer periphery of the wafer edge; 4. The semiconductor processing apparatus of claim 3, wherein the convex portion includes an interior angle that faces a central axis of the second support area, and the interior angle evenly abuts against the outer periphery of the wafer edge.

7. 2. The semiconductor processing apparatus of claim 1, wherein the first tank is located in a peripheral area of ​​the lower cavity, the first tank forms a first tank space through which one or more chemical fluids flow, and a passage is formed between the upper cavity and the lower cavity, and the passage connects the first space and the first tank space, so that one or more chemical fluids flow from the first space to the first tank space through the passage.

8. a second reservoir formed in a peripheral region of the upper cavity and positioned above the first reservoir; a resilient element is attached between the first and second reservoirs, the resilient element preventing the one or more chemical fluids from flowing from the first space to the second reservoir space; a first passage is formed in the peripheral area of ​​the second support area, and one or more chemical fluids flow between the first space and the outside of the semiconductor processing device through the first through-hole of the upper cavity; a second passageway is formed in the peripheral area of ​​the first support area, and one or more chemical fluids flow through a second space formed by the second passageway to corrode the peripheral area of ​​the wafer; a second through-hole formed in the lower cavity, allowing one or more chemical fluids to flow between the second space of the lower cavity and the outside of the semiconductor processing device; 8. The semiconductor processing apparatus of claim 7, wherein the peripheral area of ​​the second support area defines a first passage, the upper cavity includes a first through-hole, and one or more chemical fluids flow between the first space and the outside of the semiconductor processing apparatus through the first through-hole of the upper cavity.

9. 2. The semiconductor processing apparatus of claim 1, wherein the temperature control module includes a temperature control element and a heat conducting element, the heat conducting element being mounted between the temperature control element and the upper cavity and / or the lower cavity, and the temperature control element including a plurality of electric heating units.

10. a semiconductor processing device and a material storage device connected to the semiconductor processing device, the material storage device storing one or more chemical fluids and allowing the one or more chemical fluids to flow between the semiconductor processing device and the material storage device; The semiconductor processing apparatus includes a lower cavity in which a first support area for supporting a wafer is formed, an upper cavity having a second support area, a temperature control module attached to be close to the upper cavity and / or the lower cavity, and a first passage formed in a peripheral area of ​​the first support area or the second support area; When the upper cavity and the lower cavity are joined, the wafer is mounted between the first support area and the second support area; a temperature control module for controlling the temperature of the upper cavity and / or the lower cavity by controlling its own temperature; the first passage defines a first space, and one or more chemical fluids flow within the first space to etch the edge area of ​​the wafer; The temperature control module adjusts the temperature of the upper cavity and / or the lower cavity to adjust the heating expansion and cooling contraction of the upper cavity and / or the lower cavity, and also fine-tunes the position of the edge area of ​​the first support area and / or the second support area, and adjusts the width of the edge area of ​​the wafer inserted into the first space to suitably adjust the etching width of the edge of the wafer.

11. 11. The semiconductor processing system of claim 10, wherein the convex portion is adjacent to the second support area and extends in a direction toward the lower cavity, the central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support area is perpendicular to the lower surface of the upper cavity, the upper surface of the wafer is parallel to the lower surface of the second support area, the convex portion includes a closed loop formed in a ring shape surrounding the outer periphery of the wafer, and the convex portion evenly abuts the outer periphery of the edge of the wafer so that the central axis of the wafer and the central axis of the second support area overlap.

12. 11. The semiconductor processing system of claim 10, wherein the convex portion is adjacent to the second support area and extends in a direction toward the lower cavity, the central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support area is perpendicular to the lower surface of the upper cavity, the upper surface of the wafer is parallel to the lower surface of the second support area, and the convex portion includes a plurality of protrusions, the plurality of protrusions being arranged in a ring shape around the wafer and evenly abutting the outer periphery of the wafer's edge.

13. 11. The semiconductor processing system of claim 10, wherein the first tank is located in the peripheral area of ​​the lower cavity, forming a first tank space through which one or more chemical fluids flow; a passage is formed between the upper cavity and the lower cavity, connecting the first space and the first tank space so that the one or more chemical fluids flow from the first space to the first tank space through the passage; the second tank is formed in the peripheral area of ​​the upper cavity and located above the first tank; and an elastic member is attached between the first tank and the second tank, preventing the one or more chemical fluids from flowing from the first space to the first tank space.

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