Package substrate, package substrate processing method, and package substrate manufacturing method

Abstract

To relax accuracy of a cutting depth.SOLUTION: There is provided a package substrate 1 in which a metal-made lead frame 31 having a lattice-like first frame part 33 along a predetermined division line of partitioning a support 7 where a device chip 8 is arranged and a plurality of first electrode parts 34 extending from the first frame part 33, and a connection frame 32 having a lattice-like second frame part 36 along a predetermined division line on a side where the device chip 8 is arranged of the lead frame 31, and a plurality of second electrode parts 37 extending from the second frame part 36 are arranged, wherein a tip of the second electrode part 37 is formed into a convex shape and is connected to the first electrode parts 34, and the connection frame 32 forms an electrode when a cut surface of the first electrode part 34 formed by cutting the first electrode part 34 from the first frame part 33 is subjected to field plating processing, and a mold resin 12 covering the device chip 8 and the connection frame 32 is provided.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to a package substrate, a method for processing a package substrate, and a package Substrate manufacturing method Regarding. [Background technology]

[0002] A package substrate (QFN package substrate) is used in which a semiconductor device chip is mounted on a metal frame (lead frame) and sealed with molded resin. On the surface of the QFN package substrate, multiple electrodes, typically made of copper (Cu), are provided so as to be exposed along the planned dividing lines (streets). Each of the multiple electrodes is connected to the device chip via wires or the like inside the QFN package substrate.

[0003] The QFN package chip is formed by dividing the electrodes along the planned dividing lines with a cutting blade and cutting the QFN package substrate (see, for example, Patent Document 1). Copper electrodes are exposed on the sides of the QFN package chip formed in this way. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-206995 Summary of the Invention [Problem to be solved by the invention]

[0005] Copper electrodes are easily oxidized, and once oxidized, their solder wettability deteriorates. This deterioration in solder wettability makes it difficult to secure the electrodes of a QFN package chip to a wiring board such as a printed circuit board via solder.

[0006] To prevent this deterioration in solder wettability, a so-called wettable flank is known, in which at least the exposed side portions of the copper electrodes on the QFN package chip are plated. Plating enhances the mechanical strength of the solder joints between the copper electrodes and the wiring board. In this case, the electrodes are half-cut with a cutting blade to form the sides of the electrodes. The surfaces and sides of the electrodes are then plated, and the electrodes are then separated into individual package chips by cutting the center of the cut groove with a thin blade.

[0007] However, when half-cutting electrodes to a specified depth, it is difficult to form grooves with a highly accurate cutting depth because package substrates vary in thickness and warp, and there are many issues with half-cutting metal, such as clogging of the cutting blade and the likelihood of burrs on the electrode (metal).

[0008] The object of the present invention is to provide a package substrate, a method for processing a package substrate, and a package substrate that can relax the precision of the cutting depth. Substrate manufacturing method The purpose is to provide [Means for solving the problem]

[0009] In order to solve the above-mentioned problems and achieve the object, a package substrate of the present invention is a package substrate in which a device chip mounted on a metal frame is covered with a molding resin, the device chip; a metal lead frame having a lattice-shaped first frame portion along a planned dividing line that divides a support portion on which the device chip is to be placed, and a plurality of first electrode portions extending from the first frame portion on both sides; and a lead frame on the side of the lead frame on which the device chip is to be placed. Arranged, a connection frame having a grid-shaped second frame portion along the planned division line and a plurality of second electrode portions extending from the second frame portion toward both sides; a wire connecting the first electrode portion and the device chip; the device chip and the connection frame, which are arranged so as to be electrically connected to the first electrode portion of the lead frame; The wire and a mold resin covering the only Equipped with 、 The tip of the second electrode portion toward the first electrode portion from the second frame portion The first electrode is formed in a convex shape and is connected to the first electrode portion of the lead frame, and serves as an electrode when electrolytic plating is performed on the cross section of the first electrode portion formed by cutting the first electrode portion from the first frame portion. vinegar It is characterized by:

[0010] The processing method for a package substrate of the present invention is a processing method for the package substrate, comprising a cutting groove forming step of cutting a first cutting blade into the first frame portion of the lead frame along the planned division line on the surface side of the package substrate where the lead frame is exposed, forming a cutting groove of a depth that does not reach the connection frame covered with the mold resin, and exposing a cut surface of the first electrode portion cut by cutting the first frame portion in the cutting groove; and after the cutting groove forming step, applying a voltage to the cut first electrode portion via the connection frame, and plating the exposed surface of the first electrode portion by electrolytic plating. a dividing step in which, after the plating step, a second cutting blade thinner than the first cutting blade is used to cut the center of the cutting groove, thereby cutting the connection frame and the molding resin and dividing the package chip into individual package chips; and a soldering step in which the front side of the package chip is placed facing the wiring board on which it is to be mounted, and the plated first electrode portion of the package chip is connected to the electrode of the wiring board with solder, wherein the solder wettability of the cut surface of the electrode cut in the cutting groove forming step is ensured by the plating step.

[0011] The package of the present invention A method for manufacturing the substrate is a method for manufacturing the package substrate, in which the connection frame is placed on the side of the lead frame on which the device chip is disposed, the device chip is placed on the support portion, the first electrode portion is connected to the device chip by the wire, and the device chip, the wire, and the connection frame are covered with the molding resin. It is characterized by: [Effects of the Invention]

[0012] The present invention has the effect of making it possible to relax the precision of the cutting depth. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a plan view schematically showing a package substrate according to the first embodiment. [Figure 2]FIG. 2 is a side view of the package substrate shown in FIG. [Figure 3] FIG. 3 is a plan view of the back surface side of the package substrate shown in FIG. [Figure 4] FIG. 4 is a perspective view schematically showing a package chip obtained by dividing the package substrate shown in FIG. [Figure 5] FIG. 5 is a plan view showing a main part of a lead frame that constitutes the frame of the package substrate shown in FIG. [Figure 6] FIG. 6 is a plan view showing a main part of a connection frame that constitutes the frame of the package substrate shown in FIG. [Figure 7] FIG. 7 is a plan view showing a main part of the frame of the package substrate shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a cross-sectional view showing a state in which a device chip is mounted on the frame shown in FIG. [Figure 10] FIG. 10 is a cross-sectional view showing the device chip shown in FIG. 9 covered with a molding resin. [Figure 11] FIG. 11 is a flowchart showing the flow of the method for processing a package substrate according to the first embodiment. [Figure 12] FIG. 12 is a cross-sectional view schematically showing a cutting groove forming step in the method of processing the package substrate shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view schematically showing the package substrate after the plating step of the method for processing the package substrate shown in FIG. [Figure 14] 14A to 14C are cross-sectional views schematically showing the dividing step of the method for processing the package substrate shown in FIG. [Figure 15] FIG. 15 is a cross-sectional view schematically showing a solder fixing step in the method of processing the package substrate shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0014] Modes (embodiments) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited to the contents described in the following embodiment 1. Furthermore, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially the same. Furthermore, the configurations described below can be combined as appropriate. Furthermore, various omissions, substitutions, or modifications of the configuration can be made within the scope of the gist of the present invention.

[0015] [Embodiment 1] A package substrate, a method for processing a package substrate, and a package chip according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view schematically illustrating the package substrate according to the first embodiment. FIG. 2 is a side view of the package substrate shown in FIG. 1. FIG. 3 is a plan view of the back side of the package substrate shown in FIG. 1. FIG. 4 is a perspective view schematically illustrating a package chip obtained by dividing the package substrate shown in FIG. 1. FIG. 5 is a plan view showing a main part of a lead frame constituting the frame of the package substrate shown in FIG. 1. FIG. 6 is a plan view showing a main part of a connection frame constituting the frame of the package substrate shown in FIG. 1. FIG. 7 is a plan view showing a main part of the frame of the package substrate shown in FIG. 1. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7. FIG. 9 is a cross-sectional view showing a state in which a device chip is mounted on the frame shown in FIG. 8. FIG. 10 is a cross-sectional view showing a state in which the device chip shown in FIG. 9 is covered with a molding resin.

[0016] (Package substrate) 1, 2, and 3 according to the first embodiment is subjected to cutting or the like to be divided into individual package chips 2 shown in Fig. 4. The package substrate 1 is a so-called QFN (Quad Flat Non-leaded Package) package substrate in which a device chip 8 mounted on a metal frame 3 is covered with a mold resin 12.

[0017] The package substrate 1 according to the first embodiment is formed into a rectangular flat plate shape in plan view, as shown in Fig. 1. The package substrate 1 includes a rectangular flat plate-shaped frame 3, which has a device region 4 and a peripheral excess region 5 surrounding the device region 4. The frame 3 is made of a metal such as a metal containing copper (i.e., a copper alloy).

[0018] The device region 4 has a plurality of dividing lines 6 that intersect with each other. One of the plurality of dividing lines 6 extends in a direction parallel to the longitudinal direction of the frame 3, and the other of the dividing lines 6 extends in a direction perpendicular to the longitudinal direction of the frame 3 and parallel to the width direction of the frame 3. Device chips 8 are disposed on support sections 7 defined by the plurality of dividing lines 6 that intersect with each other. The dividing lines 6 penetrate the frame 3. The support sections 7 are formed by a portion of the frame 3, and the device chips 8 are disposed on a back surface 10 (shown in FIG. 3, etc.) behind the front surface 9. The front surface 9 of the frame 3 also serves as the front surface 9 of the package substrate 1 and the package chip 2. Electrodes 11 for connecting the package chip 2 to a wiring board or the like are provided on each dividing line 6.

[0019] The electrodes 11 are formed by parts of the frame 3, and in the first embodiment, are provided at the center of the width direction of the planned division lines 6, and are formed linearly in a direction perpendicular to the planned division lines 6. The electrodes 11 are connected to the device chip 8 by wires 18 shown in FIG.

[0020] In the first embodiment, a plurality of device regions 4 (three in the first embodiment) are arranged at intervals in the longitudinal direction of the frame 3. The peripheral surplus region 5 is an area in which no device chips 8 are arranged, and is formed by the frame 3, surrounds the entire periphery of each device region 4, and connects adjacent device regions 4 together.

[0021] 2 and 3, the package substrate 1 includes a molded resin 12 that seals (coats) the back surface 10 side of each device region 4. The molded resin 12 is made of a thermoplastic resin, and seals (coats) the device chips 8 and wires 18 arranged on the back surface 10 of the support portion 7 of the frame 3, and is also filled within the division lines 6. The molded resin 12 seals (coats) the entire device regions 4 on the back surface 10 side of the frame 3. On the front surface 9 side of the frame 3, the molded resin 12 seals the inside of the division lines 6 while leaving the support portion 7 on which the device chips 8 are arranged and the electrodes 11 exposed.

[0022] The package substrate 1 is cut at the center of the width of each planned division line 6 in each device region 4, and divided into individual package chips 2 as shown in Fig. 4. As described above, the package substrate 1 according to the first embodiment is a QFN package substrate in which metal electrodes 11 are arranged along the planned division lines 6, but is not limited to this and may also be a CSP (Chip Scale Packaging) substrate. In addition, in the first embodiment, the package chips 2 separated from the package substrate 1 are small chips with sides measuring approximately 1 mm x 1 mm, i.e., the chip size is small.

[0023] 1, the package substrate 1 has alignment marks 13 on the surface 9 of the frame 3 at both ends of the division lines 6 to indicate cutting positions of the division lines 6 during cutting. In the first embodiment, the alignment marks 13 are arranged at the center of each division line 6 in the width direction and at positions aligned along the longitudinal direction of the division lines 6.

[0024] The package chip 2 manufactured by dividing the package substrate 1 has a device chip 8 mounted on a support portion 7 of a metal frame 3 and covered with a mold resin 12. As shown in Fig. 4, the package chip 2 includes the support portion 7 of the frame 3, the device chip 8 disposed on a back surface 10 of the support portion 7, electrodes 11, and mold resin 12. The mold resin 12 seals the device chip 8 and the like with the surface 9 of the support portion 7 and the electrodes 11 exposed.

[0025] In the first embodiment, the surface 9 of the package chip 2, where the support portion 7 is exposed, is connected to each side surface 14 of the package chip 2 by a step portion 15 having a predetermined width and height. The step portion 15 is formed around the entire periphery of the surface 9 and is also formed on all side surfaces 14. The step portion 15 is parallel to the side surfaces 14 and flat in a direction perpendicular to both the surface 9 and the back surface 10, and includes a second side surface 151 on the surface 9 side, a flat surface 152 connecting the second side surface 151 and the side surface 14, and a connection portion connecting the second side surface 151 and the flat surface 152. The flat surface 152 is formed flat along both the surface 9 and the back surface 10. The height of the step portion 15 is set to a predetermined depth that is smaller than the thickness of the electrode 11 and is set in advance during the design stage or the like.

[0026] The package chip 2 also has a metal plating layer 16 (shown in FIG. 13) on the surface of the electrodes 11. The plating layer 16 improves the wettability of the electrodes 11 with the solder 22 (shown in FIG. 15) that fixes the package chip 2 to a wiring board 20 (shown in FIG. 15). The package chip 2 is mounted on the wiring board 20 with the electrodes 11 fixed to the electrodes 21 of the wiring board 20 by the solder 22. Note that the plating layer 16 is omitted from FIG. 4.

[0027] 2, the frame 3 of the package substrate 1 according to the first embodiment includes a lead frame 31 and a connection frame 32 stacked on top of each other. The lead frame 31 and the connection frame 32 are made of a metal such as a metal containing copper (i.e., a copper alloy), that is, made of metal. Note that the same parts of the lead frame 31 and the connection frame 32 as those of the frame 3 are given the same reference numerals and their description will be omitted. The lead frame 31 is disposed on the front surface 9 of the frame 3, and the connection frame 32 is disposed on the back surface 10 of the frame 3.

[0028] As shown in FIG. 5 , the lead frame 31 integrally includes a plurality of support portions 7, a plurality of first frame portions 33, a plurality of first electrode portions 34, and a surplus region forming portion (not shown) that forms the peripheral surplus region 5. The first frame portions 33 are formed in a grid pattern along the division lines 6 that define the support portions 7 on which the device chips 8 are arranged. The first frame portions 33 are arranged around each support portion 7. Note that FIG. 1 does not show the first frame portions 33. The first frame portions 33 are formed linearly parallel to the division lines 6. The first frame portions 33 are arranged at the center of the division lines 6 in the width direction. Note that the first frame portions 33 are connected to the support portions 7 by connecting pieces 35. The first frame portions 33 arranged on the division lines 6 at the outermost edges of each device region 4 among the plurality of division lines 6 are connected to the surplus region forming portion. The width of the first frame portions 33 is smaller than the width of the division lines 6.

[0029] The first electrode portions 34 extend linearly from the first frame portion 33 to both sides in the width direction of the first frame portion 33. The first electrode portions 34 are arranged within the planned division lines 6, with their tips spaced apart from the support portions 7. Wires 18 are connected to the tips of the first electrode portions 34, and the first electrode portions 34 are electrically connected to the device chip 8. The first electrode portions 34 constitute the electrodes 11 described above. In the first embodiment, the lead frame 31 is formed to have the same thickness across the support portions 7, the first frame portion 33, and the first electrode portions 34.

[0030] As shown in FIG. 6 , the connection frame 32 integrally includes a plurality of second frame portions 36, a plurality of second electrode portions 37, and a surplus area forming portion (not shown) that forms the peripheral surplus area 5. The second frame portion 36 is overlaid on the side of the first frame portion 33 of the lead frame 31 where the device chip 8 is arranged, and is formed in a grid pattern along the planned division lines 6. The second frame portion 36 is formed in a straight line parallel to the planned division lines 6. The second frame portion 36 is arranged at the center in the width direction of the planned division lines 6. The second frame portion 36 arranged on the planned division lines 6 at the outermost edge of each device area 4 among the plurality of planned division lines 6 is continuous with the surplus area forming portion. The width of the second frame portion 36 is smaller than the width of the planned division lines 6.

[0031] The second electrode portions 37 extend linearly from the second frame portion 36 to both sides in the width direction of the second frame portion 36. The second electrode portions 37 are arranged within the planned division lines 6, with their tips spaced apart from the support portions 7. The tips of the second electrode portions 37 are arranged closer to the second frame portion 36 than the tips of the first electrode portions 34. The second electrode portions 37 are placed on the side of the first electrode portions 34 of the lead frame 31 where the device chip 8 is arranged, and are electrically connected to the first electrode portions 34.

[0032] 7 and 8, the frame 3 is configured such that the first frame portion 33 of the lead frame 31 arranged on the front surface 9 side and the second frame portion 36 of the lead frame 31 arranged on the back surface 10 side overlap each other, and the first electrode portion 34 and the second electrode portion overlap each other. In addition, in the first embodiment, the tip of the second electrode portion 37 is formed in a convex shape that is more protruding toward the first electrode portion 34 than the second frame portion 36, as shown in FIG. 8, and is connected to the first electrode portion 34 of the lead frame 31, and the second frame portion 36 overlaps the first frame portion 33 with a gap therebetween, and the base end of the second electrode portion 37 overlaps the first electrode portion 34 with a gap therebetween.

[0033] In the package substrate 1 having the above-described configuration, the lead frame 31 and the connection frame 32 of the frame 3 are stacked on top of each other, and then, as shown in Fig. 9, the device chip 8 is placed on the back surface 10 of the support portion 7, and the first electrode portions 34 are connected to the device chip 8 by wires 18. After the device chip 8 is placed on the support portion 7, the package substrate 1 is manufactured by covering the device chip 8, wires 18, connection frame 32, etc. with mold resin 12, as shown in Fig. 10. In this way, the mold resin 12 covers the device chip 8, which is arranged so as to be electrically connected to the first electrode portions 34 of the lead frame 31, and the connection frame.

[0034] (Package substrate processing method) 11 is a flowchart showing the flow of the method for processing a package substrate according to embodiment 1. The method for processing a package substrate is a method for dividing a package substrate 1 into individual package chips 2 and fixing the package chips 2 to a wiring substrate 20. As shown in FIG. 11, the method for processing a package substrate includes a cutting groove forming step 1001, a plating step 1002, a dividing step 1003, and a solder fixing step 1004.

[0035] (Cutting groove formation step) Fig. 12 is a cross-sectional view schematically showing a cutting groove forming step of the processing method for the package substrate shown in Fig. 11. In cutting groove forming step 1001, first cutting blade 41 is cut into first frame portion 33 of lead frame 31 along planned division line 6 on the side of surface 9 where lead frame 31 of package substrate 1 is exposed, to form cutting groove 19 having a depth that does not reach second frame portion 36 of connection frame 32 covered with mold resin 12, and cutting first frame portion 33 to expose cut surface 341 of first electrode portion 34 on the inner surface of cutting groove 19.

[0036] In the cutting groove forming step 1001, the cutting device 40 suction-holds the back surface 10 of the package substrate 1, i.e., the molding resin 12, on the holding surface of a chuck table (not shown). In the cutting groove forming step 1001, the cutting device 40 uses an imaging unit to capture an image of the mark 13 on the front surface 9 of the package substrate 1 held on the chuck table, and performs alignment to align the first cutting blade 41 with the planned division line 6.

[0037] In the cutting groove forming step 1001, the cutting device 40 moves the chuck table and the first cutting blade 41 relatively along the division lines 6, and as shown in FIG. 12 , the cutting edge of the first cutting blade 41 cuts into the first frame portion 33 located in the center of the width of the division lines 6 to a depth that does not reach the second frame portion 36 covered with the mold resin 12, thereby forming cutting grooves 19 of the aforementioned depth in each division line 6 of the package substrate 1. Note that the depth is shallower than the distance from the surface 9 of the package substrate 1 to the second frame portion 36. In addition, the thickness of the cutting edge of the first cutting blade 41 is equal to or greater than the width of the first frame portion 33.

[0038] In the cutting groove forming step 1001, the cutting device 40 cuts the first cutting blade 41 into the first frame portion 33, cutting and removing the entire first frame portion 33, and cuts the base end of the first electrode portion 34, exposing the cut surface 341 of the first electrode portion 34 cut by the first cutting blade 41 on the inner surface of the cutting groove 19. In the cutting groove forming step 1001, the cutting device 40 forms the cutting grooves 19 on all of the planned division lines 6. In this way, in the cutting groove forming step 1001, the cutting device 40 cuts the first frame portion 33 of the lead frame 31.

[0039] (Plating step) Fig. 13 is a cross-sectional view schematically showing the package substrate after the plating step of the package substrate processing method shown in Fig. 11. In plating step 1002, after performing cutting groove formation step 1001, a voltage is applied to the cut first electrode portion 34 via connection frame 32, and the exposed surface of first electrode portion 34 is coated with plating layer 16 by electrolytic plating.

[0040] In plating step 1002, the package substrate 1 after cutting groove formation step 1001 is immersed in an electrolytic solution with the first electrode portion 34, and a voltage is applied to the electrode and connection frame 32 for a predetermined time while supplying a substance (e.g., tin) to be plated on the first electrode portion 34 into the electrolytic solution, with an electrode (not shown) in the electrolytic solution as the anode and the first electrode portion 34 of the lead frame 31 as the cathode. In plating step 1002, as shown in FIG. 13, the exposed surface of the first electrode portion 34 is coated with a plating layer 16 by electrolytic plating. Thus, in the package substrate processing method according to embodiment 1, the connection frame 32 serves as an electrode when electrolytic plating is performed on the cut surface 341 of the first electrode portion 34 formed by cutting the first electrode portion 34 from the first frame portion 33.

[0041] (Split Step) Fig. 14 is a cross-sectional view schematically showing the dividing step of the processing method for the package substrate shown in Fig. 11. In dividing step 1003, after plating step 1002 is performed, second cutting blade 51, which is thinner than first cutting blade 41, is used to cut the center of cutting groove 19 in the width direction, thereby cutting connection frame 32 and molded resin 12 and dividing into individual package chips 2.

[0042] In the dividing step 1003, the cutting device 50 suction-holds the back surface 10 of the package substrate 1, i.e., the molding resin 12, on the holding surface of a chuck table (not shown). In the dividing step 1003, the cutting device 50 uses an imaging unit to capture an image of the mark 13 on the front surface 9 of the package substrate 1 held on the chuck table, and performs alignment to align the second cutting blade 51 with the cutting groove 19.

[0043] In the dividing step 1003, the cutting device 50 moves the chuck table and the second cutting blade 51 relatively along the cutting groove 19, and, as shown in FIG. 14 , causes the cutting edge of the second cutting blade 51 to cut into the center of the width of the cutting groove 19 until it reaches the relief groove in the holding surface of the chuck table, thereby cutting the center of the width of the cutting groove 19 formed along each of the division lines 6 of the package substrate 1. The thickness of the cutting edge of the second cutting blade 51 is thinner than the thickness of the cutting edge of the first cutting blade 41. The second cutting blade 51 does not come into contact with the plating layer 16 coated in the cutting groove 19, thereby preventing the plating layer 16 from being damaged.

[0044] In the dividing step 1003, the cutting device 50 uses the second cutting blade 51 to cut the package substrate 1 along the center of the width of the cutting grooves 19 formed on each dividing line 6, thereby dividing the package substrate 1 into individual package chips 2. Thus, the package substrate 1 is divided into package chips 2 by performing the cutting groove forming step 1001, the plating step 1002, and the dividing step 1003. As a result, as shown in FIG. 4 , the first electrode 34 of the lead frame 31 electrically connected to the device chip 8 is exposed on the front surface 9 and the second side surface 151 continuing from the front surface 9 of the step portion 15, and the cut surface 371 of the second electrode 37 of the connection frame 32, the end of which is connected to the first electrode 34, is exposed on the side surface 14 continuing from the step portion 15 to the back surface 10 of the package chip 2. While FIG. 4 shows three electrodes 34 and three electrodes 37 exposed on each side surface 151 and 14, five electrodes are exposed in the first embodiment.

[0045] 14, the first electrode portion 34 of the package chip 2 is covered with the plating layer 16, while the second electrode portion 37 of the connection frame 32 is not covered with the plating layer 16. In the package chip 2 divided into individual pieces in this manner, the cut surfaces 341 of the first electrode portion 34 are covered with the plating layer 16 like so-called wettable flanks. In the package chip 2 configured as described above, the device chip 8 mounted on the support portion 7 of the metal lead frame 31 is covered with the mold resin 12.

[0046] (Solder fixing step) Fig. 15 is a cross-sectional view schematically showing the soldering step of the processing method of the package substrate shown in Fig. 11. The soldering step 1004 is a step of placing the surface 9 of the package chip 2 facing the wiring board 20 on which it is to be mounted, and connecting the plated first electrode portions 34 of the package chip 2 to the electrodes 21 of the wiring board 20 with solder 22.

[0047] 15 , in the soldering step 1004, the surface 9 of the package chip 2 is placed on the wiring board 20, and solder 22 is supplied between the wiring board 20 and the plating layer 16 covering the first electrode portion 34, so that the first electrode portion 34 is fixed and connected to the electrode 21 by the solder 22. In the soldering step 1004, the package chip 2 fixed and connected to the wiring board 20 has the cut surfaces 341 of the first electrode portions 34 cut in the cutting groove forming step 1001 covered with the plating layer 16 by the plating process, so that the wettability of the solder 22 of the first electrode portions 34 is ensured.

[0048] As described above, the package substrate 1 according to the first embodiment includes the lead frame 31 and the connection frame 32, whose frames 3 overlap each other, the second electrode portion 37 of the connection frame 32 is connected to the first electrode portion 34 of the lead frame 31, and the second frame portion 36 of the connection frame 32 is overlapped with a gap on the first frame portion 33 of the lead frame 31. Therefore, even if the first frame portion 33 of the package substrate 1 is cut, the plating layer 16 can be formed on the cut surface 341 of the first electrode portion 34 by applying a voltage via the connection frame 32.

[0049] Therefore, the package substrate 1 has a connection frame 32 that allows plating to be applied to the cut surface 341 of the first electrode portion 34, i.e., the exposed surface of the electrode 11, like a so-called wettable flank, and allows the first electrode portion 34 to be fully cut (cut) rather than half-cut. This allows the first electrode portion 34 to be cut while maintaining the wettability of the side surface (cut surface) of the electrode 11. As a result, the package substrate 1 has the advantage of being able to relax the precision of the cutting depth. Furthermore, even when the first electrode portion 34 is cut, the package substrate 1 has the advantage of being able to form a plating layer 16 on the cut surface 341 of the first electrode portion 34, etc., thereby suppressing clogging of the first cutting blade 41 and suppressing the generation of burrs.

[0050] Furthermore, in the package substrate processing method according to the first embodiment, even if the first frame portion 33 of the package substrate 1 is cut in the cutting groove forming step 1001, a plating layer 16 is formed on the cut surfaces 341 of the first electrode portion 34 and the like by applying a voltage via the connection frame 32 in the plating processing step 1002. As a result, the package substrate processing method can cut the first electrode portion 34 while maintaining the wettability of the side surface (cut surface) of the electrode 11, thereby achieving the effect of relaxing the precision of the cutting depth. Furthermore, even if the first electrode portion 34 is cut, the package substrate processing method can form the plating layer 16 on the cut surfaces 341 of the first electrode portion 34 and the like, thereby achieving the effect of suppressing clogging of the first cutting blade 41 and suppressing the generation of burrs.

[0051] Furthermore, in the package chip 2 according to the first embodiment, the first electrode portion 34 of the lead frame electrically connected to the device chip 8 is exposed on the second side surface 151 of the step portion 15, and the cut surface 341 of the second electrode portion 37 of the connection frame 32, the end of which is connected to the first electrode portion 34, is exposed on the side surface 14, and the first electrode portion 34 is covered with a plating layer 16. For this reason, even if the first frame portion 33 of the package substrate 1 of the package chip 2 is cut, the plating layer 16 can be formed on the cut surface 341 of the first electrode portion 34, etc., by applying a voltage via the connection frame 32.

[0052] As a result, the package chip 2 can cut the first electrode portion 34 while maintaining the wettability of the first electrode portion 34, thereby achieving the effect of relaxing the precision of the cutting depth. Furthermore, even when the package chip 2 cuts the first electrode portion 34, the plating layer 16 can be formed on the cut surface 341 of the first electrode portion 34, etc., achieving the effect of suppressing clogging of the first cutting blade 41 and suppressing the generation of burrs.

[0053] It should be noted that the present invention is not limited to the above-described embodiment 1. In other words, the present invention can be implemented in various modifications without departing from the gist of the present invention. [Explanation of symbols]

[0054] 1 Package substrate 2 Packaged Chips 3 frames 6 Planned division line 7 Support part 8 Device Chips 9 surface 10 Back side 12 Molding resin 14 Side 15 Step 16 plating layer 19 Cutting groove 20 Wiring board 21 electrodes 22 Solder 31 Lead frame 32 connection frames 33 First Frame 34 1st electrode part 36 Second frame section 37 Second electrode part 41 First cutting blade 51 Second cutting blade 151 Second side (surface continuing from the surface) 341 Cut surface (cross section) 371 Cut plane (cross section) 1001 Cutting groove forming step 1002 plating steps 1003 division steps 1004 Solder Fixing Step

Claims

1. A package substrate in which a device chip mounted on a metal frame is covered with a molding resin, the device chip; a metal lead frame having a lattice-shaped first frame portion along a planned division line that defines a support portion on which the device chip is to be placed, and a plurality of first electrode portions extending on both sides from the first frame portion; a connection frame disposed on the side of the lead frame where the device chip is disposed, the connection frame having a lattice-shaped second frame portion along the planned division line and a plurality of second electrode portions extending from the second frame portion toward both sides; a wire connecting the first electrode portion and the device chip; the device chip is electrically connected to the first electrode portion of the lead frame, and a molding resin covers the connection frame and the wires; The tip of the second electrode portion is formed in a convex shape toward the first electrode portion relative to the second frame portion and is connected to the first electrode portion of the lead frame, and the package substrate forms an electrode when an electrolytic plating process is performed on the cross section of the first electrode portion formed by cutting the first electrode portion from the first frame portion.

2. 2. The method for processing a package substrate according to claim 1, a cutting groove forming step of cutting a first cutting blade into the first frame portion of the lead frame along the planned division line on the surface side of the package substrate where the lead frame is exposed, to form a cutting groove of a depth that does not reach the connection frame covered with the mold resin, and exposing a cut surface of the first electrode portion cut by cutting the first frame portion in the cutting groove; a plating step of applying a voltage to the cut first electrode portion via the connection frame after the cutting groove forming step, and coating the exposed surface of the first electrode portion with a plating layer by electrolytic plating; a dividing step of cutting the center of the cutting groove with a second cutting blade thinner than the first cutting blade to cut the connection frame and the molding resin and divide the package into individual package chips after the plating step; a solder fixing step of placing the front surface of the package chip facing a mounting wiring board and connecting the plated first electrode portion of the package chip and an electrode of the wiring board with solder, The method for processing a package substrate includes plating the cut surfaces of the electrodes cut in the cutting groove forming step to ensure solder wettability.

3. A method for manufacturing a package substrate according to claim 1, comprising: A method for manufacturing a package substrate, in which the connection frame is placed on the side of the lead frame where the device chip is arranged, the device chip is placed on the support portion, the first electrode portion is connected to the device chip by the wire, and the device chip, the wire, and the connection frame are covered with the molding resin.

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