Semiconductor device and manufacturing method thereof

Abstract

To improve adhesion between a semiconductor substrate and a backside electrode covering its backside.SOLUTION: A method for manufacturing a semiconductor device is used, comprising the steps of: preparing a semiconductor substrate SB having a main surface and a back surface opposite the main surface and having semiconductor elements and including n-type silicon on the back surface; forming a first metal layer including nickel and a first metal having a smaller thermal diffusion coefficient than that of nickel on the back surface of the semiconductor substrate SB: forming a NiSiV layer NSV in contact with the back surface of the semiconductor substrate by reacting the silicon contained in the semiconductor substrate SB with the nickel contained in the first metal layer through heat treatment on the semiconductor substrate SB; and forming a Ti layer M2 containing a second metal on the NiSiV layer NSV.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having an electrode on the back surface of a semiconductor substrate and a technique that is effective when applied to a method for manufacturing the same. [Background technology]

[0002] As a configuration of the backside electrode of a power device (power module) that requires high breakdown voltage, Patent Document 1 (JP 2012-251214 A) describes a structure in which a nickel silicide layer, a titanium layer, a nickel layer, and a gold layer are laminated in this order on the backside of a semiconductor substrate. The backside of the semiconductor substrate that is in contact with the electrode is made of n-type silicon. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-251214 Summary of the Invention [Problem to be solved by the invention]

[0004] As power devices become smaller (higher power density) and their junction temperatures increase, temperature changes during power cycles or temperature cycles also become larger, which increases the mechanical stress on each electrode junction due to film stress. There is a continuous demand for improved adhesion of the back electrode to prevent inter-electrode delamination.

[0005] As in Patent Document 1, when a titanium layer is formed in contact with a nickel silicide layer as part of an electrode and heat treatment to form titanium silicide is not performed, there is a problem that adhesion between the nickel silicide layer and the titanium film is low.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A brief summary of a representative embodiment of the present invention will be given below.

[0008] One embodiment of a method for manufacturing a semiconductor device includes the steps of: (a) preparing a semiconductor substrate having a main surface and a back surface opposite the main surface, the semiconductor substrate including a semiconductor element, the back surface including n-type silicon; (b) after step (a), forming a first metal layer on the back surface of the semiconductor substrate, the first metal layer including nickel and a first metal having a thermal diffusion coefficient smaller than that of nickel; (c) performing a heat treatment on the semiconductor substrate to react the silicon contained in the semiconductor substrate with the nickel contained in the first metal layer, thereby forming a silicide layer in contact with the back surface of the semiconductor substrate; and (d) forming a second metal layer including a second metal on the silicide layer.

[0009] In one embodiment, a semiconductor device includes a semiconductor substrate, a silicide layer formed on the back surface of the semiconductor substrate and containing nickel and a first metal, and a metal layer formed on the silicide layer and containing a second metal, wherein the silicide layer has a first surface located on the semiconductor substrate side and a second surface located on the metal layer side, nickel is contained in the first surface and the second surface of the silicide layer, the first metal is contained in the second surface of the silicide layer, and in the silicide layer, the proportion of the first metal in the second surface is greater than the proportion of the first metal in the first surface. [Effects of the Invention]

[0010] According to one embodiment, the performance of the semiconductor device can be improved, particularly the adhesion between the semiconductor substrate and the back electrode can be improved. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a flow chart showing a method for manufacturing a semiconductor device according to a first embodiment. [Figure 2] 1A to 1C are cross-sectional views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 3] 3 is a cross-sectional view showing the method of manufacturing the semiconductor device subsequent to FIG. 2. [Figure 4] 4 is a cross-sectional view showing the method of manufacturing the semiconductor device subsequent to FIG. 3. [Figure 5] 5 is a cross-sectional view showing the method of manufacturing the semiconductor device subsequent to FIG. 4. [Figure 6] 6 is a cross-sectional view showing the method of manufacturing the semiconductor device subsequent to FIG. 5. [Figure 7] 7A to 7C are cross-sectional views showing the method of manufacturing the semiconductor device subsequent to FIG. 6. [Figure 8] 4 is a graph showing the composition in the vicinity of the back electrode of the semiconductor device according to the first embodiment. [Figure 9] 9 is a graph showing an enlarged view of a part of FIG. 8. [Figure 10] 9 is a graph showing an enlarged view of a part of FIG. 8. [Figure 11] 9 is a graph showing an enlarged view of a part of FIG. 8. [Figure 12] 10 is a flow chart showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 13] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 14] 14 is a cross-sectional view showing the method of manufacturing the semiconductor device subsequent to FIG. 13. [Figure 15] 15 is a cross-sectional view showing the method of manufacturing the semiconductor device subsequent to FIG. 14. [Figure 16] 16 is a cross-sectional view showing the method of manufacturing the semiconductor device subsequent to FIG. 15. [Figure 17] 17A to 17C are cross-sectional views showing the manufacturing method of the semiconductor device subsequent to FIG. 16. [Figure 18] FIG. 10 is a cross-sectional view showing a semiconductor device as a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0012] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the mentioned number, and may be more or less than the mentioned number, unless otherwise specified or when it is clearly limited in principle to a specific number.

[0013] Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0014] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0015] Also, the " - " and " + " is a symbol that indicates the relative impurity concentration of n-type or p-type conductivity. For example, "n - "," "n," "n + The impurity concentration of n-type impurities increases in the order of "p - ", "p", "p + ", "p ++ The impurity concentration of p-type impurities increases in the order of

[0016] <Details of areas for improvement> The details of this room for improvement will be explained below with reference to the drawings.

[0017] As explained in the section on the problem to be solved by the invention, power devices are subject to large temperature changes during power cycles or temperature cycles, which can lead to the problem of electrode separation due to mechanical stress, and there is a need to improve the adhesion of the back electrode.

[0018] 18 shows a cross-sectional view of a semiconductor device of a comparative example. The semiconductor device shown in FIG. 18 is a power device equipped with a diode, and has a semiconductor substrate SB mainly made of single crystal Si (silicon). The semiconductor substrate SB has n - a p-type anode layer AL formed on the main surface and an n-type semiconductor region NL formed on the rear surface; + The cathode layer CL has a p-type anode layer AL and an n-type anode layer CL. - Semiconductor regions NL and n + A diode is formed by a pn junction with an n-type layer made of a cathode layer CL. An anode electrode AE ​​made of a metal layer is connected to the top surface of the anode layer AL, and a back electrode CEA made mainly of a metal layer is connected to the bottom surface of the cathode layer CL via a NiSi (nickel silicide) layer NS.

[0019] The back electrode CEA is composed of a Ti (titanium) layer M2a, a Ni (nickel) layer M3a, and an Au (gold) layer M4a, which are formed in this order from the semiconductor substrate SB side. The NiSi layer is a silicide layer formed by heat treatment after depositing a metal layer on the back surface of the semiconductor substrate SB by sputtering using a sputtering target made of high-purity Ni (nickel, pure-Ni). That is, a junction between a semiconductor and a silicide is formed on the first face F1, which is the junction (interface) between the semiconductor substrate SB and the NiSi layer NS. On the other hand, when the NiSi layer NS and the Ti layer M2a are bonded, the heat treatment required for forming the silicide (TiSi) is not performed. That is, a junction is formed between Ti, Ni, and Si on the second face F2, which is the junction (interface) between the NiSi layer NS and the Ti layer M2a.

[0020] Here, the composition of the second surface F2 contains Si, and because the Si content is relatively high, there is room for improvement in the poor adhesion between the NiSi layer NS, which contains Ni, and the Ti layer M2a, which is mainly composed of Ti. If the adhesion between the NiSi layer NS and the Ti layer M2a is poor, the back electrode CEA will be easily peeled off from the semiconductor substrate SB during dicing, chip pick-up, tape peeling, etc.

[0021] Therefore, in the following embodiment, a device is implemented to solve the above-mentioned room for improvement. The following describes the technical concept of the embodiment that implements this device. That is, the following describes how peeling of the back electrode from the semiconductor substrate is prevented by reducing the proportion of Si on the second surface F2 and increasing the proportion of metal.

[0022] (Embodiment 1) <Method of manufacturing a semiconductor device> The semiconductor device of this embodiment will be described below with reference to Figs. 1 to 7. Fig. 1 is a flow diagram showing a method for manufacturing a semiconductor device of this embodiment. Figs. 2 to 7 are cross-sectional views showing the method for manufacturing a semiconductor device of this embodiment. Here, the method for manufacturing a semiconductor device of this embodiment will be described with reference to Figs. 2 to 7 while referring to the flow diagram of Fig. 1.

[0023] First, as shown in Figure 2, a semiconductor substrate (semiconductor wafer) SB is prepared after the surface process. The semiconductor substrate SB has a main surface (first main surface, upper surface) and a back surface (second main surface, lower surface) opposite to the main surface. The semiconductor substrate SB is - The semiconductor device has a p-type semiconductor region NL and an anode layer AL, which is a p-type semiconductor layer formed on the main surface. An anode electrode AE ​​made of a metal layer is connected to the upper surface of the anode layer AL. The anode electrode AE ​​is made of, for example, AlSi (aluminum silicon), Al (aluminum), AlSiCu (aluminum silicon copper), or AlCu (aluminum copper). The anode layer AL and the anode electrode AE ​​are formed by a well-known manufacturing method.

[0024] In subsequent steps, the semiconductor wafer is turned upside down, with the main surface facing downward and the back surface facing upward, and the manufacturing process is carried out with this in mind. However, cross-sectional views used to explain the manufacturing process are not shown upside down. For this reason, for example, when describing the formation of a metal layer or the like on the underside of the back surface of the semiconductor substrate SB in the figures, the phrase "forming a metal layer on the back surface" may be used. This means that a metal layer that contacts the exposed back surface of the semiconductor substrate SB is formed so as to cover the back surface.

[0025] Next, as shown in FIG. 3, a BG (Back Grind) tape is attached to the main surface of the semiconductor wafer, and then the back surface of the semiconductor substrate SB is ground to thin the wafer (step S1). The back grinding thickness is set according to the withstand voltage class, application, and design of the semiconductor device. For example, for high-voltage products with a withstand voltage of about 600 to 1800 V, the thickness of the semiconductor substrate SB is preferably in the range of 40 to 220 μm. After this grinding process, the BG tape on the main surface of the semiconductor wafer is peeled off.

[0026] Next, the fractured layer resulting from the backside grinding in step S1 is etched by spin etching using mixed acid (step S2). The fractured layer is mainly composed of Si. The amount of etching of the backside of the semiconductor substrate SB by spin etching is, for example, in the range of 2 to 20 μm, and specifically, preferably around 10 μm. As a result, the structure shown in FIG. 3 is obtained.

[0027] Next, as shown in FIG. 4, impurities are introduced into the rear surface of the semiconductor substrate SB by ion implantation, thereby forming n + A cathode layer CL, which is a n-type semiconductor layer, is formed (step S3). Possible ion species for ion implantation are P (phosphorus), As (arsenic), or Sb (antimony). In order to form an ohmic junction between the back electrode formed in a later step and the cathode layer CL, the n-type impurity concentration of the Si n-type layer (cathode layer CL) in contact with the back electrode is 1×10 18 ~1×10 21 / cm 3 Therefore, the dose of ion implantation must be within the range of 1×10 14 ~5×10 15 / cm2 The range is 1×10 15 / cm 2 The degree is preferable.

[0028] Next, the semiconductor substrate SB is subjected to a heat treatment (activation annealing) (step S4). From the viewpoint of suppressing the thermal influence on the surface structure of the anode layer AL and the anode electrode AE, it is preferable to activate the impurities in the injection layer (cathode layer CL) by locally heating the rear surface by laser annealing. - Semiconductor regions NL and n - Type n + The pn junction between the n-type layer and the cathode layer CL forms a diode, which is the semiconductor element. That is, the semiconductor element is formed on the semiconductor substrate SB. This results in the structure shown in FIG.

[0029] Next, as shown in FIG. 5, spin etching is performed using diluted hydrofluoric acid to remove the native oxide film (1 to 2 nm thick) covering the rear surface of the semiconductor substrate SB (step S5).

[0030] Next, the semiconductor substrate SB is placed in a sputtering apparatus, and sputtering is performed using a Ni sputtering target containing V (vanadium) to form a NiV layer (metal layer) M1 covering the back surface of the semiconductor substrate SB (step S6). If the NiV layer M1 is too thick, the semiconductor wafer will warp, and if it is too thin, the reaction amount during silicide formation in the subsequent step S7 will be insufficient. Therefore, the thickness of the NiV layer M1 is considered to be in the range of approximately 15 to 100 nm, and specifically, approximately 50 nm is preferable. Furthermore, the V content of the Ni sputtering target is approximately 2 to 10 wt%, and specifically, approximately 7 wt% is preferable.

[0031] As Ni sputtering targets become thicker, their magnetic properties become stronger, causing problems with film formation during sputtering, making it difficult to make them thicker than a certain thickness. However, adding V to a Ni sputtering target reduces the magnetic effects of thickening the Ni sputtering target, allowing for thicker Ni sputtering targets and improving the productivity of semiconductor devices. This results in the structure shown in Figure 5.

[0032] Next, as shown in FIG. 6, the semiconductor substrate SB is placed in a furnace, and furnace annealing is performed to form a NiSiV layer NSV (step S7). That is, by performing heat treatment, Si on the back surface of the semiconductor substrate SB reacts with the NiV layer M1 to form a silicide layer, the NiSiV layer NSV. The NiSiV layer NSV is a nickel silicide layer containing V. The annealing conditions here are 350°C and a range of 1 to 30 minutes, with the annealing time preferably being approximately 10 minutes. If the annealing time is too long, the composition of the NiSiV layer NSV may become silicon-rich, and warping of the semiconductor substrate SB may increase. The annealing atmosphere may be N2 (nitrogen) only, but may also contain H2 (hydrogen). Regarding silicide formation, localized back surface heating using a lamp heating device or a laser annealing device in a sputtering device may be performed instead of furnace annealing. When the thickness of the NiV layer M1 is 50 nm and the annealing conditions in step S7 are 350° C. and 10 minutes, the thickness of the NiSiV layer NSV is about 200 nm, thereby obtaining the structure shown in FIG.

[0033] Next, as shown in FIG. 7, a back electrode CE is formed by depositing electrode films, such as a Ti (titanium) layer M2, a NiV (nickel vanadium) layer M3, and an Au (gold) layer M4, in that order on the NiSiV layer NSV by sputtering or the like (step S8). Here, after the Ti layer M2 is formed on the NiSiV layer NSV, the heat treatment required for silicide (TiSi) formation is not performed. The back electrode CE is composed of the Ti layer M2, the NiV layer M3, and the Au layer M4, which are formed in that order from the semiconductor substrate SB side. Thus, the back electrode CE has a stacked structure composed of multiple metal layers (the Ti layer M2, the NiV layer M3, and the Au layer M4).

[0034] The NiV layer M3 may be a Ni (nickel) layer. The Au layer M4 may be an Ag (silver) layer. The thickness of the Au layer M4 may be, for example, in the range of 50 to 200 nm, but in the case of an Ag layer, the thickness must be in the range of 500 to 1500 nm, and the specific thickness of the Ag layer is preferably about 1000 nm. This completes the back surface process, and the semiconductor device of this embodiment is nearly completed.

[0035] <Effects of this embodiment> Figure 8 shows a graph of the composition of the components of the semiconductor device of this embodiment, extending from the bottom edge of the back electrode to the semiconductor substrate near the back electrode. The graph in Figure 8 represents the composition ratio detected by AES (Auger Electron Spectroscopy). AES is a method for analyzing the elements that make up the sample surface, their composition, and their chemical bonding state by irradiating the sample surface with a finely focused electron beam and measuring the kinetic energy of the Auger electrons emitted from the sample surface. Here, the element composition is graphed from the spectral information obtained by alternately repeating sputtering and measurement. The sputtering rate is 10 nm / min (SiO2 equivalent).

[0036] The vertical axis of the graph shown in Figure 8 represents the element ratio (concentration of each element), and the horizontal axis represents the sputtering time. The longer the sputtering time, the deeper the composition can be detected from the sample surface. Here, AES measurements were performed from the back side of the semiconductor device shown in Figure 7, i.e., from the underside of the back electrode CE. Therefore, the horizontal axis of the graph represents the compositions of the Au layer M4, NiV layer M3, Ti layer M2, NiSiV layer NSV, and semiconductor substrate SB, in that order from left to right.

[0037] Here, the graph shows only five elements, namely metals (Ni, V, Ti, Au) and Si, as the results of the AES analysis, but in reality, C (carbon), O (oxygen), and P (phosphorus) were also detected, and the element ratios on the vertical axis are calculated from eight elements (all elements detected), not five elements.

[0038] To make the details of the graph shown in FIG. 8 easier to understand, FIG. 9 shows a graph in the range 1A where the time on the horizontal axis is 90 to 120 minutes, FIG. 10 shows a graph in the range 1B where the time on the horizontal axis is 60 to 90 minutes, and FIG. 11 shows a graph in the range 1C where the time on the horizontal axis is 0 to 30 minutes. FIG. 9 is a graph showing the ratio (composition) near the interface (second surface F2) between the Ti layer M2 and the NiSiV layer NSV and the interface (first surface F1) between the NiSiV layer NSV and the semiconductor substrate SB. FIG. 10 is a graph showing the composition near the interface between the NiV layer M3 and the Ti layer M2. FIG. 11 is a graph showing the composition near the interface between the Au layer M4 and the NiV layer M3.

[0039] In Figure 9, the percentage of Si is plotted with black circles, the percentage of Ni is plotted with white triangles, the percentage of V is plotted with cross marks, and the percentage of Ti is plotted with white squares. In Figure 10, the percentage of Ni is plotted with white triangles, the percentage of V is plotted with cross marks, and the percentage of Ti is plotted with white squares. In Figure 11, the percentage of Ni is plotted with white triangles, the percentage of V is plotted with cross marks, and the percentage of Au is plotted with white circles.

[0040] One of the main features of this embodiment is that V segregates at and near the second surface F2, which is the interface between the Ti layer M2 and the NiSiV layer NSV, as indicated by the arrows in FIG. 9. In FIG. 7, the region VR between the two dashed lines is shown, and V segregates in this region VR, which includes the second surface F2. As a result, the proportion of metal (concentration, composition ratio) at the second surface F2 of the NiSiV layer NSV is relatively higher and the proportion of Si (concentration, composition ratio) is lower than when the metals (Ni and V) are uniformly dispersed in the NiSiV layer NSV and when V is not present in the NiSiV layer NSV. This improves adhesion between the Ti layer M2 and the NiSiV layer NSV, which are metal layers.

[0041] In this embodiment, V is contained in the Ni sputtering target used in the sputtering step (step S6) for forming the NiV layer M1, which is a reactive metal layer formed to form the silicide layer (NiSiV layer NSV). This causes V to segregate on the second surface F2.

[0042] Here, the diffusion coefficient (in silicon) of V (interstitial vanadium) is D = 10 -9 ~10 -10 cm 2 s -1 (800℃). In contrast, the diffusion coefficient of Ni (in silicon) D is D = ~10 -5 cm 2 s -1 (800°C). Therefore, the diffusion coefficient of V is much smaller than that of Ni. Because the difference in diffusion coefficients between Ni and V is large, Ni diffuses during the formation of the NiSiV layer NSV, but the diffusion distance of V is very short, resulting in V segregating on the second surface F2.

[0043] The metal to be segregated is not limited to V, and may be a metal having a smaller diffusion coefficient than Ni. Metals having a smaller diffusion coefficient than Ni, like V, include Mn (manganese), Fe (iron), Cr (chromium), Ru (ruthenium), Ti, Mo (molybdenum), W (tungsten), and Ta (tantalum).

[0044] As described above, in this embodiment, V is segregated on the second surface F2, which is the interface between the Ti layer M2 and the NiSiV layer NSV shown in FIG. 7, thereby improving the adhesion between the rear surface of the semiconductor substrate SB and the rear surface electrode CE. In other words, the performance of the semiconductor device can be improved. In this way, this embodiment can eliminate the room for improvement.

[0045] 9, almost no V is dispersed on the first surface F1, which is the interface between the NiSiV layer NSV and the semiconductor substrate SB. In other words, the proportion (concentration, composition ratio) of V on the first surface F1 is smaller than the proportion (concentration, composition ratio) of V on the second surface F2. This allows for improved adhesion on the second surface F2 without reducing the adhesion between the NiSiV layer NSV and the semiconductor substrate SB on the first surface F1.

[0046] 10 and 11, V is uniformly diffused within the NiV layer M3, which allows the NiV layer M3 to achieve high adhesion to both the Ti layer M2, which is a metal layer, and the Au layer M4, which is also a metal layer.

[0047] (Embodiment 2) In the above embodiment, a semiconductor device including a diode has been described, but the semiconductor element formed on the semiconductor substrate is not limited to a diode as long as it has an n-type semiconductor layer on the back surface of the semiconductor substrate.

[0048] In the following, a semiconductor device having a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor, MOS type field effect transistor) will be described as an example of the semiconductor device of this embodiment. A power MOSFET is a semiconductor device that can handle power of several watts or more. The semiconductor device of the present application has a trench-gate MOSFET, which is a type of power MOSFET. A trench-gate MOSFET has a gate electrode made of polysilicon or the like in a trench (a relatively long and narrow groove) formed in the upper surface (first main surface) of a semiconductor substrate, and a channel is formed in the thickness direction of the semiconductor substrate. In this case, the main surface side of the semiconductor substrate usually serves as the source, and the back surface side serves as the drain.

[0049] The semiconductor device of this embodiment will be described below with reference to Figs. 12 to 17. Fig. 12 is a flow chart showing a method for manufacturing a semiconductor device of this embodiment. Figs. 13 to 17 are cross-sectional views showing the method for manufacturing a semiconductor device of this embodiment. Here, the method for manufacturing a semiconductor device of this embodiment will be described with reference to Figs. 13 to 17 while referring to the flow chart of Fig. 12.

[0050] First, a semiconductor substrate (semiconductor wafer) SB that has undergone a surface process is prepared, as shown in Fig. 13. The semiconductor substrate SB has a main surface and a back surface opposite to the main surface. A trench gate MOSFET is formed on the semiconductor substrate SB.

[0051] 13, the semiconductor substrate SB is a laminated semiconductor substrate including a substrate SB1 and an epitaxial layer (semiconductor layer) formed on the substrate SB1 by epitaxial growth. - The mold layer ND is formed, and n - The type layer ND constitutes the drift layer of the MOSFET.

[0052] n - The semiconductor substrate SB on the main surface side of the dopant layer ND has a pair of p + A mold layer PB is formed, and a pair of p +The semiconductor substrate SB directly above each of the mold layers PB has p ++ A mold layer PS is formed. + A pair of p-type layers PC are formed in the semiconductor substrate SB between the p-type layers PB. + The p-type layer PB and the p-type layer PC form the body region of the MOSFET. ++ The mold layer PS is p + It is a high-concentration semiconductor layer for reducing the contact resistance between the source electrode SE and the dopant layer PB. ++ The mold layer PS is in ohmic contact with the source electrode SE.

[0053] The semiconductor substrate SB directly above each of the pair of p-type layers PC has n + A mold layer NE is formed. + The n-type layer NE forms the source region of the MOSFET. + A trench TR is formed between each of the p-type layers NE and between each of the pair of p-type layers PC. + From the height of the upper surface of the mold layer NE (the main surface of the semiconductor substrate SB), n - The trench TR reaches partway to the depth of the mold layer ND. A gate electrode GE is formed inside the trench TR with a gate insulating film GI interposed therebetween.

[0054] The gate insulating film GI is made of, for example, SiO2 (silicon oxide), and the gate electrode GE is made of, for example, polycrystalline Si. The gate electrode GE is formed by the gate insulating film GI. + p-type layer NE, p-type layer PC and n - The epitaxial layer is insulated from the n-type layer ND. - Type layer ND, p + type layer PB, p type layer PC, p ++ Mold layer PS and n + It is a semiconductor layer including a mold layer NE.

[0055] The top surface of the gate electrode GE and + An insulating film IF is formed to cover the upper surface of the mold layer NE. Furthermore, p ++ Type layer PS, n +The source electrode SE is formed via a barrier metal film BM so as to cover the mold layer NE and the insulating film IF. The insulating film IF is made of, for example, silicon oxide, the barrier metal film BM is made of, for example, TiW (titanium-tungsten), and the source electrode SE is made of, for example, AlSi, Al, AlSiCu, or AlCu. The barrier metal film BM has a p ++ The upper surface of the mold layer PS and n + The side of the mold layer NE is in contact with the mold layer NE. ++ Mold layer PS and n + The mold layer NE is electrically connected to the source electrode SE.

[0056] The substrate SB1 constituting the rear surface of the semiconductor substrate SB is + The trench gate MOSFET of this embodiment includes at least a gate electrode GE, a source region n + The trench gate MOSFET has a p-type layer NE, a substrate SB1 which is a drain region, and a p-type layer PC which is a body region. The trench gate MOSFET is formed by a well-known manufacturing method.

[0057] In subsequent steps, the manufacturing process is performed with the semiconductor wafer turned upside down. However, the cross-sectional views used to explain the manufacturing process are shown without being turned upside down. For this reason, for example, when explaining the formation of a metal layer on the underside of the back surface of the semiconductor substrate SB in the figures, it is sometimes expressed as "forming a metal layer on the back surface."

[0058] Next, as shown in FIG. 14, a BG tape is attached to the main surface side of the semiconductor wafer, and then the back surface of the semiconductor substrate SB is ground to thin the wafer (step S9). The back surface grinding thickness is set according to the application and design of the semiconductor device (on-resistance, wafer warpage, etc.). Here, only the substrate SB1 is ground, and the epitaxial layer is not ground. Therefore, the grinding thickness is set to an appropriate thickness taking into consideration the on-resistance or wafer warpage, rather than the withstand voltage. The thickness of the substrate SB1 after grinding is, for example, about 50 to 300 μm. After this grinding process, the BG tape on the main surface side of the semiconductor wafer is peeled off.

[0059] Next, the fractured layer resulting from the backside grinding in step S9 is etched by spin etching using mixed acid (step S10). The fractured layer is mainly composed of Si. The amount of etching of the backside of the semiconductor substrate SB by spin etching is, for example, in the range of 2 to 20 μm, and specifically, preferably around 10 μm. As a result, the structure shown in FIG. 14 is obtained.

[0060] Next, as shown in FIG. 15, spin etching is performed using diluted hydrofluoric acid to remove the native oxide film (1 to 2 nm thick) covering the rear surface of the semiconductor substrate SB (step S11).

[0061] Next, the semiconductor substrate SB is placed in a sputtering apparatus, and sputtering is performed using a Ni sputtering target containing V (vanadium) to form a NiV layer (metal layer) M1 covering the back surface of the semiconductor substrate SB (step S12). If the NiV layer M1 is too thick, the semiconductor wafer will warp, and if it is too thin, the reaction amount during silicide formation in the subsequent step S13 will be insufficient. Therefore, the thickness of the NiV layer M1 is considered to be in the range of approximately 15 to 100 nm, and specifically, approximately 50 nm is preferable. Furthermore, the V content of the Ni sputtering target is approximately 2 to 10 wt%, and specifically, approximately 7 wt% is preferable. This results in the structure shown in FIG. 15.

[0062] Next, as shown in FIG. 16, the semiconductor substrate SB is placed in a furnace, and furnace annealing is performed to form a NiSiV layer NSV (step S13). That is, by performing heat treatment, Si on the back surface of the semiconductor substrate SB reacts with the NiV layer M1 to form a silicide layer, the NiSiV layer NSV. The NiSiV layer NSV is a nickel silicide layer containing V. The annealing conditions here are 350°C and a range of 1 to 30 minutes, with the annealing time preferably being approximately 10 minutes. If the annealing time is too long, the composition of the NiSiV layer NSV may become silicon-rich, and warping of the semiconductor substrate SB may increase. The annealing atmosphere may consist of only N2, but may also contain H2. Regarding silicide formation, localized back surface heating using lamp heating or a laser annealing device in a sputtering device may be performed instead of furnace annealing. When the thickness of the NiV layer M1 is 50 nm and the annealing conditions in step S13 are 350° C. and 10 minutes, the thickness of the NiSiV layer NSV is about 200 nm, thereby obtaining the structure shown in FIG.

[0063] Next, as shown in FIG. 17, a back electrode DE is formed by depositing electrode films, such as a Ti (titanium) layer M2, a NiV (nickel vanadium) layer M3, and an Au (gold) layer M4, in this order on the NiSiV layer NSV by sputtering or the like (step S14). After the Ti layer M2 is formed on the NiSiV layer NSV, the heat treatment required for silicide (TiSi) formation is not performed. The back electrode DE is composed of the Ti layer M2, the NiV layer M3, and the Au layer M4, formed in this order from the semiconductor substrate SB side. The NiV layer M3 may be a Ni (nickel) layer. The Au layer M4 may be an Ag (silver) layer. The thickness of the Au layer M4 may be, for example, in the range of 50 to 200 nm. However, the thickness of the Ag layer should be in the range of 500 to 1500 nm, and the Ag layer preferably has a thickness of approximately 1000 nm. This completes the back surface process, and the semiconductor device of this embodiment is essentially completed.

[0064] As in the present embodiment, even in a semiconductor device including a vertical MOSFET, by segregating V in the region VR including the second surface F2, which is the interface between the Ti layer M2 and the NiSiV layer NSV, the same effect as in the first embodiment can be obtained. That is, the adhesion between the back surface of the semiconductor substrate SB and the back surface electrode DE can be increased, and the performance of the semiconductor device can be improved.

[0065] The invention made by the present inventors has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0066] AE anode electrode AL anode layer CE, DE rear electrode CL cathode layer F1 front page F2 2nd side M1 NiV layer M2 Ti layer M3 NiV layer M4 Au layer NL Semiconductor Area NSV NiSiV layer SB semiconductor substrate

Claims

1. (a) preparing a semiconductor substrate having a main surface and a back surface opposite to the main surface, the semiconductor substrate including a semiconductor element, the back surface including n-type silicon; (b) after the step (a), forming a first metal layer containing nickel and vanadium, which has a thermal diffusion coefficient smaller than that of nickel, on the back surface of the semiconductor substrate; (c) performing a heat treatment on the semiconductor substrate to react silicon contained in the semiconductor substrate with nickel contained in the first metal layer, thereby forming a silicide layer in contact with the back surface of the semiconductor substrate; (d) forming a second metal layer comprising titanium on the silicide layer; (e) forming a third metal layer containing vanadium and nickel on the second metal layer; (f) forming a fourth metal layer comprising gold on the third metal layer; The method for manufacturing a semiconductor device comprising the steps of:

2. 2. The method of manufacturing a semiconductor device according to claim 1, In the step (b), the first metal layer is formed by a sputtering method using a Ni sputtering target containing vanadium.

3. 2. The method of manufacturing a semiconductor device according to claim 1, a proportion of vanadium in a second surface, which is an interface between the second metal layer and the silicide layer, being greater than a proportion of vanadium in a first surface, which is an interface between the silicide layer and the semiconductor substrate;

4. In the method for manufacturing a semiconductor device according to claim 3, The method for manufacturing a semiconductor device, wherein vanadium is uniformly diffused within the third metal layer.

5. a semiconductor substrate; a silicide layer containing nickel and vanadium formed on a rear surface of the semiconductor substrate; a second metal layer formed on the silicide layer and including titanium; a third metal layer formed on the second metal layer and including vanadium and nickel; a fourth metal layer formed on the third metal layer and including gold; and the silicide layer has a first surface located on the semiconductor substrate side and a second surface located on the second metal layer side; nickel is contained within the first surface and the second surface of the silicide layer; Vanadium is contained within the second surface of the silicide layer; In the silicide layer, the proportion of vanadium on the second surface is greater than the proportion of vanadium on the first surface.

6. The semiconductor device according to claim 5, The vanadium is uniformly diffused within the third metal layer.

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