Power-on reset circuit

Abstract

In the present invention, a voltage dividing circuit (10) outputs a divided voltage (Vdiv) divided from a power source voltage (AVDD) to a first node (N1). A voltage rate detection circuit (30) detects the voltage change rate of the power source voltage (AVDD) at the time the power source voltage (AVDD) starts. A voltage determination circuit (20) generates an output signal (VPOR) that represents the results of comparison of the voltage of the first node (N1) and a predetermined threshold value voltage. The voltage dividing circuit (10) is configured so that, with the voltage division ratio kept constant, the impedance between power source wiring (PL) and reference voltage wiring (NL) is set so as to vary in accordance with the voltage change rate detected by the voltage rate detection circuit (30). The impedance of the voltage dividing circuit (10) is set so as to become lower as the voltage change rate becomes higher.

Description

[Technical Field]

[0001] The present disclosure relates to a power-on reset circuit. [Background technology]

[0002] When the supply of power supply voltage to a semiconductor device begins, if the semiconductor device starts operating at a stage where the power supply voltage is not at a sufficient level, specifically at a stage where the voltage is so low that the transistor cannot be turned on, there is a risk of malfunction.

[0003] For this reason, a power-on reset circuit has been used to detect whether the power supply voltage is above a certain level and generate a power-on reset (POR) signal. By starting operation after the POR signal is generated, the semiconductor device can prevent malfunction.

[0004] For example, Japanese Patent Laid-Open Publication No. 2019-186943 (Patent Document 1) describes a power-on reset circuit with low current consumption. In the power-on reset circuit described in Patent Document 1, a voltage detector 115 detects that the power supply voltage has risen above a threshold voltage level (VPOR_R) when the power supply voltage is started, and a POR signal is generated by holding the output signal of the voltage detector 115 in a POR latch 120. Then, after the power supply voltage has risen, power consumption can be reduced by turning off the voltage detector 115.

[0005] Furthermore, Patent Document 1 describes that, as shown in Figures 2A and 2B, adjustable resistors (R1, R2) are arranged in a voltage divider circuit of the power supply voltage (V_BUS), and the threshold voltage level (VPOR_R) of the power-on reset circuit is determined by changing the resistance value of the adjustable resistors. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2019-186943 Summary of the Invention [Problem to be solved by the invention]

[0007] In recent years, the application of energy harvesting, which converts natural energy such as sunlight into electric power, has expanded, but when using an energy harvesting power supply, it is expected that the voltage change rate and the length of the period during which voltage is supplied will vary each time the power supply voltage is started up depending on changes in the environment (for example, the luminous intensity on the solar cell). Therefore, even if the voltage change rate (increase rate) differs each time the power supply voltage is started up, the challenge is to generate a POR signal at the appropriate timing to accommodate various voltage change rates.

[0008] In particular, in applications where a POR signal is expected to be generated appropriately to operate a semiconductor device in response to a relatively short-term power supply, such as a wireless sensor network that operates when power is obtained through energy harvesting, it is necessary to generate a POR signal at the appropriate time without delay when the rate of change of the power supply voltage is large.

[0009] However, in the power-on reset circuit described in Patent Document 1, although it is possible to adapt the resistance values ​​of the adjustable resistors (R1, R2) according to the expected slew rate of the power supply voltage, it is not assumed that the slew rate of the power supply voltage will change each time the power supply voltage is started up.

[0010] Furthermore, in the power-on reset circuit of Patent Document 1, in order to reduce power consumption, a transistor connected in series with the voltage divider circuit and a latch 120 at the subsequent stage are required to turn off the voltage detector 115, which includes a voltage divider circuit. This raises concerns that the generation of the POR signal may be delayed when the power supply voltage rises at a high rate.

[0011] The present disclosure has been made to solve such problems, and the purpose of the present disclosure is to provide a power-on reset circuit that can reduce power consumption and operate appropriately even if the voltage change rate at power-on of the power supply voltage changes. [Means for solving the problem]

[0012] According to one aspect of the present disclosure, a power-on reset circuit includes a power supply line receiving a power supply voltage, a reference voltage line transmitting a reference voltage, a voltage divider circuit, a voltage rate detection circuit, and a voltage evaluation circuit. The voltage divider circuit is connected between the power supply line and the reference voltage and outputs a divided voltage of the power supply voltage on the power supply line to a first node. The voltage rate detection circuit detects a voltage change rate of the power supply voltage when the power supply voltage is started up. The voltage evaluation circuit generates an output signal indicating a comparison result between the voltage at the first node and a predetermined voltage. The voltage divider circuit is configured to variably set an impedance between the power supply line and the reference voltage while maintaining a constant voltage division ratio of the divided voltage to the power supply voltage in accordance with the voltage change rate detected by the voltage rate detection circuit. This impedance is set to decrease as the voltage change rate increases. [Effects of the Invention]

[0013] According to the present disclosure, by appropriately changing the impedance of the voltage divider circuit in accordance with the rate of voltage change at the time of startup of the power supply voltage, it is possible to provide a power-on reset circuit that can reduce power consumption and operate appropriately even if the rate of voltage change at the time of startup of the power supply voltage changes. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 10 is a circuit diagram illustrating a configuration of a power-on reset circuit according to a comparative example. [Figure 2] 10 is a conceptual operational waveform diagram of a power-on reset circuit when a power supply voltage is started up; [Figure 3] 1 is a block diagram illustrating a configuration of a power-on reset circuit according to a first embodiment. [Figure 4] 4 is a circuit diagram illustrating a configuration example of a voltage dividing circuit in FIG. 3. [Figure 5] 4 is a circuit diagram illustrating a configuration example of a voltage determination circuit in FIG. 3. [Figure 6] 1 is an equivalent circuit diagram of a power-on reset circuit according to a first embodiment. [Figure 7] FIG. 10 is a circuit diagram illustrating a configuration example of a voltage rate detection circuit according to a second embodiment. [Figure 8] 8 is a conceptual waveform diagram illustrating the operation of the voltage rate detection circuit shown in FIG. 7. [Figure 9] 8 is a diagram illustrating the operation of the voltage rate detection circuit shown in FIG. 7. [Figure 10] FIG. 10 is a circuit diagram illustrating a configuration example of a voltage evaluation circuit according to a third embodiment. [Figure 11] FIG. 10 is a circuit diagram illustrating a configuration example of a voltage rate detection circuit according to a third embodiment. [Figure 12] 3 is a conceptual operational waveform diagram at the time of starting up the power supply voltage of the power-on reset circuit according to the first embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be denoted by the same reference numerals, and their description will not be repeated in principle.

[0016] Embodiment 1 Before describing the power-on reset circuit according to the first embodiment, a comparative example will be described.

[0017] (Explanation of Comparative Example) FIG. 1 is a circuit diagram illustrating a configuration of a power-on reset circuit 5# according to a comparative example.

[0018] As shown in FIG. 1, power-on reset circuit 5# includes a voltage dividing circuit 10# and a voltage determining circuit 20#.

[0019] The voltage divider circuit 10# has resistors RH and RL connected in series between a power supply line PL that receives a power supply voltage AVDD and a reference voltage line NL that transmits a reference voltage VSS. Since the reference voltage VSS is typically ground (ground voltage), hereinafter the reference voltage VSS will be referred to as the ground voltage VSS, and the reference voltage line NL will also be referred to as the ground line NL.

[0020] The resistor element RH is connected between the power supply line PL and the node N1, and the resistor element RL is connected between the node N1 and the ground line NL. Therefore, a divided voltage Vdiv of the power supply voltage AVDD by the resistor elements RH and RL is generated at the node N1.

[0021] Hereinafter, in this specification, the electrical resistance value of each resistive element will be represented by the same symbol. Therefore, the following equation (1) holds between the divided voltage Vdiv and the power supply voltage AVDD. That is, the voltage division ratio of voltage divider circuit 10# is Kv=RL / (RL+RH) (Kv<1).

[0022] Vdiv=Kv·AVDD …(1) Voltage evaluation circuit 20# has a transistor 21, a current supply circuit 22, and a signal generation circuit 25 formed of an inverter.

[0023] The transistor 21 is an N-type field effect transistor, connected between the node N2 and the ground line NL, and has a gate (control electrode) connected to the node N1. The current supply circuit 22 has a resistive element RD connected between the power supply line PL and the node N2. The signal generation circuit 25 outputs an output signal VPOR having a logic level corresponding to the voltage Vdet of the node N2. The output signal VPOR corresponds to a so-called power-on reset signal (POR signal).

[0024] 1, where the signal generating circuit 25 is composed of an inverter, when the voltage Vdet drops to the ground voltage VSS in response to the transistor 21 being turned on, the output signal VPOR is set to a logic high level (hereinafter referred to as an "H level"). On the other hand, during the off period of the transistor 21, the node N2 is pulled up to the power supply voltage AVDD in response to the output signal VPOR being set to a logic low level (hereinafter referred to as an "L level"). With respect to the threshold voltage Vt1 of the transistor 21, when Vdiv≦Vt1, the transistor 21 is turned off, and when Vdiv>Vt1, the transistor 21 is turned on.

[0025] Therefore, when the power supply voltage AVDD rises from the ground voltage VSS during startup of a semiconductor device equipped with a power-on reset circuit, the output signal VPOR is at the L level (ground voltage VSS) while Vdiv≦Vt1, and is at the H level (power supply voltage AVDD) while Vdiv>Vt1. As a result, based on the output signal VPOR, it can be determined whether the power supply voltage AVDD is higher than the determination voltage Vpr, which corresponds to (Vt1 / Kv). By adjusting the voltage division ratio Kv so that the determination voltage Vpr corresponds to the lower limit voltage at which operation of the semiconductor device can be guaranteed, the output signal VPOR can be used as a POR signal that allows each circuit mounted on the semiconductor device to start operating.

[0026] FIG. 2 shows a conceptual operational waveform diagram of the power-on reset circuit when the power supply voltage is turned on.

[0027] 2 shows waveforms 101 to 103 of the power supply voltage AVDD at startup. The waveforms 101 to 103 have different voltage change rates (dAVDD / dt) at startup. For example, when the power supply voltage AVDD is supplied from the output of a solar cell, the voltage change rate differs depending on the amount of light received by the solar cell. Therefore, the timing at which the power supply voltage AVDD reaches the rated value Vst differs among the waveforms 101 to 103.

[0028] Similarly, the timing at which the power supply voltage AVDD reaches the above-mentioned determination voltage Vpr differs among the waveforms 101 to 103. In the waveform 101, the power supply voltage AVDD reaches the determination voltage Vpr at time t1. In the waveform 102, the power supply voltage AVDD reaches the determination voltage Vpr at time t2, which is later than time t1. In the waveform 103, the power supply voltage AVDD reaches the determination voltage Vpr at time t3, which is later than time t2.

[0029] In the power-on reset circuit 5#, at the timing when the power supply voltage AVDD reaches the determination voltage Vpr, the divided voltage Vdiv reaches the threshold voltage Vt1 of the transistor 21. Therefore, ideally, as shown by the solid lines in FIG. 2, the transistor 21 turns on at each of times t1 to t3, causing the output signal VPOR to change from the L level (ground voltage VSS) to the H level (power supply voltage AVDD).

[0030] 1, however, node N1 has parasitic capacitance Cp, such as the gate capacitance of transistor 21. Therefore, the on-timing of transistor 21 is delayed from times t1 to t3 to times t1x to t3x due to the charging time of parasitic capacitance Cp. As a result, output signal VPOR actually changes from L level to H level at times t1x to t3x, which are later than times t1 to t3, as shown by the dotted line.

[0031] In this case, it can be seen that the voltage error ΔVer between the power supply voltage AVDD and the determination voltage Vpr when the output signal VPOR actually changes to H level varies depending on the voltage change rate for each of the waveforms 101 to 103. Specifically, the voltage error ΔVer increases as the voltage change rate increases.

[0032] As a result, there is a concern that a delay will occur in the start of operation of the semiconductor device in response to the output signal VPOR. In particular, in energy harvesting power supply applications, it is expected that the supply of the power supply voltage AVDD will be sporadic and for short periods of time, and in such cases, a delay in the start of operation will be a concern, resulting in a deterioration in the performance of the semiconductor device.

[0033] Here, the delay time from time t1-t3 to time t1x-t3x is mainly determined by the RC time constant, which is the product of the R component of voltage divider circuit 10# and the parasitic capacitance Cp. Therefore, if the resistance value (RH+RL) of voltage divider circuit 10# is reduced, the charging current of parasitic capacitance Cp increases, and the delay time due to the RC time constant can be shortened. That is, power-on reset circuit 5# Operating speed can be increased.

[0034] However, when the resistance value (RH+RL) is reduced, the current steadily generated between the power supply wiring PL and the ground wiring NL in the voltage divider circuit 10# increases. The configuration of FIG. 1 can generate the output signal VPOR (POR signal) at high speed without using a transistor connected in series with the voltage divider circuit or a latch circuit in the subsequent stage, as in Patent Document 1. However, the steady current steadily occurs during the supply period of the power supply voltage AVDD. As a result, in the power-on reset circuit 5#, when the resistance value (RH+RL) in the voltage divider circuit 10# is reduced, the operating speed increases but the power consumption increases, whereas when the resistance value (RH+RL) is increased, the power consumption decreases but the operating speed decreases.

[0035] Furthermore, when the transistor 21 is turned on, the speed at which the voltage Vdet at the node N2 changes to the ground voltage VSS is affected by the magnitude of the current supplied by the current supply circuit 22. In the example of FIG. 2, the lower the resistance value RD, the larger the supply current becomes, and the faster the voltage Vdet can be changed to the ground voltage VSS. As a result, the timing at which the output signal VPOR changes to the H level can be advanced, and the delay time from time t1 to t3 to time t1x to t3x can be shortened. That is, the power-on reset circuit 5# Operating speed can be increased.

[0036] On the other hand, transistor 21 is maintained in the ON state while output signal VPOR is at H level. Therefore, due to resistor element RD and transistor 21 (ON state), a steady current is generated between power supply line PL and ground line NL in voltage evaluation circuit 20# as well. As a result, in power-on reset circuit 5# of FIG. 1, in voltage evaluation circuit 20#, lowering resistance value RD increases the operating speed but also increases power consumption, whereas increasing resistance value RD decreases power consumption but also decreases operating speed.

[0037] (Power-on reset circuit according to first embodiment) FIG. 3 is a block diagram illustrating the configuration of the power-on reset circuit 5 according to this embodiment.

[0038] 3, the power-on reset circuit 5 includes a voltage divider circuit 10, a voltage evaluation circuit 20, and a voltage rate detection circuit 30, which are connected between a power supply line PL and a ground line NL. The voltage divider circuit 10 outputs a divided voltage Vdiv of the power supply voltage AVDD on the power supply line PL to a node N1. The voltage evaluation circuit 20 generates an output signal VPOR indicating the result of comparison between the voltage at the node N1 and a predetermined threshold voltage (e.g., the threshold voltage Vt1 of the transistor 21). In other words, the node N1 corresponds to a "first node."

[0039] The voltage rate detection circuit 30 detects the voltage change rate (i.e., dAVdd / dt) of the power supply wiring PL when the power supply voltage AVDD is started up, for example, using a differentiating circuit with a capacitor. In the example of Fig. 3, the voltage rate detection circuit 30 determines the voltage change rate VRT [V / s] in predetermined N stages (N: an integer of 2 or more), and sets one of the selection signals SEL(0) to SEL(N-1) to the H level according to the determination result.

[0040] Hereinafter, in this specification, when signals, circuit elements, etc. corresponding to each of the above N stages are to be distinguished, numbers in parentheses will be added to represent the N signals, circuit elements, etc. On the other hand, when these N signals, circuit elements, etc. are to be collectively represented, numbers in parentheses will not be added.

[0041] When the voltage change rate VRT is at the highest level among the N levels, the selection signal SEL(N-1) is set to H level, and the remaining SEL(0) to SEL(N-2) are set to L level. On the other hand, when the voltage change rate VRT is at the lowest level among the N levels, the selection signal SEL(0) is set to H level, and the remaining SEL(1) to SEL(N-1) are set to L level. In this way, the smaller the voltage change rate VRT, the more one of the selection signals SEL(i) corresponding to integers i=0 to (N-1) on the lower bit side (the side with smaller i) is set to H level. In other words, the larger the voltage change rate VRT, the more one of the selection signals SEL(i) on the higher bit side (the side with larger i) is set to H level. A preferred configuration example of the voltage rate detection circuit 30 will be described in detail in the second embodiment.

[0042] FIG. 4 shows a circuit diagram illustrating an example of the configuration of the voltage dividing circuit 10 in FIG. 4, the voltage dividing circuit 10 includes N voltage dividing resistors connected in parallel between a power supply line PL and a ground line NL, and a selection circuit 15. The voltage dividing circuit 10 includes N voltage dividing resistors connected in parallel between a power supply line PL and a ground line NL.

[0043] The N voltage dividing resistors each include resistive elements RH(0) to RH(N-1) connected between the power supply wiring PL and node N1, and resistive elements RL(0) to RL(N-1) connected between node N1 and ground wiring NL. In FIG. 4, resistive elements RH(0) and RL(0) constituting the voltage dividing resistors on the lowest bit side, RH(N-1) and RL(N-1) constituting the voltage dividing resistors on the highest bit side, and RH(M) and RL(M) constituting the voltage dividing resistors on the middle bit side are shown (0 <M<(N-1))。

[0044] The voltage division ratio Kv, i.e., the ratio of the resistance values ​​of the resistive elements RH(0) to RH(N-1) to the resistive elements RL(0) to RL(N-1), is equal among the N voltage dividing resistors, i.e., RH(0):RL(0) = ... = RH(M):RL(M) = ... = RH(N-1):RL(N-1).

[0045] On the other hand, the sum of the resistance values ​​of each of the resistive elements RH(0) to RH(N-1) and each of the resistive elements RL(0) to RL(N-1), i.e., the impedance between the power supply wiring PL and the ground wiring NL, varies among the N voltage dividing resistors. Specifically, RH(0)+RL(0)>...>RH(M)+RL(M)>...>RH(N-1)+RL(N-1).

[0046] The selection circuit 15 has switch elements SWH(0) to SWH(N-1) and switch elements SWL(0) to SWL(N-1). The switch elements SWH(0) to SWH(N-1) are connected in series with the resistance elements RH(0) to RH(N-1), respectively, between the power supply wiring PL and the node N1. Similarly, the switch elements SWL(0) to SWL(N-1) are connected in series with the resistance elements RL(0) to RL(N-1), respectively, between the ground wiring NL and the node N1.

[0047] Switch elements SWH(0) to SWH(N-1) and switch elements SWL(0) to SWL(N-1) are turned on and off in response to selection signals SEL(0) to SEL(N-1). Specifically, each of switch elements SWH(0) to SWH(N-1) and SWL(0) to SWL(N-1) is turned on when the corresponding selection signal SEL is at H level, and turned off when the corresponding selection signal SEL is at L level.

[0048] For example, when the selection signal SEL(0) is at H level, the switch elements SWH(0) and SWL(0) are turned on. At this time, the other selection signals SEL(1) to SEL(N-1) are at L level, so the other switch elements SWH(1) to SWH(N-1) and SWL(1) to SWL(N-1) are turned off.

[0049] As described above, the voltage rate detection circuit 30 sets one of the N selection signals SEL to H level and the remaining (N-1) selection signals SEL to L level in accordance with the voltage change rate of the power supply voltage AVDD, thereby turning on the switch elements SWH and SWL to which the selection signal SEL set to H level has been input.

[0050] As a result, in the voltage divider circuit 10, one of the N voltage divider resistors is selected in accordance with the voltage rate detected by the voltage rate detection circuit 30 and connected between the power supply wiring PL and the ground wiring NL. On the other hand, in the other (N-1) voltage divider resistors, the corresponding switch elements SWH, SWL are turned off, so no current is generated between the power supply wiring PL and the ground wiring NL. Furthermore, until the voltage rate is detected by the voltage rate detection circuit 30, the switch elements SWH(0) to SWH(N-1) and SWL(0) to SWL(N-1) are all in the off state.

[0051] In the example of FIG. 4, the voltage rate detection circuit 30 sets the selection signal SEL(M) to an H level, turning on the switch elements SWH(M) and SWL(M), and the voltage dividing resistors formed by the resistance elements RH(M) and RL(M) are selectively connected between the power supply wiring PL and the ground wiring NL.

[0052] 4, each of the resistor elements RH(0) to RH(N-1) corresponds to an example of a "second resistor element," and each of the resistor elements RL(0) to RL(N-1) corresponds to an example of a "third resistor element." Also, the node N1 corresponds to an example of a "first node," as described above.

[0053] FIG. 5 shows a circuit diagram illustrating an example of the configuration of the voltage evaluation circuit 20 in FIG. 5, voltage evaluation circuit 20 differs from voltage evaluation circuit 20# shown in FIG. 1 in that it has a current control circuit 27 instead of current supply circuit 22. Current control circuit 27 has resistance elements RD(0) to RD(N-1) and switch elements SWD(0) to SWD(N-1) connected in parallel between power supply line PL and node N2. Switch elements SWD(0) to SWD(N-1) are connected in series with resistance elements RD(0) to RD(N-1), respectively, between power supply line PL and node N2.

[0054] The switch elements SWD(0) to SWD(N-1) are turned on and off in response to the selection signals SEL(0) to SEL(N-1). Specifically, each of the switch elements SWD(0) to SWD(N-1) is turned on when the corresponding selection signal SEL is at H level, and turned off when the corresponding selection signal SEL is at L level. Furthermore, all of the switch elements SWD(0) to SWD(N-1) are in the off state until the voltage rate detection circuit 30 detects the voltage rate.

[0055] In the example of FIG. 5, the voltage rate detection circuit 30 sets the selection signal SEL(M) to an H level, thereby turning on the switch element SWD(M), and the resistance element RD(M) is selectively connected between the power supply wiring PL and the node N2.

[0056] The resistance values ​​of the resistance elements RD(0) to RD(N-1) are different, and specifically, the resistance values ​​are set so that the resistance value increases on the lower bit side, i.e., RD(0)>RD(1)>...RD(M)...>RD(N-1). The other configuration of voltage evaluation circuit 20 is the same as that of voltage evaluation circuit 20# shown in FIG.

[0057] In the voltage evaluation circuit 20, when the switch element SWD is turned on to which the selection signal SEL set to H level is input, one of N resistance elements RD(0) to RD(N-1) having different resistance values ​​is selected according to the voltage rate detected by the voltage rate detection circuit 30, and is connected between the power supply wiring PL and the node N2.

[0058] Therefore, the higher the voltage change rate detected by the voltage rate detection circuit 30, the lower the resistance value of the resistor element RD connected between the power supply line PL and node N2 when the selection signal SEL on the higher-order bit side is set to H level. That is, the current Idet supplied from the current control circuit 27 to node N2 increases. This increases the rate of change in the voltage at node N2 when the transistor 21 is turned on.

[0059] On the other hand, the lower the voltage change rate detected by the voltage rate detection circuit 30, the higher the resistance value of the resistor element RD connected between the power supply line PL and node N2 by setting the lower-order bit side selection signal SEL to H level, thereby making it possible to reduce the steady-state current generated between the power supply line PL and the ground line NL while the transistor 21 is on.

[0060] In this way, in the voltage evaluation circuit 20, the current control circuit 27 can variably control the supply current Idet so that the supply current Idet increases as the voltage change rate increases. In Fig. 5, the resistance elements RD(0) to RD(N-1) correspond to an embodiment of "plurality of first resistance elements," and the node N2 corresponds to an embodiment of "second node." Furthermore, the switch elements SWD(0) to SWD(N-1) correspond to an embodiment of "plurality of switch elements," and the transistor 21 corresponds to an embodiment of "first transistor."

[0061] FIG. 6 is an equivalent circuit diagram of the power-on reset circuit 5 according to the first embodiment. 6, the selection signal SEL(M) is set to H level in accordance with the voltage change rate detected by the voltage rate detection circuit 30. As a result, in the voltage divider circuit 10, a voltage dividing resistor formed by the resistance elements RH(M) and RL(M) is connected between the power supply wiring PL and the ground wiring NL.

[0062] As a result, in the voltage divider circuit 10, the voltage division ratio Kv is constant according to the voltage change rate detected by the voltage rate detection circuit 30, while the impedance (resistance value) between the power supply wiring PL and the ground wiring NL becomes larger as the voltage change rate increases. Low Conversely, the smaller the voltage change rate, high The voltage dividing resistors (RH and RL) are selected so that

[0063] Therefore, according to the power-on reset circuit 5 of the first embodiment, when the voltage change rate is large, the impedance between the power supply wiring PL and the ground wiring NL can be reduced by the voltage divider circuit 10. This reduces the delay time until the transistor 21 turns on when the power supply voltage AVDD reaches the determination voltage Vpr (Vdiv>Vt1), thereby increasing the operating speed. small In some cases, by increasing the impedance between the power supply wiring PL and the ground wiring NL using the voltage divider circuit 10, it is possible to suppress the current that steadily occurs between the power supply wiring PL and the ground wiring NL, thereby achieving low power consumption.

[0064] Furthermore, in the voltage evaluation circuit 20, a resistive element RD(M) is connected between the power supply line PL and the node N2, and a supply current Idet according to the resistance value RD(M) is applied to the node N2. Therefore, in the voltage evaluation circuit 20, the resistive element RD is selected according to the voltage change rate detected by the voltage rate detection circuit 30 so that the supply current Idet increases as the voltage change rate increases, and conversely, the supply current Idet decreases as the voltage change rate decreases.

[0065] As a result, in the power-on reset circuit 5 according to the first embodiment, when the voltage change rate is high, the supply current Idet by the current control circuit 27 is increased, thereby shortening the time required for the output signal VPOR to change from L level to H level when the transistor 21 is turned on, thereby further increasing the operating speed. On the other hand, when the voltage change rate is high, the supply current Idet by the current control circuit 27 is reduced, thereby suppressing the current steadily generated between the power supply wiring PL and the ground wiring NL while the transistor 21 is on, thereby achieving low power consumption.

[0066] 12 shows a conceptual operational waveform diagram of the power-on reset circuit according to the first embodiment at the time of starting up the power supply voltage, which is to be compared with FIG. 12. In FIG. 12, waveforms 101 to 103 of the power supply voltage AVDD at the time of starting up are the same as those in FIG.

[0067] In the power-on reset circuit 5 according to the first embodiment, the timing at which the output signal VPOR changes from an L level to an H level for each of the waveforms 101 to 103 is between times t1y and t3y, which is later than times t1 and t3, due to the time required for the voltage rate detection circuit 30 to detect the voltage rate and the charging time of the node N1 (parasitic capacitance Cp).

[0068] In FIG. 12, the time delay (e.g., time t1 to t1y) when the voltage change rate is large is shortened compared to the comparative example in FIG. 2 by mainly changing the impedance of the voltage divider circuit 10 and further changing the supply current Idet by the current control circuit 27 according to the voltage change rate.

[0069] Furthermore, when the voltage change rate is small, the time delay becomes large (for example, from time t3 to t3y), but as a result, it can be understood from a comparison with Figure 2 that the voltage error ΔVer between the power supply voltage AVDD and the judgment voltage Vpr when the output signal VPOR actually changes to the H level can be equalized even if the voltage change rate is different.

[0070] As described above, the power-on reset circuit according to the first embodiment can generate a POR signal at an appropriate timing without increasing power consumption, even if the voltage change rate of the power supply voltage changes during startup. Furthermore, since the power-on reset circuit does not include a transistor connected in series with a voltage-dividing resistor or a downstream latch circuit as in Patent Document 1, the POR signal can be generated at high speed. Furthermore, as shown in FIG. 12, even if the voltage change rate changes, the level of the power supply voltage AVDD when the output signal VPOR actually changes to the H level is the same, thereby stabilizing the startup operation of a semiconductor device incorporating the power-on reset circuit.

[0071] Embodiment 2 In the second embodiment, a preferred configuration example of a voltage rate detection circuit will be described.

[0072] FIG. 7 is a circuit diagram illustrating a configuration example of a voltage rate detection circuit according to the second embodiment. 7, the voltage rate detection circuit 30 includes N rate detection units RDUT(0) to RDUT(N−1) and a control logic 35.

[0073] The rate detection units RDUT(0) to RDUT(N-1) output rate detection signals SRDET(0) to SRDET(N-1), respectively, based on the voltage change rate of the power supply voltage AVDD. The control logic 35 generates the selection signals SEL(0) to SEL(N-1) of FIG. 1 in accordance with the rate detection signals SRDET(0) to SRDET(N-1).

[0074] 7 shows rate detection units RDUT(0), RDUT(M), and RDUT(N-1) as examples, each of which has the same circuit configuration, with only some of the circuit constants being different, as will be described later. Below, the configuration of the Mth rate detection unit RDUT(M) will be described as a representative example.

[0075] The rate detection unit RDUT(M) includes a detection capacitor CDET(M), a charging capacitor CREF(M), transistors MND1(M) and MND2(M), a current supply circuit 36(M), and an inverter INVD(M).

[0076] The detection capacitor CDET(M) is connected between the power supply wiring PL and a node N3(M), and the transistor MND1(M) is connected between the node N3(M) and the ground wiring NL. The transistor MND2(M) is connected between the node N4(M) and the ground wiring NL. The gates of the transistors MND1(M) and MND2(M) are connected to the node N3(M), and the charging capacitor CREF(M) is connected between the node N3(M) and the ground wiring NL. That is, the transistor MND1(M) is diode-connected.

[0077] The charging capacitor CREF(M) includes at least the gate capacitance (parasitic capacitance) of the transistor MND2(M), and may further be configured by additionally connecting a parallel plate capacitor, a MOS (Metal Oxide Semiconductor) capacitor, etc. In the following description, the capacitance values ​​of each capacitor will be denoted by the same symbol.

[0078] The current supply circuit 36(M) is connected between the power supply wiring PL and the node N4(M) and supplies a current to the node N4(M). In the example of Fig. 7, the current supply circuit 36(M) has a resistance element RDET(M) connected between the power supply wiring PL and the node N4(M). That is, the supply current Ird(M) by the current supply circuit 36(M) is adjusted by the resistance value of the resistance element RDET(M), and the lower the RDET(M), the larger the supply current Ird(M).

[0079] The inverter INVD(M) outputs a rate detection signal SRDET(M) having a logic level corresponding to the voltage of the node N4(M). The voltage of the node N4(M) is the power supply voltage AVDD while the transistor MND2(M) is off, and changes to the ground voltage VSS at a speed corresponding to the supply current Ird(M) in response to the transistor MND2(M) being on. Therefore, the rate detection signal SRDET(M) is at the L level (ground voltage VSS) when the transistor MND2(M) is off, and changes from the L level to the H level in response to the transistor MND2(M) being on.

[0080] Next, the operation of the rate detection unit RDUT(M) in response to the input of the power supply voltage AVDD will be described.

[0081] When a change occurs in the voltage Vc applied to a capacitor with capacitance C, a current of Ic = C dVc / dt is generated in the capacitor. Therefore, for a voltage change rate VRT [V / s] (VRT = dAVDD / dt), which is the time rate of change of the power supply voltage AVDD applied to the detection capacitor CDET(M), a detection current Ic(M) is generated in the detection capacitor CDET(M) according to the following equation (2). As can be seen from equation (2), the larger the detection capacitor CDET(M) is, the larger the detection current Ic(M) is, and the larger the voltage change rate VRT is.

[0082] Ic(M)=CDET(M)·VRT …(2) When the power supply voltage AVDD starts up, the charging capacitor CREF(M) at node N3(M) is charged by the detection current Ic(M) that is generated in response to changes in the power supply voltage AVDD. When the voltage at node N3(M) becomes higher than the threshold voltage Vt2 of transistor MND2(M) due to charging, transistor MND2(M) turns on, and the rate detection signal SRDET(M) changes from L level to H level. This generates the rate detection signal SRDET(M).

[0083] The capacitance ratios Kc of the detection capacitors CDET(0) to CDET(N-1) to the charging capacitors CREF(0) to CREF(N-1) differ among the rate detection units RDUT(0) to RDUT(N-1). In FIG. 7, CDET(0) / CREF(0)>...>CDET(M) / CREF(M)>...>CDET(N-1) / CREF(N-1), and the rate detection units RDUT on the lower-order bit side are designed to have larger capacitance ratios Kc. Element constants other than the capacitance ratio Kc are set in common among the rate detection units RDUT(0) to RDUT(N-1). That is, the threshold voltage Vt2 is also common among the transistors MND2(0) to MND2(N-1).

[0084] In the following, an example will be described in which, to achieve the above capacitance ratio Kc, the capacitance values ​​of the charging capacitors CREF(0) to CREF(N-1) are common among the rate detection units RDUT(0) to RDUT(N-1), while the capacitance values ​​of the detection capacitors CDET(0) to CDET(N-1) are designed to gradually increase in order for the rate detection unit RDUT to be located on the lower-order bit side. That is, CDET(0)>...>CDET(M)>...>CDET(N-1). For example, the capacitance values ​​of the detection capacitors CDET(0) to CDET(N-1) can be set gradually so that the capacitance value decreases by a factor of 2 in increments of 1 / 2.

[0085] 7, the transistor MND2 of each rate detection unit RDUT corresponds to an embodiment of a “second transistor,” the node N3 corresponds to an embodiment of a “third node,” and the node N4 corresponds to an embodiment of a “fourth node.” Furthermore, the transistor MND2, the current supply circuit 36, and the inverter INVD can form an embodiment of a “rate determination circuit” for generating the rate detection signal SRDET.

[0086] 8 is a conceptual waveform diagram illustrating the operation of the voltage rate detection circuit, in which the vertical axis represents the voltage VN3 at the node N3.

[0087] Referring to FIG. 8, when the power supply voltage AVDD is turned on at time t0, the detection currents Ic(0) to Ic(N-1) generated in each of the rate detection units RDUT(0) to RDUT(N-1) are proportional to the capacitance values ​​of the detection capacitors CDET(0) to CDET(N-1).

[0088] 8, in a certain rate detection unit RDUT, at time ta, when T0 has elapsed since time t0, the voltage VN3 at node N3 reaches the threshold voltage Vt2 of transistors MND2(0) to MND2(N-1). In this case, in a rate detection unit RDUT in which the capacitance value of the detection capacitor CDET is k times (k: real number) that of the rate detection unit RDUT, the voltage VN3 reaches the threshold voltage Vt2 at time tb, when (T0 / k) has elapsed since time t0, earlier than time ta. Conversely, in a rate detection unit RDUT in which the capacitance value of the detection capacitor CDET is (1 / k) times, it can be seen that the voltage VN3 reaches the threshold voltage Vt2 at time tc, when (k·T0) has elapsed since time t0, later than time ta.

[0089] Therefore, when the minimum rate value and the maximum rate value of the detection range of the voltage change rate of the power supply voltage AVDD are predetermined, the capacitance value (or the capacitance ratio Kc) of the detection capacitor CDET is set so that when the power supply voltage AVDD of the minimum rate value is applied to the rate detection unit RDUT(0) having the maximum capacitance value (i.e., capacitance ratio Kc) of the detection capacitor CDET, the voltage of the node N3 rises to the threshold voltage Vt2 within a predetermined reference time.

[0090] Conversely, in the rate detection unit RDUT(N-1) in which the capacitance value (i.e., capacitance ratio Kc) of the detection capacitor CDET is the smallest, the capacitance value (or capacitance ratio Kc) of the detection capacitor CDET is set so that when the power supply voltage AVDD of the maximum rate value is applied, the voltage of node N3 rises to the threshold voltage Vt2 in the same reference time.

[0091] Furthermore, in the intermediate rate detection units RDUT(1) to RDUT(N-2), the capacitance value (or capacitance ratio Kc) of the detection capacitor CDET is set in stages so that the value becomes smaller toward the more significant bit side within the range between the rate detection units RDUT(0) and RDUT(N-1). As a result, the rate detection signals SRDET(0) to SRDET(N-1) from the rate detection units RDUT(0) to RDUT(N-1) are generated as shown in FIG.

[0092] FIG. 9 shows a diagram illustrating the operation of the voltage rate detection circuit shown in FIG. 9, when a power supply voltage AVDD having a minimum rate value R1 is input to the rate detection units RDUT(0) to RDUT(N-1), at the point in time when the reference time has elapsed since the start of the power supply voltage AVDD was detected based on the voltage of the power supply wiring PL, the transistor MND2(0) is turned on only in the rate detection unit RDUT(0) having the largest capacitance value (i.e., capacitance ratio Kc) of the detection capacitor CDET. Meanwhile, in the other rate detection units RDUT(1) to RDUT(N-1), the transistors MND2(1) to MND2(N-1) remain off. As a result, after the reference time has elapsed, the rate detection signal SRDET(0) is at an H level, while the rate detection signals SRDET(1) to SRDET(N-1) are at an L level. That is, the rate detection signal SRDET is generated only in the rate detection unit RDUT(0).

[0093] When the power supply voltage AVDD, whose voltage change rate VRT is a rate value RM between the minimum rate value R1 and the maximum rate value RN, is input to the rate detection units RDUT(0) to RDUT(N-1), the transistors MND2(0) to MND2(M) turn on in the rate detection units RDUT(0) to RDUT(M) after the reference time has elapsed. On the other hand, in the rate detection units RDUT(M+1) to RDUT(N-1) that are on the more significant bit side and whose detection capacitor CDET has a smaller capacitance value (i.e., capacitance ratio Kc) than the rate detection unit RDUT(M), the transistors MND2(M+1) to MND2(N-1) remain off. As a result, after the reference time has elapsed, the rate detection signals SRDET(0) to SRDET(M) are at H level, while the rate detection signals SRDET(M+1) to SRDET(N-1) are at L level. That is, the rate detection signal SRDET is generated in the (M+1) rate detection units RDUT(0) to RDUT(M).

[0094] In this way, the greater the voltage change rate of the power supply voltage AVDD is than the minimum rate value R1, the greater the number of rate detection units RDUT that generate the rate detection signal SRDET by turning on the transistor MND2 when the reference time has elapsed, starting from the least significant bit side.

[0095] When a power supply voltage AVDD having a maximum rate value RN is input to the rate detection units RDUT(0) to RDUT(N-1), after the reference time has elapsed, the transistor MND2(N-1) is also turned on in the rate detection unit RDUT(N-1) whose detection capacitor CDET has the smallest capacitance value (i.e., capacitance ratio Kc). Therefore, after the reference time has elapsed, all of the rate detection signals SRDET(0) to SRDET(N-1) become H level. The rate detection signal SRDET is generated in the N rate detection units RDUT(0) to RDUT(N-1).

[0096] The control logic 35 sets only one of the selection signals SEL(0) to SEL(N - 1) to the H level and sets the other (N - 1) to the L level according to the rate detection signals SRDET(0) to SRDET(N - 1) generated as described above.

[0097] Specifically, the control logic 35 can be constructed such that only the corresponding 1 bit of the selection signal SEL is set to the H level corresponding to the uppermost bit among the bits set to the H level among the rate detection signals SRDET(0) to SRDET(N - 1). Also, when all of the rate detection signals SRDET(0) to SRDET(N - 1) are at the L level, the selection signal SEL(0) is set to the H level.

[0098] By inputting the selection signals SEL(0) to SEL(N - 1) generated in this way into the voltage dividing circuit 10 and the voltage determination circuit 20 described in the first embodiment, the power-on reset circuit 5 can operate according to the equivalent circuit diagram shown in FIG. 6.

[0099] According to the voltage rate detection circuit 30 described in the second embodiment, the voltage change rate can be detected in multiple stages (N stages) at high speed when the power supply voltage AVDD is started with a simple configuration.

[0100] It is also possible to set the supply currents Ird(0) to Ird(N - 1) of the current supply circuits 36(0) to 36(N - 1) to different values among the rate detection units RDUT(0) to RDUT(N - 1) shown in FIG. 7. Specifically, since the rate detection units RDUT on the upper bit side are arranged to detect a relatively large voltage change rate, it is preferable to set Ird(0) < … < Ird(M) < … < Ird(N - 1) so that the supply current Ird increases as the upper bit side is reached.

[0101] In the example of FIG. 7, for the resistance value of the resistance element RD ET about RD ET (0) > … > RD ET (M) > … > RD ETBy setting the resistor element RD to (N-1), it is possible to realize the setting of the supply currents Ird(0) to Ird(N-1). ET (0)~RD ET Each of (N-1) corresponds to an example of a "fourth resistive element."

[0102] 7 and 5, regarding the threshold voltage Vt1 of the transistor 21 of the voltage determination circuit 20 and the threshold voltage Vt2 of the transistor MND2 of each rate detection unit RDUT, it is preferable that the threshold voltage Vt1 (transistor 21) be set higher than the threshold voltage Vt2 (transistor MND2) (Vt1>Vt2). That is, it is preferable that the voltage of the node N1 when the transistor 21 is turned on be higher than the voltage of the node N3 when the transistor MND2 is turned on. In this way, it is possible to suppress malfunction of the power-on reset circuit 5, which may result in the POR signal being erroneously generated (i.e., the output signal VPOR erroneously changing from L level to H level), thereby ensuring reliable operation.

[0103] Embodiment 3 In the third embodiment, a modified example of the configuration of the voltage evaluation circuit and the voltage rate detection circuit exemplified in the first and second embodiments will be described.

[0104] FIG. 10 is a circuit diagram illustrating a configuration example of a voltage evaluation circuit according to the third embodiment. 10, a voltage evaluation circuit 20X according to the third embodiment differs from voltage evaluation circuit 20 shown in FIG. 5 in that current control circuit 27 is replaced with a current control circuit 27X.

[0105] The current control circuit 27X differs from the current control circuit 27 in that it has current source circuits CSD(0) to CSD(N - 1) composed of transistors instead of the resistance elements RD(0) to RD(N - 1). Other configurations of the current control circuit 27X are the same as those of the current control circuit 27. That is, the current control circuit 27X has current source circuits CSD(0) to CSD(N - 1) connected in parallel between the power supply wiring PL and the node N2, and switch elements SWD(0) to SWD(N - 1). And the switch elements SWD(0) to SWD(N - 1) are connected in series with each of the current source circuits CSD(0) to CSD(N - 1) between the power supply wiring PL and the node N2.

[0106] The output currents Id(0) to Id(N - 1) of the current source circuits CSD(0) to CSD(N - 1) are different. Specifically, they are set such that Id(0) < Id(1) < … Id(M) … < Id(N - 1) so that the output current increases on the upper bit side. The switch elements SWD(0) to SWD(N - 1) are turned on and off according to the selection signals SEL(0) to SEL(N - 1) in the same manner as described in the first embodiment. Therefore, the higher the voltage change rate detected by the voltage rate detection circuit 30, the higher the output current, and the current source circuit CSD with a larger output current is connected between the power supply wiring PL and the node N2 by the switch element SWD.

[0107] As a result, similar to the first embodiment, the higher the voltage change rate detected by the voltage rate detection circuit 30, the larger the supply current Idet from the current control circuit 27X to the node N2 can be made. Thereby, the change speed of the voltage of the node N2 at the time of turning on the transistor 21 can be increased.

[0108] Therefore, even when using the voltage determination circuit 20X shown in FIG. 10, the same power - on reset circuit 5 as described in the first embodiment can be realized. In FIG. 10, each of the current source circuits CSD(0) to CSD(N - 1) corresponds to an example of the "first current source circuit".

[0109] FIG. 11 is a circuit diagram for explaining a configuration example of a voltage rate detection circuit according to Embodiment 3. Referring to FIG. 11, the voltage rate detection circuit 30X according to Embodiment 3 is different from the voltage rate detection circuit 30 shown in FIG. 7 in that the rate detection units RDUT(0) to RDUT(N−1) have current supply circuits 36X(0) to 36X(N−1) instead of current supply circuits 36(0) to 36(N−1).

[0110] The current supply circuits 36X(0) to 36X(N−1) are different in that they have current source circuits CSDT(0) to CSDT(N−1) including transistors (not shown) instead of resistance elements RD(0) to RD(N−1). Other configurations of the voltage rate detection circuit 30X are the same as those of the voltage rate detection circuit 30.

[0111] As described at the end of Embodiment 2, it is preferable that the supply currents Ird(0) to Ird(N−1) of the current supply circuits 36(0) to 36(N−1) be such that Ird(0)<…<Ird(M)<…<Ird(N−1), with the supply current Ird increasing as the rate detection unit RDUT on the upper bit side is reached. In the configuration of FIG. 11, such a setting of the supply currents Ird(0) to Ird(N−1) can be realized by designing the output currents of the current source circuits CSDT(0) to CSDT(N−1) such that the output current increases in the rate detection unit RDUT on the upper bit side. In FIG. 11, each of the current source circuits CSDT(0) to CSDT(N−1) corresponds to an embodiment of a “second current source circuit”. Also, in the configuration example of FIG. 11, an embodiment of a “rate determination circuit” for generating a rate detection signal SRDET is constituted by the transistor MND2, the current supply circuit 36X, and the inverter INVD.

[0112] It should be considered that all the embodiments disclosed this time are illustrative and not restrictive in any way. The scope of the present disclosure is shown not by the above description but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims are included.

Description of Reference Numerals

[0113] 5,5♯ Power-on reset circuit, 10,10♯ Voltage divider circuit, 15 Selection circuit, 20,20X,20♯ Voltage judgment circuit, 21,MND1(0)~MND1(N-1),MND2(0)~MND2(N-1) Transistor, 22,36,36X Current supply circuit, 25 Signal generation circuit, 27,27X Current control circuit, 30,30X Voltage rate detection circuit, 35 Control logic, AVDD Power supply voltage, CDET(0)~CDET(N-1) Detection capacitor, CREF(0)~CREF(N-1) Charging capacitor, CSD(0)~CSD(N-1),CSDT(0)~CSDT(N-1) Current source circuit, INVD(0)~INVD(N-1) Inverter, Ic(0)~Ic(N-1) Detection current, Id(0)~ID(N-1) Output current (current source circuit), Idet(0) to Idet(N-1), Ird(0) to Ird(N-1) supply current, N1 to N4 nodes, NL reference voltage wiring (ground wiring), PL power supply wiring, RD(0) to RD(N-1), RDET(0) to RDET(N-1), RH(0) to RH(N-1), RL(0) to RL(N-1) resistor element, RDUT(0) to RDUT(N-1) rate detection unit, SEL(0) to SEL(N-1) selection signal, SRDET(0) to SRDET(N-1) rate detection signal, SWD(0) to SWD(N-1), SWH(0) to SWH(N-1), SWL(0) to SWL(N-1) switch element, VPOR output signal, VRT voltage change rate, VSS reference voltage (ground voltage), Vdiv divided voltage, Vt1, Vt2 Threshold voltage, Vpr judgment voltage.

Claims

1. a power supply wiring for receiving a power supply voltage; a reference voltage wiring for transmitting a reference voltage; a voltage divider circuit connected between the power supply wiring and the reference voltage, which divides the power supply voltage and outputs a divided voltage to a first node; a voltage rate detection circuit for detecting a voltage change rate of the power supply voltage at the time of starting the power supply voltage; a voltage determination circuit that generates an output signal indicating a comparison result between the voltage of the first node and a predetermined voltage; the voltage divider circuit is configured to variably set an impedance between the power supply wiring and the reference voltage while maintaining a constant voltage division ratio of the divided voltage to the power supply voltage in accordance with the voltage change rate detected by the voltage rate detection circuit; The power-on reset circuit is configured such that the impedance decreases as the voltage change rate increases.

2. The voltage determination circuit a current control circuit connected between the power supply wiring and a second node, the current control circuit variably controlling a supply current from the power supply wiring to the second node in accordance with the voltage change rate detected by the voltage rate detection circuit; a first transistor connected between the second node and the reference voltage wiring and turned on and off in response to a voltage of the first node; the output signal is generated to have a logic level corresponding to the voltage of the second node which changes with the on / off of the first transistor; 2. The power-on reset circuit according to claim 1, wherein said current control circuit controls said supply current so that said supply current increases as said voltage change rate increases.

3. The current control circuit a plurality of first resistor elements connected in parallel between the power supply wiring and the second node; a plurality of switch elements connected in series with the plurality of first resistor elements, respectively, between the power supply wiring and the second node; 3. The power-on reset circuit according to claim 2, wherein the on / off of the plurality of switch elements is controlled in accordance with the voltage change rate detected by the voltage rate detection circuit so that the greater the voltage change rate, the smaller the electrical resistance value between the power supply wiring and the second node.

4. the current control circuit includes a plurality of first current source circuits each including a transistor, which are connected in parallel between the power supply wiring and the second node; a plurality of switch elements connected in series with the plurality of first current source circuits between the power supply wiring and the second node; 3. The power-on reset circuit according to claim 2, wherein the on / off of the plurality of switch elements is controlled in accordance with the voltage change rate detected by the voltage rate detection circuit, so that the supply current from the plurality of first current source circuits increases as the voltage change rate increases.

5. The voltage divider circuit A plurality of voltage dividing resistors; a selection circuit for selectively connecting the plurality of voltage dividing resistors between the power supply wiring and the reference voltage wiring in accordance with the voltage change rate detected by the voltage rate detection circuit; Each of the plurality of voltage dividing resistors is a second resistor element connected between the power supply wiring and the first node; a third resistor element connected between the reference voltage wiring and the first node, a ratio of the electrical resistance values ​​of the second resistance element and the third resistance element is common among the plurality of voltage dividing resistors, while a sum of the electrical resistance values ​​of the second resistance element and the third resistance element differs among the plurality of voltage dividing resistors; 5. The power-on reset circuit according to claim 1, wherein the selection circuit is controlled so that the electrical resistance value between the power supply wiring and the reference voltage wiring decreases as the voltage change rate increases.

6. The voltage rate detection circuit includes N rate detection units; N is an integer of 2 or more, Each of the N rate detection units a detection capacitor connected between the power supply wiring and a third node; a rate determination circuit that generates a rate detection signal in response to the voltage at the third node increasing above a predetermined voltage; The ratio of the capacitance value of the detection capacitor to the capacitance value of the third node is different among the N rate detection units, the voltage rate detection circuit detects the voltage change rate in N stages based on the number of rate detection units that generate the rate detection signal among the N rate detection units at a time point when a predetermined reference time has elapsed since the start of the power supply voltage; 2. The power-on reset circuit according to claim 1, wherein the detected rate of change in voltage increases as the number of the voltages increases.

7. The rate determination circuit a current supply circuit connected between the power supply wiring and a fourth node, the current supply circuit supplying a current from the power supply wiring to the fourth node; a second transistor connected between the fourth node and the reference voltage wiring and turned on and off in response to the voltage of the third node; the rate detection signal is generated when the voltage of the fourth node changes as the second transistor is turned on; the current supplied by the current supply circuit differs among the N rate detection units; 7. The power-on reset circuit according to claim 6, wherein the supply current is set to be larger for a rate detection unit having a smaller capacitance value of the detection capacitor.

8. The voltage determination circuit a current control circuit connected between the power supply wiring and a second node, the current control circuit controlling a supply current from the power supply wiring to the second node; a first transistor connected between the second node and the reference voltage wiring and turned on and off in response to a voltage of the first node; the output signal is generated to have a logic level corresponding to the voltage of the second node which changes with the on / off of the first transistor; The voltage rate detection circuit includes N rate detection units; N is an integer of 2 or more, Each of the N rate detection units a detection capacitor connected between the power supply wiring and a third node; a current supply circuit connected between the power supply wiring and a fourth node, the current supply circuit supplying a current from the power supply wiring to the fourth node; a second transistor connected between the fourth node and the reference voltage wiring and turned on and off in response to the voltage of the third node; generating a rate detection signal when the voltage of the fourth node changes as the second transistor is turned on; The ratio of the capacitance value of the detection capacitor to the capacitance value of the third node is different among the N rate detection units, the voltage rate detection circuit detects the voltage change rate in N stages based on the number of rate detection units that generate the rate detection signal among the N rate detection units at a time point when a predetermined reference time has elapsed since the start of the power supply voltage; 2. The power-on reset circuit according to claim 1, wherein the voltage at said first node when said first transistor is turned on is higher than the voltage at said third node when said second transistor is turned on.

9. The current supply circuit includes: a fourth resistor element connected between the power supply wiring and the fourth node, the fourth resistor element having a different electrical resistance value among the N rate detection units; 9. The power-on reset circuit according to claim 7, wherein the electric resistance value is set smaller for a rate detection unit having a smaller capacitance value of the detection capacitor.

10. The current supply circuit includes: a second current source circuit connected between the power supply wiring and the fourth node, the second current source circuit having different output currents among the N rate detection units; 9. The power-on reset circuit according to claim 7, wherein the rate detection unit has a smaller capacitance value of the detection capacitor, and the output current of the second current source circuit is larger.

11. 9. The power-on reset circuit according to claim 7, wherein the capacitance value of the third node is common among the N rate detection units, but the capacitance values ​​of the detection capacitors are different from one another.

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