Semiconductor device and manufacturing method thereof

Abstract

To suppress the drop in withstand voltage of a vertical type semiconductor device comprising a group III nitride semiconductor.SOLUTION: A drift layer 11 is provided on a substrate 10. The drift layer 11 contains n--GaN. A p-type layer 12 is provided on the drift layer 11. The p-type layer 12 contains p-GaN. The p-type layer 12 has a partial region where a groove 20 is provided. The groove 20 has such a depth that it extends through the p-type layer 12 and reaches a position deeper than the surface of the drift layer 11. That is, the groove 20 is over-etched. The groove 20 has a side face inclined. An embedding layer 13 is provided so as to fill the groove 20. The embedding layer 13 has a thickness equal to the depth of the groove 20. The embedding layer 13 contains n--GaN. The embedding layer 13 is composed of a re-grown layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a vertical semiconductor device made of a Group III nitride semiconductor and a manufacturing method thereof, particularly to a device having a structure in which a portion of a p-type Group III nitride semiconductor provided on an n-type Group III nitride semiconductor is etched to form a groove, and an n-type Group III nitride semiconductor is regrown to fill the groove. [Background technology]

[0002] A known trench-type vertical FET has a structure in which a p-type layer is located laterally away from the corners of the gate trench, which can prevent a high electric field from being applied to the corners of the gate trench when the drain voltage is increased.

[0003] There are two possible methods for realizing such a structure in a semiconductor device made of a group III nitride semiconductor. - The other method is to etch a portion of the n-GaN to form a groove, and then re-grow p-GaN to fill the groove. - By etching a part of the p-GaN on the -GaN, - A trench is formed that reaches the GaN, and then the trench is filled with n - -GaN regrowth. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-130699 [Patent Document 2] Japanese Patent Application Publication No. 2019-89690 Summary of the Invention [Problem to be solved by the invention]

[0005] However, after careful consideration by the inventors, it was found that the method of regrowing p-GaN reduces the breakdown voltage and makes it impossible to achieve the intended operation. This is because unintended high-concentration Si adheres to the GaN regrowth interface, forming a high-concentration donor region at the regrowth interface. In other words, the area near the regrowth interface is n - -GaN, n + The structure is a stack of n-GaN and p-GaN, and the presence of a high-concentration n-type layer prevents the depletion layer from expanding sufficiently, resulting in a decrease in breakdown voltage.

[0006] So the inventors decided to - In this case, there is no regrowth interface below the p-GaN, and the n-GaN is grown near the regrowth interface. - -GaN, n + -GaN, n - -GaN layered structure, and there did not appear to be any decrease in breakdown voltage.

[0007] However, after careful consideration, the inventors found that the breakdown voltage also decreased in this case. This decrease in breakdown voltage was due to over-etching (n - The greater the etching depth of p-GaN, the more pronounced this became. Ideally, only p-GaN would be etched to eliminate the amount of over-etching. However, due to the controllability and variability of the etching depth, it is necessary to ensure that the n-GaN is etched. - - Over-etching is necessary to expose the GaN.

[0008] An object of the present invention is to suppress a decrease in breakdown voltage in a semiconductor device having a structure in which a partial region of a p-type Group III nitride semiconductor on an n-type Group III nitride semiconductor is etched to form a groove deep enough to reach a position deeper than the surface of the n-type Group III nitride semiconductor, and an n-type Group III nitride semiconductor is regrown in the groove. [Means for solving the problem]

[0009] The present invention provides a vertical semiconductor device made of a group III nitride semiconductor, the device comprising: an n-type first semiconductor layer; a p-type second semiconductor layer provided on the first semiconductor layer; a trench provided in a partial region of the second semiconductor layer, the trench having a depth that penetrates the second semiconductor layer and reaches a position deeper than the surface of the first semiconductor layer; and an n-type third semiconductor layer that is regrown so as to fill the trench, the side surface of the trench having a slope such that a cross-sectional area of ​​the trench in a plane parallel to a major surface of the first semiconductor layer increases from a bottom surface toward an upper surface of the trench. The inclination angle of the side surface of the groove is set to increase from the bottom surface of the groove toward the top surface. The semiconductor element is characterized by:

[0010] The present invention also provides a method for manufacturing a vertical semiconductor device made of a group III nitride semiconductor, the method comprising the steps of: forming a p-type second semiconductor layer on an n-type first semiconductor layer; forming a trench in a partial region of the second semiconductor layer, the trench having a depth that penetrates the second semiconductor layer and reaches a position deeper than the surface of the first semiconductor layer; and regrowing an n-type third semiconductor layer so as to fill the trench, wherein the side surface of the trench has a slope such that a cross-sectional area of ​​the trench in a plane parallel to a main surface of the first semiconductor layer increases from a bottom surface toward an upper surface of the trench. The inclination angle of the side surface of the groove increases from the bottom surface to the top surface of the groove. The method for manufacturing a semiconductor device is characterized in that the groove is formed.

[0011] In the present invention, the inclination angle of the side surface of the groove is preferably 45° or less.

[0012] In the present invention, the inclination angle of the side surface of the groove may increase from the bottom surface to the top surface of the groove.

[0013] The inclination angle of the side surface of the groove may vary continuously.

[0014] The bottom and side surfaces of the groove may be continuously curved. [Effects of the Invention]

[0015] According to the present invention, by providing a slope on the side surface of the trench, it is possible to prevent the impact ionization region from overlapping with the regrowth interface, and it is possible to suppress a decrease in breakdown voltage. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a diagram showing the configuration of a semiconductor element according to a first embodiment. [Figure 2] FIG. 4 is a diagram showing a modified example of the semiconductor element of the first embodiment. [Figure 3] FIG. 4 is a diagram showing a modified example of the semiconductor element of the first embodiment. [Figure 4] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor element according to the first embodiment. [Figure 5] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor element according to the first embodiment. [Figure 6] Graph showing Id-Vds characteristics. [Figure 7] Graph showing Id-Vds characteristics. [Figure 8] Graph showing Id-Vds characteristics. [Figure 9] 1 is a graph showing the distribution of impact ionization intensity in the cross section of an element. [Figure 10] 1 is a graph showing the distribution of impact ionization intensity in the cross section of an element. [Figure 11] 1 is a graph showing the distribution of impact ionization intensity in the cross section of an element. [Figure 12] 10 is a graph showing the relationship between the inclination angle θ of the side surface of the groove 20 and the withstand voltage. [Figure 13] FIG. 10 is a diagram showing the configuration of a semiconductor element according to a second embodiment. [Figure 14] FIG. 10 is a diagram showing a modified example of the semiconductor element of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0018] (First embodiment) Fig. 1 is a diagram showing the configuration of a semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment is a vertical MISFET with a trench gate structure, and as shown in Fig. 1, has a substrate 10, a drift layer 11, a p-type layer 12, a buried layer 13, a channel layer 14, a contact layer 15, a gate insulating film 16, a gate electrode 17, a source electrode 18, and a drain electrode 19. The drift layer 11 corresponds to the first semiconductor layer of the present invention, the p-type layer 12 corresponds to the second semiconductor layer of the present invention, and the buried layer 13 corresponds to the third semiconductor layer of the present invention.

[0019] The substrate 10 is + The substrate 10 is made of GaN. The Si concentration is 1×10 18 / cm 3 That's all. The material of the substrate 10 may be other than GaN, and any material can be used as long as it is a highly conductive material on which a group III nitride semiconductor can be grown. For example, n-type Si, n-type SiC, ZnO, etc. can be used. Although the substrate 10 has been referred to as a substrate for convenience, it should be noted that n + An epitaxial thin film layer of GaN may also be used.

[0020] The drift layer 11 is provided on the substrate 10. The drift layer 11 has an n - The drift layer 11 is made of GaN. The thickness of the drift layer 11 is 5 to 30 μm, and preferably 5 to 12 μm. The Si concentration of the drift layer 11 is 1×10 15 ~5×10 16 / cm 3 is.

[0021] The p-type layer 12 is provided on the drift layer 11. The p-type layer 12 is made of p-GaN. The thickness of the p-type layer 12 is 0.1 to 1 μm, preferably 0.3 to 0.7 μm. The acceptor concentration of the p-type layer 12 is 5×10 16 ~8×10 19 / cm 3 As the acceptor, Mg is preferable, but other acceptors such as C or Be may also be used.

[0022] Grooves 20 are provided in a partial region of the p-type layer 12. The depth of the grooves 20 penetrates the p-type layer 12 and reaches a position deeper than the surface of the drift layer 11. In other words, the grooves 20 are over-etched. The drift layer 11 is exposed at the bottom of the grooves 20. Furthermore, the drift layer 11 and the p-type layer 12 are exposed on the side surfaces of the grooves 20, in that order from the bottom side. The amount of over-etching (the depth from the drift layer 11 to the bottom of the grooves 20) is 1 to 100 nm, and preferably 5 to 50 nm. This is to ensure that the drift layer 11 is exposed at the bottom of the grooves 20 while suppressing a decrease in breakdown voltage due to over-etching.

[0023] The side surfaces of the grooves 20 are inclined. This inclination is tapered so that the cross-sectional area of ​​the grooves 20 in a plane parallel to the major surface of the drift layer 11 increases from the bottom surface of the grooves 20 toward the top surface. The inclination of the side surfaces of the grooves 20 can suppress a decrease in the breakdown voltage due to over-etching of the grooves 20. The reason for this will be described later. The inclination angle θ of the side surfaces of the grooves 20 (the angle with respect to the bottom surface of the grooves 20) may be any angle less than 90°, but is preferably 45° or less. Within the range of 45 to 90°, the smaller the angle, the less the decrease in the breakdown voltage. However, if the angle is 45° or less, the decrease in the breakdown voltage stops, and a breakdown voltage equivalent to that when the depth of the grooves 20 is the same as the thickness of the p-type layer 12 (assuming no over-etching) can be obtained.

[0024] The inclination angle of the side surface of the trench 20 does not have to be constant, but may vary stepwise or continuously. A continuously varying inclination angle means that at least a portion of the surface is curved. Furthermore, it is not necessary to provide an inclination on the entire side surface of the trench 20; it is sufficient that the inclination is provided at least in the region where the drift layer 11 is exposed. When the inclination angle of the side surface of the trench 20 is varied, it is preferable that the inclination angle increases from the bottom surface of the trench 20 toward the top surface, and it is particularly preferable that the curved surface have a continuously varying inclination angle (see FIG. 2 ). By providing such an inclination angle on the side surface of the trench 20, the overall distance from the trench 23 to the p-type layer 12 in the lateral direction can be increased compared to the case of FIG. 1 , and in particular, the distance between the corners of the bottom of the trench 23 and the p-type layer 12 can be increased, thereby further reducing the channel resistance.

[0025] The bottom and side surfaces of the trench 20 may be continuously curved (convex toward the substrate 10) to form a bowl shape (see FIG. 3). That is, the bottom surface of the trench 20 may be curved convex toward the substrate 10, and the side surfaces of the trench 20 may be curved surfaces that are continuous with the bottom surface. The distance from the trench 23 to the p-type layer 12 in the lateral direction can be increased compared to the case of FIG. 1, and in particular the distance between the corners of the bottom of the trench 23 and the p-type layer 12 can be increased, thereby reducing the channel resistance. Note that such a shape of the trench 20 can be easily formed by isotropic etching or an etching method similar to isotropic etching.

[0026] The buried layer 13 is provided so as to fill the grooves 20. The thickness of the buried layer 13 may be equal to the depth of the grooves 20, or 80% to 120% of the depth of the grooves 20. The upper surface of the p-type layer 12 and the upper surface of the buried layer 13 do not necessarily have to be at the same height. It is sufficient that the channel layer 14, which will be described later, grows on the upper surfaces of the p-type layer 12 and the buried layer 13 without step discontinuities. The buried layer 13 is an n -The buried layer 13 is a layer regrown by epitaxial growth using MOCVD, and the interface between the buried layer 13 and the trench 20 (the bottom and side surfaces of the trench 20) is called the regrowth interface 21. Regrowth means that crystal growth is temporarily stopped, followed by etching and other processes, and then crystal growth is resumed. The Si concentration of the buried layer 13 is 0.5×10 16 ~5×10 16 / cm 3 On the other hand, the inventors' investigation revealed that high concentrations of Si impurities unintentionally adhere to the regrowth interface when GaN is exposed to the air. The Si concentration at the regrowth interface 21 is 1×10 18 / cm 3 The Si concentration at the regrowth interface 21 is higher than that at the drift layer 11 and the buried layer 13. Depending on the regrowth conditions, the Si concentration at the regrowth interface 21 may be 1×10 17 ~5×10 18 / cm 3 It may vary within the range.

[0027] The channel layer 14 and the contact layer 15 are continuously formed on the p-type layer 12 and the buried layer 13. The channel layer 14 is made of p-GaN. The thickness of the channel layer 14 is 0.1 to 1 μm, preferably 0.3 to 0.7 μm. The Mg concentration of the p-type layer 12 is 5×10 16 ~8×10 19 / cm 3 The channel layer 14 and the contact layer 15 are regrown layers, and the region near the interface between the upper surface of the p-type layer 12 and the upper surface of the buried layer 13 and the channel layer 14 is called a regrowth interface 22. A high concentration of Si impurities is attached to the regrowth interface 22 by exposing the GaN to the air. The concentration of this Si is 1×10 18 / cm 3 Depending on the regrowth conditions, the Si concentration at the regrowth interface 22 is about 1×10 17 ~5×10 18 / cm 3 It may vary within the range.

[0028] The contact layer 15 is provided on the channel layer 14. The contact layer 15 is an n + The contact layer 15 is made of GaN. The thickness of the contact layer 15 is 0.1 to 0.5 μm. The Si concentration of the contact layer 15 is 1×10 18 ~5×10 19 / cm 3 is.

[0029] A trench 23 is provided in a region above the contact layer 15 and above the buried layer 13, penetrating the channel layer 14 from the contact layer 15 to a depth reaching the buried layer 13. The buried layer 13 is exposed at the bottom of the trench 23. The buried layer 13, the channel layer 14, and the contact layer 15 are exposed on the side surfaces of the trench 23, in that order from the bottom. A p-type layer 12 is located laterally from the corners of the trench 23, sandwiching the buried layer 13 between them. This prevents a high electric field from being applied to the corners of the trench 23. The bottom of the trench 23 should be at the same depth as or shallower than the bottom of the p-type layer 12. If the bottom of the trench 23 is deeper than the bottom of the p-type layer 12, the electric field applied to the corners of the trench 23 increases, making the corners of the trench 23 more susceptible to breakdown due to the high electric field. The corners of the trench 23 should also be spaced apart from the side surfaces of the buried layer 13. This is because when the corners of the trench 23 approach the side surfaces of the buried layer 13, the thickness of the inversion layer, which is the channel formed in the buried layer 13 near the trench 23, is limited, and the channel resistance increases.

[0030] The gate insulating film 16 is provided continuously over the bottom and side surfaces of the trench 23 and the surface of the contact layer 15 in the vicinity of the trench 23. The gate insulating film 16 is made of, for example, SiO2. The gate insulating film may also be made of Al2O3, SiN, AlN, or a composite film containing any of these.

[0031] The gate electrode 17 is provided in contact with the gate insulating film 16. The gate electrode 17 is made of, for example, TiN / Al.

[0032] The source electrode 18 is provided on the contact layer 15. The source electrode 18 is made of, for example, Ti / Al.

[0033] The drain electrode 19 is provided on the back surface of the substrate 10. The drain electrode 19 is made of, for example, Ti / Al.

[0034] Next, a method for manufacturing the semiconductor device of the first embodiment will be described with reference to the drawings.

[0035] First, the drift layer 11 and the p-type layer 12 are formed in this order on the substrate 10 by MOCVD (see FIG. 4(a)).

[0036] Next, a patterned mask 24 is formed on a partial region of the p-type layer 12, and the surface of the p-type layer 12 that is not covered by the mask 24 is dry-etched to form grooves 20 (see FIG. 4(b)). Materials for the mask 24 include SiO2, AlN, and Al2O3 as a hard mask. The hard mask is obtained by forming SiO2 or the like on the p-type layer 12 of FIG. 4(a), applying photoresist onto the p-type layer 12, exposing and developing it using a stepper, patterning the photoresist, and then etching the SiO2 or the like using the patterned photoresist as a mask to remove the photoresist.

[0037] Here, the depth of grooves 20 is set to a depth that penetrates p-type layer 12 and reaches a position deeper than the surface of drift layer 11. Ideally, dry etching would be stopped when the surface of drift layer 11 is exposed, and the amount of over-etching (etching depth of drift layer 11) would be set to 0. However, in practice, such over-etching is performed in consideration of controllability of the etching depth and variations in the etching depth within the surface, in order to reliably expose drift layer 11 at the bottom of grooves 20.

[0038] In addition, by adjusting the dry etching conditions, etching is performed so that the side surfaces of the grooves 20 are inclined. The angle of inclination can be controlled by controlling the etching method, etching gas, etc. The side surfaces of the grooves 20 may be flat, but can also be curved as shown in Figure 2 depending on the etching conditions. Furthermore, by using isotropic etching or etching similar to isotropy (etching with little anisotropy), the bottom and side surfaces of the grooves 20 can be made bowl-shaped as shown in Figure 3. Note that the formation of the grooves 20 is not limited to dry etching, and wet etching can also be used.

[0039] Next, the burying layer 13 is regrown by MOCVD while leaving the mask 24 used to form the trench 20 (see FIG. 4(c)). The presence of the mask 24 allows selective growth on the bottom surface of the trench 20. After the growth is complete, the mask 24 is removed. Because the trench 20 formed in FIG. 4(b) is exposed to the atmosphere before being placed in the MOCVD apparatus, unintended high-concentration Si impurities adhere to the GaN surface of the trench 20. During the subsequent regrowth of the burying layer 13, the high-concentration Si is not removed even by heating in the MOCVD apparatus, and a high-concentration Si remains at the regrowth interface 21 (the bottom and side surfaces of the trench 20). The high-concentration Si at the regrowth interface 21 affects the breakdown voltage of the semiconductor device of the first embodiment, as described below.

[0040] Next, a channel layer 14 is regrown on the p-type layer 12 and the buried layer 13 by MOCVD, and a contact layer 15 is regrown on the channel layer 14 (see FIG. 5(a)). Here, in the step of FIG. 4(c), when the GaN surface is removed from the MOCVD apparatus and the mask 24 is removed, high concentrations of Si impurities are unintentionally deposited on the surfaces of the buried layer 13 and the p-type layer 12. When the channel layer 14 is subsequently regrown, the high concentration of Si is not removed by heating in the MOCVD apparatus, and a high concentration of Si remains at the regrowth interface 22 (the surfaces of the p-type layer 12 and the buried layer 13). As will be described later, the regrowth interface 21 affects the breakdown voltage, whereas the regrowth interface 22 does not.

[0041] Next, a patterned hard mask such as SiO2 is formed on the contact layer 15 (not shown), and a portion of the contact layer 15 that is above the buried layer 13 is dry-etched until the buried layer 13 is exposed, thereby forming a trench 23 (see FIG. 5(b)). Thereafter, the hard mask is removed using HF or the like.

[0042] Next, the gate insulating film 16 is formed continuously on the bottom and side surfaces of the trench 23 and on the surface of the contact layer 15 by CVD or ALD (see FIG. 5(c)).

[0043] Next, a gate electrode 17 is formed on the gate insulating film 16 by sputtering, and then a hard mask is formed on part of the gate electrode 17, and the rest is removed using a metal etcher, leaving only the area corresponding to the top of the trench 23 (see Figure 5(d)).

[0044] Next, the region of the gate insulating film 16 on which the gate electrode 17 is not formed is removed by etching, and a source electrode 18 is formed in a predetermined region on the surface of the contact layer 15 by sputtering and lift-off. Next, a drain electrode 19 is formed on the back surface of the substrate 10 by sputtering. In this way, the semiconductor element of the first embodiment is manufactured.

[0045] In the semiconductor element of the first embodiment, the side surfaces of the trenches 20 are inclined, which makes it possible to suppress a decrease in breakdown voltage due to over-etching of the trenches 20. The reason for this will be explained based on the results of a simulation.

[0046] (Experiment 1) The impact ionization distribution and breakdown voltage were determined by simulation for Comparative Example 1, Comparative Example 2, and Example 1. Example 1 has the same structure as the semiconductor element of the first embodiment, in which the side surfaces of the grooves 20 are inclined and the grooves 20 are over-etched (FIG. 1). Comparative Example 1 is a modification of Example 1 in which the side surfaces of the grooves 20 are vertical and there is no over-etching in the grooves 20 (in which the depth of the grooves 20 is the same as the thickness of the p-type layer 12), and is otherwise the same as Example 1. Comparative Example 2 is a modification of Example 1 in which the side surfaces of the grooves 20 are vertical and there is over-etching in the grooves 20, and is otherwise the same as Example 1.

[0047] The conditions for each layer were set as follows: the thickness of the p-type layer 12 was 0.3 μm, the thickness of the channel layer 14 was 0.7 μm, and the thickness of the contact layer 15 was 0.2 μm. The acceptor concentrations of the p-type layer 12 and the channel layer 14 were 6×10 18 cm -3 The donor concentration of the drift layer 11 and the buried layer 13 was 1×10 15 cm -3 , the donor concentration of the contact layer 15 is 5×10 18 cm -3 The donor concentration at the regrowth interfaces 21 and 22 was 5×10 18 cm -3 The depth of the groove 20 in Comparative Example 1 was 0.3 μm with no over-etching, while the depth of the groove 20 in Comparative Example 2 and Example 1 was 0.4 μm, i.e., the amount of over-etching was 0.1 μm. The inclination angle of the side surface of the groove 20 in Example 1 was 45°.

[0048] 6 to 8 are graphs showing the Id-Vds characteristics of Comparative Example 1, Comparative Example 2, and Example 1, respectively. Id is the drain current, and Vds is the drain-source voltage. The gate voltage is 0 V. As shown in FIGS. 6 and 7, Comparative Example 2, which has over-etching, exhibits a breakdown voltage (drain-source voltage Vds when the drain current Id starts to flow) that is reduced to approximately half that of Comparative Example 1, which does not have over-etching. Furthermore, as shown in FIGS. 6 to 8, Example 1, which has a slope in the groove 20, exhibits a breakdown voltage that is higher than that of Comparative Example 2 and is equivalent to that of Comparative Example 1, despite the presence of over-etching. In other words, it was found that Example 1 can suppress the reduction in breakdown voltage due to over-etching of the groove 20 to almost zero.

[0049] 9 to 11 are graphs showing the distribution of impact ionization intensity in the device cross section for Comparative Example 1, Comparative Example 2, and Example 1, respectively. Vds was set to 1200 V, and the gate voltage was set to 0 V. As in Comparative Examples 1 and 2 and Example 1, it was found that the impact ionization region (a region with strong impact ionization intensity) extends obliquely downward from the corner of the p-type layer 12 (the side surface of the trench 20, which is the interface between the drift layer 11 and the p-type layer 12) toward the trench 23. In Comparative Example 2, because the side surface of the trench 20 is vertical, the obliquely extending impact ionization region extends over the corner of the trench 20 and over the regrowth interface 21. On the other hand, in Comparative Example 1, because there is no over-etching, the bottom surface of the trench 20 and the surface of the drift layer 11 are flush with each other, and the impact ionization region does not extend over the regrowth interface 21. Furthermore, in Example 1, because the side surface of the trench 20 is inclined, the impact ionization region does not extend over the corner of the trench 20 and does not overlie the regrowth interface 21. Therefore, it is believed that the impact ionization region overlaps with the regrowth interface 21, which is the cause of the decrease in breakdown voltage.

[0050] It should be noted that the impact ionization region does not affect the regrowth interface 22 in any of Comparative Examples 1 and 2 and Example 1, and therefore it is considered that over-etching does not affect the decrease in breakdown voltage.

[0051] (Experiment 2) The dependence of the breakdown voltage of Example 1 on the taper angle of the side surface of the trench 20 was determined by simulation. Fig. 12 is a graph showing the results. As shown in Fig. 12, the breakdown voltage increases as the inclination angle θ of the side surface of the trench 20 decreases from 90° to 45°, and the breakdown voltage becomes almost constant when the angle is 45° or less. This indicates that it is preferable to set the inclination angle of the side surface of the trench 20 to 45°. This is thought to be because when the inclination angle is 45° or less, there is almost no overlap between the impact ionization region and the regrowth interface 21.

[0052] (Second embodiment) 13 is a diagram showing the configuration of a semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is a planar vertical MISFET, and includes a substrate 210, a drift layer 211, a channel layer 214, a buried layer 213, a contact layer 215, a gate insulating film 216, a gate electrode 217, a source electrode 218, and a drain electrode 219.

[0053] The substrate 210 is similar to the substrate 10. The drift layer 211 is provided on the substrate 210. The drift layer 211 has an n - The channel layer 214 is formed on the drift layer 211. The channel layer 214 is formed of p-GaN.

[0054] Grooves 220 are provided in a partial region of channel layer 214. Grooves 220 have a depth that reaches from channel layer 214 to drift layer 211, and is 10 to 100 μm deeper than the surface of drift layer 211. Drift layer 211 is exposed at the bottom of groove 220. Furthermore, drift layer 211 and channel layer 214 are exposed on the side surfaces of groove 220, in that order from the bottom side.

[0055] The side surfaces of the groove 220 are inclined. This inclination can suppress a decrease in the breakdown voltage of the groove 220 due to over-etching, as in the first embodiment. Various modifications of the groove 20 in the first embodiment can also be applied to the groove 220. For example, as shown in FIG. 14, the side surfaces of the groove 220 may be curved.

[0056] The buried layer 213 is provided so as to fill the trench 220. The thickness of the buried layer 213 is equal to the depth of the trench 220. The buried layer 213 has a thickness of n - The buried layer 213 is a regrown layer, and the interface between the buried layer 213 and the trench 20 (the bottom and side surfaces of the trench 220) is called a regrowth interface 221. The Si concentration of the regrowth interface 221 is 1×10 18 / cm 3 The Si concentration is higher than that of the drift layer 211 and the buried layer 213.

[0057] A groove 225 is provided in a partial region of the channel layer 214, which is spaced apart from the groove 220. The depth of the groove 225 is such that it does not penetrate the channel layer 214.

[0058] The contact layer 215 is provided so as to fill the groove 225. The thickness of the contact layer 215 is equal to the depth of the groove 225. The contact layer 215 has an n + The contact layer 215 is a regrown layer, and the interface between the contact layer 215 and the trench 225 (the bottom and side surfaces of the trench 225) is called a regrowth interface 222. The Si concentration of the regrowth interface 222 is 1×10 18 / cm 3 This regrowth interface 222 does not affect the decrease in breakdown voltage due to over-etching of the trench 220.

[0059] The gate insulating film 216 is provided over the buried layer 213 , the channel layer 214 , and the contact layer 215 .

[0060] The gate electrode 217 is provided on the gate insulating film 216 at a position corresponding to the upper part of the buried layer 213, the channel layer 214, and the contact layer 215. The source electrode 218 is provided on the contact layer 215. The drain electrode 219 is provided on the back surface of the substrate 10.

[0061] As described above, in the semiconductor element of the second embodiment, the side surfaces of the trenches 220 are inclined, and therefore, similar to the semiconductor element of the first embodiment, it is possible to suppress a decrease in the breakdown voltage due to over-etching of the trenches 220. That is, due to the inclination of the side surfaces of the trenches 220, the impact ionization region extending obliquely downward from the corners of the channel layer 214 (the side surfaces of the trenches 220, which are the interfaces between the drift layer 211 and the channel layer 214) does not reach the regrowth interface 221, and therefore it is possible to suppress a decrease in the breakdown voltage.

[0062] (Variation) Although the first embodiment is a trench-type vertical MISFET and the second embodiment is a planar-type vertical MISFET, the present invention is not limited to these semiconductor devices. The present invention can be applied to any vertical semiconductor device having a structure in which a partial region of a p-type Group III nitride semiconductor layer formed on an n-type Group III nitride semiconductor layer is etched to form a trench that reaches deeper than the surface of the n-type Group III nitride semiconductor layer, and then an n-type Group III nitride semiconductor is regrown to fill the trench. For example, the present invention can also be applied to vertical IGBTs, vertical HFETs, vertical JFETs, etc. [Industrial Applicability]

[0063] The present invention can be used in power devices for power conversion, etc. [Explanation of symbols]

[0064] 10, 210: Substrate 11, 211: Drift layer 12:p-type layer 13, 213: Embedding layer 14, 214: Channel layer 15, 215: Contact layer 16, 216: Gate insulating film 17, 217: gate electrode 18, 218: Source electrode 19, 219: Drain electrode 20, 220: Groove 21, 22, 221, 222: Regrowth interface 23: Trench

Claims

1. A vertical semiconductor device made of a group III nitride semiconductor, an n-type first semiconductor layer; a p-type second semiconductor layer provided on the first semiconductor layer; a groove provided in a partial region of the second semiconductor layer, the groove having a depth that penetrates the second semiconductor layer and reaches a position deeper than the surface of the first semiconductor layer; a regrown n-type third semiconductor layer provided so as to fill the trench; and a side surface of the groove has a slope such that a cross-sectional area of ​​the groove in a plane parallel to the major surface of the first semiconductor layer increases from a bottom surface of the groove toward an upper surface thereof; The inclination angle of the side surface of the groove is set so that the inclination angle increases from the bottom surface of the groove toward the top surface. A semiconductor element characterized by:

2. 2. The semiconductor device according to claim 1, wherein the inclination angle of the side surface of the groove is 45 degrees or less.

3. 3. The semiconductor device according to claim 1, wherein the inclination angle of the side surface of the groove changes continuously.

4. 4. The semiconductor device according to claim 3, wherein the bottom and side surfaces of the groove are continuously curved surfaces.

5. A method for manufacturing a vertical semiconductor device made of a Group III nitride semiconductor, comprising: forming a p-type second semiconductor layer on an n-type first semiconductor layer; forming a groove in a partial region of the second semiconductor layer, the groove having a depth penetrating the second semiconductor layer and reaching a position deeper than the surface of the first semiconductor layer; regrowing an n-type third semiconductor layer so as to fill the trench; and The groove is formed so that a side surface of the groove has an inclination such that a cross-sectional area of ​​the groove in a plane parallel to the main surface of the first semiconductor layer increases from a bottom surface of the groove toward an upper surface thereof, and the inclination angle of the side surface of the groove increases from the bottom surface of the groove toward an upper surface thereof. A method for manufacturing a semiconductor device comprising the steps of:

6. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the groove is formed so that the inclination angle of the side surface of the groove is 45 degrees or less.

7. 7. The method for manufacturing a semiconductor device according to claim 5, wherein the groove is formed so that the inclination angle of the side surface of the groove changes continuously.

8. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the groove is formed so that the bottom and side surfaces of the groove are continuously curved.

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