Semiconductor Devices

Abstract

To provide a semiconductor device capable of improving short-circuit resistance.SOLUTION: A semiconductor device comprises a first electrode, a first semiconductor region, a gate electrode, a second semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of a first conductivity type, a fifth semiconductor region of the first conductivity type, and a second electrode. The first semiconductor region includes a first region of the first conductivity type. The gate electrode is provided on the first semiconductor region. The second semiconductor region faces the gate electrode in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region. The third semiconductor region is provided between the first semiconductor region and the second semiconductor region in the first direction. A width at a lower part of the third semiconductor region is longer than that at an upper part of the third semiconductor region. The fourth semiconductor region is provided between the third semiconductor region and the gate electrode, having an impurity concentration of the first conductivity type higher than that of the first region. The fifth semiconductor region is provided on the second semiconductor region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used for power conversion, etc. There is a demand for technology that can improve the short-circuit resistance of semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-27138 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor device capable of improving short-circuit resistance. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region, a gate electrode, a second semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of a first conductivity type, a fifth semiconductor region of the first conductivity type, and a second electrode. The first semiconductor region is provided on the first electrode and includes a first region of the first conductivity type. The gate electrode is provided on the first semiconductor region via a gate insulating layer. The second semiconductor region faces the gate electrode via the gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region. The third semiconductor region is provided between the first semiconductor region and the second semiconductor region in the first direction. The length of a lower portion of the third semiconductor region in the second direction is longer than the length of an upper portion of the third semiconductor region in the second direction. The fourth semiconductor region is provided between the third semiconductor region and the gate electrode and has a higher impurity concentration of the first conductivity type than the first region. The fifth semiconductor region is provided on the second semiconductor region. The second electrode is provided on the second semiconductor region and the fifth semiconductor region. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a perspective cross-sectional view showing a part of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is an enlarged cross-sectional view of a part of FIG. [Figure 3] 1A to 1C are cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment. [Figure 4] 1A to 1C are cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment. [Figure 5] 1A to 1C are cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment. [Figure 6] FIG. 10 is a perspective cross-sectional view showing a part of a semiconductor device according to a first modified example of the embodiment. [Figure 7] FIG. 10 is a perspective cross-sectional view showing a part of a semiconductor device according to a second modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In addition, in the present specification and each drawing, elements similar to those already explained are given the same reference numerals, and detailed explanations will be omitted as appropriate. In the following description and drawings, n + , n, n - and p + The notation "p" indicates the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation with neither "+" nor "-" attached, and a notation with "-" indicates a relatively lower impurity concentration than a notation with neither attached. When both p-type and n-type impurities are contained in each region, these notations indicate the relative level of the net impurity concentration after the impurities compensate for each other. In each of the embodiments described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0008] FIG. 1 is a perspective cross-sectional view showing a part of a semiconductor device according to an embodiment. 1, the semiconductor device 100 according to the embodiment is a MOSFET. As shown in FIG. 1, the semiconductor device 100 according to the embodiment includes a semiconductor region 1 (first semiconductor region), a p-type (second conductivity type) base region 2 (second semiconductor region), a p-type semiconductor region 3 (third semiconductor region), an n-type (first conductivity type) semiconductor region 4 (fourth semiconductor region), and an n-type (first conductivity type) semiconductor region 5 (fourth semiconductor region). + source region 5 (fifth semiconductor region), p + Shape contact area 6, n + The semiconductor device includes a drain region 7, a gate electrode 10, a drain electrode 21 (first electrode), and a source electrode 22 (second electrode).

[0009] An XYZ Cartesian coordinate system is used to explain the embodiments. The direction from the drain electrode 21 toward the semiconductor region 1 is defined as the Z direction (first direction). A direction perpendicular to the Z direction is defined as the X direction (second direction). A direction perpendicular to the X and Z directions is defined as the Y direction (third direction). Here, the direction from the drain electrode 21 toward the semiconductor region 1 is referred to as "up," and the opposite direction is referred to as "down." These directions are based on the relative positional relationship between the drain electrode 21 and the semiconductor region 1 and are unrelated to the direction of gravity.

[0010] The drain electrode 21 is provided on the bottom surface of the semiconductor device 100. + The n-type drain region 7 is provided on the drain electrode 21 and is electrically connected to the drain electrode 21. + The gate electrode 10 is provided on the semiconductor region 1 with a gate insulating layer 11 interposed therebetween. The semiconductor region 1 includes an n-type first region 1a. In the semiconductor device 100 according to this embodiment, the first region 1a is provided over the entire semiconductor region 1. The n-type impurity concentration of the first region 1a is n + The first region 1a has an n-type impurity concentration lower than that of the n-type drain region 7. + The semiconductor layer 1 is electrically connected to the drain electrode 21 via the drain region 7 .

[0011] The p-type base region 2 is provided above the semiconductor region 1 and faces the gate electrode 10 in the X direction via a gate insulating layer 11. The p-type semiconductor region 3 is provided between the semiconductor region 1 and the p-type base region 2 in the Z direction. The n-type semiconductor region 4 is provided between the p-type semiconductor region 3 and the gate electrode 10 and between the first region 1a and the gate electrode 10. + Shape source region 5 and p + The p-type contact region 6 is selectively provided on the p-type base region 2. In the example shown in the figure, the gate electrode 10 is connected in the X direction to a part of the n-type semiconductor region 4 and the n-type semiconductor region 5 via the gate insulating layer 11. + The first region 1a of the semiconductor region 1 also faces a part of the n-type source region 5.+ between the drain region 7 and the gate electrode 10 and + The n-type semiconductor region 3 is located between the n-type drain region 7 and the p-type semiconductor region 3 .

[0012] The source electrode 22 is + Shape source region 5 and p + provided on the contact region 6, + Shape source region 5 and p + The p-type base region 2 is electrically connected to the p-type contact region 6. + The gate electrode 10 is electrically connected to the source electrode 22 via the contact region 6. The gate electrode 10 is electrically isolated from the source electrode 22 by the gate insulating layer 11.

[0013] FIG. 2 is an enlarged cross-sectional view of a part of FIG. As shown in FIG. 2, in the p-type semiconductor region 3, the width W2 of the lower portion is longer than the width W1 of the upper portion. The "width" corresponds to the length in the X direction. In the semiconductor device 100, the lower end of the p-type semiconductor region 3 (the interface between the semiconductor region 1 and the p-type semiconductor region 3) is located below the lower end of the gate electrode 10. The width of the lower portion of the p-type semiconductor region 3 increases downward, and a part of the p-type semiconductor region 3 is located below the gate insulating layer 11.

[0014] The n-type semiconductor region 4 is in contact with the first region 1a and the gate insulating layer 11. The n-type impurity concentration of the n-type semiconductor region 4 is higher than the n-type impurity concentration of the first region 1a. In the illustrated example, the width of the lower end of the gate electrode 10 decreases toward the bottom. The gate insulating layer 11 and the n-type semiconductor region 4 are provided with a substantially uniform thickness along the side and bottom surfaces of the gate electrode 10. The width of the lower part of the p-type semiconductor region 3 increases by the amount corresponding to the decrease in the width of the lower end of the gate electrode 10.

[0015] As shown in the figure, the n-type semiconductor region 4 is preferably provided thinly along the gate insulating layer 11. For example, the thickness of the n-type semiconductor region 4 is smaller than the width W1 or W2 of the p-type semiconductor region 3. The "thickness of the n-type semiconductor region 4" corresponds to the length of the n-type semiconductor region 4 in the normal direction to the surface of the gate insulating layer 11.

[0016] 2, the p-type base region 2 may include a first portion 2a and a second portion 2b. The first portion 2a is separated from the gate insulating layer 11 in the X direction. The second portion 2b is provided between the gate insulating layer 11 and the first portion 2a and is located on the n-type semiconductor region 4. The second portion 2b is in contact with the gate insulating layer 11. The p-type impurity concentration of the second portion 2b is lower than the p-type impurity concentration of the first portion 2a. The p-type impurity concentration of the p-type semiconductor region 3 is lower than the p-type impurity concentration of the first portion 2a and higher than the p-type impurity concentration of the second portion 2b.

[0017] p-type base region 2, p-type semiconductor region 3, n-type semiconductor region 4, n + Shape source area 5, p + The contact region 6 and the gate electrode 10 each extend in the Y direction, and a plurality of them are provided in the X direction. The p-type semiconductor region 3 is located between adjacent n-type semiconductor regions 4 in the X direction. The width of the p-type semiconductor region 3 corresponds to the length in the X direction from the boundary between one n-type semiconductor region 4 and the p-type semiconductor region 3 to the boundary between another n-type semiconductor region 4 and the p-type semiconductor region 3 adjacent to that n-type semiconductor region 4.

[0018] The operation of the semiconductor device 100 will now be described. With a positive voltage applied to the drain electrode 21 relative to the source electrode 22, a voltage equal to or greater than the threshold is applied to the gate electrode 10. This forms a channel (inversion layer) in the p-type base region 2, turning the semiconductor device 100 on. Electrons flow from the source electrode 22 through the channel to the n-type semiconductor region 4 and move toward the drain electrode 21. When the voltage applied to the gate electrode 10 becomes lower than the threshold, the channel in the p-type base region 2 disappears, turning the semiconductor device 100 off.

[0019] An example of the material of each component of the semiconductor device 100 will be described. Semiconductor region 1, p-type base region 2, p-type semiconductor region 3, n-type semiconductor region 4, n + Shape source area 5, p +shaped contact region 6, and n + The n-type drain region 7 includes a semiconductor material. The semiconductor material may be silicon carbide, silicon, gallium nitride, or gallium arsenide. The n-type impurity may be arsenic, phosphorus, or antimony. The p-type impurity may be boron.

[0020] The gate insulating layer 11 includes an electrically insulating material. For example, the gate insulating layer 11 includes silicon oxide, silicon nitride, or silicon oxynitride. The gate electrode 10 includes a conductive material such as polysilicon. The gate electrode 10 may be doped with n-type or p-type impurities. The drain electrode 21 and the source electrode 22 include a metal such as titanium, tungsten, or aluminum.

[0021] 3 to 5 are cross-sectional views showing the manufacturing process of the semiconductor device according to the embodiment. An example of a method for manufacturing the semiconductor device 100 according to the embodiment will be described with reference to FIGS. + A semiconductor substrate including a semiconductor layer 7x is prepared. + On the semiconductor layer 7x, n is epitaxially grown. - As shown in FIG. 3(a), an n-type semiconductor layer 1x is formed by ion implantation. - A p-type semiconductor region 2x and a p-type semiconductor region 3x are formed on the upper portion of the n-type semiconductor layer 1x. - The p-type semiconductor region 3x is formed at a position away from the upper surface of the n-type semiconductor layer 1x. - The p-type semiconductor region 2x is located between the p-type semiconductor layer 1x and the p-type semiconductor region 2x. The p-type impurity concentration of the p-type semiconductor region 2x is higher than the p-type impurity concentration of the p-type semiconductor region 3x.

[0022] On the p-type semiconductor region 2x, n-type impurities matter p-type impurity Things Sequential ion implantation, n + Semiconductor regions 5x and p + As shown in FIG. 3(b), the n-type semiconductor region 6x is formed by reactive ion etching (RIE). +A trench T is formed through the semiconductor region 5x. The trench T has an n - The semiconductor layer 1x has not yet been reached.

[0023] As shown in Figure 4(a), the inner surface of the trench T is covered with n-type impurities. Things Ion implantation is performed. The conductivity type of part of the p-type semiconductor region 3x changes from p-type to n-type, and an n-type semiconductor region 4x is formed along the inner surface of the trench T. The p-type semiconductor region 2x has a higher p-type impurity concentration than the p-type semiconductor region 3x. Therefore, the conductivity type of the p-type semiconductor region 2x does not change during the ion implantation to form the n-type semiconductor region 4x. As a result of this ion implantation, the p-type impurity concentration in the part of the p-type semiconductor region 2x adjacent to the trench T becomes lower than the p-type impurity concentration in the part of the p-type semiconductor region 2x away from the trench T.

[0024] An insulating layer 11x is formed along the inner surface of the trench T and the upper surface of each semiconductor region by thermal oxidation. A conductive layer that fills the trench T is formed on the insulating layer 11x by chemical vapor deposition (CVD). The upper surface of the conductive layer 10x is recessed by chemical dry etching (CDE). As a result, the conductive layer 10x is formed inside the trench T, as shown in FIG. 4(b).

[0025] An insulating layer 11y is formed to cover the conductive layer 10x. Part of the insulating layer 11x and part of the insulating layer 11y are removed by RIE, and n + Semiconductor regions 5x and p + The shaped semiconductor region 6x is exposed. As shown in Fig. 5(a), a metal layer 22x is formed on the insulating layer 11y.

[0026] n + The semiconductor layer 7x is then grown to a predetermined thickness. + The lower surface of the semiconductor layer 7x is ground. + A metal layer 21x is formed under the conductive semiconductor layer 7x. Through the above steps, the semiconductor device 100 shown in FIG.

[0027] n shown in Figure 5(b) - The p-type semiconductor layer 1x corresponds to the first region 1a of the semiconductor region 1 shown in FIG. 1. The p-type semiconductor region 2x corresponds to the p-type base region 2. The p-type semiconductor region 3x corresponds to the p-type semiconductor region 3. The n-type semiconductor region 4x corresponds to the n-type semiconductor region 4. + The semiconductor region 5x is n + Corresponding to the shape source region 5. p + The semiconductor region 6x is p + corresponding to the contact area 6. + The semiconductor layer 7x is n + The conductive layer 10x corresponds to the gate electrode 10. The insulating layers 11x and 11y correspond to the gate insulating layer 11. The metal layer 21x corresponds to the drain electrode 21. The metal layer 22x corresponds to the source electrode 22.

[0028] The advantages of the embodiment will be described. When the semiconductor device 100 is connected to an external circuit, a load is connected in series to the semiconductor device 100. When the semiconductor device 100 is in an on state, a voltage drop occurs in the load, which allows the voltage applied to the semiconductor device 100 to be reduced. When a short circuit occurs in the load, a high voltage is applied to the semiconductor device 100. It is desirable that the time from when a high voltage is applied until the semiconductor device 100 is destroyed is long. In other words, it is desirable that the short-circuit resistance is high.

[0029] In the semiconductor device 100, a p-type semiconductor region 3 is provided between a semiconductor region 1 and a p-type base region 2. An n-type semiconductor region 4 is provided between the p-type semiconductor region 3 and a gate electrode 10. When the semiconductor device 100 is in an on-state, a current flows through the n-type semiconductor region 4. When a load is short-circuited and a high voltage is applied to the semiconductor device 100, a depletion layer expands from the pn junction between the p-type semiconductor region 3 and the n-type semiconductor region 4 toward the n-type semiconductor region 4. This narrows the current path. The current flowing through the semiconductor device 100 is reduced, and the temperature rise is suppressed.

[0030] In particular, in the semiconductor device 100, the width W2 of the lower portion of the p-type semiconductor region 3 is longer than the width W1 of the upper portion, and the n-type semiconductor region 4 is formed thin along the gate insulating layer 11. Therefore, when the load is short-circuited, the current path is easily narrowed, improving the short-circuit resistance. Furthermore, the n-type impurity concentration of the n-type semiconductor region 4 is higher than the n-type impurity concentration of the first region 1a. Therefore, even if the thickness of the n-type semiconductor region 4 is small, the electrical resistance in the n-type semiconductor region 4 can be reduced, and an increase in the on-resistance of the semiconductor device 100 can be suppressed. According to the embodiment, the short-circuit resistance of the semiconductor device 100 can be improved while suppressing an increase in the on-resistance of the semiconductor device 100.

[0031] 4(a), the n-type semiconductor region 4 can be formed in a self-aligned manner with respect to the trench T by ion implantation through the trench T. Even when the distance between the gate electrodes 10 is shortened and the structure of the semiconductor device 100 is miniaturized, it is possible to reduce variations in the width of the p-type semiconductor region 3, the thickness of the n-type semiconductor region 4, and the positional relationship between the p-type semiconductor region 3 and the n-type semiconductor region 4. According to the embodiment, even when the structure of the semiconductor device 100 is miniaturized, it is possible to reduce variations in short-circuit resistance and improve the reliability of the semiconductor device 100.

[0032] Preferably, the p-type base region 2 includes a first portion 2a and a second portion 2b having different p-type impurity concentrations. The second portion 2b is located between the gate insulating layer 11 and the first portion 2a. The p-type impurity concentration of the second portion 2b is lower than the p-type impurity concentration of the first portion 2a, thereby reducing the electrical resistance of the channel. The p-type impurity concentration of the first portion 2a is higher than the p-type impurity concentration of the second portion 2b, thereby suppressing a decrease in the threshold voltage for turning the semiconductor device 100 on. For example, malfunction of the semiconductor device 100 due to a decrease in the threshold voltage can be suppressed.

[0033] Furthermore, the p-type impurity concentration of the p-type semiconductor region 3 is preferably lower than the p-type impurity concentration of the first portion 2a of the p-type base region 2. The semiconductor device 100 includes a body diode consisting of the first region 1a and the p-type semiconductor region 3. If the p-type impurity concentration of the p-type semiconductor region 3 is lower than the p-type impurity concentration of the first portion 2a of the p-type base region 2, changes in the impurity concentration near the pn junction between the first region 1a and the p-type semiconductor region 3 can be suppressed. For example, when the body diode of the semiconductor device 100 operates during switching, changes in the capacitance of the body diode are gradual, thereby reducing noise. In other words, the operation of the body diode can be more stabilized.

[0034] (First Modification) FIG. 6 is a cross-sectional view showing a part of a semiconductor device according to a first modification of the embodiment. The semiconductor device 110 shown in FIG. 6 has a different n + As shown in FIG. + The n-type source region 5 includes a third portion 5c and a fourth portion 5d. The third portion 5c is separated from the gate insulating layer 11 in the X direction and is located on the first portion 2a. The fourth portion 5d is provided between the gate insulating layer 11 and the third portion 5c and is located on the n-type semiconductor region 4 and the second portion 2b. The fourth portion 5d is in contact with the gate insulating layer 11. The n-type impurity concentration of the fourth portion 5d is higher than the n-type impurity concentration of the third portion 5c.

[0035] n + The source region 5 may further include a fifth portion 5e. The third portion 5c and the fourth portion 5d are located between the gate insulating layer 11 and the fifth portion 5e in the X direction. The fifth portion 5e contacts the source electrode 22. The n-type impurity concentration of the fifth portion 5e is higher than the n-type impurity concentration of the third portion 5c and higher than the n-type impurity concentration of the fourth portion 5d. As shown in the figure, the length of the fifth portion 5e in the Z direction may be shorter than the lengths of the third portion 5c and the fourth portion 5d in the Z direction.

[0036] When the n-type impurity concentration of the third portion 5c is lower than the n-type impurity concentrations of the fourth portion 5d and the fifth portion 5e, the electrical resistance of the third portion 5c is higher than the electrical resistance of the fourth portion 5d and the fifth portion 5e. + Compared to the case where the n-type impurity concentration of the entire source region 5 is reduced, the increase in the on-resistance is suppressed and the n-type impurity concentration is reduced during a short circuit. + Therefore, the current flowing through the source region 5 can be suppressed.

[0037] Also, n + The source region 5 includes the fifth portion 5e, + This reduces the electrical resistance between the source region 5 and the source electrode 22. This further reduces the on-resistance of the semiconductor device 110.

[0038] (Second Modification) FIG. 7 is a perspective cross-sectional view showing a part of a semiconductor device according to a second modification of the embodiment. The semiconductor device 120 shown in FIG. 7 has a different structure of the semiconductor region 1 compared to the semiconductor device 100. As shown in FIG. 7, the semiconductor region 1 includes second regions 1b of a second conductivity type. The first regions 1a and the second regions 1b are alternately provided in the X direction. Each of the first regions 1a and each of the second regions 1b extends in the Y direction.

[0039] A portion of the n-type semiconductor region 4 is located on and in contact with the first region 1a. The p-type semiconductor region 3 is located on and in contact with the second region 1b. The p-type impurity concentration of the p-type semiconductor region 3 is higher than the p-type impurity concentration of the second region 1b. For example, the width of the second region 1b is wider than the width of the first region 1a and wider than the width of the upper portion of the p-type semiconductor region 3.

[0040] When a high voltage is applied to the semiconductor device 120, a depletion layer spreads not only from the pn junction between the p-type semiconductor region 3 and the n-type semiconductor region 4 but also from the pn junction between the first region 1a and the second region 1b. Not only the current path in the n-type semiconductor region 4 but also the current path in the first region 1a is narrowed. According to the second modification, the short-circuit resistance of the semiconductor device 120 can be further improved compared to the semiconductor device 100.

[0041] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0042] 1: Semiconductor region, 1a: First region, 1b: Second region, 1x:n - type semiconductor layer, 2: p type base region, 2a: first part, 2b: second part, 2x,3,3x:p type semiconductor region, 4,4x:n semiconductor region, 5:n + Shape source area, 5c: third part, 5d: fourth part, 5e: fifth part, 5x: n + Shape semiconductor area, 6:p + Shape contact area, 6x:p + Shape semiconductor area, 7:n + Shaped drain region, 7x:n + Semiconductor layer, 10: gate electrode, 10x: conductive layer, 11: gate insulating layer, 11x, 11x: insulating layer, 21: drain electrode, 21x: metal layer, 22: source electrode, 22x: metal layer, 100-120: semiconductor device, T: trench

Claims

1. A first electrode; a first semiconductor region provided on the first electrode and including a first region of a first conductivity type; a gate electrode provided on the first semiconductor region via a gate insulating layer; a second semiconductor region of a second conductivity type facing the gate electrode via the gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region; a third semiconductor region of the second conductivity type provided between the first semiconductor region and the second semiconductor region in the first direction, the third semiconductor region having a lower portion whose length in the second direction is longer than a top portion whose length in the second direction is longer; a fourth semiconductor region of the first conductivity type provided between the third semiconductor region and the gate electrode and having a higher impurity concentration of the first conductivity type than the first region; a fifth semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided on the second semiconductor region and the fifth semiconductor region; Equipped with The second semiconductor region is a first portion spaced apart from the gate insulating layer in the second direction; a second portion provided between the gate insulating layer and the first portion and positioned above the fourth semiconductor region; Including, a second portion having a lower impurity concentration of the second conductivity type than a first portion having a lower impurity concentration of the second conductivity type than a third semiconductor region having a lower impurity concentration of the second conductivity type;

2. The fifth semiconductor region is a third portion spaced apart from the gate insulating layer in the second direction; a fourth portion provided between the gate insulating layer and the third portion and located above the fourth semiconductor region; Including, 2. The semiconductor device according to claim 1, wherein the fourth portion has a higher impurity concentration of the first conductivity type than the third portion.

3. the fifth semiconductor region further includes a fifth portion; the third portion and the fourth portion are located between the gate insulating layer and the fifth portion in the second direction, 3. The semiconductor device according to claim 2, wherein the fifth portion has a higher impurity concentration of the first conductivity type than the third portion.

4. the first semiconductor region further includes a second region of a second conductivity type; 4. The semiconductor device according to claim 1, wherein the first regions and the second regions are provided alternately in the second direction.

5. the third semiconductor region is in contact with one of the second regions; The semiconductor device according to claim 4 , wherein said fourth semiconductor region is in contact with one of said plurality of first regions.

6. 6. The semiconductor device according to claim 1, wherein a lower end of said third semiconductor region is located lower than a lower end of said gate electrode.

7. 7. The semiconductor device according to claim 1, wherein a portion of said third semiconductor region is located below said gate insulating layer.

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