Semiconductor device and data storage system including the same

Abstract

To provide a semiconductor device with improved integration degree and reliability, and a data storage system including the same.SOLUTION: In a semiconductor device 10, a cell region CR includes a peripheral circuit region PERI including a circuit element 20 provided on a first substrate 11, and a memory cell region CELL disposed on the peripheral circuit region. The memory cell region includes a second substrate 101 on the peripheral circuit region, a memory stack structure including a first stack structure GS1 including a first gate electrode 130 and a first interlayer insulating layer 120 stacked alternately on the second substrate and a second stack structure GS2 including a second gate electrode 230 and a second interlayer insulating layer 220 stacked alternately on the first stack structure, and a channel structure CH connected to the second substrate penetrating the memory stack structure vertically and including a channel layer.SELECTED DRAWING: Figure 2a

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a data storage system including the same. [Background technology]

[0002] In data storage systems that require data storage, semiconductor devices capable of storing large amounts of data are in demand. Accordingly, methods for increasing the data storage capacity of semiconductor devices have been researched. For example, as one method for increasing the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally arranged memory cells has been proposed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-112363 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the prior art, and an object of the present invention is to provide a semiconductor device with improved integration density and reliability. Another object of the present invention is to provide a data storage system including a semiconductor device with improved integration and reliability. [Means for solving the problem]

[0005] In order to achieve the above object, a semiconductor device according to one aspect of the present invention includes a first substrate, a peripheral circuit region including circuit elements provided on the first substrate, and a memory cell region disposed on the peripheral circuit region, wherein the memory cell region includes a second substrate on the peripheral circuit region, a memory stack structure including: a first stack structure including first gate electrodes and first interlayer insulating layers alternately stacked on the second substrate, and a second stack structure including second gate electrodes and second interlayer insulating layers alternately stacked on the first stack structure; and a channel structure vertically penetrating the memory stack structure and connected to the second substrate, the channel structure including a channel layer. The semiconductor device includes a first dummy structure disposed on the second substrate at a distance from at least one side of the first stacked structure and including first and second insulating layers that are alternately stacked; a second dummy structure disposed on the first dummy structure at a distance from at least one side of the second stacked structure and including third and fourth insulating layers that are alternately stacked; a first capping insulating layer covering the first stacked structure and the first dummy structure; and a second capping insulating layer covering the second stacked structure and the second dummy structure, wherein at least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction.

[0006] In order to achieve the above object, a semiconductor device according to one aspect of the present invention includes a first substrate, a peripheral circuit region including circuit elements provided on the first substrate, a second substrate disposed on the peripheral circuit region, a memory cell structure disposed on the second substrate, and a dummy structure disposed on at least one side of the memory cell structure on the second substrate, wherein the memory cell structure includes a first stacked structure including first gate electrodes and first interlayer insulating layers alternately stacked on the second substrate, a second stacked structure including second gate electrodes and second interlayer insulating layers alternately stacked on the first stacked structure, and a dummy structure disposed on the first stacked structure and a front and a channel structure connected to the second substrate through the second laminated structure, wherein the dummy structure includes a first dummy structure disposed on the second substrate at a distance from the first laminated structure and including alternatingly stacked first and second insulating layers, and a second dummy structure disposed on the second substrate at a distance from the second laminated structure and the first dummy structure and including alternatingly stacked third and fourth insulating layers, wherein a central axis between side surfaces of the second dummy structure is shifted from a central axis between side surfaces of the first dummy structure in at least one direction parallel to the top surface of the second substrate.

[0007] In order to achieve the above object, a data storage system according to one aspect of the present invention includes a first substrate, a peripheral circuit region including circuit elements provided on the first substrate, a second substrate disposed on the peripheral circuit region, a memory cell structure disposed on the second substrate, a dummy structure disposed on at least one side of the memory cell structure on the second substrate, and an input / output pad electrically connected to the circuit elements, wherein the memory cell structure includes a first stacked structure including first gate electrodes and first interlayer insulating layers alternately stacked on the second substrate, a second stacked structure including second gate electrodes and second interlayer insulating layers alternately stacked on the first stacked structure, and an input / output pad electrically connected to the second substrate through the first stacked structure and the second stacked structure. a channel structure connected to a plate, wherein the dummy structure includes a first dummy structure disposed on the second substrate at a distance from the first stacked structure and including first and second insulating layers alternately stacked, and a second dummy structure disposed on the second substrate at a distance from the second stacked structure and the first dummy structure and including third and fourth insulating layers alternately stacked, wherein a central axis between side surfaces of the second dummy structure is shifted in at least one direction parallel to an upper surface of the second substrate from a central axis between side surfaces of the first dummy structure; and a controller electrically connected to the semiconductor memory device via the input / output pads and controlling the semiconductor memory device. [Effects of the Invention]

[0008] According to the present invention, when dummy structures are arranged apart from the stacked structure forming the memory cell, the lower first dummy structure and the upper second dummy structure are arranged so as not to overlap in the vertical direction, thereby providing a semiconductor device with improved reliability and a data storage system including the same. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention; [Figure 2a]1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention; [Figure 2b] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention; [Figure 3a] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention; [Figure 3b] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention; [Figure 3c] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention; [Figure 4a] 1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention; [Figure 4b] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention; [Figure 4c] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention; [Figure 5a] 1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention; [Figure 5b] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention; [Figure 6] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 7a] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 7b] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 7c] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 8a] 1 is a schematic plan view of a semiconductor device according to an embodiment; [Figure 8b] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 9a] 1 is a schematic plan view of a semiconductor device according to an embodiment; [Figure 9b] 1 is a schematic plan view of a semiconductor device according to an embodiment; [Figure 10a] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 10b] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 11a] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 11b] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 12] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 13] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 14] 1 is a schematic plan view for explaining a method for manufacturing a semiconductor device according to an embodiment; [Figure 15a] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 15b] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 15c] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 15d] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 16a] 1 is a diagram illustrating a schematic diagram of a data storage system including a semiconductor device according to one embodiment. [Figure 16b] 1 is a perspective view schematically illustrating a data storage system including a semiconductor device according to an embodiment. [Figure 17] 1 is a cross-sectional view schematically illustrating a semiconductor package according to an embodiment. [Figure 18] 1 is a cross-sectional view schematically illustrating a semiconductor package according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

[0011] FIG. 1 is a schematic plan view of a semiconductor device according to one embodiment of the present invention.

[0012] 2a and 2b are schematic cross-sectional views of a semiconductor device according to an embodiment of the present invention, taken along the lines II' and II-II' in FIG.

[0013] 1, 2a, and 2b, the semiconductor device 10 includes a memory cell region CELL and a peripheral circuit region PERI. The memory cell region CELL is arranged in the upper stage of the peripheral circuit region PERI. In one embodiment, the memory cell region CELL may be arranged in the lower stage of the peripheral circuit region PERI.

[0014] The peripheral circuit region PERI includes a first substrate 11, a circuit element 20 arranged on the first substrate 11, a circuit contact plug 70, and a circuit wiring line 80.

[0015] The first substrate 11 has a top surface extending in the x-direction and the y-direction, and includes a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor.

[0016] The first substrate 11 has a central region C1 and a guard ring region C2 surrounding the central region C1. The guard ring region C2 includes an edge region 10eg of the semiconductor device 10. The edge region 10eg is formed during the process of separating multiple semiconductor devices on a semiconductor wafer. In some embodiments, the region 10eg further includes a structure identical to the structure disposed in the scribe lane region. A guard ring structure GR, which serves as a moisture oxidation barrier structure and / or a crack stop structure, is disposed on the guard ring region C2.

[0017] Another element isolation layer is formed on the first substrate 11 to define an active region, and impurity-containing source / drain regions 30 are disposed in part of the active region.

[0018] The circuit elements 20 include planar transistors. Each circuit element 20 includes a circuit gate dielectric layer 22, a spacer layer 24, and a circuit gate electrode 25. Source / drain regions 30 are disposed in the first substrate 11 on either side of the circuit gate electrode 25.

[0019] The peripheral region insulating layer 90 is disposed on the first substrate 11 and on the circuit elements 20. The circuit contact plugs 70 penetrate the peripheral region insulating layer 90 and are connected to the source / drain regions 30. Electrical signals are applied to the circuit elements 20 through the circuit contact plugs 70. In a region not shown, the circuit contact plugs 70 are also connected to the circuit gate electrodes 25. The circuit wiring lines 80 are connected to the circuit contact plugs 70 and are disposed in multiple layers.

[0020] The memory cell region CELL includes a second substrate 101, memory cell structures MC1 and MC2, and dummy structures DS1 and DS2. The dummy structures DS1 and DS2 are disposed on at least one side of the memory cell structures MC1 and MC2 and spaced apart from the memory cell structures MC1 and MC2. The memory cell region CELL further includes capping insulating layers 190 and 290, upper insulating layers 310, 320, and 330, gate contact plugs CP1, channel contact plugs CP2, bit lines 350, and upper wirings 355.

[0021] The second substrate 101 has a cell region CR and a peripheral region CT. The cell region CR includes a cell array region CA where memory cells are formed and a connection region CB for connecting gate electrodes of the memory cells to upper wiring. The peripheral region CT is a region on at least one side of the cell region CR for connecting circuit elements 20 in the peripheral circuit region PERI to upper wiring. The connection region CB is disposed at least at one end of the cell array region CA in at least one direction, for example, the x-direction, or along the edge of the cell array region CA.

[0022] The second substrate 101 has an upper surface extending in the x-direction and the y-direction. The second substrate 101 includes a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor includes silicon, germanium, or silicon-germanium. The second substrate 101 is made of, for example, polycrystalline silicon, which may or may not contain impurities.

[0023] The memory cell structures MC1 and MC2 are arranged side by side and spaced apart from each other on the second substrate 101. However, in the embodiment, the number and arrangement of the memory cell structures MC1 and MC2 arranged in the cell region CR may be variously changed. Below, one memory cell structure MC1 will be described.

[0024] The memory cell structure MC1 includes memory stack structures GS1 and GS2, a channel structure CH, first and second conductive layers 104 and 105, and an isolation structure MS. The memory stack structures GS1 and GS2 include a first stack structure GS1 on the second substrate 101 and a second stack structure GS2 on the first stack structure GS1.

[0025] The first stacked structure GS1 includes a first gate electrode 130 and a first interlayer insulating layer 120 alternately stacked on the second substrate 101. The second stacked structure GS2 includes a second gate electrode 230 and a second interlayer insulating layer 220 alternately stacked on the first stacked structure GS1.

[0026] The first and second gate electrodes 130, 230 are disposed vertically spaced apart on the second substrate 101. The first and second gate electrodes 130, 230 include one or more lower gate electrodes, a plurality of middle gate electrodes, and one or more upper gate electrodes.

[0027] The one or more lower gate electrodes include a gate electrode of a ground selection transistor and / or a gate electrode of a lower erase control transistor. The one or more upper gate electrodes include a gate electrode of a string selection transistor and / or a gate electrode of an upper erase control transistor. The lower erase control transistor and the upper erase control transistor are transistors that use an erase operation utilizing the Gate Induced Drain Leakage (GIDL) phenomenon.

[0028] The plurality of intermediate gate electrodes are gate electrodes of memory cell transistors. Some of the upper or lower gate electrodes of the plurality of intermediate gate electrodes are dummy gate electrodes. The number of first and second gate electrodes 130, 230 constituting a memory cell is determined depending on the capacity of the semiconductor device 10.

[0029] The first and second gate electrodes 130, 230 are stacked vertically and spaced apart on the cell region CR and extend from the cell array region CA to the connection region CB at different lengths to form a stepped structure. The first and second gate electrodes 130, 230 have a stepped structure in which the lower gate electrode extends longer than the upper gate electrode, providing ends exposed to the upper part from the first and second interlayer insulating layers 120, 220.

[0030] In one embodiment, the first and second gate electrodes 130, 230 are arranged such that a certain number of gate electrodes, for example, two, four, or six gate electrodes, form a gate group, forming a stepped structure between the gate groups in the x direction, and the gate electrodes in one gate group are also arranged to have a stepped structure relative to each other in the y direction.

[0031] 2b, the first and second gate electrodes 130, 230 are separated from adjacent first and second gate electrodes 130, 230 in the y direction by a pair of isolation structures MS extending in the x direction. The first and second gate electrodes 130, 230 between the pair of isolation structures MS form one memory block, but the scope of the memory block is not limited thereto. A portion of the first and second gate electrodes 130, 230, for example, the first and second gate electrodes 130, 230 forming a memory cell, forms one layer within one memory block.

[0032] The first and second gate electrodes 130, 230 include a metal material, such as tungsten (W). According to some embodiments, the first and second gate electrodes 130, 230 include polycrystalline silicon or a metal silicide material. In one embodiment, the first and second gate electrodes 130, 230 further include a diffusion barrier. For example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0033] The first and second interlayer insulating layers 120 and 220 are disposed between the gate electrodes 130 and 230, respectively. Like the first and second gate electrodes 130 and 230, the first and second interlayer insulating layers 120 and 220 are also disposed to be spaced apart from each other in a direction perpendicular to the top surface of the second substrate 101 and to extend in at least one direction. The first and second interlayer insulating layers 120 and 220 include an insulating material such as silicon oxide or silicon nitride.

[0034] The channel structures CH each form one memory cell string and are arranged spaced apart from each other in rows and columns on the cell array region CA of the second substrate 101. The channel structures CH may be arranged in a lattice pattern or in a staggered pattern in one direction. The channel structures CH have a columnar shape and have sloping side surfaces that become thinner as they approach the second substrate 101 according to an aspect ratio. In one embodiment, dummy channels that do not actually form memory cell strings are arranged in the connection region CB and at the end of the cell array region CA adjacent to the connection region CB.

[0035] A channel layer 140 is disposed within the channel structure CH. In the channel structure CH, the channel layer 140 is annular and surrounds an internal channel insulating layer 150. However, in some embodiments, the channel layer 140 may have a columnar or rectangular columnar shape without the channel insulating layer 150. The channel layer 140 is connected to the first conductive layer 104 at its bottom. The channel layer 140 is connected to the second substrate 101. The channel layer 140 includes a semiconductor material such as polycrystalline silicon or single crystalline silicon.

[0036] In the channel structure CH, a channel pad 155 is disposed on the channel layer 140. The channel pad 155 is disposed to cover the upper surface of the channel insulating layer 150 and to be electrically connected to the channel layer 140. The channel pad 155 includes, for example, doped polycrystalline silicon.

[0037] The gate dielectric layer 145 is disposed between the first and second gate electrodes 130 and 230 and the channel layer 140. The gate dielectric layer 145 extends above the channel layer 140, and a portion of its inner surface contacts the channel pad 155. Although not shown, the gate dielectric layer 145 includes a tunneling layer, an information storage layer, and a blocking layer, which are stacked in sequence from the channel layer 140. The tunneling layer tunnels charges to the information storage layer and includes, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof. The information storage layer is a charge trap layer or a floating gate conductive layer. The blocking layer includes silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof.

[0038] The channel structure CH vertically penetrates the memory stack structures GS1 and GS2 and is connected to the second substrate 101. The channel structure CH includes first and second channel structures CH1 and CH2 that are vertically stacked, as shown in FIG. 2b.

[0039] The channel structure CH has a configuration in which a first channel structure CH1 penetrating the first stack structure GS1 and a second channel structure CH2 penetrating the second stack structure GS2 are connected to each other. As shown in the enlarged view of FIG. 2b, the connection region has a bent portion due to the difference in width. Between the first channel structure CH1 and the second channel structure CH2, the channel layer 140, the gate dielectric layer 145, and the channel insulating layer 150 are connected to each other. A channel pad 155 is disposed only on the upper end of the upper second channel structure CH2. However, in one embodiment, the first channel structure CH1 and the second channel structure CH2 each include a channel pad 155. In this case, the channel pad 155 of the first channel structure CH1 is connected to the channel layer 140 of the second channel structure CH2.

[0040] In one embodiment, the channel structure CH includes an epitaxial layer connected at its bottom end to the second substrate 101. The epitaxial layer is connected to the channel layer 140. In this case, the semiconductor device 10 may not include the first and second conductive layers 104 and 105.

[0041] The first and second conductive layers 104 and 105 are stacked on the upper surface of the second substrate 101. At least a portion of the first and second conductive layers 104 and 105 functions as a common source line of the semiconductor device 10, and functions together with the second substrate 101 as the common source line. As shown in the enlarged view of FIG. 2b, the first conductive layer 104 is directly connected to the channel layer 140 around the channel layer 140. The first and second conductive layers 104 and 105 include a semiconductor material, such as polycrystalline silicon. In this case, at least the first conductive layer 104 is a doped layer, and the second conductive layer 105 is a doped layer or a layer containing impurities diffused from the first conductive layer 104.

[0042] 2a, the first and second source sacrificial layers 111 and 112 are not replaced by the first conductive layer 104 and remain partially on the second substrate 101 in the connection region CB. The first and second source sacrificial layers 111 and 112 do not substantially function in the semiconductor device 10. In the peripheral region CT, the first and second source sacrificial layers 111 and 112 and the second conductive layer 105 are also stacked on the second substrate 101, but are not limited to this.

[0043] As shown in FIG. 2b, the isolation structure MS penetrates the memory stack structures GS1 and GS2 in a vertical direction, for example, the z direction. The isolation structure MS separates the memory stack structures GS1 and GS2 in the y direction. The isolation structure MS extends in the x direction from the cell array region CA to the connection region CB. The isolation structure MS penetrates the first and second gate electrodes 130 and 230 in the z direction and contacts the second substrate 101. The isolation structure MS is disposed by recessing a portion of the upper portion of the second substrate 101, or is disposed on the second substrate 101 so as to contact the upper surface of the second substrate 101. The isolation structure MS includes an insulating material, for example, silicon oxide, silicon nitride, or a combination thereof.

[0044] In one embodiment, the isolation structure MS includes auxiliary isolation regions that extend intermittently or are arranged only in a partial region, for example, a plurality of auxiliary isolation regions are arranged in the connection region CB at predetermined intervals in the x direction.

[0045] The dummy structures DS1 and DS2 are disposed apart from the memory cell structure MC1 on the second substrate 101. In the embodiment, the number, size, and arrangement of the dummy structures DS1 and DS2 disposed in the peripheral region CT may be variously changed.

[0046] The dummy structures DS1 and DS2 include a first dummy structure DS1 arranged at a distance from the first stacked structure GS1 on the second substrate 101, and a second dummy structure DS2 arranged at a distance from the second stacked structure GS2 on the second substrate 101. The first dummy structure DS1 is referred to as the "first insulating structure," and the second dummy structure DS2 is referred to as the "second insulating structure."

[0047] The first dummy structure DS1 includes first insulating layers 170 and second insulating layers 180 alternately stacked on the second substrate 101. The first dummy structure DS1 has a stepped structure. For example, the second insulating layers 180 extend to different lengths, forming a stepped structure. Due to the stepped structure, the second insulating layers 180 form a stepped structure in which the lower second insulating layer 180 extends longer than the upper second insulating layer 180. The first insulating layer 170 also forms a stepped structure, similar to the second insulating layer 180. Due to the stepped structure, the first dummy structure DS1 has a shape in which the width at the top is smaller than the width at the bottom.

[0048] The first dummy structure DS1 is disposed at a distance from at least one side of the first stacked structure GS1. The first dummy structure DS1 is disposed to overlap the first stacked structure GS1, for example, in the x-direction. The first dummy structure DS1 and the first stacked structure GS1 are covered by the first capping insulating layer 190. One or more first dummy structures DS1 are disposed on the second substrate 101.

[0049] Between the first dummy structure DS1 and the second substrate 101, first and second source sacrificial layers 111, 112 and a second conductive layer 105 are disposed, but are not limited thereto.

[0050] The second dummy structure DS2 includes a third insulating layer 270 and a fourth insulating layer 280 alternately stacked on the first dummy structure DS1. The second dummy structure DS2 has a stepped structure. For example, the fourth insulating layers 280 extend at different lengths to form a stepped structure. Due to the stepped structure, the fourth insulating layer 280 forms a stepped shape in which the lower fourth insulating layer 280 extends longer than the upper fourth insulating layer 280. The third insulating layer 270 also forms a stepped structure, similar to the fourth insulating layer 280. Due to the stepped structure described above, the second dummy structure DS2 has a shape in which the width at the top is smaller than the width at the bottom.

[0051] The second dummy structure DS2 is disposed at a distance from at least one side of the second stack structure GS2. The second dummy structure DS2 is disposed at a distance from the first dummy structure DS1. The second dummy structure DS2 is disposed to overlap the second stack structure GS2, for example, in the x-direction. The second dummy structure DS2, together with the first stack structure GS1, is covered by the second capping insulating layer 290. One or more second dummy structures DS2 are disposed on the first dummy structure DS1.

[0052] The first insulating layer 170 is located at a height level corresponding to the first interlayer insulating layer 120. The first insulating layer 170 has substantially the same thickness as the first interlayer insulating layer 120. The first insulating layer 170 is formed of the same material as the first interlayer insulating layer 120.

[0053] The second insulating layer 180 is located at a height level corresponding to the first gate electrode 130. The second insulating layer 180 has substantially the same thickness as the first gate electrode 130. The second insulating layer 180 is formed of a different material from the first gate electrode 130.

[0054] The third insulating layer 270 is located at a height level corresponding to the second interlayer insulating layer 220. The third insulating layer 270 has substantially the same thickness as the second interlayer insulating layer 220. The third insulating layer 270 is formed of the same material as the second interlayer insulating layer 220.

[0055] The fourth insulating layer 280 is located at a height level corresponding to the second gate electrode 230. The fourth insulating layer 280 has substantially the same thickness as the second gate electrode 230. The fourth insulating layer 280 is formed of a different material from the second gate electrode 230.

[0056] The first dummy structure DS1 does not overlap the second dummy structure DS2 in the vertical direction (for example, the z direction). The second dummy structure DS2 does not overlap the first dummy structure DS1 in the vertical direction.

[0057] The uppermost second insulating layer 180 of the first dummy structure DS1 does not overlap the second dummy structure DS2 in the vertical direction.

[0058] The top surface of the first dummy structure DS1 does not overlap with the second dummy structure DS2 in the vertical direction. The top surface of the second dummy structure DS2 does not overlap with the first dummy structure DS1 in the vertical direction. Here, the top surfaces of the first dummy structure DS1 and the second dummy structure DS2 refer to the top surfaces of the uppermost second insulating layer 180 and the uppermost fourth insulating layer 280, respectively. The top surface of the first dummy structure DS1 does not face the bottom surface of the second dummy structure DS2.

[0059] The side surfaces of the first dummy structure DS1 do not overlap with the second dummy structure DS2 in the vertical direction. Here, the side surfaces of the first dummy structure DS1 refer to the side surfaces of the first insulating layer 170 and the second insulating layer 180. In one embodiment, the side surfaces of the first dummy structure DS1 and the second dummy structure DS2 are inclined with respect to the top surface of the second substrate 101.

[0060] The top step of the first dummy structure DS1 does not overlap vertically with the second dummy structure DS2. In one embodiment, the top step of the first dummy structure DS1 does not overlap vertically with the bottom step of the second dummy structure DS2.

[0061] The lowest step of the first dummy structure DS1 does not overlap with the lowest step of the second dummy structure DS2 in the vertical direction. In one embodiment, the lowest step of the first dummy structure DS1 does not overlap with the lowest step of the second dummy structure DS2 in the vertical direction.

[0062] The central axis between the side surfaces of the second dummy structures DS2 is shifted from the central axis between the side surfaces of the first dummy structures DS1 in at least one direction parallel to the top surface of the second substrate 101, for example, the x direction.

[0063] The central axis of the first dummy structure DS1 and the central axis of the second dummy structure DS2 are spaced apart from the central axis of the memory cell structure MC1 by different distances. For example, as shown in FIG. 1, a first distance d1 between the central axis of the memory cell structure MC1 and the central axis of the first dummy structure DS1 is different from a second distance d2 between the central axis of the memory cell structure MC1 and the central axis of the second dummy structure DS2.

[0064] By disposing the first and second dummy structures DS1 and DS2, process variations of the staircase structure are minimized in the connection regions CB on both sides of the first and second stack structures GS1 and GS2 in the x direction, and dishing, in which the upper portion of the second capping insulating layer 290 is locally recessed downward toward the second substrate 101, is minimized during the planarization process of the second capping insulating layer 290.

[0065] By arranging the first and second dummy structures DS1 and DS2 so that they do not overlap in the vertical direction, it is possible to minimize variations in the planarization process of the second capping insulating layer 290 that occur when the dished portion of the second substrate 101 is transferred to the upper structure. In addition, it is possible to prevent the curved upper portions of the first and second outer insulating layers 275 and 285 (see FIG. 15b), which act as alignment keys in the process of manufacturing semiconductor devices on a semiconductor wafer basis, from being scraped off.

[0066] The capping insulating layers 190 and 290 include a first capping insulating layer 190 covering the first stack structure GS1 and the first dummy structure DS1, and a second capping insulating layer 290 covering the second stack structure GS2 and the second dummy structure DS2. The first capping insulating layer 190 and the second capping insulating layer 290 include an insulating material, for example, silicon oxide.

[0067] The first dummy structure DS1 vertically overlaps the second capping insulating layer 290. The top surface of the first dummy structure DS1 vertically overlaps the second capping insulating layer 290.

[0068] The second dummy structure DS2 overlaps the first capping insulating layer 190 in the vertical direction.

[0069] The upper insulating layers 310, 320, and 330 include a first upper insulating layer 310, a second upper insulating layer 320, and a third upper insulating layer 330 that are sequentially stacked on the second capping insulating layer 290. The upper insulating layers 310, 320, and 330 include an insulating material, for example, silicon oxide.

[0070] The gate contact plug CP1 is electrically connected to the first and second gate electrodes 130 and 230, respectively, in the connection region CB. The gate contact plug CP1 penetrates the first and second capping insulating layers 190 and 290 and the first and second upper insulating layers 310 and 320 in the connection region CB to be connected to the first and second gate electrodes 130 and 230, respectively, whose upper portions are exposed. The gate contact plug CP1 is connected to the first and second gate electrodes 130 and 230 by recessing portions of the first and second gate electrodes 130 and 230. The gate contact plug CP1 is connected to another contact plug 344 at its upper portion and to an upper interconnection 355. The gate contact plug CP1 includes a conductive material, such as tungsten (W), copper (Cu), or aluminum (Al). The gate contact plug CP1 further includes a diffusion barrier layer.

[0071] The channel contact plug CP2 is electrically connected to the channel structure CH in the cell array region CA. The channel contact plug CP2 penetrates the first to third upper insulating layers 310, 320, and 330 in the cell array region CA and is connected to the channel pad 155 of the channel structure CH. A bit line 350 is disposed on the channel contact plug CP2 and is electrically connected to the channel contact plug CP2. The channel contact plug CP2 includes a conductive material.

[0072] The upper interconnection 355 constitutes an interconnection structure electrically connected to the memory cells in the memory cell region CELL. The upper interconnection 355 is electrically connected to, for example, the first and second gate electrodes 130 and 230. The number of contact plugs and interconnection lines constituting the interconnection structure may vary depending on the embodiment. The upper interconnection 355 includes a conductive material.

[0073] The guard ring structure GR is disposed adjacent to the edge region 10eg of the semiconductor device 10. The guard ring structure GR is disposed on the guard ring region C2 of the first substrate 11. The guard ring structure GR includes a plurality of contact plugs and a plurality of wiring lines that penetrate the first and second capping insulating layers 190 and 290 and are connected to the first substrate 11. The guard ring structure GR is disposed to surround the circuit element 20 disposed on the central region C1 of the first substrate 11, the memory cell structures MC1 and MC2, and the dummy structures DS1 and DS2 disposed on the second substrate 101.

[0074] 3a, 3b, and 3c are schematic cross-sectional views of a semiconductor device according to an embodiment of the present invention. Figures 3a to 3c show cross sections corresponding to those of Figure 2a. In Figures 3a to 3c, the arrangement and number of first dummy structures DS1 and second dummy structures DS2 are different from those of the embodiment of Figure 2a.

[0075] 3a, in the semiconductor device 10a, at least two first dummy structures DS1 are arranged on the second substrate 101. The second dummy structure DS2 is arranged on the first dummy structure DS1 so as not to overlap with the first dummy structure DS1 in the vertical direction.

[0076] In FIG. 2a, there are one or more first dummy structures DS1, one or more second dummy structures DS2, and the number of second dummy structures DS2 is greater than the number of first dummy structures DS1.

[0077] In FIG. 3a, there are one or more first dummy structures DS1, one or more second dummy structures DS2, and the number of first dummy structures DS1 is greater than the number of second dummy structures DS2.

[0078] 3b, in the semiconductor device 10b, at least two first dummy structures DS1 are arranged on the second substrate 101, and at least two second dummy structures DS2 are also arranged on the first dummy structures DS1. Each of the first dummy structures DS1 does not overlap each of the second dummy structures DS2 in the vertical direction.

[0079] 3c, in a semiconductor device 10c, at least two first dummy structures DS1 are arranged closer to each other than at least two second dummy structures DS2, and the at least two first dummy structures DS1 do not overlap the at least two second dummy structures DS2 in the vertical direction.

[0080] Figure 4a is a schematic plan view of a semiconductor device according to an embodiment of the present invention, and Figures 4b and 4c are schematic cross-sectional views of a semiconductor device according to an embodiment, where Figures 4b and 4c show cross sections corresponding to Figure 2a.

[0081] 4a and 4b, in the semiconductor device 10d, the gradients of the step structures of the first dummy structure DS1a and the second dummy structure DS2a are different from those in the embodiment of FIG. 2a. The gradients of the step structures of the first dummy structure DS1a and the second dummy structure DS2a are substantially the same as the gradients of the step structures in the connection region CB of the memory cell structure MC1.

[0082] In one embodiment, a portion of the first dummy structure DS1a overlaps the second dummy structure DS2a in the vertical direction, another portion of the first dummy structure DS1a does not overlap the second dummy structure DS2a in the vertical direction, and the uppermost second insulating layer 180 of the first dummy structure DS1a does not overlap the second dummy structure DS2a in the vertical direction.

[0083] In one embodiment, a portion of the side surface of the first dummy structure DS1a overlaps with the second dummy structure DS2 in the vertical direction, and another portion of the side surface of the first dummy structure DS1a does not overlap with the second dummy structure DS2 in the vertical direction.

[0084] In one embodiment, at least a portion of the step on one side of the first dummy structure DS1a overlaps with the second dummy structure DS2a in the vertical direction, but the step on the other side of the first dummy structure DS1a does not completely overlap with the second dummy structure DS2a in the vertical direction.

[0085] However, depending on the embodiment, the first dummy structure DS1a and the second dummy structure DS2a do not completely overlap in the vertical direction.

[0086] 4a and 4c, in the semiconductor device 10e, the first dummy structure DS1a is disposed closer to the cell region CR than the second dummy structure DS2a. The first dummy structure DS1a is disposed closer to the memory cell structure MC1 than the second dummy structure DS2a. The non-overlapping portions of the first dummy structure DS1a and the second dummy structure DS2a are as described with reference to FIG. 4b.

[0087] Figure 5a is a schematic plan view of a semiconductor device according to an embodiment of the present invention, Figure 5b is a schematic cross-sectional view of a semiconductor device according to an embodiment, Figure 5b shows a cross section corresponding to Figure 2a.

[0088] 5a and 5b, in a semiconductor device 10f, a first dummy structure DS1a includes portions that vertically overlap at least two second dummy structures DS2, and in this case, a portion of the first dummy structure DS1a does not vertically overlap with the second dummy structures DS2.

[0089] However, depending on the embodiment, the first dummy structure DS1a may have a larger size or a gentler step gradient than the second dummy structure DS2, and may not completely overlap the second dummy structure DS2 in the vertical direction.

[0090] Figure 6 is a schematic cross-sectional view of a semiconductor device according to one embodiment, showing a cross section corresponding to Figure 2a.

[0091] 6, in the semiconductor device 10g, the first dummy structure DS1b and the second dummy structure DS2b each have a side surface that is inclined with respect to the top surface of the second substrate 101. The inclined side surface is formed during etching of the first dummy structure DS1b and the second dummy structure DS2b. The first dummy structure DS1b and the second dummy structure DS2b each have a shape in which the width at the top is smaller than the width at the bottom. The first dummy structure DS1b and the second dummy structure DS2b each have a shape in which the width decreases toward the top. According to an embodiment, the first dummy structure DS1b and the second dummy structure DS2b have a side surface that is perpendicular to the top surface of the second substrate 101.

[0092] The shape of the inclined side surfaces of the first dummy structure DS1b and the second dummy structure DS2b can be similarly applied to other embodiments in this specification.

[0093] 7a is a schematic cross-sectional view of a semiconductor device according to an embodiment, showing a cross section of the semiconductor device in a different region than that of FIG. 2a.

[0094] 7a, the semiconductor device 10 includes a through region TH in the peripheral region CT that penetrates the second substrate 101 and the first and second source sacrificial layers 111 and 112. A through insulating layer is disposed in the through region TH. At least a portion of the first dummy structure DS1 is disposed on the through region TH. The through region TH is formed by forming an insulating film in a region where a portion of the second substrate 101 and the first and second source sacrificial layers 111 and 112 has been removed, followed by a planarization process. The through insulating layer in the through region TH may be formed by filling the region with the same material as that forming the interlayer insulating layer 120. The arrangement of the through region TH may be variously modified depending on the embodiment.

[0095] Figure 7b is a schematic cross-sectional view of a semiconductor device according to one embodiment, showing an enlarged area corresponding to "C" in Figure 7a.

[0096] Referring to FIG. 7b, the shape of the first dummy structure DS1c differs from that of the above-described embodiment. A portion of the first insulating layer 170a and a portion of the second insulating layer 180a of the first dummy structure DS1c are curved downward. For example, each of the second insulating layers 180a includes a first portion P1 on the second substrate 101 and a second portion P2 on the through-hole region TH. The second portion P2 extends from the first portion P1 and includes a portion that is curved downward. The second portion P2 protrudes downward toward the first substrate 11 more than the first portion P1. The second portion P2 includes a curved portion. For example, the lower surface of the second portion P2 is convex downward, and the upper surface of the second portion P2 is concave downward.

[0097] The length of the curved portion of the second portion P2 of the second insulating layer 180a changes toward the top. The radius of curvature of the curved portion of the second portion P2 of the second insulating layer 180a changes toward the top. For example, but not limited to, the radius of curvature of the curved portion of the second portion P2 of the second insulating layer 180a increases toward the top.

[0098] Similar to the second insulating layer 180a, the first insulating layer 170a also includes a downwardly curved or downwardly protruding portion. In the embodiment of FIG. 7b, the structure of the first dummy structure DS1c appears when the through region TH is disposed below the first dummy structure DS1c. The structure of the first dummy structure DS1c is formed by stress caused by an upper structure disposed above the first dummy structure DS1c. The shape of the first dummy structure DS1c in this embodiment is similarly applicable to other embodiments herein.

[0099] Figure 7c is a schematic cross-sectional view of a semiconductor device according to one embodiment, Figure 7c shows a cross-section of the semiconductor device in a different region than Figure 2a.

[0100] 7c, the semiconductor device 10 further includes a via contact plug CV. A plurality of via regions TH are further arranged through the second substrate 101. A via insulating layer penetrating the second substrate 101 is arranged in the plurality of via regions TH. The via contact plug CV extends through the first and second capping insulating layers 190 and 290 and the via insulating layer to the peripheral circuit region PERI. The via contact plug CV vertically penetrates at least one of the first dummy structure DS1 and the second dummy structure DS2 and the second substrate 101. The via contact plug CV is electrically connected to the circuit element 20 in the peripheral circuit region PERI. For example, the via contact plug CV is connected to a portion of the circuit wiring line 80.

[0101] 8a is a schematic plan view of a semiconductor device according to one embodiment, showing an area corresponding to FIG.

[0102] Figure 8b is a schematic cross-sectional view of a semiconductor device according to one embodiment, taken along section line IIa-IIa' in Figure 8a.

[0103] 8a and 8b, the semiconductor device 10h differs from the embodiment of FIG. 1 in the arrangement of the first dummy structures DS1_1 and the second dummy structures DS2_1 in a plane. In the embodiment of FIG. 1, the first and second dummy structures DS1 and DS2 each have a shape in which the length in the y direction is longer than the length in the x direction, are spaced apart in the x direction, and are arranged so as not to overlap each other in the vertical direction. In the embodiment of FIG. 8a, the first and second dummy structures DS1_1 and DS2_1 each have a shape in which the length in the x direction is longer than the length in the y direction, are spaced apart in the y direction, and are arranged so as not to overlap each other in the vertical direction. In the embodiment of FIG. 1, the first and second dummy structures DS1 and DS2 are alternately arranged along the x direction in a plane, but in the embodiment of FIG. 8a, the first and second dummy structures DS1_1 and DS2_1 are alternately arranged along the y direction in a plane. The number of first and second dummy structures DS1_1 and DS2_1 arranged is greater than that in the embodiment of FIG.

[0104] 9a is a schematic plan view of a semiconductor device according to one embodiment, showing an area corresponding to FIG.

[0105] 9a, the semiconductor device 10i differs from the embodiment of FIG. 1 in the arrangement of the first dummy structures DS1_2 and the second dummy structures DS2_2 in a plane. In the embodiment of FIG. 9a, the first and second dummy structures DS1_2 and DS2_2 are arranged in a staggered manner in a plane so as not to overlap each other in the vertical direction. For example, in a plane, the first and second dummy structures DS1_2 and DS2_2 are arranged alternately along the x direction and alternately along the y direction. In a plane, the first and second dummy structures DS1_2 and DS2_2 are arranged spaced apart from each other in the x direction and spaced apart from each other in the y direction.

[0106] The cross sections taken along the cutting lines Ia-Ia' and Ib-Ib' shown in FIG. 9a correspond to FIGS. 2a and 3a, respectively.

[0107] 9b is a schematic plan view of a semiconductor device according to one embodiment, showing an area corresponding to FIG.

[0108] Referring to FIG. 9b, the semiconductor device 10j differs from the embodiment of FIG. 1 in the planar arrangement of the first dummy structures DS1_3 and the second dummy structures DS2_3. In the embodiment of FIG. 9b, the first and second dummy structures DS1_3 and DS2_3 do not overlap each other in the vertical direction and are arranged without any regularity in the x and / or y directions. Some of the first dummy structures DS1_3 have patterns with shapes different from other first dummy structures DS1_3. For example, some of the first dummy structures DS1_3 have shapes that are folded in one direction in the planar view. The planar patterns of the first and second dummy structures DS1_3 and DS2_3 can be variously modified from those shown in the figure.

[0109] Figure 10a is a schematic cross-sectional view of a semiconductor device according to one embodiment, showing the area corresponding to the portion marked "A" in Figure 2a.

[0110] Figure 10b is a schematic cross-sectional view of a semiconductor device according to one embodiment, showing the area corresponding to the portion marked "B" in Figure 2a.

[0111] 10a and 10b, in a semiconductor device 10k, the cross-sectional shapes of memory stack structures GS1 and GS2 and dummy structures DS1d and DS2d are different from those of the embodiment of FIG. 2a.

[0112] 10a, the first gate electrodes 130aa of the first stack structure GS1 are arranged such that, for example, four gate electrodes form one gate group, forming a stepped structure between the gate groups in the x direction. The four gate electrodes of one gate group each form a stepped structure in the x direction. The second gate electrodes 230aa of the second stack structure GS2 are also arranged similarly to the first gate electrodes 130aa, with four gate electrodes forming one gate group and forming a stepped structure in the x direction. The first interlayer insulating layer 120aa and the second interlayer insulating layer 220aa also have a similar structure. In the first stack structure GS1 and the second stack structure GS2, the uppermost gate electrode of each gate group has a pad region LP that extends relatively long.

[0113] 10b, the second and fourth insulating layers 180aa and 280aa of the dummy structures DS1d and DS2d have a stepped structure similar to that of the first and second gate electrodes 130aa and 230aa. For example, the second insulating layer 180aa has four insulating layers that form a single dummy insulating structure, forming a stepped structure between the dummy insulating structures along the x-direction. The four insulating layers that form a single dummy insulating structure each form a stepped structure along the x-direction. The fourth insulating layer 280aa of the second dummy structure DS2d is also similar to the second insulating layer 270aa, having four insulating layers that form a single dummy insulating structure along the x-direction, and the first insulating layer 170aa and the third insulating layer 270aa have similar structures.

[0114] Figure 11a is a schematic cross-sectional view of a semiconductor device according to one embodiment, showing the area corresponding to the portion labeled "A" in Figure 2a.

[0115] Figure 11b is a schematic cross-sectional view of a semiconductor device according to one embodiment, showing the area corresponding to the portion marked "B" in Figure 2a.

[0116] 11a and 11b, in a semiconductor device 10l, the cross-sectional shapes of memory stack structures GS1, GS2 and dummy structures DS1e, DS2e are different from those in the embodiment of FIG. 2a.

[0117] First, referring to FIG. 11a, it can be seen that compared to the embodiment of FIG. 10a, the first stacked structure GS1 further includes a first dummy cell structure DCS1, and the second stacked structure GS2 further includes a second dummy cell structure DCS2.

[0118] This embodiment has the same structure as the embodiment of FIG. 10a, except that first dummy cell structures DCS1 are further disposed on the pad region LP of the uppermost gate electrode. Each of the first dummy cell structures DCS1 includes a first interlayer insulating layer 120aa and a first gate electrode 130aa. At least one of the first dummy cell structures DCS1 has one side inclined with respect to the top surface of the second substrate 101 and the other side having a staircase structure. At least one of the first dummy cell structures DCS1 has one side inclined with respect to the top surface of the second substrate 101 and the other side having both an inclined side and a staircase structure. The second dummy cell structures DCS2 of the second stacked structure GS2 also have a structure similar to that of the first dummy cell structures DCS1.

[0119] Referring to FIG. 11b, compared to the embodiment of FIG. 10b, one side of the first dummy structure DS1e includes both a sloped portion S1 and a stepped portion SP1. For example, the side surface S1 of the upper region of the first dummy structure DS1e is sloped, and the lower region of the first dummy structure DS1e has a stepped portion SP1 where the step between the first and second insulating layers 170aa and 180aa is lowered in one direction. At least a portion of the first dummy structure DS1e is formed in the same process step as the first dummy cell structure DCS1 and has a sloped side surface with substantially the same slope as the sloped side surface of the first dummy cell structure DCS1. The second dummy structure DS2e has a structure similar to the first dummy structure DS1e and includes both a sloped portion S2 and a stepped portion SP2 on one side of the second dummy structure DS2e. The first and second dummy structures DS1e and DS2e do not overlap vertically.

[0120] Figure 12 is a schematic cross-sectional view of a semiconductor device according to one embodiment, showing the area corresponding to Figure 2a.

[0121] 12, the memory cell region CELL of the semiconductor device 10m further includes a third stack structure GS3 and a third dummy structure DS3. While the above-described embodiments show a two-stage stack structure of the memory cell structure, the embodiment of FIG. 12 shows a three-stage stack structure of the memory cell structure. The semiconductor device 10m further includes a third capping insulating layer 390.

[0122] The third stacked structure GS3 includes alternately stacked third interlayer insulating layers 320 and third gate electrodes 330. The third interlayer insulating layer 320 is described in relation to the first and second interlayer insulating layers 120 and 220, and the third gate electrode 330 is described in relation to the first and second gate electrodes 130 and 230. However, among the descriptions of the first and second gate electrodes 130 and 230, the descriptions of the gate electrodes of the upper erase control transistor and the upper string select transistor are applicable to the upper third gate electrode 330 of the third gate electrodes 330.

[0123] The third dummy structure DS3 is disposed on the first and second dummy structures DS1 and DS2. The third dummy structure DS3 is disposed apart from the third stack structure GS3 of the memory cell structure MC1. The third dummy structure DS3 is referred to as a "third insulating structure." The third dummy structure DS3 includes a fifth insulating layer 370 and a sixth insulating layer 380 alternately stacked on the second substrate 101. The third dummy structure DS3 has a stair-like step. The structure of the third dummy structure DS3 is similar to that of the first and second dummy structures DS1 and DS2.

[0124] In this embodiment, the first dummy structure DS1 does not overlap the second dummy structure DS2 in the vertical direction, and the third dummy structure DS3 does not overlap the second dummy structure DS2 in the vertical direction. The first dummy structure DS1 and the third dummy structure DS3 may partially overlap in the vertical direction.

[0125] The channel structure CH and the isolation structure MS are disposed to penetrate the first to third memory cell structures MC1, MC2, and MC3. The upper insulating layers 310, 320, and 330, the bit line 350, and the upper wiring 355 are disposed on the third memory cell structure MC3 and the third capping insulating layer 390. The gate contact plug CP1 and the channel contact plug CP2 are disposed on the third memory cell structure MC3 and connected to the third gate electrode 330 and the channel structure CH.

[0126] This embodiment can also be applied to an embodiment in which the stacked structure of the memory cell structure has a multi-stack structure with three or more layers, and in this case, the dummy structures arranged adjacent to each other above / below are arranged so as not to overlap in the vertical direction.

[0127] Figure 13 is a schematic cross-sectional view of a semiconductor device according to one embodiment, showing the area corresponding to Figure 2a.

[0128] 13, the semiconductor device 10_B has a C2C (chip to chip) structure. The C2C structure refers to fabricating an upper chip including a cell region CELL on a first wafer, fabricating a lower chip including a peripheral circuit region PERI on a second wafer different from the first wafer, and then connecting the upper and lower chips to each other by a bonding method. For example, the bonding method refers to a method of electrically connecting a bonding metal formed on the top metal layer of the upper chip to a bonding metal formed on the top metal layer of the lower chip. For example, if the bonding metal is made of copper (Cu), the bonding method is Cu-Cu bonding, and the bonding metal may be made of aluminum or tungsten.

[0129] The semiconductor device 10_B further includes a first lower junction structure 193a and a first upper junction structure 195a arranged in the cell array region CA, a second lower junction structure 193b and a second upper junction structure 195b arranged in the connection region CB, and a third lower junction structure 193c and a third upper junction structure 195c arranged in the peripheral region CT.

[0130] The bit lines 350 are electrically connected to the circuit elements 20 providing the page buffer in the peripheral circuit region PERI of the cell array region CA. In one embodiment, the bit lines 350 are connected to the first upper junction structure 195a in the peripheral circuit region PERI, and the first upper junction structure 195a is connected to the first lower junction structure 193a, which is connected to the circuit elements 20 of the page buffer via the circuit wiring lines 80.

[0131] The gate contact plug CP1 is coupled to the peripheral circuit region PERI in the coupling region CB via the second upper junction structure 195b in the cell region CELL and the second lower junction structure 193b in the peripheral circuit region PERI. The gate contact plug CP1 is electrically coupled to a circuit element 20 providing a row decoder in the peripheral circuit region PERI. In one embodiment, the operating voltage of the circuit element 20 providing the row decoder is different from the operating voltage of the circuit element 20 providing the page buffer. For example, the operating voltage of the circuit element 20 providing the page buffer is higher than the operating voltage of the circuit element 20 providing the row decoder.

[0132] FIG. 14 is a schematic plan view for explaining a method for manufacturing a semiconductor device according to an embodiment.

[0133] 14, the first and second dummy structures DS1 and DS2 substantially uniform the spacing between stacked structures forming memory cells between adjacent semiconductor devices. For example, a first memory cell structure MC1 of a semiconductor device 10 is spaced a first distance a1 from a second memory cell structure MC2 of an adjacent semiconductor device 10', and the first and second memory cell structures MC1 and MC2 within one semiconductor device 10 are spaced a second distance a2 that is smaller than the first distance a1. According to the technical concept of the present invention, the first and second dummy structures DS1 and DS2 are disposed on at least one side of the stacked structures forming the memory cells of one semiconductor device, thereby reducing the first distance a1.

[0134] The effect of reducing the first distance a1 by placing the first dummy structure DS1 minimizes process variations in the staircase structure of the first gate electrodes 130, 230 in the connection regions CB on both sides along the x-direction within one memory stack structure GS1, GS2.

[0135] 15a, 15b, 15c, and 15d are schematic cross-sectional views illustrating a semiconductor device manufacturing method according to one embodiment, each showing a region corresponding to a cross section taken along line I1-I1' in FIG.

[0136] 15a, a peripheral circuit region PERI (see FIG. 2a) including circuit elements 20, circuit contact plugs 70, and circuit wiring lines 80 is formed on a first substrate 11. A second substrate 101 is formed, first and second source sacrificial layers 111 and 112, a second conductive layer 105 are formed, a first sacrificial insulating layer 180′ and a first interlayer insulating layer 120 are alternately stacked, and a first insulating layer 170 and a second insulating layer 180 are alternately stacked. A first capping insulating layer 190 is formed, and a first vertical structure VS1 is formed penetrating the first sacrificial insulating layer 180′ and the first interlayer insulating layer 120. A sacrificial vertical structure VS′ penetrating the first capping insulating layer 190 is formed on the outer region C3 of the first substrate 11, and a mask layer 198 is formed on the central region C1 and the guard ring region C2 of the first substrate 11, followed by a wet etching process.

[0137] First, a circuit gate dielectric layer 22 and a circuit gate electrode 25 are sequentially formed on the first substrate 11. The circuit gate dielectric layer 22 and the circuit gate electrode 25 are formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 22 is formed of silicon oxide, and the circuit gate electrode 25 is formed of at least one of, but not limited to, polycrystalline silicon or a metal silicide layer. Next, a spacer layer 24 and source / drain regions 30 are formed on both sidewalls of the circuit gate dielectric layer 22 and the circuit gate electrode 25. Depending on the embodiment, the spacer layer 24 may be made of multiple layers. Next, an ion implantation process is performed to form the source / drain regions 30.

[0138] The circuit contact plug 70 of the lower wiring structure is formed by forming a portion of the peripheral region insulating layer 90, etching away a portion of the insulating layer, and filling the portion with a conductive material. The circuit wiring line 80 is formed, for example, by depositing a conductive material and then patterning the deposited conductive material.

[0139] The peripheral region insulating layer 90 is made up of a plurality of insulating layers, with a portion of the peripheral region insulating layer 90 being formed in each step of forming the lower wiring structure, and a portion of the peripheral region insulating layer 90 being formed on the uppermost circuit wiring line 80, so that the peripheral region insulating layer 90 is ultimately formed to cover the circuit elements 20 and the lower wiring structure.

[0140] Next, the second substrate 101 is formed on the peripheral region insulating layer 90. The second substrate 101 is made of, for example, polycrystalline silicon and is formed by a CVD process. The polycrystalline silicon that forms the second substrate 101 contains impurities. The second substrate 101 is formed to be smaller than or equal in size to the first substrate 11.

[0141] First and second source sacrificial layers 111 and 112 and a second conductive layer 105 are formed. The first source sacrificial layer 111 is formed on and under the second source sacrificial layer 112. The first source sacrificial layer 111 is formed of a material having etching selectivity with respect to the second source sacrificial layer 112. For example, the first source sacrificial layer 111 is formed of silicon oxide, and the second source sacrificial layer 112 is formed of silicon nitride. The second conductive layer 105 is formed of a semiconductor material.

[0142] After removing a portion of the second substrate 101, a portion of the first and second source sacrificial layers 111 and 112, and a portion of the second conductive layer 105, an insulating material is filled to form a lower insulating layer, and a planarization process is further performed using a chemical mechanical polishing (CMP) process. The lower insulating layer is formed in the cell region CR or the peripheral region CT.

[0143] The first sacrificial insulating layer 180′ is a layer whose portion will be replaced by the first gate electrode 130 (see FIG. 2a) through a subsequent process. The first sacrificial insulating layer 180′ is made of a different material from the first interlayer insulating layer 120 and is made of a material that can be etched with etching selectivity to the first interlayer insulating layer 120 under specific etching conditions. For example, the first interlayer insulating layer 120 is made of at least one of silicon oxide and silicon nitride, and the first sacrificial insulating layer 180′ is made of a different material from the first interlayer insulating layer 120, selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In an embodiment, the thicknesses of the first interlayer insulating layer 120 and the first sacrificial insulating layer 180′ may not all be the same. The thicknesses and the number of layers constituting the first interlayer insulating layer 120 and the first sacrificial insulating layer 180′ may vary from those shown in the drawings.

[0144] The first insulating layer 170 is formed at a height level corresponding to the first interlayer insulating layer 120 and is made of the same material as the first interlayer insulating layer 120, and the second insulating layer 180 is formed at a height level corresponding to the first sacrificial insulating layer 180' and is made of the same material as the first sacrificial insulating layer 180'.

[0145] Photolithography and etching processes are repeatedly performed on the first sacrificial insulating layer 180′ using a mask layer so that the upper first sacrificial insulating layer 180′ extends shorter than the lower first sacrificial insulating layer 180′ in the connection region CB of the second substrate 101. As a result, the first sacrificial insulating layer 180′ has a stepped shape, providing a pad region.

[0146] In the peripheral region CT of the second substrate 101, photolithography and etching processes are repeatedly performed on the second insulating layer 180 using a mask layer so that the upper second insulating layer 180 extends shorter than the lower second insulating layer 180. As a result, the second insulating layer 180 has a stepped shape. The stepped shape of the first sacrificial insulating layer 180′ and the stepped shape of the second insulating layer 180 are formed in the same process step, but are not limited to this and may be formed in different process steps.

[0147] The first vertical structure VS1 is formed by performing an etching process to penetrate the first sacrificial insulating layer 180′ and the first interlayer insulating layer 120 at a position corresponding to the first channel structure CH1 in FIG. 2a or 2b. First, a through hole corresponding to the first channel structure CH1 in FIG. 2a is formed. The through hole is formed by recessing a portion of the second substrate 101. The first vertical structure VS1 is formed in the through hole. The first vertical structure VS1 is formed of a semiconductor material such as polycrystalline silicon or single crystal silicon.

[0148] The sacrificial vertical structure VS' is formed on the outer region C3 of the first substrate 11. The sacrificial vertical structure VS' is configured to form part of an alignment key or an overlay key used in the exposure process in the outer region C3. The outer region C3 of the first substrate 11 is an area outside the guard ring region C2 and surrounding the guard ring region C2. The outer region C3 is a scribe lane area. The scribe lane area corresponds to an area where a dicing process is performed to separate the semiconductor wafer into individual semiconductor chips after forming semiconductor devices on the semiconductor chips. The scribe lane area is an area including an alignment key or an overlay key used in the exposure process performed to form the semiconductor device.

[0149] A mask layer 198 is formed on the central region C1 and the guard ring region C2 of the first substrate 11, and a wet etching process is performed to selectively remove a portion of the first capping insulating layer 190 in the outer region C3 with respect to the sacrificial vertical structure VS'. As a result, the sacrificial vertical structure VS' protrudes above the first capping insulating layer 190 in the outer region C3. Then, the mask layer 198 is removed.

[0150] 15b, second sacrificial insulating layers 280′ and second interlayer insulating layers 220 are alternately stacked, and third insulating layers 270 and fourth insulating layers 280 are alternately stacked. In the outer region C3 of the first substrate 11, first outer insulating layers 275 and second outer insulating layers 285 are alternately stacked on the sacrificial vertical structures VS′.

[0151] The second sacrificial insulating layer 280' is a layer whose portion will be replaced by the second gate electrode 230 (see FIG. 2a) through a subsequent process. The second sacrificial insulating layer 280' is made of a different material from the second interlayer insulating layer 220 and is made of a material that has etching selectivity and can be etched under specific etching conditions with respect to the second interlayer insulating layer 220. The second sacrificial insulating layer 280' is formed of the same material as the first sacrificial insulating layer 180', and the second interlayer insulating layer 220 is formed of the same material as the first interlayer insulating layer 120.

[0152] The third insulating layer 270 is formed at a height level corresponding to the second interlayer insulating layer 220 and is made of the same material as the second interlayer insulating layer 220, and the fourth insulating layer 280 is formed at a height level corresponding to the second sacrificial insulating layer 280' and is made of the same material as the second sacrificial insulating layer 280'.

[0153] Photolithography and etching processes are repeatedly performed on the second sacrificial insulating layer 280′ using a mask layer so that the upper second sacrificial insulating layer 280′ extends shorter than the lower second sacrificial insulating layer 280′ in the connection region CB of the second substrate 101. As a result, the second sacrificial insulating layer 280′ has a stepped shape, providing a pad region.

[0154] In the peripheral region CT of the second substrate 101, photolithography and etching processes are repeatedly performed on the fourth insulating layer 280 using a mask layer so that the upper fourth insulating layer 280 extends shorter than the lower fourth insulating layer 280. This results in a stepped shape in the fourth insulating layer 280. The stepped shape of the second sacrificial insulating layer 280′ and the stepped shape of the fourth insulating layer 280 are formed in the same process step, but are not limited to this and may be formed in different process steps.

[0155] The first outer insulating layer 275 is formed at a height level corresponding to the third insulating layer 270 and is made of the same material as the third insulating layer 270, and the second outer insulating layer 285 is formed at a height level corresponding to the fourth insulating layer 280 and is made of the same material as the fourth insulating layer 280.

[0156] The first outer insulating layer 275 and the second outer insulating layer 285 are formed so that the sacrificial vertical structure VS′ has a bent shape on the sacrificial vertical structure VS′, with the sacrificial vertical structure VS′ protruding from the first capping insulating layer 190. The first and second outer insulating layers 275, 285 and the sacrificial vertical structure VS′ serve as an alignment key or an overlay key in the outer region C3.

[0157] In this step, another stopper layer is formed on the top of the second sacrificial insulating layer 280′ and the fourth insulating layer 280. The stopper layer serves to stop the progress of planarization in a subsequent planarization process. The stopper layer is removed after the planarization process.

[0158] Referring to FIG. 15c, a channel structure CH including a first channel structure CH1 and a second channel structure CH2 is formed, and a planarization process is performed to planarize the top surface of the second capping insulating layer 290.

[0159] First, an etching process is performed to penetrate the upper stack structure at a position corresponding to the channel structure CH in FIG. 2a to form a channel through-hole. Then, the first vertical structure VS1 is removed to extend the channel through-hole to the lower stack structure. The channel through-hole is then filled to form the channel structure CH. The sidewalls of the channel structure CH are not perpendicular to the top surface of the second substrate 101. The channel structure CH is formed by recessing a portion of the second substrate 101. As shown in FIG. 2b, a channel layer 140 and a channel insulating layer 150 are formed within the channel structure CH. The channel layer 140 is formed to have a uniform thickness using an ALD or CVD process. The channel insulating layer 150 is formed to fill the internal space of the channel layer 140 and is made of an insulating material. However, depending on the embodiment, the space between the channel layers 140 may be filled with a conductive material instead of the channel insulating layer 150.

[0160] A planarization process is performed to planarize the upper surface of the second capping insulating layer 290. During the planarization process, the first and second dummy structures DS1 and DS2 are disposed on the peripheral region CT of the second substrate 101, thereby minimizing dishing, in which the upper portion of the second capping insulating layer 290 is locally recessed downward toward the second substrate 101.

[0161] Referring to FIG. 15d, the first and second gate electrodes 130 and 230 are formed.

[0162] An opening is formed through the stacked structure of the first and second sacrificial insulating layers 180′, 280′ and the first and second interlayer insulating layers 120, 220 in an area corresponding to the isolation structure MS (see FIG. 2b), and a tunnel portion is formed by removing a portion of the first and second sacrificial insulating layers 180′, 280′ through the opening. Before forming the isolation structure MS, a first upper insulating layer 310 is formed on the second capping insulating layer 290.

[0163] First, another sacrificial spacer layer is formed in the opening, and then the second source sacrificial layer 112 is selectively removed. The first and second source sacrificial layers 111 and 112 are then removed, for example, by a wet etching process. A conductive material is deposited in the area where the first and second source sacrificial layers 111 and 112 were removed to form the first conductive layer 104, and the sacrificial spacer layer is then removed from the opening. Next, a conductive material is filled in the tunnel portion where portions of the first and second sacrificial insulating layers 180′ and 280′ were removed, forming the first and second gate electrodes 130 and 230. The conductive material may include metal, polycrystalline silicon, or a metal silicide material. After forming the first and second gate electrodes 130 and 230, the conductive material deposited in the opening is removed using an additional process, and then an insulating material is filled.

[0164] 2a, a second upper insulating layer 320 and a third upper insulating layer 330 are formed, followed by the formation of gate contact plugs CP1, channel contact plugs CP2, through contact plugs CV (see FIG. 7c), guard ring structures GR, and upper wiring 355. The outer region C3 is cut and removed.

[0165] The gate contact plug CP1 is formed to be electrically connected to the first and second gate electrodes 130 and 230 in the connection region CB, and the channel contact plug CP2 is formed to be electrically connected to the channel structure CH. Although not shown, a substrate contact plug is also formed to be electrically connected to the second substrate 101. The guard ring structure GR penetrates the first and second capping insulating layers 190 and 290 and is disposed along the edge region 10eg of the semiconductor device 10 to surround the internal structure. The guard ring structure GR is formed by forming an opening through the first and second capping insulating layers 190 and 290 and a portion of the peripheral region insulating layer 90 to expose the circuit wiring line 80, and then filling the opening with a conductive material.

[0166] The gate contact plug CP1, the channel contact plug CP2, and the substrate contact plug are formed to different depths by simultaneously forming contact holes using an etch stop layer, etc., and then filling the contact holes with a conductive material. However, in some embodiments, some of the gate contact plug CP1, the channel contact plug CP2, and the substrate contact plug may be formed in different process steps.

[0167] The upper contact plug is formed by forming the third upper insulating layer 330, etching away a portion of the third upper insulating layer 330, and filling the third upper insulating layer 330 with a conductive material. The bit line 350 and the upper wiring 355 are formed by depositing a conductive material and then patterning the deposited conductive material.

[0168] Next, the external region C3 is cut and removed in the chip region separation process.

[0169] As a result, the semiconductor device 10 shown in FIGS. 1 to 2b is finally manufactured.

[0170] FIG. 16a is a schematic diagram of a data storage system including a semiconductor device according to one embodiment.

[0171] 16a, a data storage system 1000 according to one embodiment of the present invention includes a semiconductor device 1100 and a controller 1200 electrically coupled to the semiconductor device 1100. The data storage system 1000 is a storage device including one or more semiconductor devices 1100, or an electronic device including a storage device. For example, the data storage system 1000 is a solid state drive device (SSD device), a Universal Serial Bus (USB), a computer system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0172] The semiconductor device 1100 is a nonvolatile memory device, such as the NAND flash memory device described above with reference to FIGS. 1 to 12. The semiconductor device 1100 includes a first structure 1100F and a second structure 1100S on the first structure 1100F. In one embodiment, the first structure 1100F is disposed next to the second structure 1100S. The first structure 1100F is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S is a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines UL1 and UL2, first and second gate lower lines LL1 and LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0173] In the second structure 1100S, each memory cell string CSTR includes lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary depending on the embodiment.

[0174] In one embodiment, the upper transistors UT1 and UT2 comprise string select transistors, and the lower transistors LT1 and LT2 comprise ground select transistors. The lower gate lines LL1 and LL2 are the gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL is the gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 are the gate electrodes of the upper transistors UT1 and UT2, respectively.

[0175] In one embodiment, the lower transistors LT1 and LT2 include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1 and UT2 include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 is used in an erase operation that erases data stored in the memory cell transistor MCT using a gate-induced drain leakage (GIDL) phenomenon.

[0176] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word line WL, and the first and second gate upper lines UL1 and UL2 are electrically connected to the decoder circuit 1110 via a first connecting line 1115 extending from within the first structure 1100F to the second structure 1100S. The bit line BL is electrically connected to the page buffer 1120 via a second connecting line 1125 extending from within the first structure 1100F to the second structure 1100S.

[0177] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 perform control operations on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 are controlled by a logic circuit 1130. The semiconductor device 1100 communicates with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 is electrically connected to the logic circuit 1130 via an input / output connecting wiring 1135 extending from within the first structure 1100F to the second structure 1100S.

[0178] The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the data storage system 1000 includes multiple semiconductor devices 1100, in which case the controller 1200 controls the multiple semiconductor devices 1100.

[0179] The processor 1210 controls the overall operation of the data storage system 1000, including the controller 1200. The processor 1210 operates according to predetermined firmware and controls the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 includes a NAND interface 1221 that handles communication with the semiconductor device 1100. Control commands for controlling the semiconductor device 1100, data to be written to the memory cell transistors MCT of the semiconductor device 1100, data to be read from the memory cell transistors MCT of the semiconductor device 1100, etc. are transmitted via the NAND interface 1221. The host interface 1230 provides a communication function between the data storage system 1000 and an external host. Upon receiving a control command from the external host via the host interface 1230, the processor 1210 controls the semiconductor device 1100 in response to the control command.

[0180] FIG. 16b is a perspective view that schematically illustrates a data storage system including a semiconductor device according to one embodiment.

[0181] 16b, a data storage system 2000 according to an embodiment of the present invention includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 are connected to the controller 2002 by a wiring pattern 2005 formed on the main board 2001.

[0182] The main board 2001 includes a connector 2006 including a plurality of pins that are coupled to an external host. The number and arrangement of the pins in the connector 2006 vary depending on the communication interface between the data storage system 2000 and the external host. In one embodiment, the data storage system 2000 communicates with the external host via any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), or M-Phy for Universal Flash Storage (UFS). In one embodiment, the data storage system 2000 operates using power supplied from the external host via the connector 2006. The data storage system 2000 further includes a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0183] The controller 2002 writes data to and reads data from the semiconductor package 2003 to improve the operating speed of the data storage system 2000 .

[0184] The DRAM 2004 is a buffer memory for mitigating the speed difference between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 also operates as a kind of cache memory, providing space for storing data in control operations for the semiconductor package 2003. When the data storage system 2000 includes the DRAM 2004, the controller 2002 further includes a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0185] The semiconductor package 2003 includes first and second semiconductor packages 2003a and 2003b spaced apart from each other. Each of the first and second semiconductor packages 2003a and 2003b includes a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b includes a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of each of the semiconductor chips 2200, a connecting structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chip 2200 and the connecting structure 2400 on the package substrate 2100.

[0186] Package substrate 2100 is a printed circuit board that includes package top pads 2130. Each semiconductor chip 2200 includes input / output pads 2210. Input / output pads 2210 correspond to input / output pads 1101 in Figure 16a. Each of semiconductor chips 2200 includes a semiconductor device as described above with reference to Figures 1 to 12.

[0187] In one embodiment, the connecting structure 2400 is a bonding wire that electrically connects the I / O pad 2210 and the package upper pad 2130. Therefore, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 are electrically connected to each other by a bonding wire method and are electrically connected to the package upper pad 2130 of the package substrate 2100. According to an embodiment, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 are electrically connected to each other by a connecting structure including a through silicon via (TSV), instead of the connecting structure 2400 using a bonding wire method.

[0188] In one embodiment, the controller 2002 and the semiconductor chip 2200 are included in one package. In another embodiment, the controller 2002 and the semiconductor chip 2200 are mounted on an interposer substrate separate from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 are connected to each other by wiring formed on the interposer substrate.

[0189] Fig. 17 is a cross-sectional view schematically illustrating a semiconductor package according to one embodiment, illustrating one embodiment of the semiconductor package 2003 of Fig. 16b, and conceptually illustrating a region obtained by cutting the semiconductor package 2003 of Fig. 16b along cutting line II'.

[0190] 17, in a semiconductor package 2003, a package substrate 2100 is a printed circuit board. The package substrate 2100 includes a package substrate body 2120, package upper pads 2130 disposed on the upper surface of the package substrate body 2120, lower pads 2125 disposed on the lower surface of the package substrate body 2120 or exposed through the lower surface, and internal wiring 2135 electrically connecting the upper pads 2130 and the lower pads 2125 inside the package substrate body 2120. The upper pads 2130 are electrically connected to a connecting structure 2400. The lower pads 2125 are connected to a wiring pattern 2005 of a main board 2001 of a data storage system 2000 via conductive connecting parts 2800, as shown in FIG. 16b.

[0191] As shown in the enlarged view, each of the semiconductor chips 2200 includes a peripheral circuit region PERI including a first substrate 11 and circuit wiring lines, a second substrate (or common source line) 101, memory stack structures GS1 and GS2 on the second substrate 101, channel structures CH and isolation structures MS (see FIG. 2b) penetrating the memory stack structures GS1 and GS2, bit lines 350 electrically connected to the channel structures CH, and a memory cell region CELL including gate contact plugs CP1 and upper wirings 355 electrically connected to word lines (WL in FIG. 16a) of the memory stack structures GS1 and GS2. As shown in the enlarged view, each of the semiconductor chips 2200 further includes first and second dummy structures DS1 and DS2 that do not overlap each other in the vertical direction.

[0192] Each of the semiconductor chips 2200 further includes input / output connecting wiring electrically connected to the circuit elements (20 in FIG. 2a) and circuit wiring lines (80 in FIG. 2a) of the peripheral circuit region PERI and extending into the peripheral circuit region PERI, and input / output pads 2210 electrically connected to the input / output connecting wiring. Each of the semiconductor chips 2200 further includes upper insulating layers 410 and 420. The input / output connecting wiring extends from a lower portion of the input / output pad 2210 through the upper insulating layers 310, 320, 330, and 410, the capping insulating layers 190 and 290, and the second substrate 101 into the peripheral circuit region PERI.

[0193] The semiconductor chips 2200 in Fig. 17 are electrically connected to each other by bonding wire-type connecting structures 2400. However, in one embodiment, semiconductor chips within a single semiconductor package, such as the semiconductor chip 2200 in Fig. 17, are electrically connected to each other by connecting structures including through-silicon vias (TSVs).

[0194] 18, in the semiconductor package 2003A, each semiconductor chip 2200a includes a peripheral circuit region PERI including a first substrate 11 and circuit wiring lines, a second substrate 101, memory stack structures GS1 and GS2 on the second substrate 101, channel structures CH and isolation structures MS (see FIG. 2b) penetrating the memory stack structures GS1 and GS2, bit lines 350 electrically connected to the channel structures CH, and a memory cell region CELL including gate contact plugs CP and upper wiring 355 electrically connected to word lines (WL in FIG. 16a) of the memory stack structures GS1 and GS2. The peripheral circuit region PERI further includes lower junction structures 193a, 193b, and 193c, and the cell region CELL further includes upper junction structures 195a, 195b, and 195c.

[0195] The upper junction structures 195a and 195b include a first upper junction structure 195a electrically connected to the channel structure CH and a second upper junction structure 195b electrically connected to the word lines (WL in FIG. 16a) of the memory stack structures GS1 and GS2. The lower structures 193a and 193b include a first lower junction structure 193a connected to the first upper junction structure 195a and electrically connected to the circuit elements 20 in the peripheral circuit region PERI and a second lower junction structure 193b connected to the second upper junction structure 195b and electrically connected to the circuit elements 20 in the peripheral circuit region PERI.

[0196] The lower junction structures 193a and 193b in the peripheral circuit region PERI and the upper junction structures 195a and 195b in the cell region CELL are bonded to each other while being in contact with each other. The bonded portions of the lower junction structures 193a and 193b and the upper junction structures 195a and 195b are made of, for example, copper (Cu).

[0197] As shown in the enlarged view, the memory cell region CELL further includes a first dummy structure DS1 and a second dummy structure DS2 that do not overlap in the vertical direction (z). Each of the semiconductor chips 2200a further includes an I / O pad 2210 formed in the upper insulating layer 430 and an I / O connecting wire below the I / O pad 2210. The I / O connecting wire is electrically connected to a portion of the junction structures 193c and 195c.

[0198] The semiconductor chip 2200 of Figure 17 and the semiconductor chip 2200a of Figure 18 are electrically connected to each other by a bonding wire-type connecting structure 2400. However, in one embodiment, semiconductor chips within a single semiconductor package, such as the semiconductor chip 2200 of Figure 17 and the semiconductor chip 2200a of Figure 18, are electrically connected to each other by a connecting structure including a through-silicon via (TSV).

[0199] The present invention is not limited to the above-described embodiments and drawings, and various substitutions, modifications, and combinations of the embodiments may be made by those skilled in the art without departing from the scope of the present invention. [Explanation of symbols]

[0200] C1 central area C2 Guard Ring CA cell array area CB connection area CH Channel Structure CP1 Gate Contact Plug CP2 Channel Contact Plug CR Cell Area CT peripheral area DS1, DS2 dummy structures GR Guard Ring Structure GS1, GS2 laminated structure MC1, MC2 memory cell structures MS separation structure 10, 1100 Semiconductor device 11 First board 20 Circuit Elements 22 Circuit gate dielectric layer 24 spacer layer 25 Circuit gate electrode 30 Source / drain region 70 Circuit Contact Plug 80 Circuit Wiring Line 90 Peripheral area insulating layer 101 Second board 104 First conductive layer 105 Second conductive layer 111 First source sacrificial layer 112 Second Source Sacrificial Layer 120 First interlayer insulating layer 130 first gate electrode 140 channel layer 145 Gate Dielectric Layer 150 channel insulating layer 155 Channel Pad 170 First insulating layer 180 Second insulating layer 190 First capping insulating layer 220 Second interlayer insulating layer 230 Second gate electrode 270 Third insulating layer 280 Fourth insulating layer 290 Second capping insulating layer 310 first upper insulating layer 320 Second upper insulating layer 330 Third upper insulating layer 344 Contact plug 350 bit lines 355 Upper Wiring 1000, 2000 Data Storage System 1101, 2210 Input / Output Pads 1100F 1st structure 1100S 2nd structure 1115 1st connection wiring 1125 2nd connection wiring 1135 Input / output connection wiring 1200, 2002 Controller 2001 Main board 2003, 2003A Semiconductor Package 2004 DRAM 2005 Wiring Pattern 2006 Connector 2100 package substrate 2120 Package substrate main body 2125 Lower Pad 2130 Package top pad 2135 Internal wiring 2200, 2200a semiconductor chips 2300 Adhesive layer 2400 Connected structures 2500 molding layer 2800 Conductive connection part

Claims

1. a first substrate and a peripheral circuit area including circuit elements provided on the first substrate; a memory cell region arranged on the peripheral circuit region, The memory cell region includes: a second substrate on the peripheral circuit region; a memory stack structure including: a first stack structure including first gate electrodes and first interlayer insulating layers alternately stacked on the second substrate; and a second stack structure including second gate electrodes and second interlayer insulating layers alternately stacked on the first stack structure; a channel structure vertically penetrating the memory stack structure and connected to the second substrate, the channel structure including a channel layer; a first dummy structure disposed on the second substrate and spaced apart from at least one side of the first stacked structure, the first dummy structure including first and second insulating layers alternately stacked; a second dummy structure disposed on the first dummy structure and spaced apart from at least one side of the second stacked structure, the second dummy structure including a third insulating layer and a fourth insulating layer alternately stacked; a first capping insulating layer covering the first stacked structure and the first dummy structure; a second capping insulating layer covering the second stacked structure and the second dummy structure, At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction; The semiconductor device is characterized in that the second dummy structure is spaced apart from the first stacked structure without overlapping with the first stacked structure in the vertical direction.

2. 2. The semiconductor device according to claim 1, wherein the uppermost second insulating layer of the second insulating layers of the first dummy structure does not overlap the second dummy structure in the vertical direction.

3. 2. The semiconductor device according to claim 1, wherein at least a portion of a side surface of the first dummy structure does not overlap with the second dummy structure in the vertical direction.

4. the first dummy structure and the second dummy structure each have a step-like step; 2. The semiconductor device according to claim 1, wherein the top step of the first dummy structure does not overlap the bottom step of the second dummy structure in the vertical direction.

5. 5. The semiconductor device according to claim 4, wherein the lowest step of the first dummy structure does not overlap the lowest step of the second dummy structure in the vertical direction.

6. 2. The semiconductor device according to claim 1, wherein the first dummy structure and the second dummy structure each have a side surface inclined with respect to the upper surface of the second substrate.

7. a through contact plug that penetrates at least one of the first dummy structure and the second dummy structure and the second substrate and is electrically connected to the circuit element in the peripheral circuit region; 2. The semiconductor device of claim 1, further comprising: a guard ring structure adjacent to an edge region of the semiconductor device, arranged to surround the first and second stack structures and the first and second dummy structures, and connected to the first substrate through the first and second capping insulating layers.

8. The first dummy structure may be one or more.

2. The semiconductor device according to claim 1, wherein the second dummy structure is one or more.

9. 9. The semiconductor device according to claim 8, wherein the number of the second dummy structures is greater than the number of the first dummy structures.

10. 9. The semiconductor device according to claim 8, wherein the number of the first dummy structures is greater than the number of the second dummy structures.

11. a first substrate and a peripheral circuit area including circuit elements provided on the first substrate; a second substrate disposed on the peripheral circuit region; a memory cell structure disposed on the second substrate; a dummy structure disposed on at least one side of the memory cell structure on the second substrate, The memory cell structure includes: a first stacked structure including first gate electrodes and first interlayer insulating layers alternately stacked on the second substrate; a second stacked structure including second gate electrodes and second interlayer insulating layers alternately stacked on the first stacked structure; a channel structure connected to the second substrate through the first stacked structure and the second stacked structure, The dummy structure is a first dummy structure disposed on the second substrate and spaced apart from the first stacked structure, the first dummy structure including first and second insulating layers alternately stacked; a second dummy structure disposed on the second substrate at a distance from the second stacked structure and the first dummy structure, the second dummy structure including a third insulating layer and a fourth insulating layer alternately stacked thereon; a central axis between the side surfaces of the second dummy structure is shifted from a central axis between the side surfaces of the first dummy structure in at least one direction parallel to the top surface of the second substrate; The semiconductor device is characterized in that the second dummy structure is separated from the first stacked structure without overlapping with the first stacked structure in the vertical direction.

12. The semiconductor device of claim 11 , wherein the top surface of the first dummy structure does not face the bottom surface of the second dummy structure.

13. The semiconductor device of claim 11 , wherein the first dummy structure does not overlap the second dummy structure in the vertical direction.

14. a first capping insulating layer covering the first stacked structure and the first dummy structure; a second capping insulating layer covering the second stacked structure and the second dummy structure, The semiconductor device of claim 11 , wherein an upper surface of the first dummy structure overlaps the second capping insulating layer in the vertical direction.

15. the first dummy structure and the second dummy structure each have a step-like step; 12. The semiconductor device of claim 11, wherein the top step of the first dummy structure does not overlap the bottom step of the second dummy structure in the vertical direction.

16. 12. The semiconductor device of claim 11, wherein the central axis of the first dummy structure and the central axis of the second dummy structure are spaced apart from the central axis between the side surfaces of the memory cell structure by different distances.

17. the second insulating layers are disposed at height levels corresponding to the first gate electrodes and have the same thickness; 12. The semiconductor device according to claim 11, wherein the fourth insulating layers are disposed at a height level corresponding to the second gate electrodes and have the same thickness.

18. each of the first and second insulating layers includes a first portion and a second portion extending from the first portion; The semiconductor device according to claim 11 , wherein the second portion includes a portion that is bent downward toward the first substrate.

19. a first substrate, a peripheral circuit region including circuit elements provided on the first substrate, a second substrate disposed on the peripheral circuit region, a memory cell structure disposed on the second substrate, a dummy structure disposed on at least one side of the memory cell structure on the second substrate, and an input / output pad electrically connected to the circuit elements, wherein the memory cell structure comprises a first stacked structure including first gate electrodes and first interlayer insulating layers alternately stacked on the second substrate, a second stacked structure including second gate electrodes and second interlayer insulating layers alternately stacked on the first stacked structure, and an input / output pad connected to the second substrate through the first stacked structure and the second stacked structure; a channel structure formed on the second substrate, the dummy structure including a first dummy structure disposed on the second substrate at a distance from the first stacked structure and including alternately stacked first and second insulating layers, and a second dummy structure disposed on the second substrate at a distance from the second stacked structure and the first dummy structure and including alternately stacked third and fourth insulating layers, a central axis between side surfaces of the second dummy structure being shifted in at least one direction parallel to an upper surface of the second substrate from a central axis between side surfaces of the first dummy structure, and the second dummy structure being separated from the first stacked structure in a vertical direction without overlapping with the first stacked structure; a controller electrically connected to the semiconductor memory device via the input / output pads and controlling the semiconductor memory device.

20. 20. The data storage system of claim 19, wherein the first dummy structure and the second dummy structure of the semiconductor memory device do not overlap in the vertical direction.

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