Semiconductor Devices

Abstract

To provide a semiconductor device capable of suppressing defects in bonding between a lead and a semiconductor element.SOLUTION: Included are a semiconductor element 3, a support member 1, a bonding layer 4 interposed between the semiconductor element 3 and the support member 1, and a sealing resin 6 that covers the semiconductor element 3 and at least a portion of the support member 1. The bonding layer 4 is a layer in which a layer containing first metal and a layer containing second metal are integrated without going through a molten state. The support member 1 includes a first surface 1a facing in a z direction and facing a side on which the semiconductor element 3 is located, and a plurality of first recesses 18 located outside the bonding layer 4 and recessed from the first surface 1a when viewed along the z direction.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] A semiconductor device is disclosed that includes leads, a semiconductor element, and solder that joins the leads and the semiconductor element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-088319 Summary of the Invention [Problem to be solved by the invention]

[0004] When a temperature change occurs during mounting or use of a semiconductor device, thermal stress occurs due to the difference in the thermal expansion coefficient between the lead and the semiconductor element. This thermal stress tends to increase as the thickness of the bonding layer, such as solder, becomes thinner. This thermal stress may cause defects such as cracks and peeling in the bond between the lead and the semiconductor element.

[0005] The present disclosure has been made in light of the above circumstances, and an object of the present disclosure is to provide a semiconductor device that can suppress defects in the bonding between the leads and the semiconductor element. [Means for solving the problem]

[0006] The semiconductor device provided by the present disclosure comprises a semiconductor element, a support member, a bonding layer interposed between the semiconductor element and the support member, and a sealing resin covering the semiconductor element and at least a portion of the support member, wherein the bonding layer is a layer formed by integrating a layer containing a first metal and a layer containing a second metal without going through a molten state, and the support member has a first surface facing in a thickness direction and toward the side where the semiconductor element is located, and a plurality of first recesses located outside the bonding layer when viewed along the thickness direction and recessed from the first surface. [Effects of the Invention]

[0007] According to the present disclosure, defects in the bonding between the lead and the semiconductor element can be suppressed.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 3] FIG. 3 is a front view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is a side view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 5] FIG. 5 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is an enlarged cross-sectional view of a main part showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 8] 8 is an enlarged cross-sectional view of a main part taken along line VI-VI in FIG. [Figure 9] 9 is an enlarged cross-sectional view of a main part taken along line VI-VI in FIG. [Figure 10] FIG. 10 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. [Figure 11] FIG. 11 is a plan view of a main part illustrating the method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. [Figure 12] 12 is an enlarged cross-sectional view of a main part taken along line XII-XII in FIG. [Figure 13] FIG. 13 is a plan view of a main part illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. [Figure 14] 14 is an enlarged cross-sectional view of a main part taken along line XIV-XIV in FIG. [Figure 15] FIG. 15 is a cross-sectional view of a main part illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. [Figure 16] FIG. 16 is an enlarged cross-sectional view of a main part illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. [Figure 17] FIG. 17 is an enlarged cross-sectional view of a main part illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. [Figure 18] FIG. 18 is an enlarged cross-sectional view of a main part illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. [Figure 19] FIG. 19 is a cross-sectional view of a main part illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. [Figure 20] FIG. 20 is an enlarged cross-sectional view of a main part showing a first modified example of the semiconductor device according to the first embodiment of the present disclosure. [Figure 21] FIG. 21 is an enlarged cross-sectional view of a main part illustrating a manufacturing method of a first modified example of the semiconductor device according to the first embodiment of the present disclosure. [Figure 22] FIG. 22 is a perspective view showing a semiconductor device according to the second embodiment of the present disclosure. [Figure 23] FIG. 23 is a perspective view showing a first modified example of the semiconductor device according to the second embodiment of the present disclosure. [Figure 24] FIG. 24 is a perspective view showing a second modified example of the semiconductor device according to the second embodiment of the present disclosure. [Figure 25]FIG. 25 is a perspective view showing a third modified example of the semiconductor device according to the second embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0011] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.

[0012] First Embodiment 1 to 9 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of this embodiment includes a support member 1, a conductive member 2, a semiconductor element 3, a bonding layer 4, wires 5, and a sealing resin 6.

[0013] FIG. 1 is a perspective view showing the semiconductor device A1. FIG. 2 is a plan view showing the semiconductor device A1. FIG. 3 is a front view showing the semiconductor device A1. FIG. 4 is a side view showing the semiconductor device A1. FIG. 5 is a cross-sectional view taken along line VV in FIG. 2. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 2. FIG. 7 is an enlarged cross-sectional view showing a main part of the semiconductor device A1. FIG. 8 is an enlarged cross-sectional view taken along line VI-VI in FIG. 2. FIG. 9 is an enlarged cross-sectional view taken along line VI-VI in FIG. 2. In these figures, the z direction is the thickness direction in this disclosure. The x direction and the y direction are both perpendicular to the z direction and perpendicular to each other. In FIGS. 1 to 4, the sealing resin 6 is shown by an imaginary line. For ease of understanding, the bonding layer 4 is omitted in FIGS. 1 to 6. FIG. 7 is an enlarged cross-sectional view showing a main part near the center of the semiconductor element 3 as viewed along the z direction.

[0014] [Support member 1] The support member 1 is a member that supports the semiconductor element 3. There are no particular limitations on the specific configuration of the support member 1. As shown in FIGS. 1 to 6, the support member 1 of this embodiment has a die bonding portion 13 and an extending portion 14.

[0015] The die bonding portion 13 is a portion that supports the semiconductor element 3. The shape of the die bonding portion 13 is not particularly limited, and in the illustrated example, it is rectangular.

[0016] The extension portion 14 is a portion extending from the die bonding portion 13 to one side in the x direction. The shape of the extension portion 14 is not particularly limited, and in the illustrated example, it is a strip-like shape extending in the x direction when viewed along the z direction. Furthermore, the extension portion 14 has a bent portion as shown in FIGS. 1, 3, and 5.

[0017] In this embodiment, as shown in FIGS. 7 and 8, the support member 1 has a base material 11 and a surface layer 12. The base material 11 is a portion that forms the main body of the support member 1. The base material 11 contains a metal such as Cu, Fe, or Ni, or an alloy thereof. In the following description, an example will be given in which the base material 11 contains Cu. The thickness of the base material 11 is not particularly limited and is, for example, 100 mm or more and 400 mm or less.

[0018] The surface layer 12 is a layer formed on the base material 11 and contains a second metal. Examples of the second metal in the present disclosure include Ag, Au, Cu, Pt, Pd, Ni, Co, Fe, Mn, V, Ti, Ce, Dy, Y, Yb, Hf, Mg, and Sn. In this embodiment, a metal capable of forming an alloy with the first metal described below is selected as the second metal. The following description will be given using an example in which the second metal is Ag. The thickness of the surface layer 12 is, for example, 2 μm to 5 μm, for example, approximately 3 μm. The method for forming the surface layer 12 is not particularly limited, and it may be formed by plating, for example. In this embodiment, the surface layer 12 is formed on the die bonding portion 13. The surface layer 12 constitutes a first surface 1a of the die bonding portion 13. The first surface 1a is a surface facing one side in the z direction.

[0019] As shown in FIGS. 2 and 8 , the support member 1 of this embodiment has a plurality of first recesses 18. In FIG. 2 , the plurality of first recesses 18 are indicated by a plurality of straight lines extending in the x direction. The plurality of first recesses 18 are recessed from the first surface 1a. When viewed along the z direction, the plurality of first recesses 18 are formed at positions that avoid the semiconductor element 3 and the bonding layer 4. In the illustrated example, the plurality of first recesses 18 are formed in an annular region that surrounds the semiconductor element 3 when viewed along the z direction. The plurality of first recesses 18 are filled with the sealing resin 6.

[0020] The method for forming the plurality of first recesses 18 is not limited in any way, and examples thereof include laser processing, etching, stamping, etc. In the illustrated example, the plurality of first recesses 18, each extending along the x direction, are formed by laser processing.

[0021] 8, the first recesses 18 of this embodiment penetrate the surface layer 12 and reach the substrate 11. In this case, the depth of the first recesses 18 is equal to or greater than the thickness of the surface layer 12. The depth of the first recesses 18 is, for example, equal to or greater than 3 μm and equal to or less than 5 μm.

[0022] [Conductive member 2] The conductive member 2 is a member that forms a conductive path between the semiconductor element 3 and the outside. The specific configuration of the conductive member 2 is not limited in any way. The conductive member 2 is separated from the support member 1, and in this embodiment, is separated from the support member 1 in the x direction. As shown in FIGS. 1 to 6 , the conductive member 2 of this embodiment has a wire bonding portion 23 and an extending portion 24.

[0023] The wire bonding portion 23 is a portion to which the wire 5 is bonded. There are no particular limitations on the shape of the wire bonding portion 23, and in the illustrated example, it has an elongated rectangular shape with the y direction as the longitudinal direction.

[0024] The extension portion 24 is a portion extending from the wire bonding portion 23 to the other side in the x direction. The shape of the extension portion 24 is not particularly limited, and in the illustrated example, it is a strip-like shape extending in the x direction when viewed along the z direction. Furthermore, the extension portion 24 has a bent portion as shown in FIGS. 1, 3, and 5.

[0025] In this embodiment, as shown in Fig. 9, the conductive member 2 has a base material 21 and a surface layer 22. The base material 21 is a portion that forms the main body of the conductive member 2. The base material 21 contains a metal such as Cu, Fe, or Ni, or an alloy thereof. In the following description, the case where the base material 21 contains Cu will be described as an example. The thickness of the base material 21 is not particularly limited and is, for example, 100 mm or more and 400 mm or less.

[0026] The surface layer 22 is a layer formed on the base material 21. There are no limitations on the metal contained in the surface layer 22, and in this embodiment, the surface layer 22 contains Ag, which is the same as the second metal contained in the surface layer 12. The surface layer 22 may also contain a metal different from the metal contained in the surface layer 12. The thickness of the surface layer 22 is, for example, 2 μm or more and 5 μm or less, and is set to, for example, approximately 3 μm. There are no limitations on the method for forming the surface layer 22, and it may be formed by plating, for example. In this embodiment, the surface layer 22 is formed on the wire bonding portion 23. The surface layer 22 constitutes the second surface 2a of the wire bonding portion 23. The second surface 2a is a surface facing one side in the z direction.

[0027] As shown in FIGS. 2 and 9 , the conductive member 2 of this embodiment has a plurality of second recesses 28. In FIG. 2 , the plurality of second recesses 28 are indicated by a plurality of straight lines extending in the x direction. The plurality of second recesses 28 are recessed from the second surface 2a. When viewed along the z direction, the plurality of second recesses 28 are formed at positions that avoid second bonding portions 52 (described below) of the wire 5. In the illustrated example, the plurality of second recesses 28 are formed in an annular region that surrounds the second bonding portion 52 when viewed along the z direction. The plurality of second recesses 28 are filled with the sealing resin 6.

[0028] The method for forming the plurality of second recesses 28 is not limited in any way, and examples thereof include laser processing, etching, stamping, etc. In the illustrated example, the plurality of second recesses 28, each extending along the x direction, are formed by laser processing.

[0029] 9, the second recesses 28 of this embodiment penetrate the surface layer 22 and reach the substrate 21. In this case, the depth of the second recesses 28 is equal to or greater than the thickness of the surface layer 22. The depth of the first recesses 18 is, for example, equal to or greater than 3 μm and equal to or less than 5 μm.

[0030] [Semiconductor element 3] The semiconductor element 3 functions to form part of an electric circuit when the semiconductor device A1 is incorporated into the electric circuit. The specific configuration of the semiconductor element 3 is not limited in any way. Examples of the semiconductor element 3 include a diode and a transistor. In this embodiment, a diode is selected as the semiconductor element 3.

[0031] The semiconductor element 3 is supported by the die bonding portion 13 of the support member 1. A surface layer 12 is formed in the portion of the die bonding portion 13 that supports the semiconductor element 3, and the plurality of first recesses 18 are not formed therein.

[0032] 7 and 8, the semiconductor element 3 includes a semiconductor layer 30. The semiconductor layer 30 includes a semiconductor such as Si, SiC, or GaN. An electrode (not shown) is formed on the semiconductor layer 30, and a wire 5 is bonded to this electrode.

[0033] In this embodiment, the semiconductor element 3 includes a first layer 31, a second layer 32, and an underlayer 39.

[0034] The first layer 31 is interposed between the semiconductor layer 30 and the bonding layer 4. The first layer 31 includes a third metal. Examples of the third metal include Ag, Au, Cu, Pt, Pd, Ni, Co, Fe, Mn, V, Ti, Ce, Dy, Y, Yb, Hf, and Mg. In this embodiment, a metal capable of forming an alloy with the first metal described below is selected as the third metal. In the following description, an example will be given in which the third metal is Ni. The thickness of the first layer 31 is, for example, It is set to 0.1 μm or more and 0.5 μm or less, for example, about 0.3 μm.

[0035] The second layer 32 is interposed between the first layer 31 and the bonding layer 4. The second layer 32 includes an alloy of a first metal and a third metal. Examples of the first metal include Ag, Au, Cu, Pt, Pd, Ni, Co, Fe, Mn, V, Ti, Ce, Dy, Y, Yb, Hf, Mg, and Sn. In this embodiment, a metal capable of forming an alloy with the second metal and the third metal is selected as the first metal. In the following description, an example in which the first metal is Sn will be described. That is, the second layer 32 of this embodiment includes a Sn-Ni alloy, which is an alloy of Sn and Ni. The thickness of the second layer 32 is, for example, 0.1 μm or more and 0.5 μm or less.

[0036] The underlayer 39 is interposed between the semiconductor layer 30 and the first layer 31 and is in direct contact with the semiconductor layer 30. The underlayer 39 contains, for example, Ti. The thickness of the underlayer 39 is, for example, not less than 0.05 μm and not more than 0.2 μm, and is set to, for example, about 0.1 μm.

[0037] [Joining layer 4] As shown in FIGS. 7 and 8, the bonding layer 4 is interposed between the semiconductor element 3 and the support member 1. The bonding layer 4 functions to bond the semiconductor element 3 and the support member 1. The bonding layer 4 includes an alloy of a first metal and a second metal. Examples of alloys of the first metal and the second metal include Ag3Sn, PtSn4, PtSn2, Pt2Sn3, PdSn4, PdSn3, PdSn2, Ni3Sn4, CoSn2, FeSn2, MnSn2, V2Sn3, CeSn3, DySn4, Sn3Y, Sn3Yb, and Hf5Sn2. As described above, Sn is selected as the first metal and Ag is selected as the second metal. In this case, the bonding layer 4 includes Ag3Sn, which is an alloy of Sn as the first metal and Ag as the second metal. The Ag composition ratio of bonding layer 4 is 73 mass % or more. There are no particular limitations on the thickness of bonding layer 4, and it is set to, for example, 2 μm or more and 5 μm or less, for example, about 3 μm.

[0038] As will be understood from the manufacturing method of the semiconductor device A1 described later, most of the bonding layer 4 overlaps with the semiconductor element 3 when viewed along the z direction. Depending on the conditions of the manufacturing method, the bonding layer 4 may have a portion that slightly protrudes from the semiconductor element 3 in a direction perpendicular to the z direction (such as the x direction or y direction) when viewed along the z direction, as shown in Fig. 8. However, unlike the example shown in the figure, the bonding layer 4 may be configured not to protrude from the semiconductor element 3 when viewed along the z direction.

[0039] 8, depending on the conditions of the manufacturing method, bonding layer 4 may have a portion located closer to base material 11 in the z direction than first surface 1a. In this case, a portion of bonding layer 4 is embedded in surface layer 12. However, bonding layer 4 may also be located farther from base material 11 in the z direction than first surface 1a.

[0040] [Wire 5] The wire 5 forms a conductive path between the semiconductor element 3 and the outside. In this embodiment, the wire 5 electrically connects the semiconductor element 3 and the conductive member 2. There are no limitations on the material of the wire 5, and examples thereof include Au, Al, Cu, etc.

[0041] The wire 5 has a first bonding portion 51 and a second bonding portion 52. The first bonding portion 51 is a portion bonded to the above-mentioned electrode (not shown) of the semiconductor element 3. The second bonding portion 52 is a portion bonded to the second surface 2a of the wire bonding portion 23 of the conductive member 2.

[0042] [Sealing resin 6] The sealing resin 6 covers parts of the support member 1 and the conductive member 2, as well as the semiconductor element 3, the bonding layer 4, and the wires 5. The sealing resin 6 contains an insulating resin, such as a black epoxy resin.

[0043] The shape of the sealing resin 6 is not limited in any way, and in the illustrated example, as shown in Figures 1 to 6, it has a first surface 61, a second surface 62, a third surface 63, a fourth surface 64, a fifth surface 65 and a sixth surface 66.

[0044] The first surface 61 faces one side in the z direction and is a flat surface in the illustrated example. The second surface 62 faces the other side in the z direction and is a flat surface in the illustrated example. The third surface 63 faces one side in the x direction and is a curved surface in the illustrated example. The fourth surface 64 faces the other side in the x direction and is a curved surface in the illustrated example. The fifth surface 65 faces one side in the y direction and is a curved surface in the illustrated example. The sixth surface 66 faces the other side in the y direction and is a curved surface in the illustrated example.

[0045] In this embodiment, the extending portion 14 of the support member 1 protrudes from the third surface 63 of the sealing resin 6 to one side in the x-direction. Also, the extending portion 24 of the conductive member 2 protrudes from the fourth surface 64 of the sealing resin 6 to the other side in the x-direction.

[0046] In this embodiment, the surface of the extending portion 14 facing the other side in the z direction is flush with the second surface 62. In addition, the surface of the extending portion 24 facing the other side in the z direction is flush with the second surface 62.

[0047] Next, a method for manufacturing the semiconductor device A1 will be described below with reference to FIGS.

[0048] 10 is a flowchart showing an example of a method for manufacturing the semiconductor device A1. The illustrated manufacturing method includes the steps of preparing a semiconductor element 3, preparing a support member 1, and forming a bonding layer 4.

[0049] First, a support member 1 is prepared as shown in Figures 11 and 12. The illustrated support member 1 is configured to be included as part of a lead frame together with a conductive member 2. This lead frame is used to collectively manufacture a plurality of semiconductor devices A1. However, the semiconductor devices A1 may also be manufactured individually.

[0050] The support member 1 shown in these figures includes a base material 11 and a surface layer 12, and has a die bonding portion 13 and an extension portion 14. In this example, the base material 11 contains Cu. The surface layer 12 is a layer of approximately uniform thickness formed on the base material 11 by plating or the like. The thickness of the surface layer 12 is, for example, not less than 2 μm and not more than 5 μm, and is set to, for example, about 3 μm. In this example, the surface layer 12 contains Ag.

[0051] The conductive member 2 includes a base material 21 and a surface layer 22, and has a wire bonding portion 23 and an extension portion 24. In this example, the base material 21 contains Cu. The surface layer 22 is a layer of approximately uniform thickness formed on the base material 21 by plating or the like. The thickness of the surface layer 22 is, for example, not less than 2 μm and not more than 5 μm, and is set to, for example, about 3 μm. In this example, the surface layer 22 contains Ag.

[0052] Next, as shown in Figures 13 and 14, a plurality of first recesses 18 are formed in the support member 1, and a plurality of second recesses 28 are formed in the conductive member 2. There are no particular limitations on the method for forming the plurality of first recesses 18 and the plurality of second recesses 28, and examples thereof include laser processing, etching, stamping, etc. In the illustrated example, a plurality of first recesses 18 and a plurality of second recesses 28 each extending along the x direction are formed. 2 recess 2 8 is formed by laser processing.

[0053] For example, laser light L is irradiated onto the first surface 1a of the die bonding portion 13 of the support member 1 and scanned sequentially in the x direction. The laser light L removes a portion of the surface layer 12 and reaches the base material 11. This forms a plurality of first recesses 18 that penetrate the surface layer 12 and reach the base material 11.

[0054] Furthermore, laser light L is irradiated onto second surface 2a of wire bonding portion 23 of conductive member 2 and scanned sequentially in the x direction. This laser light L removes a portion of surface layer 22 and reaches base material 21. As a result, a plurality of second recesses 28 are formed that penetrate surface layer 22 and reach base material 21.

[0055] 15 and 16, a semiconductor element 3 is prepared. The order of the steps of preparing the support member 1 and preparing the semiconductor element 3 is not limited, and they may be performed simultaneously.

[0056] 16, the semiconductor element 3 includes a semiconductor layer 30 and a third layer 33. The semiconductor layer 30 is a layer containing a semiconductor as described above. The third layer 33 is a layer containing a first metal, which in this example contains Sn. The thickness of the third layer 33 is not particularly limited and is set to, for example, 1.5 μm or more and 4 μm or less, for example, approximately 2.5 μm.

[0057] The semiconductor element 3 of this example also includes a fourth layer 34 , a fifth layer 35 and an underlayer 39 .

[0058] The fourth layer 34 is interposed between the semiconductor layer 30 and the third layer 33. The fourth layer 34 is a layer that becomes the first layer 31 in the semiconductor element 3 of the semiconductor device A1 described above. The fourth layer 34 includes a third metal. Examples of the third metal include Ag, Au, Cu, Pt, Pd, Ni, Co, Fe, Mn, V, Ti, Ce, Dy, Y, Yb, Hf, and Mg, and in this example, Ni. The thickness of the fourth layer 34 is, for example, not less than 0.1 μm and not more than 0.5 μm, and is set to, for example, approximately 0.3 μm.

[0059] The fifth layer 35 is interposed between the fourth layer 34 and the third layer 33. The fifth layer 35 is a layer containing the same first metal as the surface layer 12, which contains Ag in this example. The thickness of the fifth layer 35 is, for example, not less than 0.5 μm and not more than 2.0 μm, and is set to, for example, about 1.0 μm.

[0060] The base layer 39 is interposed between the semiconductor layer 30 and the fourth layer 34, and is in direct contact with the semiconductor layer 30. As described above, the base layer 39 contains, for example, Ti. The thickness of the base layer 39 is, for example, not less than 0.05 μm and not more than 0.2 μm, and is set to, for example, about 0.1 μm.

[0061] Next, a step of forming the bonding layer 4 is performed. As shown in Fig. 10 , in this embodiment, the step of forming the bonding layer 4 includes a process of heating the support member 1 and a process of bringing the third layer 33 and the surface layer 12 into contact with each other.

[0062] In the process of heating the support member 1, the support member 1 is heated to a temperature above which the first metal contained in the third layer 33 and the second metal contained in the surface layer 12 can be alloyed by coming into contact with each other.

[0063] 17, a process is performed to bring the third layer 33 into contact with the surface layer 12. This brings the surface layer 12, which is part of the heated support member 1, into contact with the third layer 33. This contact transfers heat from the preheated support member 1 to the semiconductor element 3, which includes the third layer 33, and heats the semiconductor element 3. As a result, Sn as the first metal of the third layer 33 and Ag as the second metal of the surface layer 12 are alloyed to produce Ag3Sn, an alloy of Sn and Ag, and a bonding layer 4 containing Ag3Sn is formed.

[0064] During the formation of the bonding layer 4, Sn contained in the third layer 33 may diffuse into the portion that was previously the surface layer 12. When Sn diffuses in the z direction, the bonding layer 4 has a portion that is located closer to the base material 11 in the z direction than the first surface 1a. When Sn diffuses in a direction perpendicular to the z direction, the bonding layer 4 has a portion that protrudes from the semiconductor element 3 when viewed along the z direction.

[0065] In this embodiment, in this step, the fifth layer 35 containing the second metal shown in FIG. 17 is heated, whereby it is alloyed with the third layer 33 and forms a part of the bonding layer 4 shown in FIG. 18. In this example, the entire fifth layer 35 diffuses into the third layer 33 and forms a part of the bonding layer 4. Furthermore, Ni as the third metal contained in the fourth layer 34 shown in FIG. 17 is alloyed with Sn as the first metal contained in the third layer 33, forming the second layer 32 shown in FIG. 18. In this example, the second layer 32 contains a Sn-Ni alloy, which is an alloy of Sn and Ni.

[0066] By going through the process of forming the bonding layer 4 as described above, the semiconductor element 3 is bonded to the support member 1 as shown in FIGS.

[0067] Unlike this embodiment, the bonding layer 4 may be formed by carrying out a process of bringing the third layer 33 and the surface layer 12 into contact with each other, and then carrying out a process of heating the support member 1 and the semiconductor element 3.

[0068] Thereafter, by appropriately performing the steps of bonding the wires 5 to the conductive member 2 and the semiconductor element 3 and the step of forming the sealing resin 6, the above-mentioned semiconductor device A1 is obtained.

[0069] Next, the operation of the semiconductor device A1 and the method for manufacturing the semiconductor device A1 will be described.

[0070] According to this embodiment, as shown in Figures 7 and 8, the bonding layer 4 contains an alloy of a first metal and a second metal. This makes it possible to increase the melting point of the bonding layer 4. This makes it possible to increase the melting point of the bonding layer 4 above the temperature to which the semiconductor device A1 is exposed, for example, during a mounting process in which the semiconductor device is mounted on a circuit board or the like. This makes it possible to suppress defects such as cracks and peeling in the bond between the support member 1 and the semiconductor element 3.

[0071] Sn is selected as the first metal, and Ag is selected as the second metal. This allows the bonding layer 4 to contain Ag3Sn. The melting point of Ag3Sn is 480°C. Therefore, even if the semiconductor device A1 is exposed to a temperature of approximately 400°C during the mounting process of the semiconductor device A1, defects such as cracks and peeling can be suppressed in the bonding layer 4. Having an Ag composition ratio of 73 mass% or more in the bonding layer 4 is preferable for ensuring the presence of Ag3Sn in the bonding layer 4. Furthermore, Ag has a high degree of diffusion into Sn. This allows Ag to be diffused throughout the Sn, reducing the areas where Sn remains as a single metal. This is preferable for suppressing bonding defects caused by Sn, which has a low melting point.

[0072] In manufacturing the semiconductor device A1, as shown in FIG. 17, the third layer 33 containing Sn as the first metal and the surface layer 12 containing Ag as the second metal are brought into contact with each other and heated to form the bonding layer 4. This bonding method does not require high-pressure application or other processes, and alloying is completed quickly upon contact. This improves the manufacturing efficiency of the semiconductor device A1. Furthermore, the bonding layer 4 formed by this process can be significantly thinner than the thickness of solder in a structure joined by solder, for example. This reduces the resistance and improves the thermal conductivity between the support member 1 and the semiconductor element 3. As shown in FIG. 10, the process of forming the bonding layer 4 can be further shortened by first heating the support member 1 and then bringing the third layer 33 and the surface layer 12 into contact with each other.

[0073] 17, in the step of forming the bonding layer 4, the third layer 33 is sandwiched between the surface layer 12 and the fifth layer 35. The third layer 33 contains Sn as a first metal, and the surface layer 12 and the fifth layer 35 contain Ag as a second metal. This allows Ag to diffuse from both sides of the third layer 33 in the z direction. This is therefore preferable for increasing the occupancy rate of Ag3Sn in the bonding layer 4 and reducing the areas where Sn remains as a simple metal.

[0074] As shown in FIG. 8 , the semiconductor element 3 of the semiconductor device A1 has a first layer 31. The first layer 31 contains Ni as a third metal. Furthermore, by having the first layer 31, the semiconductor element 3 also has a second layer 32. The second layer 32 contains an alloy of the first metal and a third metal, which in this example contains an Sn—Ni alloy. With this configuration, in the step of forming the bonding layer 4, the second metal, such as Ag, contained in the third layer 33 for forming the bonding layer 4 can be prevented from diffusing into the semiconductor layer 30. Providing the base layer 39 is preferable for preventing the second metal from diffusing into the semiconductor layer 30.

[0075] The support member 1 has a plurality of first recesses 18 formed therein. The plurality of first recesses 18 are filled with a sealing resin 6. As a result, for example, when the semiconductor device A1 is heated during mounting or use thereof, and the support member 1 exhibits a behavior of expanding relative to the semiconductor element 3, the sealing resin 6 functions to suppress the expansion of the support member 1. This makes it possible to reduce thermal stress occurring in the bonding layer 4 sandwiched between the support member 1 and the semiconductor element 3. In particular, when the bonding layer 4 is formed by alloying a first metal and a second metal, the thickness of the bonding layer 4 is thinner than, for example, the thickness of the solder. The thinner the thickness of the bonding layer 4, the greater the thermal stress that can be caused. In this embodiment, the provision of a plurality of first recesses 18 suppresses thermal stress. Figure et al. This can prevent bonding defects in the semiconductor device A1 in which a thin bonding layer 4 is used.

[0076] The first recesses 18 penetrate the surface layer 12 and reach the base material 11. When the bonding strength between the sealing resin 6 and the surface layer 12 is weaker than the bonding strength between the sealing resin 6 and the base material 11, the bonding strength between the sealing resin 6 and the support member 1 (plurality of first recesses 18) can be increased.

[0077] A plurality of second recesses 28 are formed in the conductive member 2. The plurality of second recesses 28 are filled with the sealing resin 6. This makes it possible to increase the bonding strength between the conductive member 2 (the plurality of second recesses 28) and the sealing resin 6.

[0078] The second recesses 28 penetrate the surface layer 22 and reach the base material 21. When the bonding strength between the sealing resin 6 and the surface layer 22 is weaker than the bonding strength between the sealing resin 6 and the base material 21, the bonding strength between the sealing resin 6 and the conductive member 2 (plurality of second recesses 28) can be increased.

[0079] 20 to 25 show modifications and other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals as those in the above embodiment.

[0080] <First Modification of First Embodiment> 20 shows a first modified example of the semiconductor device A1. In the semiconductor device A11 of this modified example, the bonding layer 4 is formed by solid-phase diffusion bonding.

[0081] The bonding layer 4 is a layer formed by solid-state diffusion bonding, in which two layers are bonded together under predetermined conditions such as temperature and pressure. The bonding layer 4 has a bonding interface 41. The bonding interface 41 is the surface where the boundary between the two layers bonded by solid-state diffusion existed. When ideal solid-state diffusion bonding is performed, the bonding interface 41 may not be clearly visible or may be barely discernible.

[0082] The bonding layer 4 in the semiconductor device A1 described above is a layer formed by an alloying process. Thus, the bonding layer 4 in the present disclosure is a layer integrated without going through a molten state. When the bonding layer 4 is formed by solid-state diffusion bonding, the first metal and the second metal are the same metal. In this modification, Ag is selected as the first metal and the second metal of the bonding layer 4.

[0083] 21 shows an example of a manufacturing method for a semiconductor device A11. The semiconductor element 3 has a semiconductor layer 30, a base layer 39, and a third layer 33. The third layer 33 contains Ag as a first metal. The support member 1 has a base material 11 and a surface layer 12. The surface layer 12 contains Ag as a second metal. The third layer 33 and the surface layer 12, both of which contain the same metal, are brought into contact under predetermined conditions such as temperature and pressure, and are solid-state diffusion bonded to each other, forming a bonding layer 4.

[0084] This modification also makes it possible to suppress defects such as cracks and peeling in the bond between the support member 1 and the semiconductor element 3. Furthermore, as can be seen from this modification, the specific configuration of the bonding layer 4 is not limited in any way as long as it is a layer in which the first metal and the second metal are integrated without going through a molten state.

[0085] Second Embodiment 22 is a perspective view showing a semiconductor device according to a second embodiment of the present disclosure. The semiconductor device A2 of this embodiment includes a support member 1A, a support member 1B, a conductive member 2, a semiconductor element 3A, a semiconductor element 3B, a plurality of bonding layers 4 (not shown), a plurality of wires 5, and a sealing resin 6.

[0086] The support member 1A has the same components as the support member 1 described above, and has a die bonding portion 13 and an extension portion 14. The support member 1A also has a base material 11 and a surface layer 12. The surface layer 12 is provided in the die bonding portion 13. A plurality of first recesses 18 are formed in the support member 1A. The semiconductor element 3A is bonded to the die bonding portion 13 of the support member 1A via a bonding layer 4. The configuration of the bonding layer 4 may be the same as that of the first embodiment described above and its modified examples, as appropriate.

[0087] Support member 1B has the same components as support member 1 described above, and has a die bonding portion 13 and an extension portion 14. Support member 1B also has a base material 11 and a surface layer 12. Surface layer 12 is provided in die bonding portion 13. Support member 1B has a plurality of first recesses 18 formed therein. Semiconductor element 3B is bonded to die bonding portion 13 of support member 1B via a bonding layer 4. The configuration of bonding layer 4 may be the same as that of the first embodiment described above and its modified examples, as appropriate.

[0088] The conductive member 2 is disposed between the support member 1A and the support member 1B. The conductive member 2 includes the same components as the above-described conductive member 2, and has a wire bonding portion 23 and an extending portion 24. The conductive member 2 also has a base material 21 and a surface layer 22. The surface layer 22 is provided on the wire bonding portion 23. The conductive member 2 has a plurality of second recesses 28 formed therein.

[0089] The semiconductor elements 3A and 3B are both diodes, for example. The electrodes (not shown) of the semiconductor elements 3A and 3B are electrically connected to the wire bonding portions 23 of the conductive member 2 by a plurality of wires 5.

[0090] This embodiment also makes it possible to suppress defects such as cracks and peeling at the joints between support members 1A and 1B and semiconductor elements 3A and 3B. As can be understood from this embodiment, the number of support members, the number of semiconductor elements, and their arrangement, etc., included in the semiconductor device according to the present disclosure are not limited in any way.

[0091] <First Modification of Second Embodiment> 23 is a perspective view showing a first modified example of the semiconductor device A2 of the present disclosure. In the semiconductor device A21 of this embodiment, the support member 1A and the support member 1B are adjacent to each other. The conductive member 2 is disposed on the opposite side of the support member 1B from the support member 1A. The semiconductor element 3A and the support member 1B are connected by a wire 5. The semiconductor element 3B and the conductive member 2 are connected by a wire 5. The bonding between the semiconductor element 3A and the support member 1A and the bonding between the semiconductor element 3B and the support member 1B are similar to those in the semiconductor device A2 described above.

[0092] This modification also makes it possible to suppress defects such as cracks and peeling at the joints between support members 1A and 1B and semiconductor elements 3A and 3B. As can be understood from this embodiment, the number of support members, the number of semiconductor elements, and their arrangement, etc., included in the semiconductor device according to the present disclosure are not limited in any way.

[0093] <Second Modification of Second Embodiment> 24 is a perspective view showing a third modified example of the semiconductor device A2 of the present disclosure. This modified example A22 has a configuration similar to the semiconductor device A21 described above, but differs from the semiconductor device A21 in the arrangement of the support member 1A, the support member 1B, and the conductive member 2. In this modified example, the support member 1A and the support member 1B are adjacent to each other, and the conductive member 2 is arranged on the opposite side of the support member 1A from the support member 1A. The semiconductor element 3B and the support member 1A are connected by a wire 5. The semiconductor element 3A and the conductive member 2 are connected by a wire 5. The bonding between the semiconductor element 3A and the support member 1A and the bonding between the semiconductor element 3B and the support member 1B are the same as those in the semiconductor device A2 described above.

[0094] This modification also makes it possible to suppress defects such as cracks and peeling at the joints between support members 1A and 1B and semiconductor elements 3A and 3B. As can be understood from this embodiment, the number of support members, the number of semiconductor elements, and their arrangement, etc., included in the semiconductor device according to the present disclosure are not limited in any way. <Third Modification of Second Embodiment> 25 is a perspective view showing a third modified example of the semiconductor device A2 of the present disclosure. The semiconductor device A23 of this modified example includes a support member 1, a conductive member 2A, a conductive member 2B, a semiconductor element 3, a bonding layer 4 (not shown), a plurality of wires 5, and a sealing resin 6.

[0095] The conductive members 2A and 2B are arranged with the support member 1 sandwiched therebetween. The semiconductor element 3 is bonded to the die bonding portion 13 of the support member 1 via a bonding layer 4 (not shown). The semiconductor element 3 in this example is, for example, a transistor. A gate electrode and a source electrode (neither of which are shown) are formed on the upper surface of the semiconductor element 3 in the figure, and a drain electrode is formed on the lower surface of the semiconductor element 3 in the figure. One of the gate electrode and the source electrode is connected to the wire bonding portion 23 of the conductive member 2A by a wire 5, and the other of the gate electrode and the source electrode is connected to the wire bonding portion 23 of the conductive member 2B by a wire 5.

[0096] This modification also makes it possible to suppress defects such as cracks and peeling at the bond between the support member 1 and the semiconductor element 3. Furthermore, as can be understood from this embodiment, the type of semiconductor element included in the semiconductor device according to the present disclosure is not limited in any way.

[0097] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are not limited to the above-described embodiment. The specific configurations of the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure can be freely modified in various ways.

[0098] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the semiconductor device according to the present disclosure and the specific configuration of the semiconductor device can be freely designed in various ways.

[0099] [Appendix 1] A semiconductor element; A support member; a bonding layer interposed between the semiconductor element and the support member; a sealing resin that covers the semiconductor element and at least a portion of the support member, the bonding layer is a layer in which a layer containing a first metal and a layer containing a second metal are integrated without going through a molten state, The support member has a first surface facing the thickness direction and facing the side where the semiconductor element is located, and a plurality of first recesses located outside the bonding layer when viewed along the thickness direction and recessed from the first surface. [Appendix 2] 2. The semiconductor device according to claim 1, wherein the plurality of first recesses are formed at positions that avoid the semiconductor element when viewed along the thickness direction. [Appendix 3] 3. The semiconductor device according to claim 2, wherein the plurality of first recesses are formed in an annular region surrounding the semiconductor element when viewed along the thickness direction. [Appendix 4] 4. The semiconductor device according to claim 1, wherein the bonding layer includes an alloy of the first metal and the second metal. [Appendix 5] the first metal is Sn, 5. The semiconductor device according to claim 4, wherein the second metal is Ag. [Appendix 6] 6. The semiconductor device according to claim 5, wherein the bonding layer contains Ag3Sn. [Appendix 7] 7. The semiconductor device according to claim 6, wherein the bonding layer has an Ag composition ratio of 73 mass % or more. [Appendix 8] 8. The semiconductor device according to any one of claims 5 to 7, further comprising a first layer interposed between the bonding layer and the semiconductor element and including a third metal. [Appendix 9] 9. The semiconductor device according to claim 8, further comprising a second layer interposed between the bonding layer and the first layer and including an alloy of the first metal and the third metal. [Appendix 10] 10. The semiconductor device of claim 9, wherein the bonding layer is thicker than the second layer. [Appendix 11] 11. The semiconductor device according to any one of claims 5 to 10, wherein the support member includes a base material and a surface layer that is interposed between the base material and the bonding layer and that constitutes the first surface. [Appendix 12] 12. The semiconductor device according to claim 11, wherein the surface layer is thinner than the base material. [Appendix 13] 13. The semiconductor device according to claim 11, wherein the surface layer contains Ag. [Appendix 14] 14. The semiconductor device according to claim 13, wherein the substrate contains Cu. [Appendix 15] 15. The semiconductor device according to any one of claims 11 to 14, wherein the first recess penetrates the surface layer and reaches the base material. [Appendix 16] a conductive member positioned apart from the support member; a wire connected to the semiconductor element and the conductive member, the conductive member has a second surface to which the wire is joined and a plurality of second recesses recessed from the second surface, A semiconductor device according to any one of appendixes 1 to 15, wherein the plurality of second recesses are formed at positions that avoid the joint between the wire and the conductive member when viewed along the thickness direction. [Appendix 17] 17. The semiconductor device according to claim 16, wherein the second recess is deeper than the first recess. [Explanation of symbols]

[0100] A1, A11, A2, A21, A23: semiconductor device 1B: Support member 1a: 1st page 2,2A,2B: Conductive member 2a: 2nd side 3,3A,3B: Semiconductor element 4: Bonding layer 5: Wire 6: Sealing resin 11: Base material 12: Surface layer 13: Die bonding section 14:Extending part 18: First recess 21: Base material 22: Surface layer 23: Wire bonding section 24:Extension part 28: Second recess 30: Semiconductor layer 31: 1st layer 32: 2nd layer 33:Third layer 34: 4th layer 35: 5th layer 39: Base layer 51: First Bonding Department 52: Second bonding section 61: 1st page 62: 2nd side 63:Side 3 64:Side 4 65:Side 5 66:Side 6 L: Laser light

Claims

1. A semiconductor element; A support member; a bonding layer interposed between the semiconductor element and the support member; a sealing resin that covers the semiconductor element and at least a portion of the support member, the bonding layer is a layer in which a layer containing a first metal and a layer containing a second metal are integrated without going through a molten state, the support member has a first surface facing a thickness direction and facing a side on which the semiconductor element is located, and a plurality of first recesses positioned outside the bonding layer as viewed along the thickness direction and recessed from the first surface, the support member includes a base material and a surface layer that is interposed between the base material and the bonding layer and that forms the first surface, the first recess has a first portion formed on the surface layer and a second portion formed on the base material, A semiconductor device, wherein the dimension of the first portion in the thickness direction is greater than the dimension of the second portion in the thickness direction.

2. A semiconductor device as described in claim 1, wherein the opening dimension at the first surface of the first part is larger than the opening dimension at the boundary surface between the surface layer of the second part and the substrate.

3. A semiconductor device as described in claim 1 or 2, wherein the thickness of the bonding layer is 2 μm or more and 5 μm or less.

4. 4. The semiconductor device according to claim 1, wherein the plurality of first recesses are formed at positions that avoid the semiconductor element when viewed along the thickness direction.

5. The semiconductor device according to claim 4 , wherein the plurality of first recesses are formed in an annular region surrounding the semiconductor element when viewed along the thickness direction.

6. 6. The semiconductor device according to claim 1, wherein the bonding layer contains an alloy of the first metal and the second metal.

7. the first metal is Sn; The semiconductor device according to claim 6 , wherein the second metal is Ag.

8. The bonding layer is made of Ag ３ The semiconductor device according to claim 7 , comprising Sn.

9. 9. The semiconductor device according to claim 8, wherein the bonding layer has an Ag composition ratio of 73 mass % or more.

10. 10. The semiconductor device according to claim 7, further comprising a first layer interposed between said bonding layer and said semiconductor element and containing a third metal.

11. The semiconductor device according to claim 10 , further comprising a second layer interposed between the bonding layer and the first layer and including an alloy of the first metal and the third metal.

12. The semiconductor device according to claim 11 , wherein the bonding layer is thicker than the second layer.

13. The semiconductor device according to claim 7 , wherein the surface layer is thinner than the base material.

14. The semiconductor device according to claim 13 , wherein the surface layer contains Ag.

15. The semiconductor device according to claim 14 , wherein the substrate contains Cu.

16. a conductive member positioned apart from the support member; a wire connected to the semiconductor element and the conductive member, the conductive member has a second surface to which the wire is joined and a plurality of second recesses recessed from the second surface, 16. The semiconductor device according to claim 1, wherein the plurality of second recesses are formed at positions that avoid joints between the wires and the conductive members when viewed along the thickness direction.

17. A semiconductor device as described in Claim 16, wherein the plurality of second recesses are formed in an annular region surrounding the joint when viewed along the thickness direction.

18. 18. The semiconductor device according to claim 16, wherein the second recess is deeper than the first recess.

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