Imaging device

Abstract

To solve the problem that a D range becomes smaller when a pixel size is tried to be reduced, in an image pickup device using an avalanche photodiode.SOLUTION: An imaging apparatus comprises: a photoelectric conversion part; a pulse signal generation part which generates a pulse signal based on a signal from the photoelectric conversion part; a counter circuit which counts the pulse signal generated by the pulse signal generation part; and a time measurement circuit which measures time. The apparatus selectively outputs only one of a count value by the counter circuit and a time measurement value by the time measurement circuit.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to an imaging device. [Background technology]

[0002] Photoelectric conversion devices are known that digitally count the number of photons arriving at an avalanche photodiode and output the counted value as a photoelectrically converted digital signal from the pixel. Digitizing pixel signals offers significant advantages in terms of noise and signal processing, and imaging devices with an array of multiple pixels that output photoelectrically converted digital signals are becoming increasingly popular. Patent Document 1 discloses a method for measuring the time when the number of counted photons reaches a threshold value in a time shorter than one frame in such an imaging device, and calculating the number of photons per frame from the time information and the number of photons. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US09210350 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the configuration of Patent Document 1, a counter for measuring time is connected to each pixel, which causes a problem that the overall circuit size becomes large. [Means for solving the problem]

[0005] The photoelectric conversion device of the present invention comprises a first pixel circuit including a first photoelectric conversion unit, a first generation unit that generates a pulse signal based on a signal from the first photoelectric conversion unit, and a first counter circuit that counts the pulse signal generated by the first generation unit; and a second pixel circuit including a second photoelectric conversion unit, a second generation unit that generates a pulse signal based on a signal from the second photoelectric conversion unit, a second counter circuit that counts the pulse signal generated by the second generation unit, and a time measurement circuit that measures time, wherein the first pixel circuit does not include a time measurement circuit, and the second pixel circuit selectively outputs either the count value counted by the second counter circuit or the time measurement value measured by the time measurement circuit. [Effects of the Invention]

[0006] According to the present invention, it is possible to ensure a sufficient dynamic range while suppressing the circuit scale. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a diagram illustrating an example of the configuration of a photoelectric conversion device according to an embodiment. [Figure 2] 1 is a diagram illustrating an example of the configuration of a sensor chip according to an embodiment; [Figure 3] 1 is a diagram illustrating an example of the configuration of a circuit chip according to an embodiment; [Figure 4] 3A and 3B are an example of an equivalent circuit and a block diagram of a pixel and a signal processing unit according to the embodiment. [Figure 5] 5 is a timing chart for explaining the operation of the APD and the waveform shaping unit according to the embodiment. FIG. [Figure 6] FIG. 10 is a block diagram showing a case where one TDC circuit according to the embodiment is connected to a plurality of pixels. [Figure 7] FIG. 10 is an image diagram of an output result of a pixel according to the embodiment. [Figure 8] 4 is a flowchart of control according to the embodiment. [Figure 9]4 is a flowchart of control according to the embodiment. [Figure 10] 1 is a timing chart according to an embodiment. [Figure 11] FIG. 1 is a block diagram according to an embodiment. [Figure 12] 4 is a flowchart of control according to the embodiment. [Figure 13] 4 is a flowchart of control according to the embodiment. [Figure 14] 4 is a timing chart of control according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Fig. 1 is a diagram showing an example of the configuration of a photoelectric conversion device according to this embodiment. As shown in Fig. 1, the photoelectric conversion device 100 is configured by stacking and electrically connecting two chips: a sensor chip 11 and a circuit chip 21. The sensor chip 11 includes a pixel region 12. The circuit chip 21 also includes a pixel circuit region 22 that processes signals detected in the pixel region 12, and a readout circuit region 23 that reads out signals from the pixel circuit region 22.

[0009] FIG. 2 is a diagram showing an example of the configuration of the sensor chip 11. As shown in FIG. 2, the pixel region 12 of the sensor chip 11 includes a plurality of pixels 101 arranged two-dimensionally in the row and column directions. Each pixel 101 has a photoelectric conversion unit 102 including an avalanche photodiode (hereinafter referred to as APD). FIG. 2 shows 36 pixels 101 arranged in six rows from row 0 to row 5 and six columns from column 0 to column 5, along with reference symbols indicating the row and column numbers. For example, the unit pixel 11 arranged in the first row and fourth column is assigned the reference symbol "P14." The number of rows and columns of the pixels 101 arranged in the pixel region 12 is not particularly limited.

[0010] Here, the pixel 101 outputs a signal for generating an image, but does not necessarily need to generate an image when used for, for example, TOF (Time of Flight). That is, the pixel 101 may be used to measure the time and amount of light that arrives.

[0011] FIG. 3 is a diagram showing an example of the configuration of a circuit chip 21. As shown in FIG. 3, the circuit chip 21 includes a pixel circuit region 22 and a readout circuit region 23. The pixel circuit region 22 includes a plurality of signal processing units 103 arranged two-dimensionally in the row and column directions. FIG. 3 shows 36 signal processing units 103 arranged in six rows (row 0) to row 5 and six columns (column 0) to column 5, along with reference symbols indicating the row and column numbers. For example, the signal processing unit 103 arranged in the first row and fourth column is assigned the reference symbol "S14." Note that the number of rows and columns of signal processing units 103 arranged in the pixel circuit region 22 is not particularly limited.

[0012] The readout circuit area 23 includes a vertical scanning circuit 110 , a horizontal scanning circuit 111 , a column circuit 112 , a control signal output circuit 114 , and a circuit pulse generation unit 115 .

[0013] A control signal line 214 is arranged in each row of the pixel circuit region 22, extending in a first direction (the horizontal direction in FIG. 3). The control signal line 214 is connected to the signal processing unit 103 in each row aligned in the first direction. The first direction in which the control signal line 214 extends may be referred to as the row direction or the horizontal direction.

[0014] The control signal line 214 of each row is connected to the vertical scanning circuit 110. The vertical scanning circuit 110 supplies a control signal VSEL for driving the signal processing unit 103 to the signal processing unit 103 via the control signal line 214. Note that FIG. 3 shows the control signal VSEL supplied to the signal processing unit 103 of each row via the control signal line 214 together with the row number. For example, the control signal line 214 of the first row is labeled "VSEL[1]."

[0015] Column signal lines 113 are arranged in each column of the pixel circuit region 22, extending in a second direction (the vertical direction in FIG. 3) intersecting the first direction. The column signal lines 113 are connected to the signal processing units 103 of each column aligned in the second direction, forming a common signal line. The second direction in which the column signal lines 113 extend may be referred to as the column direction or the vertical direction. Although not shown, n column signal lines 113 are arranged in each column for outputting n-bit digital signals.

[0016] The column signal line 113 of each column is connected to a corresponding column circuit 112. The column circuits 112 are provided corresponding to the respective columns of the pixel circuit region 22. The column circuits 112 have a function of storing pixel signals read out from the signal processing unit 103 via the corresponding column signal line 113.

[0017] The horizontal scanning circuit 111 supplies a control signal HSEL for reading out a signal from the column circuit 112 of each column to the column circuit 112 via a control signal line 117. Upon receiving the control signal HSEL from the horizontal scanning circuit 111, the column circuit 112 of each column outputs the stored pixel signal to the output circuit 114 via a horizontal output line 118.

[0018] 3, the control signal HSEL supplied to the column circuit 112 of each column via the control signal line 117 is shown together with the column number. For example, "HSEL[4]" is attached to the control signal line 117 of the fourth column. Although not shown, n horizontal output lines 118 are provided for outputting n-bit digital signals.

[0019] The output circuit 114 outputs a digital signal corresponding to the pixel signal as an output signal SOUT of the photoelectric conversion device.

[0020] The control pulse generation unit 115 supplies control signals that control the operations and timings of the horizontal scanning circuits 110, 111, and column circuits 112. Note that at least some of the control signals that control the operations and timings of the horizontal scanning circuits 110, 111, and column circuits 112 may be configured to be supplied from outside the photoelectric conversion device.

[0021] 4(a) and 4(b) are examples of an equivalent circuit and a block diagram of the pixel 101 in the sensor chip 11 in FIG. 2 and the signal processing unit 103 in the circuit chip 21 in FIG.

[0022] In FIG. 4(a), the pixel 101 includes an APD 201, which is a photoelectric conversion unit. When light is incident on the APD 201, photoelectric conversion generates charges corresponding to the incident light. A voltage VL (first voltage) is supplied to the anode of the APD 201, and a voltage VH (second voltage) higher than the voltage VL supplied to the anode is supplied to the cathode of the APD 201. In other words, a reverse bias voltage is supplied to the anode and cathode of the APD 201 such that the APD 201 performs avalanche multiplication. By supplying such a voltage, charges generated by the incident light undergo avalanche multiplication, generating an avalanche current.

[0023] When a reverse bias voltage is supplied, there are two modes: Geiger mode, in which the anode and cathode operate at a potential difference greater than the breakdown voltage, and linear mode, in which the anode and cathode operate at a potential difference close to or less than the breakdown voltage. APDs operating in Geiger mode are called SPADs. For example, the voltage VL (first voltage) is -30V, and the voltage VH (second voltage) is 1V.

[0024] The signal processing unit 103 in the sensor chip 21 includes a quench element 202 , a waveform shaping unit 210 , a counter circuit 211 , and a selection circuit 212 .

[0025] The quench element 202 is connected to a power supply that supplies a voltage VH and the APD 201. The quench element 202 has a function of converting a change in avalanche current generated in the APD 201 into a voltage signal. The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, and has the function of suppressing avalanche multiplication by suppressing the voltage supplied to the APD 201 (quench operation).

[0026] The waveform shaping unit 210 generates and outputs a pulse signal by shaping the potential change of the cathode of the APD 201 obtained when a photon is detected. For example, an inverter circuit or a buffer circuit is used as the waveform shaping unit 210 as a pulse signal generating unit.

[0027] The counter circuit 211 counts the pulse signals output from the waveform shaping section 210. Furthermore, the counter circuit 211 resets the count value when a control signal PRES is supplied via a control signal line 213.

[0028] The selection circuit 212 switches between electrical connection and disconnection between the counter circuit 211 and the signal line 113 in response to a control signal VSEL supplied from the vertical scanning circuit 110 in Fig. 3 via a control signal line 214. The selection circuit 212 also includes, for example, a buffer circuit for outputting a signal.

[0029] 4(b), in addition to the configuration shown in FIG. 4(a), a time-to-digital converter (hereinafter referred to as TDC) circuit 215 and a control signal line 216 are further added. The TDC circuit 215, which is a time measurement circuit, operates according to the count result of the counter circuit 211, and measures time using a time measurement clock supplied via a control signal line 216 until a control signal PRES is supplied via a control signal line 213.

[0030] The selection circuit 212 switches between electrical connection and disconnection between the counter circuit 211 or the TDC circuit 215 and the signal line 113 in response to a control signal VSEL supplied from the vertical scanning circuit 110 in FIG.

[0031] Fig. 5 is a timing diagram for explaining the operation of the APD 201 and the waveform shaping unit 210 shown in Fig. 4. Fig. 5(a) shows the voltage change at node A in Fig. 4, and Fig. 5(b) shows the voltage change at node B in Fig. 4.

[0032] Between times t0 and t1, a voltage of VH-VL is applied to the APD 201. At this time, the voltage of node B is at a low level.

[0033] At time t1, when a photon is incident on the APD 201, an avalanche multiplication current flows through the quench element 202, and the voltage at node A drops.

[0034] At time t2, when the voltage at node A falls below a predetermined determination threshold, the function of the waveform shaping section 210 changes the voltage at node B from low level to high level.

[0035] At time t3, the voltage drop increases further, and the voltage applied to the APD 201 decreases, causing the avalanche multiplication of the APD 201 to stop, and the voltage level at node A no longer drops below a certain value. After that, a current flows from voltage VL to node A to compensate for the voltage drop, causing the voltage to rise.

[0036] At time t4, when the voltage at node A exceeds a predetermined determination threshold, the function of the waveform shaping section 210 changes the voltage at node B from a high level to a low level.

[0037] At time t5, nodeA settles to its original potential level.

[0038] FIG. 6 is a block diagram for explaining processing when one pixel among a plurality of pixels is provided with a TDC circuit 215. In FIG.

[0039] Fig. 6 shows pixels P00, P01, P10, and P11 of the pixel chip described in Fig. 2, and signal processing units S00, S01, S10, and S11 of the circuit chip described in Fig. 3. Here, processing will be described for the case where only the signal processing unit S11 connected to pixel P11 of the four pixels is equipped with the TDC circuit 215.

[0040] Pixel P11 is the high-sensitivity pixel with the highest sensitivity among the four pixels. For example, it is assumed that pixels P00, P01, and P10 are equipped with color filters, while high-sensitivity pixel P11 is not equipped with a color filter. Alternatively, it is assumed that the pixel size of high-sensitivity pixel P11 is larger than that of the other pixels. Because high-sensitivity pixel P11 has higher sensitivity than the other pixels, it will reach a full count value first when the same amount of light is incident. Depending on the count result of counter circuit 211, signal processing unit S11 selectively outputs either the count value by counter circuit 211 or the time measurement value by TDC circuit 215.

[0041] 7 is an image diagram of the output data from the signal processing unit S11. Here, the most significant bit of the output data is a decision bit; for example, if the decision bit is 0, the data below that is processed in a subsequent stage as a pixel count value. If the decision bit is 1, it is processed in a subsequent stage as a time measurement value. By providing a decision bit in this way, it is no longer necessary to output the pixel count value and the time measurement value simultaneously, and the amount of output data can be reduced.

[0042] Next, the control of this embodiment will be described with reference to the flowcharts of FIGS.

[0043] FIG. 8 is a flowchart showing a process for outputting data from the signal processing unit S11 equipped with the TDC circuit 215 in the block diagram shown in FIG.

[0044] In S801, the reset of the counter circuit 211 by the control signal PRES is released, and counting of the pulse signal output from the waveform shaping unit 210 is started.

[0045] In S802, it is confirmed whether the counter circuit 211 has reached a full count, and if it has not reached a full count, the process proceeds to S804.

[0046] In S804, it is confirmed whether the accumulation period has ended. The accumulation period here refers to the time from when the reset of the counter circuit 211 by the control signal PRES is released until the control signal VSEL is supplied. If the accumulation period has not ended, the process returns to S802. If the accumulation period has ended, the process proceeds to S806.

[0047] In S806, the count value of the counter circuit 211 at that time is output as the pixel value.

[0048] Also, in S802, if the counter circuit 211 reaches a full count, the process proceeds to S803.

[0049] In S803, the TDC circuit 215 starts measuring time at the same time that the counter circuit 211 reaches a full count.

[0050] In S805, it is confirmed whether the accumulation period has ended, and if the accumulation period has not ended, the TDC circuit 215 continues measuring time until the accumulation period ends.

[0051] If the accumulation period has ended in S805, the process proceeds to S807.

[0052] In S807, the time measurement value by the TDC circuit 215 at the time when the accumulation period ends is output as a pixel value.

[0053] FIG. 9 is a flowchart showing a case where data is output from the signal processing units S00, S01, and S10 that do not include the TDC circuit 215 in the block diagram shown in FIG.

[0054] In S901, the reset of the counter circuit 211 by the control signal PRES is released, and counting of the pulse signal output from the waveform shaping unit 210 is started.

[0055] In S902, it is confirmed whether the counter circuit 211 of the signal processing unit S11, which is connected to the high-sensitivity pixel P11 and includes the TDC circuit 215, has reached a full count, and if it has not reached a full count, the process proceeds to S904.

[0056] In S904, it is confirmed whether the accumulation period has ended. If the accumulation period has ended before the counter circuit 211 of the signal processing unit S11 connected to the high-sensitivity pixel P11 reaches a full count, the process proceeds to S906.

[0057] In S906, the counter values ​​of the counter circuits 211 of the signal processing units S00, S01, and S10 at the time when the accumulation period ends are output as pixel values.

[0058] Furthermore, in S902, if the counter circuit 211 of the signal processing unit S11 connected to the high-sensitivity pixel P11 reaches a full count, the process proceeds to S903.

[0059] In S903, when the counter circuit 211 of the signal processing unit S11 connected to the high-sensitivity pixel P11 reaches a full count, the counter circuits 211 of the signal processing units S00, S01, and S10 are stopped, and the process proceeds to S905.

[0060] In S905, it is checked whether the accumulation period has ended, and if so, the process proceeds to S906.

[0061] In S906, the count values ​​at the time when the counter circuits 211 of the signal processing units S00, S01, and S10 are stopped are output as pixel values.

[0062] Next, a method for restoring the pixel value of each pixel from the time measurement value by the TDC circuit 215 when the counter circuit 211 of the signal processing unit S11 connected to the high-sensitivity pixel P11 reaches a full count will be described.

[0063] Even if the counter circuits 211 of the signal processing units S00, S01, and S10 that are connected to the normal pixels P00, P01, and P10 and that do not have the TDC circuit 215 stop midway, the time measurement value of the signal processing unit S11 that is connected to the high-sensitivity pixel P11 and that has the TDC circuit 215 is used. By doing so, it is possible to estimate and restore the count values ​​by the counter circuits 211 of the signal processing units S00, S01, and S10 that do not have the TDC circuit 215 until the end of the accumulation period.

[0064] FIG. 10 is a timing chart of the control signal PRES, the control signal VSEL, the clock signal CLK for time measurement by the TDC circuit 211, and the time measurement value by the TDC circuit 211 in the configuration of FIG.

[0065] At time t1001, the reset of the counter circuit 211 by the control signal PRES is released. During the accumulation period until the control signal VSEL is supplied at time t1003, the counter circuit 211 of the signal processing circuit S11, which is connected to the high-sensitivity pixel P11 and includes the TDC circuit 215, counts the pulse signal output from the waveform shaping unit 210.

[0066] At time t1002, when the counter circuit 211 reaches a full count, the TDC circuit 215 starts measuring time. The TDC circuit 215 measures the time until the accumulation period ends in synchronization with the clock signal CLK for time measurement.

[0067] In this embodiment, an example has been shown in which the time from when the counter circuit 211 of the signal processing unit S11 connected to the high-sensitivity pixel P11 reaches a full count to when the accumulation period ends is measured by the TDC circuit 215. However, the present invention is not limited to this, and the time from when the accumulation period starts to when the counter circuit 211 reaches a full count may also be measured.

[0068] Next, we will explain how to restore pixel values ​​in the configuration of Fig. 6. The pixel value C_RES of the high-sensitivity pixel P11 can be restored by the following equation. C_RES=C_MAX×TDC_FULL / (TDC_FULL-T_FULL)

[0069] Here, C_MAX is the maximum count value of the counter circuit 211 of the signal processing unit S11 connected to the high-sensitivity pixel P11, TDC_FULL is the maximum count number that the TDC circuit 215 can count during the accumulation period, and T_FULL is the time measurement value from when the counter circuit 211 of the signal processing unit S11 connected to the high-sensitivity pixel P11 reaches a full count to when the accumulation period ends.

[0070] Furthermore, if the clock period of the TDC circuit 215 is T_CNT and the accumulation period is T_ACC, the maximum count number TDC_FULL that the TDC circuit 215 can count is defined by the following equation. TDC_FULL =T_ACC / T_CNT

[0071] In the above equation, the maximum count value C_MAX, the accumulation period T_ACC, and the clock period T_CNT are each uniquely determined, so the maximum count number TDC_FULL is known, and the pixel value can be restored from the time measurement value T_FULL.

[0072] The time it takes for the high-sensitivity pixel P11 to reach a full count can affect the resolution of the restored pixel value. For example, when the accumulation period T_ACC = 16.6 [ms] and the clock period T_CNT = 1.7 [μs], the maximum count number TDC_FULL = 9803. If the maximum count value C_MAX = 256 and the time measurement value T_FULL is 8000 and 8001, the restored pixel values ​​will be 1392 [LSB] and 1391 [LSB], respectively, a difference of 1 [LSB].

[0073] On the other hand, if the time measurement value T_FULL is 9803 and 9802, the pixel restoration values ​​are 2723404 and 1306122, respectively, and although the difference of one count until the full count is reached is the same in both cases, the restored pixel values ​​are significantly different. In other words, the resolution of the pixel restoration value becomes coarser when the time from the start of the accumulation period until the full count is reached is shorter, and there is a concern that the resolution of high-brightness areas near saturated areas in the output image will be poor.

[0074] FIG. 11 is a block diagram showing a configuration in which a saturation counter 1101, a saturation time counter 1102, a memory unit 1103, and a pixel value restoration unit 1104 are further added to the configuration of FIG.

[0075] The saturation count counter 1101 counts the number of times that the counter circuit 211 of the signal processing unit S11 connected to the high-sensitivity pixel P11 reaches a full count during the accumulation period. The saturation time counter 1102 counts the total saturation time of the counter circuit 211 of the signal processing unit S11 connected to the high-sensitivity pixel P11 during the accumulation period based on the time measurement value measured by the TDC circuit 211. The memory unit 1103 stores the count values ​​of the signal processing units S00, S01, S10, and S11, and the output results of the saturation count counter 1101 and the saturation time counter 1102.

[0076] Next, the control in the configuration of FIG. 11 will be described with reference to the flowcharts of FIGS.

[0077] FIG. 12 is a flowchart showing a process for outputting data from the signal processing unit S11 equipped with the TDC circuit 215 in the block diagram shown in FIG.

[0078] In S1201, the reset of the counter circuit 211 by the control signal PRES is released, and counting of the pulse signal output from the waveform shaping unit 210 is started.

[0079] In S1202, the TDC circuit 215 starts measuring time at the same time as in S1201.

[0080] In S1203, it is confirmed whether the counter circuit 211 has reached a full count, and if it has not reached a full count, the process proceeds to S1204.

[0081] In S1204, it is confirmed whether the accumulation period has ended. The accumulation period here refers to the time from when the reset of the counter circuit 211 by the control signal PRES is released until the control signal VSEL is supplied. If the accumulation period has not ended, the process returns to S1203 again.

[0082] In S1203, if the counter circuit 211 reaches a full count, the process proceeds to S1206.

[0083] In S1206, the count values ​​of the counter circuit 211, the saturation number counter 1101, and the saturation time counter 1102 are stored in the memory unit 1103, and the process proceeds to S1207.

[0084] In S1207, the counter values ​​of the counter circuit 211 and the saturation time counter 1102 are reset.

[0085] In S1208, the time measurement value of the TDC circuit 211 is reset, and the process proceeds to S1209.

[0086] In S1209, it is checked whether the accumulation period has ended, and if the accumulation period has not ended, the process returns to S1201. In other words, even if the counter circuit 211 reaches a full count within the accumulation period, it continues counting up again until the accumulation period ends.

[0087] If the accumulation period has ended in S1204 or S1209, the process proceeds to S1210.

[0088] In S1210, it is confirmed whether or not the counter circuit 211 has reached a full count during the accumulation period. If the counter circuit 211 has not reached a full count during the accumulation period (the count value of the saturation counter 1101 is 0), the process proceeds to S1205.

[0089] In S1205, the count value of the counter circuit 211 is output as a pixel value.

[0090] In S1210, if the counter circuit 211 reaches a full count during the accumulation period, the process proceeds to S1211.

[0091] In S1211, pixel values ​​are restored using the values ​​stored in the memory unit 1103 in S1206, and the process proceeds to S1212.

[0092] In S1212, the restored pixel values ​​are output.

[0093] FIG. 13 is a flowchart showing a case where data is output from the signal processing units S00, S01, and S10 that do not include the TDC circuit 215 in the block diagram shown in FIG.

[0094] In S1301, the reset of the counter circuit 211 by the control signal PRES is released, and counting of the pulse signal output from the waveform shaping unit 210 is started.

[0095] In S1302, it is confirmed whether the counter circuit 211 of the signal processing unit S11 equipped with the TDC circuit 215 has reached a full count, and if it has not reached a full count, the process proceeds to S1303.

[0096] In S1303, it is confirmed whether the accumulation period has ended. The accumulation period here refers to the time from when the reset of the counter circuit 211 by the control signal PRES is released until the control signal VSEL is supplied. If the accumulation period has not ended, the process returns to S1302 again.

[0097] In S1302, if the counter circuit 211 of the signal processing unit S11 reaches a full count, the process proceeds to S1304.

[0098] In S1304, the counter circuit 211 of the signal processing unit S11 reaches a full count, and at the same time, the counter circuits 211 of the signal processing units S00, S01, and S10 are stopped, and the process proceeds to S1305.

[0099] In S1305, the counter values ​​of the counter circuits 211 of the signal processing units S00, S01, and S10 at that time are stored in the memory unit 1103, and the process proceeds to S1306.

[0100] In S1306, the counter values ​​of the counter circuits 211 of the signal processing units S00, S01, and S10 are reset, and the process proceeds to S1307.

[0101] In S1307, it is checked whether the accumulation period has ended, and if the accumulation period has not ended, the process returns to S1301 again.

[0102] If the accumulation period has ended in S1303 or S1307, the process proceeds to S1308.

[0103] In S1308, it is confirmed whether the counter circuit 211 of the signal processing unit S11 has reached a full count during the accumulation period. If the counter 211 of the signal processing unit S11 has not reached a full count during the accumulation period (the count value of the saturation counter 1101 is 0), the process proceeds to S1309.

[0104] In S1309, the count values ​​of the counter circuits 211 of the signal processing units S00, S01, and S10 stored in the memory unit 1103 are output as pixel values.

[0105] In S1308, if the counter 211 of the signal processing unit S11 reaches a full count during the accumulation period, the process proceeds to S1310.

[0106] In S1310, pixel values ​​are restored using the values ​​stored in the memory unit 1103, and the process proceeds to S1311.

[0107] In S1311, the restored pixel value is output.

[0108] Since the counter circuit 211 is reset at the start or end of the accumulation period, it starts measuring from the reset state in the next accumulation period.

[0109] 14 is a timing chart of the control signal PRES, the control signal VSEL, the clock signal CLK for time measurement by the TDC circuit 211, the time measurement value by the TDC circuit 211, the number of saturations stored in the memory unit 1103, and the total saturation time in the configuration of FIG.

[0110] At time t1401, the reset of the counter circuit 211 by the control signal PRES is released. During the accumulation period until the control signal VSEL is supplied at time t1405, the counter circuit 211 of the signal processing unit S11, which is connected to the high-sensitivity pixel P11 and includes a TDC circuit 215, counts the pulse signals output from the waveform shaping unit 210. At the same time, the TDC circuit 215 measures the time until the counter circuit 211 of the signal processing unit S11 reaches full count and becomes saturated.

[0111] At time t1402, when the counter circuit 211 of the signal processing unit S11 reaches a full count and becomes saturated, the saturation time counter 1102 counts the time counted by the TDC circuit 215 as the total saturation time and stores it in the memory unit 1103. At this time, the time measurement value of the TDC circuit 115 is 3, so the total saturation time is 3.

[0112] Furthermore, the saturation count counter 1101 counts the number of times the counter circuit 211 has saturated during the accumulation period and stores the count in the memory unit 1103. At this point, the number of saturations is 1. After each value is stored in the memory unit 1103, the counter circuit 211 and the TDC circuit 215 are reset and the counting is restarted.

[0113] At time t1403, when the counter circuit 211 of the signal processing unit S11 reaches a full count and saturates again, the number of saturations and the total saturation time at that time are stored in the memory unit 1103. The number of saturations at time t1403 is 2.

[0114] Also, assume that the number of counts until the counter circuit 211 of the signal processing unit S11 reaches full count between time t1402 and time t1403 is 4. In this case, the total saturation time at time t1403 is added to the saturation time from time t1401 to time t1402, resulting in 7. As before, the counter circuit 211 and the TDC circuit 215 are reset and then counting is restarted.

[0115] At time t1404, when the counter circuit 211 of the signal processing unit S11 reaches a full count and saturates again, the number of saturations and the total saturation time at that time are stored in the memory unit 1103. The number of saturations at time t1404 is three.

[0116] Furthermore, when the counter circuit 211 of the signal processing unit S11 counts 3 until it reaches full count between time t1403 and time t1404, the total saturation time at time t1404 is added to the saturation time stored in the memory unit 1103 to become 10.

[0117] The above process is repeated until the accumulation period ends at time t1405. When the accumulation period ends at time t1405 and the counter circuit 211 of the signal processing unit S11 has reached a full count during the accumulation period, pixel values ​​are restored from the information stored in the memory unit 1103.

[0118] Next, a method for restoring pixel values ​​in the configuration of FIG. 11 will be described.

[0119] First, the pixel value restoration of the high-sensitivity pixel P11 will be described. The pixel value C_RES of the high-sensitivity pixel P11 can be restored by the following equation. C_RES=C_MAX×TDC_FULL / (T_SAT / NUM_SAT)

[0120] Here, C_RES is the pixel value of the high-sensitivity pixel P11 to be restored, C_MAX is the maximum count value of the counter circuit 211 of the signal processing unit S11 connected to the high-sensitivity pixel P11, TDC_FULL is the maximum count number that the TDC circuit 215 can count during the accumulation period, NUM_SAT is the number of saturations stored in the memory unit 1103, and T_SAT is the total saturation time.

[0121] In the above equation, T_SAT / NUM_SAT represents the average time it takes for the counter circuit 211 of the signal processing unit S11 connected to the high-sensitivity pixel P11 to reach a full count during the accumulation period.

[0122] Furthermore, if the clock period of the TDC circuit 215 is T_CNT and the accumulation period is T_ACC, the maximum count number TDC_FULL that the TDC circuit 215 can count is defined by the following equation. TDC_FULL =T_ACC / T_CNT

[0123] The maximum count value C_MAX, accumulation period T_ACC, and clock cycle T_CNT are each uniquely determined. Therefore, the maximum count number TDC_FULL is known, and the pixel value can be restored from the number of saturation events NUM_SAT and total saturation time T_SAT stored in the memory unit 1103.

[0124] At the end of the accumulation period, two pieces of information are stored in the memory unit 1103: the number of saturation events NUM_SAT is 3, and the total saturation time T_SAT is 10. As a result, the average time until the counter circuit 211 of the signal processing unit S11 connected to the high-sensitivity pixel P11 reaches a full count during the accumulation period is T_SAT / NUM_SAT=3.3.

[0125] When the accumulation period T_ACC is 16.6 ms and the clock period T_CNT is 1.7 μs, the maximum count number that the TDC circuit 215 can count is TDC_FULL=9765. When the maximum count value C_MAX of the counter circuit 211 of the signal processing unit S11 connected to the high-sensitivity pixel P11 is 256, the restored pixel value is C_RES=752941 LSB.

[0126] In the configuration of Figure 6, the time measurement value T_FULL from when the counter circuit 211 of the signal processing unit S11 connected to the high-sensitivity pixel P11 reaches a full count to when the accumulation period ends is assumed to be 9801 and 9800. That is, if the time from the start of accumulation to when the full count is reached is 3 and 4 counts, the restored pixel values ​​are 640000 [LSB] and 859060 [LSB], respectively. In contrast, in the configuration of Figure 11, numbers between these values ​​can be restored as output pixel values. In other words, it is possible to increase the resolution of high-brightness areas.

[0127] Next, a method for restoring the pixel values ​​of the pixels P00, P01, and P10 other than the high-sensitivity pixel P11 will be described.

[0128] Each time the counter circuit 211 of the signal processing unit S11 connected to the high-sensitivity pixel P11 becomes saturated during the accumulation period, the count values ​​of the signal processing units S00, S01, S10, and S11 are stored in the memory unit 1103. The sums of the count values ​​of the signal processing units S00, S01, S10, and S11 during the accumulation period are denoted as SUM_S00, SUM_S01, SUM_S10, and SUM_S11, respectively.

[0129] If the ratios of the count values ​​for the high sensitivity pixel P11 are RAT_S00, RAT_S01, and RAT_S10, then RAT_S00=SUM_S00 / SUM_S11 RAT_S01=SUM_S01 / SUM_S11 RAT_S10=SUM_S10 / SUM_S11 The ratio of each count value can be obtained as:

[0130] If the pixel restoration value of the high sensitivity pixel is C_RES, the pixel restoration values ​​C_RES_S00, C_RES_S01, and C_RES_S10 connected to the signal processing units S00, S01, and S10 are respectively given by C_RES_S00=C_RES×RAT_S00 C_RES_S01=C_RES×RAT_S01 C_RES_S10=C_RES×RAT_S10 can be restored as

[0131] In the above example, each time the counter circuit 211 of the signal processing unit S11 connected to the high-sensitivity pixel P11 becomes saturated during the accumulation period, the count values ​​of the signal processing units S00, S01, S10, and S11 are stored in the memory unit 1103. Then, after the accumulation period ends, the pixel value is restored from the ratio of the count values ​​of the high-sensitivity pixel P11 and the other pixels.

[0132] There is a concern that the greater the number of pixels, the greater the amount of memory used. Therefore, when the high-sensitivity pixel P11 reaches its full count for the first time, a ratio may be calculated from the count values ​​of the high-sensitivity pixel P11 and the other pixels, stored in the memory unit 1103, and the pixel restoration value of the high-sensitivity pixel P11 may be multiplied by this ratio to restore the values ​​of the other pixels.

[0133] Furthermore, when the counter circuit 211 of the signal processing unit S11 connected to the high-sensitivity pixel P11 reaches a full count, the ratio between the high-sensitivity pixel P11 and the other pixels may be calculated from the count values ​​of the high-sensitivity pixel P11 and the other pixels, and the ratio may be stored in the memory unit 1103. Then, the next time the counter circuit of the signal processing unit S11 connected to the high-sensitivity pixel P11 reaches a full count, the ratio may be calculated again, and the ratio may be updated by, for example, averaging the ratio with the ratio stored in the memory unit 1103.

[0134] Although the present invention has been described in detail above based on preferred embodiments thereof, the present invention is not limited to these specific embodiments, and various forms within the scope of the gist of the present invention are also included in the present invention. Parts of the above-described embodiments may be combined as appropriate.

[0135] For example, while Figure 1 shows a structure in which two semiconductor chips, a sensor chip and a circuit chip, are stacked, the pixel circuit region may be incorporated within the sensor chip. In other words, a stacked structure is not necessary.

[0136] (Other embodiments) The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program.The present invention can also be realized by a circuit (e.g., ASIC) that realizes one or more functions. [Explanation of symbols]

[0137] 201 APD 210 Waveform shaping section 211 Counter Circuit 215 TDC circuit

Claims

1. a first pixel circuit including a first photoelectric conversion unit, a first generation unit that generates a pulse signal based on a signal from the first photoelectric conversion unit, and a first counter circuit that counts the pulse signal generated by the first generation unit; a second pixel circuit including a second photoelectric conversion unit, a second generation unit that generates a pulse signal based on a signal from the second photoelectric conversion unit, a second counter circuit that counts the pulse signal generated by the second generation unit, and a time measurement circuit that measures time; the first pixel circuit does not include a time measurement circuit; The photoelectric conversion device, characterized in that the second pixel circuit selectively outputs either the count value counted by the second counter circuit or the time measurement value measured by the time measurement circuit.

2. 2. The photoelectric conversion device according to claim 1, wherein the sensitivity of the second pixel circuit is higher than the sensitivity of the first pixel circuit.

3. 2. The photoelectric conversion device according to claim 1, wherein when the count value of the second counter circuit of the second pixel circuit is saturated, the first counter circuit of the first pixel circuit is stopped.

4. 4. The photoelectric conversion device according to claim 1, wherein the second pixel circuit further comprises a saturation count counter that counts the number of saturations of the second counter circuit, a saturation time counter that counts the total saturation time of the second counter circuit, and a memory unit that stores the number of saturations and the total saturation time.

5. 5. The photoelectric conversion device according to claim 4, wherein the pixel value of the first pixel circuit is restored from the number of saturation times and the total saturation time stored in the memory unit.

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