solid-state imaging device

Abstract

A solid-state image capturing device according to an embodiment of the present invention is provided with a first semiconductor layer and a second semiconductor layer stacked on each other. The first semiconductor layer includes, for each pixel, a photoelectric conversion part and a charge accumulation part in which a signal charge generated by the photoelectric conversion part is accumulated. The second semiconductor layer includes pixel transistors that read out the signal charges in the charge accumulation parts. The solid-state image capturing device is provided with a pixel separation section and a shared connection section. The pixel separation section is provided in the first semiconductor layer and partitions a plurality of pixels from each other. The shared connection section is provided between the second semiconductor layer and the first semiconductor layer. The shared connection section is provided across the pixel separation section and adjoins the plurality of charge accumulation parts. The individual charge accumulation parts and the shared connection section are connected to each other three-dimensionally.

Description

[Technical Field]

[0001] The present disclosure relates to a solid-state imaging device having a plurality of semiconductor layers stacked on top of each other. [Background technology]

[0002] In recent years, development of MOS type image sensors such as CMOS (Complementary Metal Oxide Semiconductor) has been progressing in the field of solid-state imaging devices. For example, Patent Document 1 proposes a solid-state imaging device in which a semiconductor wafer having a pixel array section and a semiconductor wafer having a logic circuit are stacked. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-245506 Summary of the Invention

[0004] In such a solid-state imaging device, it is desirable to increase the degree of freedom in design.

[0005] Therefore, it is desirable to provide a solid-state imaging device that allows for greater freedom in design.

[0006] A solid-state imaging device according to an embodiment of the present disclosure includes a first semiconductor layer and a second semiconductor layer stacked on top of each other. The first semiconductor layer includes, for each pixel, a photoelectric conversion unit and a charge accumulation unit in which signal charges generated in the photoelectric conversion unit are accumulated. The second semiconductor layer includes a pixel transistor that reads out signal charges from the charge accumulation unit. The solid-state imaging device includes a pixel separation unit and a shared connection unit. The pixel separation unit is provided in the first semiconductor layer and separates the plurality of pixels from each other. The shared connection unit is provided between the second semiconductor layer and the first semiconductor layer. The shared connection unit is provided across the pixel separation unit and is in contact with the plurality of charge accumulation units. The connection between each charge accumulation unit and the shared connection unit is three-dimensional.

[0007] In a solid-state imaging device according to an embodiment of the present disclosure, a shared connection section is provided across a pixel separation section and is in contact with a plurality of charge accumulation sections. The connection between each charge accumulation section and the shared connection section is three-dimensional. This allows for a larger contact area between each charge accumulation section and the shared connection section compared to when each charge accumulation section and the shared connection section are connected in a plane. Furthermore, even when pixels are miniaturized, a reduction in the connection area between the shared connection section and the charge accumulation section can be suppressed. As a result, it is possible to suppress an increase in the resistance component of the signal charge transfer path. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram illustrating an example of a functional configuration of an imaging device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view showing a schematic configuration of the imaging device shown in FIG. [Figure 3] FIG. 3 is a schematic diagram illustrating a cross-sectional configuration taken along line III-III′ shown in FIG. 2. [Figure 4] 2 is an equivalent circuit diagram of the pixel sharing unit shown in FIG. 1. [Figure 5] 10 is a diagram illustrating an example of a connection mode between a plurality of pixel sharing units and a plurality of vertical signal lines. FIG. [Figure 6]4 is a cross-sectional view schematically illustrating an example of a specific configuration of the imaging device shown in FIG. 3. FIG. [Figure 7A] 7 is a schematic diagram illustrating an example of a planar configuration of a main part of a first substrate illustrated in FIG. 6. [Figure 7B] 7B is a schematic diagram showing the planar configuration of the pad section together with the main part of the first substrate shown in FIG. 7A. [Figure 8A] 7 is an enlarged schematic cross-sectional view showing the main parts of the first substrate and the second substrate shown in FIG. 6. FIG. [Figure 8B] 8B is a schematic diagram illustrating a planar configuration of a main part of the first substrate and the second substrate shown in FIG. 8A. FIG. [Figure 9] 7 is a schematic diagram illustrating an example of a planar configuration in a horizontal direction relative to the main surface of the second substrate (semiconductor layer) illustrated in FIG. 6. FIG. [Figure 10] 7 is a schematic diagram showing an example of a planar configuration of the pixel circuit and the main part of the first substrate together with the first wiring layer shown in FIG. 6. FIG. [Figure 11] 7 is a schematic diagram illustrating an example of a planar configuration of the first wiring layer and the second wiring layer illustrated in FIG. 6. FIG. [Figure 12] 7 is a schematic diagram illustrating an example of a planar configuration of the second wiring layer and the third wiring layer illustrated in FIG. 6. FIG. [Figure 13] 7 is a schematic diagram illustrating an example of a planar configuration of a third wiring layer and a fourth wiring layer illustrated in FIG. 6. FIG. [Figure 14] 4 is a schematic diagram for explaining paths of input signals and the like to the imaging device shown in FIG. 3. FIG. [Figure 15] 4 is a schematic diagram for explaining a signal path of a pixel signal in the imaging device shown in FIG. 3. FIG. [Figure 16] 7 is a schematic diagram illustrating a modified example of the planar configuration of the main part of the first substrate shown in FIG. 6. FIG. [Figure 17] 17 is a schematic cross-sectional view showing, in enlarged form, the main parts of the first substrate and the second substrate in the imaging device including the first substrate shown in FIG. 16. FIG. [Figure 18] FIG. 18 is a cross-sectional view showing a modified example of the configuration shown in FIG. [Figure 19] FIG. 18 is a cross-sectional view showing a modified example of the configuration shown in FIG. [Figure 20] FIG. 18 is a cross-sectional view showing a modified example of the configuration shown in FIG. [Figure 21] FIG. 18 is a cross-sectional view showing a modified example of the configuration shown in FIG. [Figure 22] FIG. 18 is a cross-sectional view showing a modified example of the configuration shown in FIG. [Figure 23] FIG. 18 is a cross-sectional view showing a modified example of the configuration shown in FIG. [Figure 24] FIG. 18 is a cross-sectional view showing a modified example of the configuration shown in FIG. [Figure 25] FIG. 18 is a cross-sectional view showing a modified example of the configuration shown in FIG. [Figure 26] FIG. 18 is a cross-sectional view showing a modified example of the configuration shown in FIG. [Figure 27] FIG. 8C is a schematic diagram showing a modified example of the planar configuration of FIG. 8B. [Figure 28] FIG. 8C is a schematic diagram showing a modified example of the planar configuration of FIG. 8B. [Figure 29] FIG. 8C is a schematic diagram showing a modified example of the planar configuration of FIG. 8B. [Figure 30] FIG. 18 is a cross-sectional view showing a modified example of the configuration shown in FIG. [Figure 31] FIG. 1 is a diagram illustrating an example of a schematic configuration of an imaging system including an imaging device according to the above embodiment and its modified example. [Figure 32] 32 is a diagram illustrating an example of an imaging procedure of the imaging system shown in FIG. 31. [Figure 33] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 34] FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. [Figure 35] FIG. 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 36] FIG. 2 is a block diagram showing an example of the functional configuration of a camera head and a CCU. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. Embodiment (Image capture device having a stacked structure of three substrates) 2. Variations Modification A (Example where the pad area is larger than the floating diffusion) Variation B (Tapered floating diffusion) Variation C (Example of a floating diffusion with a recess) Modification D (Example of floating diffusion with protrusions) Modification E (Example in which the bottom end of the through electrode is embedded in the pad) Variation F (Pad part is in contact with the sidewall) Modification G (Modification of pixel separator) Modification H (modification of planar layout of pixel sharing unit) Modification I (modification of the contact form between the pad portion and the floating diffusion) 3. Application example (imaging system) 4. Application Examples

[0010] <1. Embodiment> [Functional configuration of imaging device 1] FIG. 1 is a block diagram showing an example of a functional configuration of a solid-state imaging device (imaging device 1) according to an embodiment of the present disclosure.

[0011] The imaging device 1 in FIG. 1 includes, for example, an input section 510A, a row driver section 520, a timing control section 530, a pixel array section 540, a column signal processing section 550, an image signal processing section 560, and an output section 510B.

[0012] In the pixel array section 540, pixels 541 are repeatedly arranged in an array. More specifically, a pixel-sharing unit 539 including a plurality of pixels 541 serves as a repeating unit. The plurality of pixel-sharing units 539 are arranged in an array having a row direction and a column direction. For convenience, the row direction may be referred to as the H direction, and the column direction perpendicular to the row direction may be referred to as the V direction in this specification. In the example of FIG. 1, one pixel-sharing unit 539 includes four pixels 541 (pixels 541A, 541B, 541C, and 541D). Each of the pixels 541A, 541B, 541C, and 541D has a photodiode PD (shown in FIG. 6, etc., described later). The pixel-sharing unit 539 is a unit that shares one pixel circuit (pixel circuit 210 in FIG. 3, described later). In other words, one pixel circuit (a pixel circuit 210, which will be described later) is provided for each of the four pixels 541 (pixels 541A, 541B, 541C, and 541D). By operating these pixel circuits in a time-division manner, the pixel signals of the pixels 541A, 541B, 541C, and 541D are read out sequentially.

[0013] The pixels 541A, 541B, 541C, and 541D are arranged in, for example, two rows and two columns. The pixel array section 540 is provided with a plurality of row drive signal lines 542 and a plurality of vertical signal lines (column readout lines) 543 in addition to the pixels 541A, 541B, 541C, and 541D. The row drive signal lines 542 drive a plurality of pixels 541 arranged in a row direction in the pixel array section 540. The row drive signal lines 542 drive each of the pixels 541 arranged in a row direction in the pixel sharing units 539. As will be described in detail later with reference to FIG. 4 , the pixel sharing units 539 are provided with a plurality of transistors. To drive each of these plurality of transistors, a plurality of row drive signal lines 542 are connected to one pixel sharing unit 539. The pixel sharing units 539 are connected to the vertical signal lines (column readout lines) 543. Pixel signals are read out from each of the pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539 via vertical signal lines (column readout lines) 543.

[0014] The row driving unit 520 includes, for example, a row address control unit that determines the position of the row for pixel driving, in other words, a row decoder unit, and a row driving circuit unit that generates signals for driving the pixels 541A, 541B, 541C, and 541D.

[0015] The column signal processing unit 550 includes, for example, a load circuit unit that is connected to the vertical signal line 543 and forms a source follower circuit together with the pixels 541A, 541B, 541C, and 541D (pixel sharing units 539). The column signal processing unit 550 may include an amplifier circuit unit that amplifies the signal read out from the pixel sharing unit 539 via the vertical signal line 543. The column signal processing unit 550 may include a noise processing unit. The noise processing unit removes the system noise level from the signal read out from the pixel sharing unit 539 as a result of photoelectric conversion, for example.

[0016] The column signal processing unit 550 includes, for example, an analog-to-digital converter (ADC). The analog-to-digital converter converts the signal read from the pixel shared unit 539 or the analog signal that has undergone the noise processing into a digital signal. The ADC includes, for example, a comparator unit and a counter unit. The comparator unit compares the analog signal to be converted with a reference signal to be compared with the analog signal. The counter unit measures the time until the comparison result in the comparator unit is inverted. The column signal processing unit 550 may also include a horizontal scanning circuit unit that controls scanning of the readout columns.

[0017] The timing control section 530 supplies signals for controlling timing to the row driving section 520 and the column signal processing section 550 based on the reference clock signal and timing control signal input to the device.

[0018] The image signal processing unit 560 is a circuit that performs various signal processing operations on data obtained as a result of photoelectric conversion, in other words, data obtained as a result of the imaging operation in the imaging device 1. The image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may also include a processor unit.

[0019] One example of signal processing executed by the image signal processing unit 560 is tone curve correction processing, which increases the gradation of AD converted imaging data when the data is of a dark subject, and decreases the gradation when the data is of a bright subject. In this case, it is desirable to store in advance in the data storage unit of the image signal processing unit 560 characteristic data of the tone curve based on which the gradation of the imaging data is to be corrected.

[0020] The input unit 510A is for inputting, for example, the reference clock signal, timing control signal, and characteristic data from outside the device to the imaging device 1. The timing control signal is, for example, a vertical synchronization signal and a horizontal synchronization signal. The characteristic data is, for example, for storage in a data holding unit of the image signal processing unit 560. The input unit 510A includes, for example, an input terminal 511, an input circuit unit 512, an input amplitude changing unit 513, an input data conversion circuit unit 514, and a power supply unit.

[0021] The input terminal 511 is an external terminal for inputting data. The input circuit unit 512 is for inputting a signal input to the input terminal 511 into the imaging device 1. The input amplitude change unit 513 changes the amplitude of the signal input by the input circuit unit 512 to an amplitude that is easily usable inside the imaging device 1. The input data conversion circuit unit 514 changes the arrangement of the data string of the input data. The input data conversion circuit unit 514 is configured, for example, by a serial-parallel conversion circuit. This serial-parallel conversion circuit converts a serial signal received as input data into a parallel signal. Note that the input amplitude change unit 513 and the input data conversion circuit unit 514 may be omitted from the input unit 510A. The power supply unit supplies power set to various voltages required inside the imaging device 1 based on power supplied from an external source to the imaging device 1.

[0022] When the imaging device 1 is connected to an external memory device, the input unit 510A may be provided with a memory interface circuit that receives data from the external memory device, such as a flash memory, an SRAM, or a DRAM.

[0023] Output unit 510B outputs image data to the outside of the device. This image data is, for example, image data captured by imaging device 1 and image data that has been signal-processed by image signal processing unit 560. Output unit 510B includes, for example, output data conversion circuit unit 515, output amplitude change unit 516, output circuit unit 517, and output terminal 518.

[0024] The output data conversion circuit unit 515 is configured by, for example, a parallel-serial conversion circuit. The output data conversion circuit unit 515 converts the parallel signals used inside the imaging device 1 into serial signals. The output amplitude change unit 516 changes the amplitude of the signals used inside the imaging device 1. The signals with the changed amplitude are easier to use in external devices connected to the outside of the imaging device 1. The output circuit unit 517 is a circuit that outputs data from inside the imaging device 1 to outside the device. The output circuit unit 517 drives wiring outside the imaging device 1 connected to an output terminal 518. The output terminal 518 outputs data from the imaging device 1 to outside the device. The output data conversion circuit unit 515 and the output amplitude change unit 516 may be omitted from the output unit 510B.

[0025] When the imaging device 1 is connected to an external memory device, the output unit 510B may be provided with a memory interface circuit that outputs data to the external memory device, such as a flash memory, an SRAM, or a DRAM.

[0026] [Schematic configuration of imaging device 1] 2 and 3 show an example of a schematic configuration of the imaging device 1. The imaging device 1 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). FIG. 2 shows a schematic planar configuration of each of the first substrate 100, the second substrate 200, and the third substrate 300. FIG. 3 shows a schematic cross-sectional configuration of the first substrate 100, the second substrate 200, and the third substrate 300 stacked on top of each other. FIG. 3 corresponds to the cross-sectional configuration taken along line III-III' shown in FIG. 2.

[0027] The imaging device 1 is a three-dimensional imaging device formed by bonding together three substrates (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. The semiconductor layer 100S corresponds to a specific example of a "first semiconductor layer" in the present disclosure. The wiring layer 100T corresponds to a specific example of a "first wiring layer" in the present disclosure. The first substrate 100 corresponds to a specific example of a "first substrate" in the present disclosure. The semiconductor layer 200S corresponds to a specific example of a "second semiconductor layer" in the present disclosure. The wiring layer 200T corresponds to a specific example of a "second wiring layer" in the present disclosure. The second substrate 200 corresponds to a specific example of a "second substrate" in the present disclosure. The third substrate 300 corresponds to a specific but not limitative example of a "third substrate" in the present disclosure.

[0028] Here, for convenience, the combination of the wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and the surrounding interlayer insulating film is referred to as the wiring layer (100T, 200T, 300T) provided on each substrate (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order, with the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T, and the semiconductor layer 300S arranged in this order along the stacking direction. The specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. The arrows in FIG. 3 indicate the direction of incidence of light L into the imaging device 1. For convenience, in the following cross-sectional views, the light incident side of the imaging device 1 may be referred to as "bottom," "lower side," or "bottom," and the side opposite the light incident side may be referred to as "top," "upper side," or "upper." Furthermore, for convenience, in the present specification, with respect to a substrate having a semiconductor layer and a wiring layer, the wiring layer side may be referred to as the front surface, and the semiconductor layer side may be referred to as the back surface. The description in the specification is not limited to the above terms. The imaging device 1 is, for example, a back-illuminated imaging device in which light is incident from the back surface (light incident surface) of the first substrate 100 having a photodiode.

[0029] The pixel array section 540 and the pixel-shared unit 539 included in the pixel array section 540 are both configured using both the first substrate 100 and the second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C, and 541D included in the pixel-shared unit 539. Each of these pixels 541 has a photodiode (a photodiode PD described below) and a transfer transistor (a transfer transistor TR described below). The second substrate 200 is provided with a pixel circuit (a pixel circuit 210 described below) included in the pixel-shared unit 539. The pixel circuit 210 reads out pixel signals transferred from the photodiodes of the pixels 541A, 541B, 541C, and 541D via the transfer transistor TR, or resets the photodiodes. In addition to the pixel circuits 210, the second substrate 200 also has a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 further has power supply lines 544 (such as power supply lines VDD, which will be described later) that extend in the row direction.

[0030] The third substrate 300 includes, for example, an input section 510A, a row driver 520, a timing control section 530, a column signal processing section 550, an image signal processing section 560, and an output section 510B. The row driver 520 is provided, for example, in a region that partially overlaps with the pixel array section 540 in the stacking direction (hereinafter simply referred to as the stacking direction) of the first substrate 100, the second substrate 200, and the third substrate 300. More specifically, the row driver 520 is provided in a region that overlaps with the vicinity of an end of the pixel array section 540 in the H direction in the stacking direction ( FIG. 2 ). The column signal processing section 550 is provided, for example, in a region that partially overlaps with the pixel array section 540 in the stacking direction. More specifically, the column signal processing section 550 is provided in a region that overlaps with the vicinity of an end of the pixel array section 540 in the V direction in the stacking direction ( FIG. 2 ). Although not shown, the input section 510A and the output section 510B may be arranged in a portion other than the third substrate 300, for example, on the second substrate 200. Alternatively, the input section 510A and the output section 510B may be provided on the rear surface (light incident surface) of the first substrate 100. The pixel circuits provided on the second substrate 200 may also be called pixel transistor circuits, pixel transistor groups, pixel transistors, pixel readout circuits, or readout circuits. In this specification, the term pixel circuits is used.

[0031] The first substrate 100 and the second substrate 200 are electrically connected by, for example, through electrodes (through electrodes 120E and 121E in FIG. 6 described below). The second substrate 200 and the third substrate 300 are electrically connected by, for example, contact portions 201, 202, 301, and 302. The second substrate 200 is provided with contact portions 201 and 202, and the third substrate 300 is provided with contact portions 301 and 302. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 has a contact region 201R in which a plurality of contact portions 201 are provided, and a contact region 202R in which a plurality of contact portions 202 are provided. The third substrate 300 has a contact region 301R in which a plurality of contact portions 301 are provided, and a contact region 302R in which a plurality of contact portions 302 are provided.

[0032] The contact regions 201R and 301R are provided between the pixel array section 540 and the row driver section 520 in the stacking direction (FIG. 3). In other words, the contact regions 201R and 301R are provided, for example, in a region where the row driver section 520 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap in the stacking direction, or in a region nearby this. The contact regions 201R and 301R are arranged, for example, at the end of such a region in the H direction (FIG. 2). On the third substrate 300, for example, the contact region 301R is provided in a position overlapping with a part of the row driver section 520, specifically, the end of the row driver section 520 in the H direction (FIGS. 2 and 3). The contact regions 201R and 301R connect, for example, the row driver section 520 provided on the third substrate 300 to a row drive signal line 542 provided on the second substrate 200. The contact sections 201 and 301 may connect, for example, the input section 510A provided on the third substrate 300 to a power supply line 544 and a reference potential line (a reference potential line VSS described later). The contact regions 202R and 302R are provided between the pixel array section 540 and the column signal processing section 550 in the stacking direction (FIG. 3). In other words, the contact regions 202R and 302R are provided, for example, in a region where the column signal processing section 550 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap in the stacking direction, or in a region nearby this. The contact regions 202R and 302R are disposed, for example, at the end of such a region in the V direction (FIG. 2). On the third substrate 300, for example, the contact region 301R is provided in a position overlapping with a part of the column signal processing section 550, specifically, the end of the column signal processing section 550 in the V direction (FIGS. 2 and 3). The contact sections 202 and 302 are for connecting, for example, pixel signals (signals corresponding to the amount of charge generated as a result of photoelectric conversion in the photodiodes) output from each of the multiple pixel sharing units 539 included in the pixel array section 540 to a column signal processing section 550 provided on the third substrate 300. The pixel signals are sent from the second substrate 200 to the third substrate 300.

[0033] As described above, FIG. 3 is an example cross-sectional view of the imaging device 1. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected via wiring layers 100T, 200T, and 300T. For example, the imaging device 1 has an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300. Specifically, the contact portions 201, 202, 301, and 302 are formed by electrodes made of a conductive material. The conductive material is made of a metal material such as copper (Cu), aluminum (Al), or gold (Au). The contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate and the third substrate by directly bonding wiring formed as electrodes, for example, thereby enabling input and / or output of signals between the second substrate 200 and the third substrate 300.

[0034] The electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 can be provided in a desired location. For example, as described as contact regions 201R, 202R, 301R, and 302R in FIG. 3, the electrical connection portion may be provided in a region that overlaps with the pixel array section 540 in the stacking direction. Alternatively, the electrical connection portion may be provided in a region that does not overlap with the pixel array section 540 in the stacking direction. Specifically, the electrical connection portion may be provided in a region that overlaps with a peripheral portion disposed outside the pixel array section 540 in the stacking direction.

[0035] The first substrate 100 and the second substrate 200 are provided with, for example, connection holes H1 and H2. The connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200 (FIG. 3). The connection holes H1 and H2 are provided outside the pixel array section 540 (or a portion overlapping the pixel array section 540) (FIG. 2). For example, the connection hole H1 is disposed outside the pixel array section 540 in the H direction, and the connection hole H2 is disposed outside the pixel array section 540 in the V direction. For example, the connection hole H1 reaches the input section 510A provided on the third substrate 300, and the connection hole H2 reaches the output section 510B provided on the third substrate 300. The connection holes H1 and H2 may be hollow or may contain a conductive material at least in part. For example, there is a configuration in which a bonding wire is connected to an electrode formed as the input portion 510A and / or the output portion 510B. Alternatively, there is a configuration in which an electrode formed as the input portion 510A and / or the output portion 510B is connected to a conductive material provided in the connection holes H1, H2. The conductive material provided in the connection holes H1, H2 may be embedded in part or all of the connection holes H1, H2, or the conductive material may be formed on the side walls of the connection holes H1, H2.

[0036] 3 shows a structure in which the input unit 510A and the output unit 510B are provided on the third substrate 300, but the present invention is not limited to this. For example, the input unit 510A and / or the output unit 510B can be provided on the second substrate 200 by sending signals from the third substrate 300 to the second substrate 200 via the wiring layers 200T and 300T. Similarly, the input unit 510A and / or the output unit 510B can be provided on the first substrate 100 by sending signals from the second substrate 200 to the first substrate 100 via the wiring layers 100T and 200T.

[0037] FIG. 4 is an equivalent circuit diagram illustrating an example of the configuration of a pixel-shared unit 539. The pixel-shared unit 539 includes a plurality of pixels 541 (four pixels 541A, 541B, 541C, and 541D are illustrated in FIG. 4), one pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210. The pixel circuit 210 includes, for example, four transistors, specifically, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. As described above, the pixel-shared unit 539 operates one pixel circuit 210 in a time-division manner to sequentially output pixel signals of each of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel-shared unit 539 to the vertical signal line 543. A state in which one pixel circuit 210 is connected to multiple pixels 541 and the pixel signals of these multiple pixels 541 are output in a time-division manner by one pixel circuit 210 is said to be "multiple pixels 541 sharing one pixel circuit 210."

[0038] Pixels 541A, 541B, 541C, and 541D have common components. Hereinafter, in order to distinguish the components of pixels 541A, 541B, 541C, and 541D from one another, the identification number 1 is added to the end of the reference numeral for the component of pixel 541A, the identification number 2 is added to the end of the reference numeral for the component of pixel 541B, the identification number 3 is added to the end of the reference numeral for the component of pixel 541C, and the identification number 4 is added to the end of the reference numeral for the component of pixel 541D. When it is not necessary to distinguish the components of pixels 541A, 541B, 541C, and 541D from one another, the identification numbers added to the end of the reference numerals for the components of pixels 541A, 541B, 541C, and 541D are omitted.

[0039] Each of the pixels 541A, 541B, 541C, and 541D includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR. The cathode of the photodiode PD (PD1, PD2, PD3, and PD4) is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (e.g., ground). The photodiode PD photoelectrically converts incident light and generates a charge corresponding to the amount of light received. The transfer transistors TR (transfer transistors TR1, TR2, TR3, and TR4) are, for example, n-type complementary metal oxide semiconductor (CMOS) transistors. The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate is electrically connected to a drive signal line. This drive signal line is one of multiple row drive signal lines 542 (see FIG. 1) connected to one pixel sharing unit 539. The transfer transistor TR transfers the charge generated in the photodiode PD to the floating diffusion FD. The floating diffusion FD (floating diffusions FD1, FD2, FD3, and FD4) is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion FD is a charge holding means that temporarily holds the charge transferred from the photodiode PD, and is also a charge-voltage conversion means that generates a voltage according to the amount of charge. The photodiode PD corresponds to a specific example of a "photoelectric conversion unit" in the present disclosure. The floating diffusion FD corresponds to a specific example of a "charge accumulation unit" in the present disclosure.

[0040] The four floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) included in one pixel-shared unit 539 are electrically connected to each other and to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST. The gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. This drive signal line is one of the multiple row drive signal lines 542 connected to one pixel-shared unit 539. The drain of the reset transistor RST is connected to a power supply line VDD. The gate of the reset transistor RST is connected to a drive signal line. This drive signal line is one of the multiple row drive signal lines 542 connected to one pixel-shared unit 539. The gate of the amplification transistor AMP is connected to the floating diffusion FD. The drain of the amplification transistor AMP is connected to the power supply line VDD. The source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to a vertical signal line 543. The gate of the selection transistor SEL is connected to the drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539 .

[0041] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD. The gate (transfer gate TG) of the transfer transistor TR includes, for example, a so-called vertical electrode, and as shown in FIG. 6, extends from the surface of the semiconductor layer (semiconductor layer 100S in FIG. 6) to a depth reaching the PD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, it resets the potential of the floating diffusion FD to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplification transistor AMP generates, as the pixel signal, a signal with a voltage corresponding to the level of the charge held in the floating diffusion FD. The amplification transistor AMP is connected to a vertical signal line 543 via the selection transistor SEL. In the column signal processing unit 550, the amplification transistor AMP forms a source follower together with a load circuit unit (see FIG. 1) connected to the vertical signal line 543. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing unit 550 via the vertical signal line 543. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, N-type CMOS transistors.

[0042] The FD conversion gain switching transistor FDG is used to change the gain of charge-to-voltage conversion in the floating diffusion FD. Generally, pixel signals are small when shooting in dark locations. Based on Q = CV, if the capacitance (FD capacitance C) of the floating diffusion FD is large during charge-to-voltage conversion, the V when converted to voltage by the amplifier transistor AMP will be small. On the other hand, in bright locations, pixel signals are large, so if the FD capacitance C is not large, the floating diffusion FD cannot fully absorb the charge from the photodiode PD. Furthermore, the FD capacitance C must be large so that the V when converted to voltage by the amplifier transistor AMP does not become too large (in other words, to reduce it). Given these factors, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, increasing the overall FD capacitance C. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall FD capacitance C decreases. In this way, by switching the FD conversion gain switching transistor FDG on and off, the FD capacitance C can be varied, thereby changing the conversion efficiency. The FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.

[0043] It is also possible to configure the pixel circuit 210 without the FD conversion gain switching transistor FDG. In this case, for example, the pixel circuit 210 is configured with three transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. The pixel circuit 210 has at least one pixel transistor, for example, the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG.

[0044] The selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to a row drive signal line 542 (see FIG. 1). The source of the amplification transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to a vertical signal line 543, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. Although not shown, the number of pixels 541 sharing one pixel circuit 210 may be other than four. For example, two or eight pixels 541 may share one pixel circuit 210.

[0045] FIG. 5 shows an example of a connection between multiple pixel-sharing units 539 and vertical signal lines 543. For example, four pixel-sharing units 539 arranged in a column direction are divided into four groups, and a vertical signal line 543 is connected to each of the four groups. For simplicity of explanation, FIG. 5 shows an example in which each of the four groups includes one pixel-sharing unit 539. However, each of the four groups may include multiple pixel-sharing units 539. In this way, in the imaging device 1, the multiple pixel-sharing units 539 arranged in the column direction may be divided into groups including one or more pixel-sharing units 539. For example, a vertical signal line 543 and a column signal processing unit 550 are connected to each of these groups, allowing pixel signals to be read out simultaneously from each group. Alternatively, in the imaging device 1, one vertical signal line 543 may be connected to multiple pixel-sharing units 539 arranged in a column direction. In this case, pixel signals are read out sequentially in a time-division manner from the multiple pixel-sharing units 539 connected to one vertical signal line 543.

[0046] [Specific Configuration of Imaging Device 1] FIG. 6 illustrates an example of a cross-sectional configuration perpendicular to the main surfaces of the first substrate 100, the second substrate 200, and the third substrate 300 of the imaging device 1. FIG. 6 is a schematic representation to facilitate understanding of the positional relationships of the components, and may differ from the actual cross section. In the imaging device 1, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. The imaging device 1 further includes a light-receiving lens 401 on the back surface (light incident surface) of the first substrate 100. A color filter layer (not shown) may be provided between the light-receiving lens 401 and the first substrate 100. The light-receiving lens 401 is provided for each of the pixels 541A, 541B, 541C, and 541D, for example. The imaging device 1 is, for example, a back-illuminated imaging device. The imaging device 1 includes a pixel array section 540 located in the center and a peripheral section 540B located outside the pixel array section 540.

[0047] The first substrate 100 has, in order from the light receiving lens 401 side, an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T. The semiconductor layer 100S is made of, for example, a silicon substrate. The semiconductor layer 100S has, for example, a p-well layer 115 in and near a part of the surface (the surface on the wiring layer 100T side), and an n-type semiconductor region 114 in the other region (a region deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 form a pn junction photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0048] 7A shows an example of the planar configuration of the first substrate 100. Fig. 7A mainly shows the planar configuration of the pixel isolation portion 117, photodiode PD, floating diffusion FD, VSS contact region 118, and transfer transistor TR of the first substrate 100. The configuration of the first substrate 100 will be described using Fig. 7A together with Fig. 6.

[0049] A floating diffusion FD and a VSS contact region 118 are provided near the surface of the semiconductor layer 100S. The floating diffusion FD is configured by an n-type semiconductor region provided in the p-well layer 115. The floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D are provided close to each other in the center of the pixel-shared unit 539 ( FIG. 7A ). As will be described in detail later, the four floating diffusions (floating diffusions FD1, FD2, FD3, and FD4) included in this pixel-shared unit 539 are electrically connected to each other via electrical connection means (pad portions 120, described later) within the first substrate 100 (more specifically, within the wiring layer 100T). Furthermore, the floating diffusion FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via electrical means (through electrodes 120E, which will be described later). In the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion FD is electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG by this electrical means. Here, the VSS contact region 118 corresponds to a specific example of an "impurity diffusion region" in the present disclosure.

[0050] The VSS contact region 118 is a region electrically connected to the reference potential line VSS and is arranged apart from the floating diffusion FD. For example, in the pixels 541A, 541B, 541C, and 541D, the floating diffusion FD is arranged at one end of each pixel in the V direction, and the VSS contact region 118 is arranged at the other end (FIG. 7A). The VSS contact region 118 is formed of, for example, a p-type semiconductor region. The VSS contact region 118 is connected to, for example, a ground potential or a fixed potential. This supplies a reference potential to the semiconductor layer 100S.

[0051] The first substrate 100 is provided with a photodiode PD, a floating diffusion FD, a VSS contact region 118, and a transfer transistor TR. The photodiode PD, floating diffusion FD, VSS contact region 118, and transfer transistor TR are provided in each of the pixels 541A, 541B, 541C, and 541D. The transfer transistor TR is provided on the front surface side of the semiconductor layer 100S (the side opposite the light incident surface, the second substrate 200 side). The transfer transistor TR has a transfer gate TG. The transfer gate TG includes, for example, a horizontal portion TGb facing the front surface of the semiconductor layer 100S and a vertical portion TGa provided within the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is in contact with the horizontal portion TGb, and the other end is provided within the n-type semiconductor region 114. By configuring the transfer transistor TR with such a vertical transistor, transfer failure of pixel signals is less likely to occur, and the readout efficiency of pixel signals can be improved.

[0052] The horizontal portion TGb of the transfer gate TG extends, for example, in the H direction from a position facing the vertical portion TGa toward the center of the pixel sharing unit 539 (FIG. 7A). This allows the H direction position of the through electrode (through electrode TGV described later) that reaches the transfer gate TG to be closer to the H direction positions of the through electrodes (through electrodes 120E and 121E described later) that are connected to the floating diffusion FD and the VSS contact region 118. For example, the multiple pixel sharing units 539 provided on the first substrate 100 have the same configuration (FIG. 7A).

[0053] 8A and 8B schematically show other examples of the configuration of the main parts of the first substrate 100 and the second substrate 200. Fig. 8A shows the cross-sectional configuration of the main parts of the first substrate 100 and the second substrate 200, and Fig. 8B shows an example of the planar configuration of the pixel sharing unit 539.

[0054] The transfer transistor TR may be configured as a planar transistor (FIG. 8A). In this case, for example, a transfer gate TG is provided on the surface of the semiconductor layer 100S. For example, the side surface of the transfer gate TG is covered with a sidewall SW. The sidewall SW includes, for example, silicon nitride (SiN). A gate insulating film (not shown in FIG. 8A; a gate insulating film TR-I in FIG. 19B described later) is provided between the semiconductor layer 100S and the transfer gate TG. The transfer gates TG (transfer gates TG1, TG2, TG3, and TG4) of the pixels 541A, 541B, 541C, and 541D are provided, for example, so as to surround the floating diffusion FD in a planar view (FIG. 8B).

[0055] The semiconductor layer 100S is provided with a pixel separator 117 that separates the pixels 541A, 541B, 541C, and 541D from one another. The pixel separator 117 is formed to extend in the normal direction of the semiconductor layer 100S (a direction perpendicular to the surface of the semiconductor layer 100S). The pixel separator 117 is provided to separate the pixels 541A, 541B, 541C, and 541D from one another, and has, for example, a lattice-like planar shape (FIGS. 7A and 7B). The pixel separator 117 electrically and optically separates the pixels 541A, 541B, 541C, and 541D from one another. The pixel separator 117 includes, for example, a light-shielding film 117A and an insulating film 117B. The light-shielding film 117A is made of, for example, tungsten (W). The insulating film 117B is provided between the light-shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. The insulating film 117B is made of, for example, silicon oxide (SiO). The pixel separating portion 117 has, for example, an FTI (Full Trench Isolation) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel separating portion 117 is not limited to an FTI structure that penetrates the semiconductor layer 100S. For example, it may have a DTI (Deep Trench Isolation) structure that does not penetrate the semiconductor layer 100S. The pixel separating portion 117 extends in the normal direction of the semiconductor layer 100S and is formed in a partial region of the semiconductor layer 100S.

[0056] The semiconductor layer 100S is provided with, for example, a first pinning region 113 and a second pinning region 116. The first pinning region 113 is provided near the back surface of the semiconductor layer 100S and is disposed between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is provided on a side surface of the pixel separating section 117, specifically, between the pixel separating section 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 are formed of, for example, a p-type semiconductor region.

[0057] A fixed charge film 112 having a negative fixed charge is provided between the semiconductor layer 100S and the insulating film 111. An electric field induced by the fixed charge film 112 forms a first pinning region 113 of the hole accumulation layer at the interface on the light-receiving surface (back surface) side of the semiconductor layer 100S. This suppresses the generation of dark current due to the interface state on the light-receiving surface side of the semiconductor layer 100S. The fixed charge film 112 is formed, for example, from an insulating film having a negative fixed charge. Examples of materials for this insulating film having a negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.

[0058] A light-shielding film 117A is provided between the fixed charge film 112 and the insulating film 111. This light-shielding film 117A may be provided continuously with the light-shielding film 117A that constitutes the pixel separating section 117. The light-shielding film 117A between the fixed charge film 112 and the insulating film 111 is selectively provided, for example, at a position facing the pixel separating section 117 in the semiconductor layer 100S. The insulating film 111 is provided so as to cover this light-shielding film 117A. The insulating film 111 is made of, for example, silicon oxide.

[0059] The wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 has, from the semiconductor layer 100S side, an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124, in this order. The horizontal portion TGb of the transfer gate TG is provided in, for example, this wiring layer 100T. The interlayer insulating film 119 is provided over the entire surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 is made of, for example, a silicon oxide film. Note that the configuration of the wiring layer 100T is not limited to the above, and may be any configuration including wiring and an insulating film. The pad portion 120 corresponds to a specific example of a "shared connection portion" in the present disclosure.

[0060] FIG. 7B shows the configuration of the pad portions 120 and 121 along with the planar configuration shown in FIG. 7A. The pad portions 120 and 121 are provided in selective regions on the interlayer insulating film 119. The pad portion 120 is used to connect the floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D to one another. The pad portion 120 is disposed, for example, for each pixel sharing unit 539 in the center of the pixel sharing unit 539 in a planar view ( FIG. 7B ). The pad portion 120 is disposed so as to straddle the pixel separating portion 117 and overlap at least a portion of each of the floating diffusions FD1, FD2, FD3, and FD4 ( FIGS. 6 and 7B ). Specifically, the pad section 120 is formed in a region overlapping at least a portion of each of the plurality of floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) that share the pixel circuit 210 and at least a portion of the pixel isolation section 117 formed between the plurality of photodiodes PD (photodiodes PD1, PD2, PD3, PD4) that share the pixel circuit 210. The pad section 120 has, for example, a rectangular shape in a plan view. The shape of the pad section 120 is not limited to the above, and the pad section 120 may have, for example, a circular shape, an elliptical shape, a triangular shape, a rectangular shape, or a polygonal shape in a plan view.

[0061] The interlayer insulating film 119 may be provided with connection vias for electrically connecting the pad portion 120 to the floating diffusions FD1, FD2, FD3, and FD4. The connection vias may be provided for each of the pixels 541A, 541B, 541C, and 541D. For example, the pad portion 120 may be electrically connected to the floating diffusions FD1, FD2, FD3, and FD4 by embedding a portion of the pad portion 120 in the connection via.

[0062] The pad portion 121 is used to connect the multiple VSS contact regions 118 to each other. For example, the pad portion 121 electrically connects the VSS contact regions 118 provided in pixels 541C and 541D of one pixel sharing unit 539 that are adjacent to each other in the V direction with the VSS contact regions 118 provided in pixels 541A and 541B of the other pixel sharing unit 539. The pad portion 121 is provided, for example, to straddle the pixel isolation portion 117 and is arranged to overlap at least a portion of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region that overlaps, in a direction perpendicular to the surface of the semiconductor layer 100S, with at least a portion of each of the multiple VSS contact regions 118 and at least a portion of the pixel isolation portion 117 formed between the multiple VSS contact regions 118.

[0063] A connection via may be provided in the interlayer insulating film 119 to electrically connect the pad portion 121 and the VSS contact region 118. A connection via may be provided in each of the pixels 541A, 541B, 541C, and 541D. For example, the pad portion 121 may be electrically connected to the VSS contact region 118 by partially embedding the pad portion 121 in the connection via. For example, the pad portion 120 and the pad portion 121 of each of the multiple pixel sharing units 539 aligned in the V direction are arranged at approximately the same position in the H direction ( FIG. 7B ).

[0064] By providing the pad section 120, it is possible to reduce the amount of wiring for connecting each floating diffusion FD to the pixel circuit 210 (for example, the gate electrode of the amplification transistor AMP) across the entire chip. Similarly, by providing the pad section 121, it is possible to reduce the amount of wiring for supplying potential to each VSS contact region 118 across the entire chip. This makes it possible to reduce the area of ​​the entire chip, suppress electrical interference between wiring in miniaturized pixels, and / or reduce costs by reducing the number of components.

[0065] The pad portions 120, 121 can be provided at desired positions on the first substrate 100 and the second substrate 200. Specifically, the pad portions 120, 121 can be provided on either the wiring layer 100T or the insulating region 212 of the semiconductor layer 200S. When provided on the wiring layer 100T, the pad portions 120, 121 may be in direct contact with the semiconductor layer 100S. Specifically, the pad portions 120, 121 may be configured to be directly connected to at least a portion of each of the floating diffusion FD and / or the VSS contact region 118. Alternatively, connection vias may be provided from each of the floating diffusion FD and / or the VSS contact region 118 connected to the pad portions 120, 121, and the pad portions 120, 121 may be provided at desired positions in the insulating region 212 of the wiring layer 100T and the semiconductor layer 200S. Alternatively, a connection via may be provided from each of the floating diffusion FD and / or VSS contact region 118 connected to the pad portions 120, 121, and the pad portions 120, 121 may be provided at desired positions in the insulating region 212 of the wiring layer 100T and the semiconductor layer 200S.

[0066] In particular, when the pad portions 120, 121 are provided in the wiring layer 100T, it is possible to reduce the wiring connected to the floating diffusion FD and / or the VSS contact region 118 in the insulating region 212 of the semiconductor layer 200S. This makes it possible to reduce the area of ​​the insulating region 212, in the second substrate 200 on which the pixel circuit 210 is formed, for forming the through wiring for connecting the floating diffusion FD to the pixel circuit 210. This makes it possible to ensure a large area for the second substrate 200 on which the pixel circuit 210 is formed. By ensuring the area for the pixel circuit 210, it is possible to form a large pixel transistor, which can contribute to improving image quality by reducing noise, etc.

[0067] In particular, when an FTI structure is used for the pixel separation section 117, it is preferable to provide a floating diffusion FD and / or a VSS contact region 118 in each pixel 541, and therefore, by using the configuration of the pad sections 120, 121, the wiring connecting the first substrate 100 and the second substrate 200 can be significantly reduced.

[0068] 7B , for example, pad portions 120 connected to a plurality of floating diffusions FD and pad portions 121 connected to a plurality of VSS contact regions 118 are alternately arranged linearly in the V direction. Furthermore, the pad portions 120 and 121 are formed in positions surrounded by a plurality of photodiodes PD, a plurality of transfer gates TG, and a plurality of floating diffusions FD. This allows elements other than the floating diffusions FD and VSS contact regions 118 to be freely arranged on the first substrate 100 on which a plurality of elements are formed, thereby improving the efficiency of the layout of the entire chip. Furthermore, symmetry is ensured in the layout of elements formed in each pixel shared unit 539, thereby suppressing variations in the characteristics of each pixel 541.

[0069] The connection between the pad section 120 and the floating diffusion FD is not limited to a plane parallel to the light incident surface, but is a three-dimensional connection. A three-dimensional connection refers to a connection form including a connection between the pad section 120 and the floating diffusion FD on a plane or a curved surface intersecting the light incident surface. In this case, the portion of the pixel separation section 117 on the semiconductor layer 200S side that is sandwiched between two adjacent floating diffusions FD (hereinafter referred to as the "upper end of the pixel separation section 117") is located at a position recessed from the surface of the semiconductor layer 100S on the semiconductor layer 200S side. The side surfaces of each floating diffusion FD are in contact with the pad section 120, as shown in FIG. 8A, for example. This allows for a larger connection area between the pad section 120 and the floating diffusion FD compared to when the upper surface of the upper end of the pixel separation section 117 is located on the same plane as the surface of the semiconductor layer 100S on the semiconductor layer 200S side. Furthermore, even when the pixel 541 is miniaturized, it is possible to prevent a reduction in the connection area between the pad section 120 and the floating diffusion FD.

[0070] The pad portions 120 and 121 are made of, for example, polysilicon (Poly Si), more specifically, doped polysilicon to which impurities are added. The pad portions 120 and 121 are preferably made of a highly heat-resistant conductive material such as polysilicon, tungsten (W), titanium (Ti), or titanium nitride (TiN). This makes it possible to form the pixel circuit 210 after bonding the semiconductor layer 200S of the second substrate 200 to the first substrate 100. The reason for this will be explained below. In the following explanation, the method of forming the pixel circuit 210 after bonding the semiconductor layer 200S of the first substrate 100 to the semiconductor layer 200S of the second substrate 200 will be referred to as the first manufacturing method.

[0071] Here, it is also conceivable to form the pixel circuits 210 on the second substrate 200 and then bond this to the first substrate 100 (hereinafter referred to as a second manufacturing method). In this second manufacturing method, electrodes for electrical connection are formed in advance on the surface of the first substrate 100 (the surface of the wiring layer 100T) and the surface of the second substrate 200 (the surface of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are bonded together, the electrodes for electrical connection formed on the surface of the first substrate 100 and the surface of the second substrate 200 simultaneously come into contact with each other. This forms an electrical connection between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, by configuring the imaging device 1 using the second manufacturing method, it is possible to manufacture the imaging device using an appropriate process depending on the configuration of the first substrate 100 and the second substrate 200, for example, and thus a high-quality, high-performance imaging device can be manufactured.

[0072] In this second manufacturing method, when bonding the first substrate 100 and the second substrate 200 together, alignment errors may occur due to the manufacturing equipment used for bonding. Furthermore, the first substrate 100 and the second substrate 200 each have a diameter of, for example, several tens of centimeters. When bonding the first substrate 100 and the second substrate 200 together, expansion and contraction of the substrates may occur in microscopic regions of each of the first substrate 100 and the second substrate 200. This expansion and contraction of the substrates is caused by a slight difference in the timing at which the substrates contact each other. Due to this expansion and contraction of the first substrate 100 and the second substrate 200, errors may occur in the positions of the electrical connection electrodes formed on the surfaces of the first substrate 100 and the second substrate 200, respectively. In the second manufacturing method, it is preferable to take measures to ensure that the electrodes of the first substrate 100 and the second substrate 200 contact each other even if such errors occur. Specifically, at least one, and preferably both, of the electrodes of the first substrate 100 and the second substrate 200 are made large in consideration of the above-mentioned error. Therefore, when the second manufacturing method is used, for example, the size (size in the substrate planar direction) of the electrode formed on the surface of the first substrate 100 or the second substrate 200 becomes larger than the size of the internal electrode extending in the thickness direction from the inside of the first substrate 100 or the second substrate 200 to the surface.

[0073] On the other hand, by forming the pad portions 120, 121 from a heat-resistant conductive material, the first manufacturing method can be used. In the first manufacturing method, after forming the first substrate 100 including the photodiode PD, the transfer transistor TR, etc., the first substrate 100 and the second substrate 200 (semiconductor layer 2000S) are bonded together. At this time, the second substrate 200 is in a state where patterns such as active elements and wiring layers that constitute the pixel circuits 210 have not yet been formed. Because the second substrate 200 is in a state before patterns are formed, even if an error occurs in the bonding position when the first substrate 100 and the second substrate 200 are bonded together, this bonding error will not cause an error in alignment between the patterns of the first substrate 100 and the second substrate 200. This is because the pattern of the second substrate 200 is formed after the first substrate 100 and the second substrate 200 are bonded together. It should be noted that when a pattern is formed on the second substrate, for example, an exposure apparatus for pattern formation uses the pattern formed on the first substrate as a target for alignment when forming the pattern. For the reasons described above, errors in the bonding position between the first substrate 100 and the second substrate 200 do not pose a problem in manufacturing the imaging device 1 in the first manufacturing method. For the same reason, errors caused by expansion and contraction of the substrates in the second manufacturing method do not pose a problem in manufacturing the imaging device 1 in the first manufacturing method.

[0074] In the first manufacturing method, after bonding the first substrate 100 and the second substrate 200 (semiconductor layer 200S) together in this manner, active elements are formed on the second substrate 200. Then, through electrodes 120E, 121E and through electrodes TGV (FIG. 6) are formed. In forming these through electrodes 120E, 121E, and TGV, for example, a pattern of the through electrodes is formed from above the second substrate 200 using reduced projection exposure with an exposure device. Because reduced projection exposure is used, even if an error occurs in the alignment between the second substrate 200 and the exposure device, the magnitude of the error in the second substrate 200 is only a fraction (the reciprocal of the reduced projection magnification) of the error in the second manufacturing method. Therefore, by configuring the imaging device 1 using the first manufacturing method, it becomes easier to align the elements formed on the first substrate 100 and the second substrate 200, and a high-quality, high-performance imaging device can be manufactured.

[0075] The imaging device 1 manufactured using such a first manufacturing method has different characteristics from the imaging device manufactured using the second manufacturing method. Specifically, in the imaging device 1 manufactured using the first manufacturing method, for example, the through electrodes 120E, 121E, and TGV have a substantially constant thickness (size in the substrate planar direction) from the second substrate 200 to the first substrate 100. Alternatively, when the through electrodes 120E, 121E, and TGV have a tapered shape, the tapered shape has a constant inclination. The imaging device 1 having such through electrodes 120E, 121E, and TGV facilitates miniaturization of the pixels 541.

[0076] Here, when the imaging device 1 is manufactured using the first manufacturing method, the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together, and then active elements are formed on the second substrate 200. Therefore, the first substrate 100 is also affected by the heat treatment required for forming the active elements. For this reason, as described above, it is preferable to use a conductive material with high heat resistance for the pad portions 120, 121 provided on the first substrate 100. For example, it is preferable to use a material with a higher melting point (i.e., higher heat resistance) for the pad portions 120, 121 than at least a portion of the wiring material included in the wiring layer 200T of the second substrate 200. For example, a conductive material with high heat resistance, such as doped polysilicon, tungsten, titanium, or titanium nitride, is used for the pad portions 120, 121. This makes it possible to manufacture the imaging device 1 using the first manufacturing method.

[0077] The pad portions 120 and 121 may be made of a metal material such as tantalum nitride (TaN), aluminum (Al), or copper (Cu).

[0078] The passivation film 122 is provided over the entire surface of the semiconductor layer 100S so as to cover, for example, the pad portions 120 and 121 and the transfer transistor TR (transfer gate TG) (FIG. 6). The passivation film 122 is made of, for example, a silicon nitride (SiN) film. The interlayer insulating film 123 covers the pad portions 120 and 121 with the passivation film 122 in between. This interlayer insulating film 123 is provided over the entire surface of the semiconductor layer 100S. The interlayer insulating film 123 is made of, for example, a silicon oxide (SiO) film. The bonding film 124 is provided on the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. This bonding film 124 is provided over the entire main surface of the first substrate 100. The bonding film 124 is made of, for example, a silicon nitride film.

[0079] The light receiving lens 401 faces the semiconductor layer 100S with the fixed charge film 112 and the insulating film 111 interposed therebetween (FIG. 6). The light receiving lens 401 is provided at a position facing the photodiode PD of each of the pixels 541A, 541B, 541C, and 541D, for example.

[0080] The second substrate 200 has, from the first substrate 100 side, a semiconductor layer 200S and a wiring layer 200T, in this order. The semiconductor layer 200S is made of a silicon substrate. A well region 211 is provided in the semiconductor layer 200S across the thickness direction. The well region 211 is, for example, a p-type semiconductor region. The second substrate 200 has a pixel circuit 210 arranged for each pixel sharing unit 539. The pixel circuit 210 is provided, for example, on the front surface side (the wiring layer 200T side) of the semiconductor layer 200S. In the imaging device 1, the second substrate 200 is bonded to the first substrate 100 such that the back surface side (the semiconductor layer 200S side) of the second substrate 200 faces the front surface side (the wiring layer 100T side) of the first substrate 100. In other words, the second substrate 200 is bonded to the first substrate 100 face-to-back.

[0081] 9 to 13 schematically show an example of the planar configuration of the second substrate 200. FIG. 9 shows the configuration of the pixel circuit 210 provided near the surface of the semiconductor layer 200S. FIG. 10 schematically shows the configuration of the wiring layer 200T (specifically, the first wiring layer W1 described below), the semiconductor layer 200S connected to the wiring layer 200T, and each part of the first substrate 100. FIGS. 11 to 13 show an example of the planar configuration of the wiring layer 200T. The configuration of the second substrate 200 will be described below using FIGS. 9 to 13 as well as FIG. 6. In FIGS. 9 and 10, the outline of the photodiode PD (the boundary between the pixel isolation section 117 and the photodiode PD) is shown by a dashed line, and the boundary between the semiconductor layer 200S and the element isolation region 213 or the insulating region 212 in the portion overlapping the gate electrode of each transistor constituting the pixel circuit 210 is shown by a dotted line. In the portion overlapping the gate electrode of the amplification transistor AMP, there is provided, on one side in the channel width direction, a boundary between the semiconductor layer 200S and the isolation region 213, and a boundary between the isolation region 213 and the insulating region 212. The configuration of the second substrate 200 will be described below with reference to FIGS. 9 to 13 as well as FIG.

[0082] The second substrate 200 is provided with an insulating region 212 that divides the semiconductor layer 200S and an element isolation region 213 that is provided in a part of the semiconductor layer 200S in the thickness direction (FIG. 6). For example, in the insulating region 212 provided between two pixel circuits 210 adjacent to each other in the H direction, the through electrodes 120E and 121E and the through electrodes TGVs (through electrodes TGV1, TGV2, TGV3, TGV4) of two pixel shared units 539 connected to the two pixel circuits 210 are arranged (FIG. 11).

[0083] The insulating region 212 has approximately the same thickness as the semiconductor layer 200S (FIG. 6). The semiconductor layer 200S is divided by this insulating region 212. The through electrodes 120E, 121E and the through electrodes TGV are arranged in this insulating region 212. The insulating region 212 is made of, for example, silicon oxide.

[0084] The through electrodes 120E, 121E are provided to penetrate the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E, 121E are connected to the wiring of the wiring layer 200T (the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the fourth wiring layer W4 described below). The through electrodes 120E, 121E are provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and the lower ends thereof are connected to the pad portions 120, 121 (FIG. 6). The through electrode 120E serves to electrically connect the pad portion 120 and the pixel circuit 210. That is, the floating diffusion FD of the first substrate 100 is electrically connected to the pixel circuit 210 of the second substrate 200 by the through electrode 120E. The through electrode 121E is for electrically connecting the pad portion 121 and the reference potential line VSS of the wiring layer 200T. That is, the through electrode 121E electrically connects the VSS contact region 118 of the first substrate 100 to the reference potential line VSS of the second substrate 200.

[0085] The through electrodes TGV are provided to penetrate the insulating region 212 in the thickness direction. The upper ends of the through electrodes TGV are connected to the wiring of the wiring layer 200T. The through electrodes TGV are provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119, and the lower ends thereof are connected to the transfer gates TG (FIG. 6). Such through electrodes TGV are intended to electrically connect the transfer gates TG (transfer gates TG1, TG2, TG3, and TG4) of the pixels 541A, 541B, 541C, and 541D to the wiring of the wiring layer 200T (part of the row drive signal line 542, specifically, the wirings TRG1, TRG2, TRG3, and TRG4 in FIG. 10, which will be described later). That is, the through-electrode TGV electrically connects the transfer gate TG of the first substrate 100 to the wiring TRG of the second substrate 200, and a drive signal is sent to each of the transfer transistors TR (transfer transistors TR1, TR2, TR3, TR4).

[0086] The insulating region 212 is a region for providing the through electrodes 120E, 121E and through electrodes TGV for electrically connecting the first substrate 100 and the second substrate 200, insulated from the semiconductor layer 200S. For example, the through electrodes 120E, 121E and through electrodes TGV (through electrodes TGV1, TGV2, TGV3, TGV4) connected to two pixel circuits 210 (pixel sharing units 539) adjacent to each other in the H direction are arranged in the insulating region 212. The insulating region 212 is provided, for example, extending in the V direction (FIG. 8). Here, by devising the position of the horizontal portion TGb of the transfer gate TG, the position of the through electrode TGV in the H direction is closer to the position of the through electrodes 120E, 121E in the H direction than the position of the vertical portion TGa (FIG. 7A). For example, the through electrodes TGV are arranged at approximately the same position as the through electrodes 120E, 120E in the H direction. This allows the through electrodes 120E, 121E and the through electrodes TGV to be collectively provided in the insulating region 212 extending in the V direction. Another possible arrangement is to provide the horizontal portion TGb only in the region overlapping the vertical portion TGa. In this case, the through electrode TGV is formed substantially directly above the vertical portion TGa, and is disposed, for example, in the substantially central portion of each pixel 541 in the H and V directions. In this case, the position of the through electrode TGV in the H direction is significantly offset from the positions of the through electrodes 120E, 121E in the H direction. Around the through electrodes TGV and the through electrodes 120E, 121E, for example, an insulating region 212 is provided to electrically insulate them from the adjacent semiconductor layer 200S. If the position of the through electrode TGV in the H direction is significantly offset from the positions of the through electrodes 120E, 121E in the H direction, it is necessary to provide an insulating region 212 independently around each of the through electrodes 120E, 121E, and TGV. This results in the semiconductor layer 200S being divided into small pieces. In contrast, a layout in which the through electrodes 120E, 121E and the through electrodes TGV are collectively disposed in the insulating region 212 extending in the V direction can increase the size of the semiconductor layer 200S in the H direction. Therefore, a large area can be secured for the semiconductor element formation region in the semiconductor layer 200S.This makes it possible to increase the size of the amplification transistor AMP and suppress noise, for example.

[0087] Furthermore, in the imaging device 1, since the pad section 120 is provided on the first substrate 100, a through electrode 120E is provided for each pixel sharing unit 539. Furthermore, since the pad section 121 is provided on the first substrate 100, a through electrode 121E is provided for each four pixels (pixels 541A, 541B, 541C, and 541D). This reduces the number of through electrodes 120E, 121E, and makes it possible to reduce the insulating region 212. The reason for this will be explained below.

[0088] The element isolation region 213 is provided on the surface side of the semiconductor layer 200S. The element isolation region 213 has an STI (Shallow Trench Isolation) structure. In this element isolation region 213, the semiconductor layer 200S is dug in the thickness direction (perpendicular to the main surface of the second substrate 200), and an insulating film is buried in this dug portion. This insulating film is made of, for example, silicon oxide. The element isolation region 213 separates the multiple transistors that make up the pixel circuit 210 according to the layout of the pixel circuit 210. The semiconductor layer 200S (specifically, the well region 211) extends below the element isolation region 213 (deep in the semiconductor layer 200S).

[0089] Here, with reference to Figures 7A, 7B and 9, the difference between the outer shape of the pixel sharing unit 539 on the first substrate 100 (outer shape in the substrate planar direction) and the outer shape of the pixel sharing unit 539 on the second substrate 200 will be described.

[0090] In the imaging device 1, pixel-sharing units 539 are provided across both the first substrate 100 and the second substrate 200. For example, the outer shape of the pixel-sharing units 539 provided on the first substrate 100 and the outer shape of the pixel-sharing units 539 provided on the second substrate 200 are different from each other.

[0091] 7A and 7B, the outlines of the pixels 541A, 541B, 541C, and 541D are represented by dashed dotted lines, and the outline shape of the pixel-sharing unit 539 is represented by a thick line. For example, the pixel-sharing unit 539 of the first substrate 100 is composed of two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction and two pixels 541 (pixels 541C and 541D) arranged adjacent to each other in the V direction. That is, the pixel-sharing unit 539 of the first substrate 100 is composed of four pixels 541 arranged adjacently in two rows and two columns, and the pixel-sharing unit 539 of the first substrate 100 has a substantially square outline shape. In the pixel array section 540, such pixel sharing units 539 are arranged adjacent to each other at a pitch of two pixels in the H direction (a pitch equivalent to two pixels 541) and at a pitch of two pixels in the V direction (a pitch equivalent to two pixels 541).

[0092] 9 and 10, the outlines of the pixels 541A, 541B, 541C, and 541D are represented by dashed dotted lines, and the outline shape of the pixel-sharing unit 539 is represented by a thick line. For example, the outline shape of the pixel-sharing unit 539 of the second substrate 200 is smaller in the H direction than the pixel-sharing unit 539 of the first substrate 100, and is larger in the V direction than the pixel-sharing unit 539 of the first substrate 100. For example, the pixel-sharing unit 539 of the second substrate 200 is formed with a size (area) equivalent to one pixel in the H direction, and is formed with a size equivalent to four pixels in the V direction. In other words, the pixel-sharing unit 539 of the second substrate 200 is formed with a size equivalent to adjacent pixels arranged in one row and four columns, and the pixel-sharing unit 539 of the second substrate 200 has a substantially rectangular outline shape.

[0093] For example, in each pixel circuit 210, the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG are arranged in this order in the V direction ( FIG. 9 ). By providing each pixel circuit 210 with a substantially rectangular outer shape as described above, four transistors (the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG) can be arranged side by side in one direction (the V direction in FIG. 9 ). This allows the drain of the amplification transistor AMP and the drain of the reset transistor RST to share a single diffusion region (a diffusion region connected to the power supply line VDD). For example, the formation region of each pixel circuit 210 can also be provided in a substantially square shape. In this case, two transistors are arranged along one direction, making it difficult to share a single diffusion region for the drain of the amplification transistor AMP and the drain of the reset transistor RST. Therefore, providing the formation region of the pixel circuit 210 in a substantially rectangular shape makes it easier to arrange the four transistors closely together, thereby reducing the formation region of the pixel circuit 210. In other words, pixels can be miniaturized. Furthermore, when it is not necessary to reduce the area in which the pixel circuit 210 is formed, it is possible to increase the area in which the amplification transistor AMP is formed and suppress noise.

[0094] For example, near the surface of the semiconductor layer 200S, in addition to the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is provided. The VSS contact region 218 is configured, for example, by a p-type semiconductor region. The VSS contact region 218 is electrically connected to the VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) via the wiring of the wiring layer 200T and the through-electrode 121E. This VSS contact region 218 is provided, for example, at a position adjacent to the source of the FD conversion gain switching transistor FDG with the element isolation region 213 interposed therebetween (FIG. 9).

[0095] Next, with reference to Figures 7B and 9, the positional relationship between the pixel-sharing units 539 provided on the first substrate 100 and the pixel-sharing units 539 provided on the second substrate 200 will be described. For example, of two pixel-sharing units 539 aligned in the V direction on the first substrate 100, one pixel-sharing unit 539 (for example, the upper side of the paper in Figure 7B) is connected to one pixel-sharing unit 539 (for example, the left side of the paper in Figure 9) of two pixel-sharing units 539 aligned in the H direction on the second substrate 200. For example, of the two pixel-sharing units 539 aligned in the V direction on the first substrate 100, the other pixel-sharing unit 539 (for example, the lower side of the paper in Figure 7B) is connected to the other pixel-sharing unit 539 (for example, the right side of the paper in Figure 9) of two pixel-sharing units 539 aligned in the H direction on the second substrate 200.

[0096] For example, of two pixel sharing units 539 lined up in the H direction on the second substrate 200, the internal layout (arrangement of transistors, etc.) of one pixel sharing unit 539 is substantially equal to a layout obtained by inverting the internal layout of the other pixel sharing unit 539 in the V and H directions. The effects obtained by this layout will be described below.

[0097] In two pixel-sharing units 539 aligned in the V direction on the first substrate 100, each pad section 120 is disposed at the center of the external shape of the pixel-sharing unit 539, i.e., the center of the pixel-sharing unit 539 in the V and H directions ( FIG. 7B ). On the other hand, the pixel-sharing unit 539 on the second substrate 200 has a substantially rectangular external shape that is long in the V direction as described above, and therefore, for example, the amplification transistor AMP connected to the pad section 120 is disposed at a position shifted upward in the plane of the drawing from the center of the pixel-sharing unit 539 in the V direction. For example, when two pixel-sharing units 539 aligned in the H direction on the second substrate 200 have the same internal layout, the distance between the amplification transistor AMP of one pixel-sharing unit 539 and the pad section 120 (for example, the pad section 120 of the pixel-sharing unit 539 on the upper side in the plane of the drawing in FIG. 7B ) is relatively short. However, the distance between the amplification transistor AMP of the other pixel sharing unit 539 and the pad section 120 (for example, the pad section 120 of the pixel sharing unit 539 on the lower side of the page in FIG. 7B) becomes longer. This increases the area of ​​the wiring required to connect this amplification transistor AMP and the pad section 120, which may complicate the wiring layout of the pixel sharing unit 539. This may affect the miniaturization of the imaging device 1.

[0098] In contrast, by inverting the internal layouts of two pixel-sharing units 539 aligned in the H direction of the second substrate 200 with respect to each other at least in the V direction, it is possible to shorten the distance between the amplification transistors AMP and the pad section 120 of both of these two pixel-sharing units 539. Therefore, compared to a configuration in which the internal layouts of two pixel-sharing units 539 aligned in the H direction of the second substrate 200 are the same, it is easier to miniaturize the imaging device 1. Note that the planar layout of each of the multiple pixel-sharing units 539 of the second substrate 200 is symmetrical within the range shown in FIGS. 7A and 7B , but becomes asymmetrical when the layout of the first wiring layer W1 shown in FIG. 9, which will be described later, is included.

[0099] Furthermore, it is preferable that the internal layouts of two pixel sharing units 539 aligned in the H direction on the second substrate 200 are also inverted relative to each other in the H direction. The reason for this will be explained below. As shown in FIG. 10 , the two pixel sharing units 539 aligned in the H direction on the second substrate 200 are connected to the pad portions 120, 121 of the first substrate 100, respectively. For example, the pad portions 120, 121 are disposed in the central portions in the H direction of the two pixel sharing units 539 aligned in the H direction on the second substrate 200 (between the two pixel sharing units 539 aligned in the H direction). Therefore, by inverting the internal layouts of the two pixel sharing units 539 aligned in the H direction on the second substrate 200 relative to each other in the H direction, it is possible to reduce the distance between each of the multiple pixel sharing units 539 on the second substrate 200 and the pad portions 120, 121. That is, it becomes easier to miniaturize the imaging device 1.

[0100] Furthermore, the positions of the outlines of the pixel-sharing units 539 on the second substrate 200 do not have to be aligned with the positions of any of the outlines of the pixel-sharing units 539 on the first substrate 100. For example, of two pixel-sharing units 539 aligned in the H direction on the second substrate 200, in one pixel-sharing unit 539 (for example, on the left side of the paper in FIG. 10 ), the outline on one side in the V direction (for example, the upper side of the paper in FIG. 10 ) is arranged outside the outline on one side in the V direction of the corresponding pixel-sharing unit 539 on the first substrate 100 (for example, the upper side of the paper in FIG. 7B ). Furthermore, of two pixel-sharing units 539 aligned in the H direction on the second substrate 200, in the other pixel-sharing unit 539 (for example, on the right side of the paper in FIG. 10 ), the outline on the other side in the V direction (for example, the lower side of the paper in FIG. 10 ) is arranged outside the outline on the other side in the V direction of the corresponding pixel-sharing unit 539 on the first substrate 100 (for example, the lower side of the paper in FIG. 7B ). In this way, by arranging the pixel sharing unit 539 of the second substrate 200 and the pixel sharing unit 539 of the first substrate 100 together, it is possible to shorten the distance between the amplification transistor AMP and the pad section 120. Therefore, it becomes easier to miniaturize the imaging device 1.

[0101] Furthermore, the positions of the outlines of the multiple pixel sharing units 539 on the second substrate 200 do not have to be aligned with each other. For example, two pixel sharing units 539 aligned in the H direction on the second substrate 200 are arranged with the positions of the outlines in the V direction shifted. This makes it possible to shorten the distance between the amplification transistor AMP and the pad section 120. This makes it easier to miniaturize the imaging device 1.

[0102] 7B and 10, the repeated arrangement of pixel-sharing units 539 in the pixel array section 540 will be described. The pixel-sharing unit 539 of the first substrate 100 has a size equivalent to two pixels 541 in the H direction and a size equivalent to two pixels 541 in the V direction (FIG. 7B). For example, in the pixel array section 540 of the first substrate 100, pixel-sharing units 539 each having a size equivalent to four pixels 541 are repeatedly arranged adjacent to each other at a two-pixel pitch in the H direction (a pitch equivalent to two pixels 541) and at a two-pixel pitch in the V direction (a pitch equivalent to two pixels 541). Alternatively, the pixel array section 540 of the first substrate 100 may be provided with a pair of pixel-sharing units 539 in which two pixel-sharing units 539 are arranged adjacent to each other in the V direction. In the pixel array section 540 of the first substrate 100, for example, a pair of pixel-sharing units 539 are repeatedly arranged adjacent to each other at a two-pixel pitch in the H direction (a pitch equivalent to two pixels 541) and at a four-pixel pitch in the V direction (a pitch equivalent to four pixels 541). The pixel-sharing unit 539 of the second substrate 200 has a size equivalent to one pixel 541 in the H direction and a size equivalent to four pixels 541 in the V direction ( FIG. 10 ). For example, the pixel array section 540 of the second substrate 200 is provided with a pair of pixel-sharing units 539, each including two pixel-sharing units 539 each having a size equivalent to four pixels 541. The pixel-sharing units 539 are arranged adjacent to each other in the H direction and offset in the V direction. In the pixel array section 540 of the second substrate 200, for example, a pair of pixel-sharing units 539 are repeatedly arranged adjacent to each other with no gaps at a pitch of two pixels in the H direction (a pitch corresponding to two pixels 541) and at a pitch of four pixels in the V direction (a pitch corresponding to four pixels 541). By repeatedly arranging the pixel-sharing units 539 in this manner, it is possible to arrange the pixel-sharing units 539 without any gaps. This makes it easier to miniaturize the imaging device 1.

[0103] The amplifier transistor AMP preferably has a three-dimensional structure, such as a fin type (FIG. 6). For example, the fin type amplifier transistor AMP has a fin formed from a portion of the semiconductor layer 200S, a gate electrode having three planes surrounding the fin, and a gate insulating film provided between the gate electrode and the fin. A three-dimensional transistor refers to a transistor having multiple planes of the gate electrode facing the channel, or a transistor having a curved surface of the gate electrode surrounding the channel. Such a three-dimensional transistor can have a larger effective gate width than a planar transistor when it has the same footprint (occupied area in FIG. 9) as a planar transistor. Therefore, a larger current flows through the three-dimensional transistor, resulting in a higher transconductance gm. This allows the three-dimensional transistor to have a higher operating speed than a planar transistor. In addition, it is possible to reduce random noise (RN). Furthermore, since a three-dimensional transistor has a larger gate area than a planar transistor, it reduces random telegraph signal (RTS) noise.

[0104] By using such a transistor with a three-dimensional structure for at least one of the amplifier transistor AMP, the select transistor SEL, the reset transistor RST, and the FD transfer transistor FDG, the transistor characteristics are improved, and, for example, image quality can be improved. In particular, by configuring the amplifier transistor AMP using a transistor with a three-dimensional structure, noise can be effectively reduced, making it possible to improve image quality. Also, all of the amplifier transistor AMP, the select transistor SEL, the reset transistor RST, and the FD transfer transistor FDG may be configured using transistors with a three-dimensional structure. In this case, manufacturing of the pixel circuit 210 becomes easier.

[0105] Next, the planar configuration of the wiring layer 200T will be described with reference to Figs. 11 to 13. Fig. 11 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2. Fig. 123 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3. Fig. 13 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4.

[0106] For example, the third wiring layer W3 includes wirings TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL extending in the H direction (row direction) (FIG. 12). These wirings correspond to the plurality of row drive signal lines 542 described with reference to FIG. 4. The wirings TRG1, TRG2, TRG3, and TRG4 are for sending drive signals to the transfer gates TG1, TG2, TG3, and TG4, respectively. The wirings TRG1, TRG2, TRG3, and TRG4 are connected to the transfer gates TG1, TG2, TG3, and TG4 via the second wiring layer W2, the first wiring layer W1, and the through-electrode 120E, respectively. The wiring SELL is for sending drive signals to the gate of the selection transistor SEL, the wiring RSTL is for sending drive signals to the gate of the reset transistor RST, and the wiring FDGL is for sending drive signals to the gate of the FD conversion gain switching transistor FDG, respectively. The wirings SELL, RSTL, and FDGL are connected to the gates of the selection transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG, respectively, via the second wiring layer W2, the first wiring layer W1, and a connection portion.

[0107] For example, the fourth wiring layer W4 includes a power supply line VDD, a reference potential line VSS, and a vertical signal line 543 extending in the V direction (column direction) (FIG. 13). The power supply line VDD is connected to the drain of the amplifier transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection portion. The reference potential line VSS is connected to the VSS contact region 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection portion 218V. The reference potential line VSS is also connected to the VSS contact region 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E, and the pad portion 121. The vertical signal line 543 is connected to the source (Vout) of the select transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection portion.

[0108] The contact portions 201 and 202 may be provided at positions overlapping the pixel array section 540 in a planar view (e.g., FIG. 3), or may be provided in a peripheral section 540B outside the pixel array section 540 (e.g., FIG. 6). The contact portions 201 and 202 are provided on the surface of the second substrate 200 (the surface on the wiring layer 200T side). The contact portions 201 and 202 are made of metal such as Cu (copper) and Al (aluminum). The contact portions 201 and 202 are exposed on the surface of the wiring layer 200T (the surface on the third substrate 300 side). The contact portions 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300 and for bonding the second substrate 200 and the third substrate 300 together.

[0109] 6 shows an example in which a peripheral circuit is provided in the peripheral portion 540B of the second substrate 200. This peripheral circuit may include a part of the row driving section 520 or a part of the column signal processing section 550. Alternatively, as shown in FIG. 3, the peripheral circuit may not be provided in the peripheral portion 540B of the second substrate 200, and the connection holes H1 and H2 may be provided near the pixel array section 540.

[0110] The third substrate 300 includes, for example, a wiring layer 300T and a semiconductor layer 300S in this order from the second substrate 200 side. For example, the surface of the semiconductor layer 300S is provided on the second substrate 200 side. The semiconductor layer 300S is made of a silicon substrate. A circuit is provided on the surface side of the semiconductor layer 300S. Specifically, the surface side of the semiconductor layer 300S includes, for example, at least some of an input unit 510A, a row driver unit 520, a timing control unit 530, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B. The wiring layer 300T provided between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, multiple wiring layers separated by the interlayer insulating film, and contact units 301 and 302. The contact portions 301 and 302 are exposed on the surface of the wiring layer 300T (the surface facing the second substrate 200). The contact portion 301 is in contact with the contact portion 201 of the second substrate 200, and the contact portion 302 is in contact with the contact portion 202 of the second substrate 200. The contact portions 301 and 302 are electrically connected to circuits formed in the semiconductor layer 300S (e.g., at least one of the input portion 510A, the row driver portion 520, the timing control portion 530, the column signal processing portion 550, the image signal processing portion 560, and the output portion 510B). The contact portions 301 and 302 are made of metal such as Cu (copper) and aluminum (Al). For example, an external terminal TA is connected to the input portion 510A via a connection hole H1, and an external terminal TB is connected to the output portion 510B via a connection hole H2.

[0111] Here, the features of the imaging device 1 will be described.

[0112] Generally, an imaging device mainly consists of a photodiode and a pixel circuit. Increasing the area of ​​the photodiode increases the amount of charge generated as a result of photoelectric conversion, thereby improving the signal-to-noise ratio (S / N ratio) of the pixel signal and enabling the imaging device to output better image data (image information). On the other hand, increasing the size of the transistors included in the pixel circuit (especially the size of the amplification transistor) reduces the noise generated in the pixel circuit, thereby improving the S / N ratio of the imaging signal and enabling the imaging device to output better image data (image information).

[0113] However, in an imaging device in which a photodiode and a pixel circuit are provided on the same semiconductor substrate, if the area of ​​the photodiode is increased within the limited area of ​​the semiconductor substrate, the size of the transistor provided in the pixel circuit may be reduced, and if the size of the transistor provided in the pixel circuit is increased, the area of ​​the photodiode may be reduced.

[0114] To solve these problems, for example, the imaging device 1 of this embodiment uses a structure in which multiple pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged so as to overlap the photodiode PD. This makes it possible to maximize the area of ​​the photodiode PD and maximize the size of the transistors provided in the pixel circuit 210 within the limited area of ​​the semiconductor substrate. This improves the S / N ratio of the pixel signal, allowing the imaging device 1 to output better image data (image information).

[0115] When realizing a structure in which multiple pixels 541 share one pixel circuit 210 and this pixel circuit 210 is arranged overlapping the photodiode PD, multiple wirings connected to one pixel circuit 210 extend from the floating diffusion FD of each of the multiple pixels 541. In order to secure a large area for the semiconductor substrate (second substrate 200) on which the pixel circuit 210 is formed, for example, it is possible to form a connection wiring that interconnects these multiple extending wirings and combines them into one. Similarly, it is possible to form a connection wiring that interconnects the multiple extending wirings and combines them into one for the multiple wirings extending from the VSS contact region 118.

[0116] For example, if the connection wiring that interconnects the multiple wirings extending from the floating diffusion FD of each of the multiple pixels 541 is formed on the semiconductor substrate 200 that forms the pixel circuit 210, it is conceivable that the area for forming the transistors included in the pixel circuit 210 will be reduced. Similarly, if the connection wiring that interconnects the multiple wirings extending from the VSS contact region 118 of each of the multiple pixels 541 and combines them into one is formed on the semiconductor substrate (second substrate 200) that forms the pixel circuit 210, it is conceivable that this will result in a reduction in the area for forming the transistors included in the pixel circuit 210.

[0117] In order to solve these problems, for example, the imaging device 1 of this embodiment can have a structure in which multiple pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged superimposed on the photodiode PD, and can have a structure in which connection wiring that interconnects the floating diffusions FD of each of the multiple pixels 541 to combine them into one, and connection wiring that interconnects the VSS contact regions 118 provided in each of the multiple pixels 541 to combine them into one, provided on the first substrate 100.

[0118] Here, when the second manufacturing method described above is used as a manufacturing method for providing, on the first substrate 100, the connection wiring that interconnects and combines the floating diffusions FD of the plurality of pixels 541 and the connection wiring that interconnects and combines the VSS contact regions 118 of the plurality of pixels 541, it is possible to manufacture the first substrate 100 and the second substrate 200 using an appropriate process depending on their respective configurations, thereby manufacturing a high-quality, high-performance imaging device. Furthermore, the connection wiring of the first substrate 100 and the second substrate 200 can be formed through a simple process. Specifically, when the second manufacturing method is used, electrodes connected to the floating diffusions FD and electrodes connected to the VSS contact regions 118 are provided on the surfaces of the first substrate 100 and the second substrate 200, which are the bonding interface between the first substrate 100 and the second substrate 200, respectively. Furthermore, it is preferable to make the electrodes formed on the surfaces of these two substrates large so that the electrodes formed on the surfaces of these two substrates will contact each other even if misalignment occurs between the electrodes formed on the surfaces of these two substrates when the first substrate 100 and the second substrate 200 are bonded together. In this case, it may be difficult to arrange the electrodes within the limited area of ​​each pixel provided in the imaging device 1.

[0119] To solve the problem of needing a large electrode at the bonding interface between the first substrate 100 and the second substrate 200, for example, the imaging device 1 of this embodiment can use the first manufacturing method described above as a manufacturing method in which multiple pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged so as to overlap the photodiode PD. This makes it easy to align the elements formed on the first substrate 100 and the second substrate 200, making it possible to manufacture an imaging device with high quality and high performance. Furthermore, it is possible to have a unique structure that is created by using this manufacturing method. That is, it has a structure in which the semiconductor layer 100S and wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and wiring layer 200T of the second substrate 200 are stacked in this order, in other words, a structure in which the first substrate 100 and the second substrate 200 are stacked face-to-back, and it also has through electrodes 120E, 121E that pass from the surface side of the semiconductor layer 200S of the second substrate 200, through the semiconductor layer 200S and the wiring layer 100T of the first substrate 100, and reach the surface of the semiconductor layer 100S of the first substrate 100.

[0120] In a structure in which connection wiring that interconnects and combines the floating diffusions FD of each of the multiple pixels 541 into one and connection wiring that interconnects and combines the VSS contact regions 118 of each of the multiple pixels 541 are provided on a first substrate 100, if this structure and a second substrate 200 are stacked using the first manufacturing method to form a pixel circuit 210 on the second substrate 200, there is a possibility that the effects of the heating process required to form the active elements provided in the pixel circuit 210 will extend to the connection wiring formed on the first substrate 100.

[0121] Therefore, in order to solve the problem that the connection wiring is affected by the heat treatment when forming the active elements, the imaging device 1 of this embodiment desirably uses a highly heat-resistant conductive material for the connection wiring that interconnects and combines the floating diffusions FD of each of the plurality of pixels 541 and for the connection wiring that interconnects and combines the VSS contact regions 118 of each of the plurality of pixels 541. Specifically, the highly heat-resistant conductive material can be a material with a higher melting point than at least a portion of the wiring material included in the wiring layer 200T of the second substrate 200.

[0122] In this way, for example, the imaging device 1 of this embodiment has: (1) a structure in which the first substrate 100 and the second substrate 200 are stacked face-to-back (specifically, a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are stacked in this order); (2) a structure in which the through electrodes 120E, 121E are provided from the front surface side of the semiconductor layer 200S of the second substrate 200, penetrating the semiconductor layer 200S and the wiring layer 100T of the first substrate 100, and reaching the front surface of the semiconductor layer 100S of the first substrate 100; and (3) a structure in which the floating diffusions FD provided in each of the plurality of pixels 541 are provided. By providing a structure in which the connection wiring that interconnects and combines the floating diffusions FD of the plurality of pixels 541 into one and the connection wiring that interconnects and combines the VSS contact regions 118 of each of the plurality of pixels 541 and the connection wiring that interconnects and combines the VSS contact regions 118 of each of the plurality of pixels 541 is formed from a highly heat-resistant conductive material, it is possible to provide the connection wiring that interconnects and combines the floating diffusions FD of the plurality of pixels 541 into one and the connection wiring that interconnects and combines the VSS contact regions 118 of each of the plurality of pixels 541 on the first substrate 100 without providing a large electrode at the interface between the first substrate 100 and the second substrate 200.

[0123] [Operation of imaging device 1] Next, the operation of the imaging device 1 will be described using FIGS. 14 and 15. FIGS. 14 and 15 are diagrams similar to FIG. 3, with arrows added to indicate the paths of each signal. FIG. 14 uses arrows to indicate the paths of input signals input to the imaging device 1 from the outside, as well as the paths of the power supply potential and the reference potential. FIG. 15 uses arrows to indicate the signal paths of pixel signals output from the imaging device 1 to the outside. For example, an input signal (e.g., a pixel clock and a synchronization signal) input to the imaging device 1 via the input unit 510A is transmitted to the row driver 520 of the third substrate 300, and a row drive signal is generated in the row driver 520. This row drive signal is sent to the second substrate 200 via the contact units 301 and 201. Furthermore, this row drive signal reaches each pixel shared unit 539 of the pixel array unit 540 via a row drive signal line 542 in the wiring layer 200T. Of the row drive signals that reach the pixel sharing unit 539 on the second substrate 200, the drive signals other than those for the transfer gate TG are input to the pixel circuit 210, driving each transistor included in the pixel circuit 210. The drive signal for the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 on the first substrate 100 via the through-electrodes TGV, driving the pixels 541A, 541B, 541C, and 541D (FIG. 14). In addition, a power supply potential and a reference potential supplied from the outside of the imaging device 1 to the input section 510A (input terminal 511) of the third substrate 300 are sent to the second substrate 200 via the contact sections 301 and 201, and are supplied to the pixel circuit 210 of each pixel sharing unit 539 via wiring in the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D on the first substrate 100 via the through-electrode 121E. Meanwhile, pixel signals photoelectrically converted in the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are sent to the pixel circuit 210 of the second substrate 200 for each pixel sharing unit 539 via the through-electrode 120E. Pixel signals based on these pixel signals are sent from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contact units 202 and 302. These pixel signals are processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300, and then output to the outside via the output unit 510B ( FIG. 15 ).

[0124] [effect] In this embodiment, the pixels 541A, 541B, 541C, and 541D (pixel shared unit 539) and the pixel circuit 210 are provided on different substrates (first substrate 100 and second substrate 200). This allows the areas of the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 to be larger than when the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 are formed on the same substrate. As a result, the amount of pixel signal obtained by photoelectric conversion can be increased and the transistor noise of the pixel circuit 210 can be reduced. This improves the signal-to-noise ratio of the pixel signal, allowing the imaging device 1 to output better pixel data (image information). Furthermore, this allows the imaging device 1 to be miniaturized (in other words, reduced pixel size and miniaturized). By reducing the pixel size, the imaging device 1 can increase the number of pixels per unit area and output high-quality images.

[0125] Furthermore, in the imaging device 1, the first substrate 100 and the second substrate 200 are electrically connected to each other by through-electrodes 120E, 121E provided in the insulating region 212. For example, the first substrate 100 and the second substrate 200 can be connected by bonding pad electrodes to each other or by through-wiring (e.g., TSV (Through Si Via)) that penetrates the semiconductor layer. Compared to these methods, providing the through-electrodes 120E, 121E in the insulating region 212 reduces the area required for connecting the first substrate 100 and the second substrate 200. This reduces the pixel size, enabling the imaging device 1 to be made more compact. Furthermore, further miniaturization of the area per pixel allows for higher resolution. When miniaturization of the chip size is not necessary, the area in which the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 are formed can be expanded. As a result, it is possible to increase the amount of pixel signals obtained by photoelectric conversion and reduce noise in the transistors provided in the pixel circuits 210. This improves the signal-to-noise ratio of the pixel signals, enabling the imaging device 1 to output better pixel data (image information).

[0126] Furthermore, in the imaging device 1, the pixel circuit 210, the column signal processing unit 550, and the image signal processing unit 560 are provided on different substrates (the second substrate 200 and the third substrate 300). This allows the area of ​​the pixel circuit 210 and the areas of the column signal processing unit 550 and the image signal processing unit 560 to be increased compared to when the pixel circuit 210, the column signal processing unit 550, and the image signal processing unit 560 are formed on the same substrate. This makes it possible to reduce noise generated in the column signal processing unit 550 and to install a more advanced image processing circuit in the image signal processing unit 560. This improves the signal-to-noise ratio of the pixel signals, allowing the imaging device 1 to output better pixel data (image information).

[0127] In the imaging device 1, the pixel array section 540 is provided on the first substrate 100 and the second substrate 200, and the column signal processing section 550 and the image signal processing section 560 are provided on the third substrate 300. Furthermore, contact sections 201, 202, 301, and 302 connecting the second substrate 200 and the third substrate 300 are formed above the pixel array section 540. Therefore, the contact sections 201, 202, 301, and 302 can be freely laid out without being interfered with by various wirings provided in the pixel array. This allows the contact sections 201, 202, 301, and 302 to be used for electrical connection between the second substrate 200 and the third substrate 300. Using the contact sections 201, 202, 301, and 302 increases the degree of freedom in the layout of the column signal processing section 550 and the image signal processing section 560, for example. This makes it possible to reduce noise generated in the column signal processing unit 550 and to install a more advanced image processing circuit in the image signal processing unit 560. Therefore, the signal-to-noise ratio of pixel signals is improved, and the imaging device 1 can output better pixel data (image information).

[0128] Furthermore, in the imaging device 1, the pixel separator 117 penetrates the semiconductor layer 100S. This makes it possible to suppress color mixing between the pixels 541A, 541B, 541C, and 541D even when the distance between adjacent pixels (pixels 541A, 541B, 541C, and 541D) decreases due to miniaturization of the area per pixel. This improves the signal-to-noise ratio of the pixel signal, enabling the imaging device 1 to output better pixel data (image information).

[0129] Furthermore, in the imaging device 1, a pixel circuit 210 is provided for each pixel shared unit 539. This allows for a larger formation area for the transistors (amplification transistor AMP, reset transistor RST, selection transistor SEL, FD conversion gain switching transistor FDG) that constitute the pixel circuit 210 compared to when a pixel circuit 210 is provided for each of the pixels 541A, 541B, 541C, and 541D. For example, by increasing the formation area for the amplification transistor AMP, it becomes possible to suppress noise. This improves the signal-to-noise ratio of the pixel signal, enabling the imaging device 1 to output better pixel data (image information).

[0130] Furthermore, in the imaging device 1, the pad section 120 electrically connecting the floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of the four pixels (pixels 541A, 541B, 541C, and 541D) is provided on the first substrate 100. This allows for a reduction in the number of through electrodes (through electrodes 120E) connecting the first substrate 100 and the second substrate 200 compared to when such pad sections 120 are provided on the second substrate 200. This makes it possible to reduce the insulating region 212 and ensure a sufficient area (semiconductor layer 200S) for forming the transistors constituting the pixel circuit 210. This reduces noise from the transistors included in the pixel circuit 210, improves the signal-to-noise ratio of the pixel signal, and enables the imaging device 1 to output better pixel data (image information). Furthermore, the reduced number of through electrodes allows for greater flexibility in layout. This also makes it possible to reduce, for example, parasitic capacitance.

[0131] Furthermore, in the imaging device 1, transistors such as the amplifier transistor AMP included in the pixel circuit 210 are configured with transistors having a three-dimensional structure. This allows the effective gate width to be increased while maintaining the footprint compared to when planar transistors are used. This allows for improved transistor performance (operating speed, RN, etc.) without hindering pixel miniaturization. Furthermore, the increased gate area also makes it possible to reduce RTS noise. This allows for more effective suppression of the effects of noise on images.

[0132] Furthermore, in the imaging device 1, the hole diameter of the connection portion (for example, connection portion 218V) provided in the wiring layer 200T of the second substrate 200 is different from the hole diameter of the through electrodes 120E, 121E, and TGV that reach the first substrate 100 from the second substrate 200. This makes it possible to improve the degree of freedom in layout.

[0133] Furthermore, in the imaging device 1, the pad section 120 is provided across the pixel separation section 117 and is in contact with multiple floating diffusions FD. The connection between each floating diffusion FD and the pad section 120 is three-dimensional. This allows for a larger contact area between each floating diffusion FD and the pad section 120 compared to when each floating diffusion FD and the pad section 120 are connected only on a surface parallel to the light incident surface of the imaging device 1. Furthermore, even when the pixel 541 is miniaturized, a reduction in the connection area between the pad section 120 and the floating diffusion FD can be suppressed. Therefore, an increase in the resistance component of the signal charge transfer path can be suppressed, thereby reducing constraints on miniaturizing the pixel 541 and increasing design freedom.

[0134] Furthermore, in the imaging device 1, the portion of the pixel separator 117 on the semiconductor layer 200S side sandwiched between two adjacent floating diffusions FD is located at a position recessed from the surface of the semiconductor layer 100S on the semiconductor layer 200S side. The side of the floating diffusion FD contacts the pad section 120. This allows for a larger contact area between each floating diffusion FD and the pad section 120 compared to when each floating diffusion FD and the pad section 120 are connected only on a surface parallel to the light incident surface of the imaging device 1. Furthermore, even when the pixel 541 is miniaturized, a reduction in the connection area between the pad section 120 and the floating diffusion FD can be suppressed. Therefore, an increase in the resistance component of the signal charge transfer path can be suppressed, which reduces constraints on miniaturizing the pixel 541 and allows for greater design freedom.

[0135] <2. Modifications> Modifications of the imaging device 1 according to the above embodiment will be described below. In the following modifications, the same components as those in the above embodiment will be denoted by the same reference numerals.

[0136] [Variation A] In the above-described embodiment, the pad section 120 may be large enough to cover the four floating diffusions FD that share the pad section 120 in plan view, as shown in, for example, Figures 16 and 17. In this case, when the pad section 120 is formed on the floating diffusion FD during the manufacturing process, poor contact between the floating diffusion FD and the pad section 120 can be suppressed. As a result, the contact area between the floating diffusion FD and the pad section 120 can be reliably increased.

[0137] 17, the portion of the pad portion 120 directly above the transfer transistor TR (transfer gate TG) protrudes toward the second substrate 200. Therefore, it is not easy to make the upper surface of the interlayer insulating film 123 flat. Therefore, for example, as shown in FIG. 18, the pad portion 120 may be formed so that its height does not exceed the upper surface of the transfer transistor TR (transfer gate TG).

[0138] [Variation B] In the above-described embodiment, the side surface of the floating diffusion FD may have a tapered shape, for example, as shown in FIGS. 19 and 20 . In this case, the pad section 120 contacts the surface of the tapered portion of the side surface of the floating diffusion FD. FIG. 19 illustrates a case in which a surface parallel to the light incident surface of the imaging device 1 exists on a part of the upper surface of the floating diffusion FD. FIG. 20 illustrates a case in which no surface parallel to the light incident surface of the imaging device 1 remains (exists) on the upper surface of the floating diffusion FD. This makes it possible to increase the contact area between each floating diffusion FD and the pad section 120 compared to a case in which each floating diffusion FD and the pad section 120 are connected only by a surface parallel to the light incident surface of the imaging device 1. Furthermore, even when the pixel 541 is miniaturized, it is possible to prevent a reduction in the connection area between the pad section 120 and the floating diffusion FD. Therefore, an increase in the resistance component of the transfer path of the signal charge can be suppressed, which reduces restrictions on miniaturizing the pixel 541 and allows for greater freedom in design.

[0139] [Variation C] In the above-described embodiment, the side surface of the floating diffusion FD may have a concave shape, as shown in, for example, FIGS. 21 and 22. In this case, the pad section 120 contacts the surface of the concave portion of the side surface of the floating diffusion FD. FIG. 21 illustrates a case in which a surface parallel to the light incident surface of the imaging device 1 exists on a part of the upper surface of the floating diffusion FD. FIG. 22 illustrates a case in which no surface parallel to the light incident surface of the imaging device 1 remains (exists) on the upper surface of the floating diffusion FD. This makes it possible to increase the contact area between each floating diffusion FD and the pad section 120 compared to a case in which each floating diffusion FD and the pad section 120 are connected only by a surface parallel to the light incident surface of the imaging device 1. Furthermore, even when the pixel 541 is miniaturized, it is possible to prevent a reduction in the connection area between the pad section 120 and the floating diffusion FD. Therefore, an increase in the resistance component of the transfer path of the signal charge can be suppressed, which reduces restrictions on miniaturizing the pixel 541 and allows for greater freedom in design.

[0140] [Variation D] In the above-described embodiment, the side surface of the floating diffusion FD may have a convex shape, as shown in, for example, FIGS. 23 and 24. In this case, the pad section 120 contacts the surface of the convex portion of the side surface of the floating diffusion FD. FIG. 23 illustrates a case in which a surface parallel to the light incident surface of the imaging device 1 exists on a part of the upper surface of the floating diffusion FD. FIG. 24 illustrates a case in which no surface parallel to the light incident surface of the imaging device 1 remains (exists) on the upper surface of the floating diffusion FD. This makes it possible to increase the contact area between each floating diffusion FD and the pad section 120 compared to a case in which each floating diffusion FD and the pad section 120 are connected only by a surface parallel to the light incident surface of the imaging device 1. Furthermore, even when the pixel 541 is miniaturized, it is possible to prevent a reduction in the connection area between the pad section 120 and the floating diffusion FD. Therefore, an increase in the resistance component of the transfer path of the signal charge can be suppressed, which reduces restrictions on miniaturizing the pixel 541 and allows for greater freedom in design.

[0141] [Variation E] 25, for example, the lower end of the through electrode 120E electrically connecting the pad section 120 and the pixel circuit 210 may be embedded in the pad section 120. In this case, it is possible to reduce the contact resistance between the through electrode 120E and the pad section 120. As a result, it is possible to suppress an increase in the resistance component of the transfer path of the signal charge, thereby reducing restrictions on miniaturizing the pixel 541 and increasing the degree of freedom in design.

[0142] [Variation F] 26, the passivation film 122 may be omitted and the pad portion 120 may be in direct contact with the sidewall SW. In this case, it is preferable that the pad portion 120 is formed so that its height does not exceed the upper surface of the transfer transistor TR (transfer gate TG). In this case, it is possible to prevent the pad portion 120 from contacting the transfer gate TG.

[0143] [Variation G] In the above-described embodiment, the pixel separator 117 may have a configuration other than the FTI structure. For example, the pixel separator 117 does not have to be provided so as to completely penetrate the semiconductor layer 100S, and may have a so-called DTI (Deep Trench Isolation) structure.

[0144] [Variation H] In the above-described embodiment and its modified examples, the floating diffusion FD has a rectangular shape in a plan view, and the transfer transistor TR (transfer gate TG) is provided around the floating diffusion FD. However, in the above-described embodiment and its modified examples, the floating diffusion FD may have a triangular shape in a plan view, and the transfer transistor TR (transfer gate TG) may be provided around the floating diffusion FD, as shown in, for example, Figures 27, 28, and 29.

[0145] 27 illustrates a case where the pad portion 120 has a rectangular shape in a plan view and is in contact with a portion of each of the floating diffusions FD1, FD2, FD3, and FD4. FIG. 28 illustrates a case where the pad portion 120 has a rectangular shape in a plan view and covers all of the floating diffusions FD1, FD2, FD3, and FD4 in a plan view. FIG. 29 illustrates a case where the pad portion 120 has a circular shape in a plan view and is in contact with a portion of the sidewall SW. The shape of the pad portion 120 is not limited to the above, and the pad portion 120 may have, for example, an elliptical, triangular, rectangular, or polygonal shape in a plan view.

[0146] [Variation I] In the above-described embodiment and its modified examples, the above-described three-dimensional connection is realized by having a portion of the side surface of the floating diffusion FD (the side surface closer to the pixel separation section 117) in the depth direction contact a portion of the pad section 120. However, in the above-described embodiment and its modified examples, the above-described three-dimensional connection may also be realized by having the entire side surface of the floating diffusion FD (the side surface closer to the pixel separation section 117) in the depth direction contact a portion of the pad section 120. In this case, for example, the upper surface of the upper end portion of the pixel separation section 117 may be formed at a depth approximately the same as or deeper than the bottom surface of each floating diffusion FD.

[0147] For example, as shown in FIG. 30 , the semiconductor layer 100S is recessed in the thickness direction (perpendicular to the main surface of the first substrate 100), and the bottom surface of the recess forms the upper surface of the upper end of the pixel separation section 117. In this case, the upper surface of the upper end of the pixel separation section 117 may be formed to a depth similar to that of the bottom surface of each floating diffusion FD, and a portion of the pad section 120 may be embedded in the recess. In this case, the entire side surface of the floating diffusion FD that is closer to the pixel separation section 117 contacts the pad section 120. This makes it possible to further increase the contact area between each floating diffusion FD and the pad section 120. Furthermore, even when the pixel 541 is miniaturized, it is possible to further suppress a reduction in the connection area between the pad section 120 and the floating diffusion FD. Therefore, it is possible to suppress an increase in the resistance component of the signal charge transfer path, thereby reducing constraints on miniaturizing the pixel 541 and increasing design freedom.

[0148] <14. Application Examples> FIG. 31 shows an example of a schematic configuration of an imaging system 7 including the imaging device 1 according to the above embodiment and its modifications.

[0149] The imaging system 7 is, for example, an electronic device such as an imaging device such as a digital still camera or a video camera, or a mobile terminal device such as a smartphone or a tablet terminal. The imaging system 7 includes, for example, the imaging device 1 according to the above-described embodiment and its modifications, a DSP circuit 243, a frame memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248. In the imaging system 7, the imaging device 1 according to the above-described embodiment and its modifications, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, the operation unit 247, and the power supply unit 248 are connected to each other via a bus line 249.

[0150] The imaging device 1 according to the above embodiment and its modified examples outputs image data corresponding to incident light. The DSP circuit 243 is a signal processing circuit that processes the signal (image data) output from the imaging device 1 according to the above embodiment and its modified examples. The frame memory 244 temporarily stores the image data processed by the DSP circuit 243 on a frame-by-frame basis. The display unit 245 is formed of a panel display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays moving or still images captured by the imaging device 1 according to the above embodiment and its modified examples. The storage unit 246 records image data of moving or still images captured by the imaging device 1 according to the above embodiment and its modified examples in a recording medium such as a semiconductor memory or a hard disk. The operation unit 247 issues operation commands for various functions of the imaging system 7 in accordance with user operations. The power supply unit 248 appropriately supplies various power sources to these power sources as operating power for the imaging device 1, DSP circuit 243, frame memory 244, display unit 245, storage unit 246, and operation unit 247 according to the above embodiment and its modified examples.

[0151] Next, the imaging procedure in the imaging system 7 will be described.

[0152] 32 shows an example of a flowchart of the imaging operation in the imaging system 7. The user operates the operation unit 247 to instruct the start of imaging (step S101). Then, the operation unit 247 transmits an imaging command to the imaging device 1 (step S102). Upon receiving the imaging command, the imaging device 1 performs imaging in a predetermined imaging method (step S103).

[0153] The imaging device 1 outputs image data obtained by imaging to the DSP circuit 243. Here, the image data refers to data for all pixels of pixel signals generated based on the charges temporarily stored in the floating diffusion FD. The DSP circuit 243 performs predetermined signal processing (e.g., noise reduction processing) based on the image data input from the imaging device 1 (step S104). The DSP circuit 243 stores the image data that has undergone the predetermined signal processing in the frame memory 244, and the frame memory 244 stores the image data in the storage unit 246 (step S105). In this manner, imaging is performed in the imaging system 7.

[0154] In this application example, the imaging device 1 according to the above-described embodiment and its modification example is applied to an imaging system 7. This allows the imaging device 1 to be made smaller or have higher resolution, and therefore a small or high-resolution imaging system 7 can be provided.

[0155] <10. Application Examples> [Application example 1] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0156] FIG. 33 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0157] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 33, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0158] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0159] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0160] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0161] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or may be invisible light such as infrared light.

[0162] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0163] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0164] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0165] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0166] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 33, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0167] FIG. 34 is a diagram showing an example of the installation position of the imaging unit 12031.

[0168] In FIG. 34, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0169] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0170] 34 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0171] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0172] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on driver operation.

[0173] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0174] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0175] An example of a mobile object control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the imaging device 1 according to the above-described embodiment and its modified example can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain a high-resolution captured image with little noise, thereby enabling high-precision control using the captured image in the mobile object control system.

[0176] [Application example 2] FIG. 35 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0177] 35 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment instrument 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0178] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0179] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens towards an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0180] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0181] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0182] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0183] The light source device 11203 is configured from a light source such as an LED (Light Emitting Diode), and supplies irradiation light to the endoscope 11100 when photographing an operation site or the like.

[0184] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiating light, magnification, focal length, etc.) of the endoscope 11100.

[0185] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0186] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical site can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 11203. In this case, it is also possible to capture images corresponding to each RGB in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0187] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0188] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto body tissues and observing the fluorescence from the tissues (autofluorescence observation), or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0189] FIG. 36 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0190] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so that they can communicate with each other.

[0191] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0192] The imaging unit 11402 is configured with an imaging element. The imaging element constituting the imaging unit 11402 may be one (a so-called single-chip type) or multiple (a so-called multi-chip type). When the imaging unit 11402 is configured with a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured with a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. 3D display enables the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured with a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0193] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0194] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0195] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0196] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0197] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0198] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0199] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0200] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0201] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data sent from the camera head 11102 .

[0202] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0203] Furthermore, the control unit 11413 causes the display device 11202 to display a captured image showing the surgical site, etc., based on the image signal that has been image processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0204] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0205] In the illustrated example, communication is performed by wire using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0206] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. Of the configurations described above, the technology according to the present disclosure can be suitably applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100. By applying the technology according to the present disclosure to the imaging unit 11402, it is possible to reduce the size or increase the resolution of the imaging unit 11402, thereby providing a compact or high-resolution endoscope 11100.

[0207] The present disclosure has been described above by way of embodiments, their modifications, application examples, and applied examples. However, the present disclosure is not limited to the above-described embodiments, etc., and various modifications are possible. Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than those described in this specification.

[0208] Furthermore, for example, the present disclosure can be configured as follows. (1) a first semiconductor layer for each pixel, the first semiconductor layer having a photoelectric conversion unit and a charge accumulation unit for accumulating signal charges generated in the photoelectric conversion unit; a pixel separating section provided in the first semiconductor layer and separating the plurality of pixels from each other; a pixel transistor for reading out the signal charge of the charge accumulation portion; and a second semiconductor layer stacked on the first semiconductor layer; a shared connection portion provided between the second semiconductor layer and the first semiconductor layer, across the pixel separation portion, and in contact with the plurality of charge accumulation portions; Equipped with The connection between each of the charge storage sections and the shared connection section is a three-dimensional connection. Solid-state imaging device. (2) The connection between each of the charge accumulation sections and the shared connection section is not limited to a connection on a plane parallel to the light incident surface of the solid-state imaging device, but includes a connection on a plane or a curved surface intersecting the light incident surface. The solid-state imaging device according to (1). (3) a portion of the pixel separating section on the second semiconductor layer side that is sandwiched between two adjacent charge accumulation sections is provided at a position recessed from a surface of the first semiconductor layer on the second semiconductor layer side, A side surface of the charge storage portion is in contact with the shared connection portion. A solid-state imaging device according to (1) or (2). (4) The entire side surface of the charge accumulation section that is closer to the pixel separation section is in contact with the shared connection section. (3) A solid-state imaging device according to (3). (5) The side surface of the charge storage portion has a tapered shape, a concave shape, or a convex shape. (3) A solid-state imaging device according to (3). (6) a first substrate including the first semiconductor layer and a first wiring layer in which the shared connection portion is provided; a second substrate including the second semiconductor layer and a second wiring layer facing the first substrate with the second semiconductor layer therebetween; a third substrate facing the first substrate with the second substrate therebetween and including a circuit electrically connected to the second semiconductor layer; The solid-state imaging device according to any one of (1) to (5). (7) The pixel transistor is electrically connected to the shared connection portion, and the pixel transistor is further provided with a through electrode provided in the first substrate and the second substrate. (6) A solid-state imaging device according to (6). (8) The shared connection portion is large enough to cover the plurality of charge accumulation portions that share the shared connection portion in a plan view. The solid-state imaging device according to any one of (1) to (7). (9) The shared connection includes polysilicon. The solid-state imaging device according to any one of (1) to (8).

[0209] In a solid-state imaging device according to an embodiment of the present disclosure, a shared connection section is provided across a pixel separation section and is in contact with a plurality of charge accumulation sections. The connection between each charge accumulation section and the shared connection section is three-dimensional. This allows for a larger contact area between each charge accumulation section and the shared connection section compared to when each charge accumulation section and the shared connection section are connected in a plane. Furthermore, even when pixels are miniaturized, a reduction in the connection area between the shared connection section and the charge accumulation section can be suppressed. Therefore, an increase in the resistance component of the signal charge transfer path can be suppressed, thereby reducing constraints on pixel miniaturization and increasing design freedom.

[0210] This application claims priority based on Japanese Patent Application No. 2020-217951, filed on December 25, 2020, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0211] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. a first semiconductor layer for each pixel, the first semiconductor layer having a photoelectric conversion unit and a charge accumulation unit for accumulating signal charges generated in the photoelectric conversion unit; a pixel separating section provided in the first semiconductor layer and separating the plurality of pixels from each other; a pixel transistor for reading out the signal charge of the charge accumulation portion; and a second semiconductor layer stacked on the first semiconductor layer; a shared connection portion provided between the second semiconductor layer and the first semiconductor layer, across the pixel separation portion, and in contact with the plurality of charge accumulation portions; Equipped with the connection between each of the charge storage units and the shared connection unit is a three-dimensional connection; a portion of the pixel separating section on the second semiconductor layer side that is sandwiched between two adjacent charge accumulation sections is provided at a position recessed from a surface of the first semiconductor layer on the second semiconductor layer side, The entire side surface of the charge accumulation section that is closer to the pixel separation section is in contact with the shared connection section. Solid-state imaging device.

2. The side surface of the charge storage portion has a tapered shape, a concave shape, or a convex shape. The solid-state imaging device according to claim 1 .

3. a first substrate including the first semiconductor layer and a first wiring layer provided with the shared connection portion; a second substrate including the second semiconductor layer and a second wiring layer facing the first substrate with the second semiconductor layer therebetween; a third substrate facing the first substrate with the second substrate therebetween and including a circuit electrically connected to the second semiconductor layer; The solid-state imaging device according to claim 1 .

4. The pixel transistor is electrically connected to the shared connection portion, and the pixel transistor is further provided with a through electrode provided in the first substrate and the second substrate. The solid-state imaging device according to claim 3 .

5. The shared connection portion is large enough to cover the plurality of charge accumulation portions that share the shared connection portion in a plan view. The solid-state imaging device according to claim 1 .

6. The shared connection includes polysilicon. The solid-state imaging device according to claim 1 .

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