Semiconductor chip, semiconductor device and method of forming same

Abstract

The present invention relates to a semiconductor chip, a semiconductor device and a method for forming the same, the semiconductor chip comprises a base including a top surface and a bottom surface, and a plurality of pairs of signal via groups independent of each other, each of the signal via groups is arranged at intervals in the base, the two signal via groups of each pair of the signal via groups are distributed symmetrically with respect to an axis on the top surface of the base, and are respectively distributed in a first region and a second region on both sides of the axis, the axis is parallel to a first direction or a second direction, each of the signal via groups includes a plurality of signal vias arranged in a polygonal shape, any two of the signal vias of each of the signal via groups are electrically insulated, and each of the signal vias penetrates the base along a third direction.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed on September 7, 2022, bearing application number 202211090956.6, and entitled "Semiconductor chip, semiconductor device and method for forming same," the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to the field of semiconductor manufacturing, and more particularly to semiconductor chips, semiconductor devices and methods of forming the same. [Background technology]

[0003] With the development of integrated circuit technology, the manufacturing process of semiconductor devices has made great strides. However, in recent years, the development of 2D semiconductor technology has faced various challenges, including physical limitations, limitations of existing lithography technology, and limitations in electron storage density. Against this background, 3D semiconductor devices have emerged to overcome the difficulties of 2D semiconductor devices and further reduce the manufacturing cost per unit memory cell.

[0004] Currently, semiconductor devices having a 3D stacked chip structure can be formed by stacking multiple chips using a bonding process. However, the current process of stacking multiple chips is relatively complicated, for example, it requires the use of multiple mask sets or the provision of multiple contact plugs within the chip, which increases the manufacturing cost and difficulty of the semiconductor device and is also disadvantageous in improving the yield of the semiconductor device.

[0005] Therefore, how to simplify the manufacturing process of semiconductor devices having a structure in which multiple chips are stacked, reduce the manufacturing cost of semiconductor devices, and improve the yield of semiconductor devices has become an urgent issue to be solved. Summary of the Invention [Problem to be solved by the invention]

[0006] The semiconductor chip, semiconductor device, and method of forming the same according to some embodiments of the present invention simplify the manufacturing process of a semiconductor device having a structure in which multiple chips are stacked, reduce the manufacturing cost of the semiconductor device, and improve the yield of the semiconductor device. [Means for solving the problem]

[0007] Based on this, in one aspect, the present invention provides a semiconductor chip, the semiconductor chip comprising: a base including a top surface and a bottom surface opposite the top surface; and a plurality of pairs of signal via groups that are independent of each other, each of the signal via groups arranged at intervals within the base, the two signal via groups of each pair being distributed symmetrically with respect to an axis on the top surface of the base, and being distributed in a first region and a second region on either side of the axis, respectively, the axis being parallel to a first direction or a second direction, each of the signal via groups including a plurality of signal vias arranged in a polygonal shape, any two of the signal vias in each of the signal via groups being electrically isolated, and each of the signal vias penetrating the base along a third direction, wherein the first direction and the second direction are perpendicular to each other and both are parallel to the top surface, and the third direction is a direction perpendicular to the top surface of the base.

[0008] In some embodiments, the semiconductor chip comprises: The base includes a plurality of top metal wiring structures, all of which are disposed on the top surface of the base, and the top metal wiring structures are electrically connected to the plurality of signal via groups in one-to-one correspondence, and each of the top metal wiring structures includes a plurality of conductive paths electrically connected to the plurality of signal vias in the corresponding signal via group in one-to-one correspondence.

[0009] In some embodiments, the top metallization structure comprises: a first conductive layer located on a top surface of the base, the first conductive layer including a plurality of first conductive elements arranged at intervals, the plurality of first conductive elements being arranged in the polygonal shape, and the plurality of first conductive elements being electrically connected in one-to-one correspondence with the plurality of signal vias in the corresponding signal via group; a second conductive layer located on the first conductive layer, the second conductive layer including a plurality of second conductive elements arranged at intervals and corresponding one-to-one to a plurality of the first conductive elements, the plurality of second conductive elements being arranged in the polygonal shape, and each of the second conductive elements being provided so as to partially overlap the corresponding first conductive element; and a plurality of connection elements each corresponding one-to-one to the plurality of first conductive elements and the plurality of second conductive elements, each of the connection elements being used to electrically connect the corresponding first conductive element and the corresponding second conductive element to form the conductive path.

[0010] In some embodiments, the first conductive element includes a first end and a second end that are oppositely distributed along the extension direction thereof, and the second conductive element includes a third end and a fourth end that are oppositely distributed along the extension direction thereof; the first ends of the plurality of first conductive elements are electrically connected to the plurality of signal vias in one-to-one correspondence; For the first conductive element and the second conductive element that correspond to each other, one end of the connection element is electrically connected to the third end of the second conductive element, and the other end of the connection element is electrically connected to the second end of the first conductive element.

[0011] In some embodiments, the semiconductor chip comprises: The semiconductor device includes a plurality of internal circuits that correspond one-to-one to the plurality of top metal wiring structures, and each of the internal circuits is electrically connected to one conductive path in the corresponding top metal wiring structure.

[0012] In some embodiments, the semiconductor chip comprises: The semiconductor device includes a plurality of lead wires corresponding one-to-one to the plurality of internal circuits, and one end of each lead wire is electrically connected to one of the internal circuits, and the other end is electrically connected to only one of the first conductive elements in the top layer metal wiring structure.

[0013] In some embodiments, each of the signal via groups includes four of the signal vias, and the four signal vias are arranged in a square or diamond shape.

[0014] In another aspect, the present invention further provides a semiconductor device, the semiconductor device comprising: A substrate; a stacked structure disposed on the substrate, the stacked structure including N unit structures sequentially stacked and electrically connected along the third direction, each unit structure including four semiconductor chips according to claim 1, where N is a positive integer; the four semiconductor chips in the unit structure are stacked sequentially along a third direction, a first semiconductor chip located in the bottom layer and a second semiconductor chip located thereon are stacked face to face, the second semiconductor chip and a third semiconductor chip located thereon are stacked back to back, and the third semiconductor chip and a fourth semiconductor chip located thereon are stacked face to face; the axes of any two adjacent semiconductor chips in the stacked structure are aligned, and the first region of one semiconductor chip is aligned with the second region of the other semiconductor chip; Here, face-to-face means that the top surfaces of two adjacent semiconductor chips face each other, and back-to-back means that the bottom surfaces of two adjacent semiconductor chips face each other.

[0015] In some embodiments, the semiconductor device comprises: The semiconductor device includes a plurality of pairs of signal transmission link groups, each of which corresponds one-to-one with a plurality of pairs of signal via groups in each of the semiconductor chips, and the signal transmission link group includes a plurality of signal transmission links, and the plurality of signal transmission links in the signal transmission link group are independent of each other and all extend spirally along the third direction, and the plurality of signal transmission links in each of the signal transmission link groups correspond one-to-one with the plurality of signal vias in the corresponding signal via group in each of the semiconductor chips, and each of the signal transmission links includes one corresponding signal via in each of the semiconductor chips.

[0016] In some embodiments, the semiconductor device comprises: The semiconductor device includes a plurality of pairs of bonding pillar groups, the bonding pillar groups being located only between the semiconductor chips stacked face-to-face and corresponding one-to-one to the plurality of pairs of signal via groups of the two semiconductor chips stacked face-to-face, and being used to realize signaling between the semiconductor chips stacked face-to-face, each of the bonding pillar groups including a plurality of the bonding pillars, each of which corresponds one-to-one to the plurality of signal vias of the two semiconductor chips stacked face-to-face, a plurality of pairs of signal transmission link groups corresponding one-to-one to the plurality of pairs of bonding pillar groups between each of the two semiconductor chips stacked face-to-face, a plurality of the signal transmission links in each of the signal transmission link groups corresponding one-to-one to the plurality of bonding pillars of the plurality of pairs of bonding pillar groups, and each of the signal transmission links including one corresponding bonding pillar between the two semiconductor chips stacked face-to-face.

[0017] In some embodiments, in two semiconductor chips stacked back to back, the multiple signal vias of one of the semiconductor chips correspond one-to-one to the multiple signal vias of the other semiconductor chip and are electrically connected by direct contact.

[0018] In some embodiments, each of the semiconductor chips comprises a plurality of top metal wiring structures, all of which are disposed on the top surface of the base, the plurality of top metal wiring structures being electrically connected to the plurality of signal via groups in one-to-one correspondence, each of the top metal wiring structures including a plurality of conductive paths electrically connected to the plurality of signal vias in the corresponding signal via group in one-to-one correspondence, and each of the signal transmission links including one corresponding signal via in each of the semiconductor chips and one corresponding conductive path; the top metal wiring structure includes a first conductive layer, a second conductive layer, and a plurality of connection elements, the first conductive layer being located on the top surface of the base, the first conductive layer including a plurality of first conductive elements arranged at intervals, the plurality of first conductive elements being arranged in the polygonal shape, the plurality of first conductive elements being electrically connected in one-to-one correspondence with the plurality of signal vias in the corresponding signal via groups; the second conductive layer being located on the first conductive layer, the second conductive layer including a plurality of second conductive elements arranged at intervals and in one-to-one correspondence with the plurality of first conductive elements, the plurality of second conductive elements being arranged in the polygonal shape, each second conductive element being partially overlapped with its corresponding first conductive element; the plurality of connection elements being in one-to-one correspondence with the plurality of first conductive elements and the plurality of second conductive elements, each connection element being used to electrically connect the corresponding first conductive element and the second conductive element to form the conductive path; The first conductive element includes a first end and a second end distributed opposite each other along its extension direction, and the second conductive element includes a third end and a fourth end distributed opposite each other along its extension direction, the first ends of the plurality of first conductive elements are electrically connected to the plurality of signal vias in one-to-one correspondence, and for the corresponding first conductive elements and second conductive elements, one end of the connection element is electrically connected to the third end of the second conductive element, and the other end of the connection element is electrically connected to the second end of the first conductive element.

[0019] In some embodiments, for the two semiconductor chips stacked face-to-face, each of the multiple pairs of bonding pillar groups corresponds one-to-one to multiple top layer metal wiring structures of the two semiconductor chips, and one end of each bonding pillar is electrically connected to the fourth end of a corresponding one of the second conductive elements in one of the semiconductor chips, and the other end of the bonding pillar is electrically connected to the fourth end of a corresponding one of the second conductive elements in another one of the semiconductor chips.

[0020] In some embodiments, each of the semiconductor chips further includes a plurality of internal circuits, each of which corresponds one-to-one with a plurality of the top metal wiring structures, and each of the internal circuits is electrically connected to one conductive path in the corresponding top metal wiring structure; and a plurality of lead wires corresponding one-to-one to the plurality of internal circuits, wherein one end of each of the lead wires is electrically connected to one of the internal circuits and the other end is electrically connected to only one of the first conductive elements in the corresponding top layer metal wiring structure.

[0021] In some embodiments, for each of the unit structures, one of the signal transmission links is electrically connected to only one of the leads of one of the semiconductor chips.

[0022] In some embodiments, the semiconductor device comprises: an interface circuit disposed within the substrate and electrically connected to the plurality of pairs of signal transmission link groups, the interface circuit being used to transmit a plurality of control signals to the signal transmission link groups, each of which corresponds one-to-one with a plurality of the signal transmission links within the signal transmission link groups, and each of the control signals being drawn from only one of the lead wires within one of the semiconductor chips within each of the unit structures; For each pair of signal via groups in one of the semiconductor chips, the interface circuit outputs a first control signal to the lead wire electrically connected to one of the signal vias in one of the signal via groups via one corresponding signal transmission link, and transmits a second control signal different from the first control signal to the lead wire electrically connected to one of the signal vias in another of the signal via groups via another corresponding signal transmission link.

[0023] In another aspect, the present invention further provides a method of forming a semiconductor device, said method comprising: Providing a substrate; forming a semiconductor chip, the semiconductor chip including: a base; and a plurality of pairs of signal via groups independent of each other; the base including a top surface and a bottom surface opposite the top surface; each of the signal via groups being arranged at intervals within the base; the two signal via groups of each pair being distributed symmetrically with respect to an axis on the top surface of the base, and being distributed in a first region and a second region on both sides of the axis, respectively; the axis being parallel to a first direction or a second direction; each of the signal via groups including a plurality of signal vias arranged in a polygonal shape; any two of the signal vias in each of the signal via groups being electrically isolated; and each of the signal vias penetrating the base along a third direction, wherein the first direction and the second direction are perpendicular to each other and both are parallel to the top surface; and the third direction is a direction perpendicular to the top surface of the base; forming a stacked structure on the substrate based on the plurality of semiconductor chips, the stacked structure including N unit structures stacked sequentially along the third direction and electrically connected, each unit structure including four of the semiconductor chips, the four semiconductor chips in the unit structure being stacked sequentially along the third direction, a first semiconductor chip located at the bottom layer and a second semiconductor chip located thereon are stacked face to face, the second semiconductor chip and a third semiconductor chip located thereon are stacked back to back, and the third semiconductor chip and a fourth semiconductor chip located thereon are stacked face to face, and N is a positive integer; the axes of any two adjacent semiconductor chips in the stacked structure are aligned, and the first region of one semiconductor chip is aligned with the second region of the other semiconductor chip; Here, face-to-face means that the top surfaces of two adjacent semiconductor chips face each other, and back-to-back means that the bottom surfaces of two adjacent semiconductor chips face each other.

[0024] In some embodiments, forming the semiconductor chip comprises: forming a base, the base defining the first region and the second region on opposite sides of the axis; forming the signal via group penetrating the base along the third direction in the first region and the second region; forming a plurality of top layer metal wiring structures on the top surface of the base, the plurality of top layer metal wiring structures being electrically connected in one-to-one correspondence with the plurality of signal via groups, and each of the top layer metal wiring structures including a plurality of conductive paths being electrically connected in one-to-one correspondence with the plurality of signal vias in the corresponding signal via group.

[0025] In some embodiments, forming a top metallization structure on the top surface of the base comprises: forming a first conductive layer on the top surface of the base, the first conductive layer including a plurality of first conductive elements arranged at intervals, the plurality of first conductive elements being arranged in the polygonal shape, the first conductive elements including first end portions and second end portions oppositely distributed along the extending direction thereof, the first end portions of the plurality of first conductive elements being electrically connected in one-to-one correspondence with the plurality of signal vias in the corresponding signal via group; forming a second conductive layer on the first conductive layer, the second conductive layer including a plurality of second conductive elements arranged at intervals and corresponding one-to-one to a plurality of the first conductive elements, the plurality of second conductive elements being arranged in the polygonal shape, the second conductive elements including third and fourth ends distributed opposite to each other along an extension direction thereof, and each of the second conductive elements being arranged to partially overlap the corresponding first conductive element; forming a connection element between the first conductive layer and the second conductive layer, wherein for each of the first conductive element and the second conductive element corresponding to each other, one end of the connection element is electrically connected to the third end of the second conductive element and the other end of the connection element is electrically connected to the second end of the first conductive element, thereby forming the conductive path.

[0026] In some embodiments, forming a stacked structure on the substrate based on the plurality of semiconductor chips includes: providing four of said semiconductor chips; disposing a first semiconductor chip on the substrate; stacking a second semiconductor chip face-to-face on the first semiconductor chip; stacking a third semiconductor chip back-to-back on the second semiconductor chip; stacking a fourth semiconductor chip face-to-face on the third semiconductor chip to form the unit structure including the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip; and repeatedly performing the above process on the formed unit structure to sequentially form N unit structures stacked along the third direction, Here, the axes of any two adjacent semiconductor chips in the stacked structure are aligned, and the first region of one semiconductor chip is aligned with the second region of the other semiconductor chip.

[0027] In some embodiments, stacking the second semiconductor chip face-to-face on the first semiconductor chip includes: forming a bonding pillar group on the top metal wiring structure of the first semiconductor chip, the bonding pillar group including a plurality of the bonding pillars, a lower end of the bonding pillar being bonded to the fourth end of one of the second conductive elements in the first semiconductor chip; The upper end of the bonding pillar is bonded to the top metal wiring structure of the second semiconductor chip, and the upper end of the bonding pillar is bonded to the fourth end of one of the second conductive elements in the second semiconductor chip.

[0028] In some embodiments, stacking a third semiconductor chip back-to-back on the second semiconductor chip includes: The method includes directly contacting or electrically connecting a plurality of the signal vias located in the second semiconductor chip with a corresponding plurality of the signal vias located in the third semiconductor chip.

[0029] In some embodiments, the semiconductor chip further comprises a plurality of internal circuits corresponding one-to-one to the plurality of top metal wiring structures, and the method for forming the semiconductor device further comprises: The method further includes forming a lead between the internal circuit and the corresponding top metal wiring structure, so that each of the internal circuits is electrically connected to one conductive path in the corresponding top metal wiring structure.

[0030] In some embodiments, the method further comprises: forming an interface circuit within the substrate; electrically connecting any two adjacent semiconductor chips in the stacked structure to form a plurality of pairs of signal transmission link groups corresponding one-to-one to the plurality of pairs of signal via groups of each of the semiconductor chips, each of the signal transmission link groups including a plurality of signal transmission links, each of the signal transmission links including one corresponding signal via in each of the semiconductor chips, one corresponding conductive path in each of the semiconductor chips, and one corresponding bonding pillar between two semiconductor chips stacked face-to-face; The present invention further includes electrically connecting the interface circuit to a plurality of pairs of signal via groups in the semiconductor chip located at the bottom layer of the stacked structure, and electrically connecting the interface circuit to a plurality of pairs of the signal transmission link groups to transmit a plurality of control signals to the signal transmission link groups, each of which corresponds one-to-one with a plurality of the signal transmission links in the signal transmission link groups, wherein each of the control signals is drawn to one corresponding internal circuit via only one of the lead wires in one of the semiconductor chips in each of the unit structures, and for each pair of the signal via groups in one of the semiconductor chips, the interface circuit is further used to output a first control signal to the lead wire electrically connected to one of the signal vias in one of the signal via groups via one corresponding signal transmission link, and to transmit a second control signal different from the first control signal to the lead wire electrically connected to one of the signal vias in another of the signal via groups via another corresponding signal transmission link. [Effects of the Invention]

[0031] According to some embodiments of the present invention, a semiconductor chip, a semiconductor device, and a method for forming the same include providing a plurality of pairs of signal via groups independent of each other within the semiconductor chip, each of the signal via groups being arranged at intervals within the base, and the two signal via groups of each pair being distributed symmetrically with respect to an axis on the top surface of the base, and being distributed in a first region and a second region on both sides of the axis, respectively. Thus, when stacking a plurality of the semiconductor chips, a simple rotation operation can be performed to achieve face-to-face stacking connection of the semiconductor chips, thereby ensuring that the same control signal within the semiconductor device propagates upward in one direction, reducing the number of masks required in the semiconductor device formation process, simplifying the operation of sequentially stacking a plurality of semiconductor chips, easing the difficulty of manufacturing the semiconductor device, and helping to improve the yield of the semiconductor device. [Brief explanation of the drawings]

[0032] [Figure 1] 1 is an exemplary top view of a structure of a semiconductor chip in a specific embodiment of the present invention; [Figure 2] 2 is a schematic diagram of a three-dimensional structure of a first region of a semiconductor chip in a specific embodiment of the present invention. [Figure 3] 3 is a schematic diagram of a three-dimensional structure of a second region of a semiconductor chip in a specific embodiment of the present invention. FIG. [Figure 4A] 1 is a schematic diagram of a stack structure of a semiconductor device in a specific embodiment of the present invention. [Figure 4B] 1 is a schematic diagram of a stack structure of a semiconductor device in a specific embodiment of the present invention. [Figure 4C] 1 is a schematic diagram of a stack structure of a semiconductor device in a specific embodiment of the present invention. [Figure 5] 3 is an exemplary structural diagram after a first region of a first semiconductor chip and a second region of a second semiconductor chip are bonded together in a specific embodiment of the present invention; FIG. [Figure 6]4 is an exemplary structural diagram after the second region of the first semiconductor chip and the first region of the second semiconductor chip are bonded together in a specific embodiment of the present invention; FIG. [Figure 7] 1 is a schematic cross-sectional view of a semiconductor device in accordance with a specific embodiment of the present invention; [Figure 8] 1 is a flowchart of a method for forming a semiconductor device in accordance with a specific embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0033] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the semiconductor device and the method for forming the same according to the present invention will be described in detail with reference to the drawings.

[0034] This specific embodiment provides a method for forming a semiconductor device, in which Fig. 1 is an exemplary top view of the structure of a semiconductor chip in a specific embodiment of the present invention, Fig. 2 is a schematic diagram of the three-dimensional structure of a first region of the semiconductor chip in a specific embodiment of the present invention, and Fig. 3 is a schematic diagram of the three-dimensional structure of a second region of the semiconductor chip in a specific embodiment of the present invention. As shown in Figs. 1 to 3, the semiconductor chip includes: a base 10 including a top surface 31 and a bottom surface 30 opposite the top surface 31; and a plurality of pairs of signal via groups that are independent of each other, each signal via group arranged at intervals within the base 10, the two signal via groups of each pair being distributed symmetrically with respect to one axis AA on the top surface 31 of the base 10, and being distributed respectively in a first region P1 and a second region P2 on both sides of the axis AA, the axis AA being parallel to the first direction D1 or the second direction D2, each signal via group including a plurality of signal vias arranged in a polygonal shape, any two signal vias in each signal via group being electrically isolated, and each signal via penetrating the base along a third direction D3, wherein the first direction D1 and the second direction D2 are perpendicular to each other and both are parallel to the top surface 31, and the third direction D3 is a direction perpendicular to the top surface 31 of the base 10.

[0035] Specifically, the semiconductor chip is a dynamic random access memory (DRAM) chip. The multiple pairs in this specific embodiment may be two or more pairs. The following description will be given taking as an example a pair of signal via groups in a semiconductor chip, each of which includes four signal vias. As shown in FIG. 1 , the semiconductor chip includes a first region P1 and a second region P2 symmetrically distributed about an axis AA. Each pair of signal via groups includes a first signal via group 20 located in the first region P1 and a second signal via group 21 located in the second region P2. The first signal via group 20 and the second signal via group 21 are symmetrically distributed about the axis AA. Both the first signal via group 20 and the second signal via group 21 include a plurality of signal vias arranged in a polygonal shape, each of which is used to transmit various different control signals. This distribution of the signal via groups simplifies the manufacturing process by eliminating the need to change the manufacturing process of each individual semiconductor chip when stacking semiconductor chips (e.g., face-to-face stacking). In one example, the specific number, structure, and material of the multiple signal vias in the first signal via group 20 and the multiple signal vias in the second signal via group 21 are the same, which not only simplifies the manufacturing process of the semiconductor chip, but also makes it easy to transmit different types of control signals through the multiple signal vias, respectively, thereby reducing the driving load of the semiconductor chip. The above is just one example, and in other specific embodiments, the semiconductor chip may include two or more pairs of signal via groups, where the two signal via groups in each pair are distributed symmetrically with respect to the axis AA, and the multiple signal via groups located on the same side of the axis AA are arranged with an interval between them.

[0036] For example, continuing to refer to FIG. 1, first signal via group 20 includes first signal via 201, second signal via 202, third signal via 203, and fourth signal via 204 arranged sequentially in a counterclockwise direction, and second signal via group 21 includes fifth signal via 211, sixth signal via 212, seventh signal via 213, and eighth signal via 214 arranged sequentially in a clockwise direction.

[0037] 2 and 3, in some embodiments, the semiconductor chip further comprises: The base 10 includes a plurality of top metal wiring structures, all of which are disposed on the top surface 31 of the base 10, and the plurality of top metal wiring structures are electrically connected to the plurality of signal via groups in one-to-one correspondence, and each top metal wiring structure includes a plurality of conductive paths electrically connected to the plurality of signal vias in the corresponding signal via group in one-to-one correspondence.

[0038] Specifically, by providing multiple, mutually independent conductive paths in the top-layer metal wiring structure of a semiconductor chip, it becomes possible to transmit various control signals through the multiple conductive paths, which not only ensures stable transmission of each control signal within the semiconductor chip, but also reduces crosstalk between different control signals.Furthermore, when semiconductor chips are stacked, a spiral-rising signal transmission path can be realized, thereby improving the electrical performance of the semiconductor chip.

[0039] Continuing with reference to FIGS. 2 and 3, in some embodiments, the top metallization structure comprises: a first conductive layer located on the top surface of the base 10, the first conductive layer including a plurality of first conductive elements arranged at intervals, the plurality of first conductive elements being arranged in a polygonal shape, and the plurality of first conductive elements being electrically connected in one-to-one correspondence with the plurality of signal vias in the corresponding signal via group; a second conductive layer located on the first conductive layer, the second conductive layer including a plurality of second conductive elements arranged at intervals and corresponding one-to-one to the plurality of first conductive elements, the plurality of second conductive elements being arranged in a polygonal shape, and each second conductive element being provided so as to partially overlap a corresponding first conductive element; and a plurality of connection elements 35 corresponding one-to-one to the plurality of second conductive elements, each connection element being used to electrically connect the second conductive element with its corresponding first conductive element.

[0040] Specifically, the top metal wiring structure includes a first conductive layer and a second conductive layer arranged in layers along the third direction D3. The number of first conductive elements in the first conductive layer, the number of second conductive elements in the second conductive layer, and the number of connecting elements 35 are all the same. In the following, an example will be described in which a semiconductor chip includes a first top metal wiring structure located on a first signal via group 20 and a second top metal wiring structure located on a second signal via group 21. As shown in FIG. 2, the first conductive layer in the first top metal wiring structure includes four first conductive elements (i.e., a left-side first conductive element 321 electrically connected to the first signal via 201, a front-side first conductive element 322 electrically connected to the second signal via 202, a right-side first conductive element 323 electrically connected to the third signal via 203, and a rear-side first conductive element 324 electrically connected to the fourth signal via) electrically connected in one-to-one correspondence with the four signal vias of the first signal via group 20 (i.e., a first signal via 201, a second signal via 202, a third signal via 203, and a fourth signal via 204). The second conductive layer includes a plurality of second conductive elements electrically connected in one-to-one correspondence with the plurality of first conductive elements (i.e., left second conductive element 331 electrically connected to left first conductive element 321 via connection element 35, front second conductive element 332 electrically connected to front first conductive element 322 via connection element 35, right second conductive element 333 electrically connected to right first conductive element 323 via connection element 35, and rear second conductive element 334 electrically connected to rear first conductive element 324 via connection element 35). As shown in FIG. 3, the specific structures of the second top layer metal wiring structure and the first top layer metal wiring structure located on second signal via group 21 are the same.

[0041] In some embodiments, the first conductive element includes a first end and a second end that are oppositely distributed along the extension direction thereof, and the second conductive element includes a third end and a fourth end that are oppositely distributed along the extension direction thereof; first ends of the plurality of first conductive elements are electrically connected to the plurality of signal vias in one-to-one correspondence; For each corresponding first conductive element and second conductive element, one end of the connection element 35 is electrically connected to the third end of the second conductive element, and the other end of the connection element is electrically connected to the second end of the first conductive element.

[0042] For example, as shown in Figures 2 and 3, the left first conductive element 321 and the right first conductive element 323 in the first conductive layer extend along the second direction D2, and both the left first conductive element 321 and the right first conductive element 323 include first ends and second ends distributed oppositely along the second direction D2, and the front first conductive element 322 and the rear first conductive element 324 both extend along the first direction D1, and both the front first conductive element 322 and the rear first conductive element 324 include first ends and second ends distributed oppositely along the first direction D1. Of any two first conductive elements adjacent counterclockwise or clockwise in the first conductive layer, the first end of one first conductive element is adjacent to but not connected to the second end of the other first conductive element, so that the multiple first conductive elements in the first conductive layer are arranged with their leading ends and trailing ends (e.g., the first end of the first conductive element is the leading end and the second end is the trailing end) facing each other to form a polygonal shape (e.g., a square or diamond shape). The left second conductive element 331 and the right second conductive element 333 in the second conductive layer extend along the second direction D2, and both the left second conductive element 331 and the right second conductive element 333 include third and fourth ends distributed opposite each other along the second direction D2. The front second conductive element 332 and the rear second conductive element 334 both extend along the first direction D1, and both include third and fourth ends distributed opposite each other along the first direction D1. Of any two second conductive elements adjacent counterclockwise or clockwise in the second conductive layer, the third end of one second conductive element is adjacent to the fourth end of the other second conductive element. Therefore, the multiple second conductive elements in the second conductive layer are arranged with their leading and trailing ends (e.g., the third end of the second conductive element is the leading end and the fourth end is the trailing end) facing each other, forming a polygonal shape (e.g., a square or diamond shape). One end of the connection element 35 is electrically connected to the third end of the second conductive element, and the other end of the connection element is electrically connected to the second end of the first conductive element. By adopting the above-mentioned top layer metal wiring structure including the first conductive layer and the second conductive layer, the specific structure of the top layer metal wiring structure can be simplified, and the difficulty of manufacturing the top layer metal wiring structure can be reduced.In one example, the top metal wiring structure further includes an insulating dielectric layer located between the first conductive layer and the second conductive layer to electrically isolate the first end of the first conductive element from the second conductive element.

[0043] In some embodiments, the semiconductor chip further comprises: The semiconductor device includes a plurality of internal circuits that correspond one-to-one to the plurality of top metal wiring structures, and each internal circuit is electrically connected to one conductive path in the corresponding top metal wiring structure.

[0044] In some embodiments, the semiconductor chip further comprises: The semiconductor chip has a plurality of lead wires corresponding one-to-one to the plurality of internal circuits, one end of each lead wire 50 being electrically connected to one internal circuit and the other end being electrically connected to only one first conductive element of the top layer metal wiring structure, and external control signals are transmitted to the internal circuits inside the semiconductor chip via the lead wires.

[0045] For example, as shown in FIG. 1, a first signal via group 20 of a pair of signal via groups in a semiconductor chip is electrically connected to a first internal circuit in the semiconductor chip via a first lead wire 50, and a second signal via group 20 is electrically connected to a second internal circuit in the semiconductor chip via a second lead wire 51.

[0046] In some embodiments, each signal via group includes four signal vias, and the four signal vias are arranged in a square or diamond shape. In other embodiments, the signal via group may further include more than four signal vias, for example, the signal via group may include five, six, seven, or eight signal vias.

[0047] This specific embodiment further provides a semiconductor device. FIGS. 4A to 4C are schematic diagrams of a stacked structure of a semiconductor device in a specific embodiment of the present invention. FIG. 5 is an exemplary structural diagram of a specific embodiment of the present invention after a first region of a first semiconductor chip and a second region of a second semiconductor chip are bonded together. FIG. 6 is an exemplary structural diagram of a specific embodiment of the present invention after a second region of a first semiconductor chip and a first region of a second semiconductor chip are bonded together. FIG. 7 is a schematic cross-sectional view of a semiconductor device in a specific embodiment of the present invention. In FIG. 7, the first region P1 and the second region P2 of each semiconductor chip are symmetrically distributed on opposite sides of the axis AA (see FIG. 1), and the axis AA is not visible from the perspective shown in FIG. 7. As shown in FIGS. 4A and 7, the semiconductor device has a substrate 110; a stacked structure disposed on a substrate 110, the stacked structure including N unit structures sequentially stacked and electrically connected along a third direction D3, each unit structure including four of the above-mentioned semiconductor chips, where N is a positive integer; The four semiconductor chips in the unit structure are stacked sequentially along the third direction D3, with the first semiconductor chip 101 located at the bottom layer and the second semiconductor chip 102 located thereon stacked face to face, the second semiconductor chip 102 and the third semiconductor chip 103 located thereon stacked back to back, and the third semiconductor chip 103 and the fourth semiconductor chip 104 located thereon stacked face to face, The axes AA of any two adjacent semiconductor chips in the stacked structure are aligned, and the first region P1 of one semiconductor chip is aligned with the second region P2 of the other semiconductor chip; Here, face-to-face means that the top surfaces of two adjacent semiconductor chips face each other, and back-to-back means that the bottom surfaces of two adjacent semiconductor chips face each other.

[0048] 4A and 7, "first semiconductor chip 101 located in the bottom layer and second semiconductor chip 102 located thereon are stacked face-to-face" means that, for first semiconductor chip 101 and second semiconductor chip 102, the top surface 31 of base 10 of first semiconductor chip 101 and the top surface 31 of base 10 of second semiconductor chip 102 face each other. "second semiconductor chip 102 and third semiconductor chip 103 located thereon are stacked back-to-back" means that, for second semiconductor chip 102 and third semiconductor chip 103, the bottom surface 30 of base 10 of second semiconductor chip 102 faces each other. In this specific embodiment, first semiconductor chip 101, second semiconductor chip 102, third semiconductor chip 103, and fourth semiconductor chip 104 all have the same structure as the semiconductor chips shown in FIGS. 1 to 3. In this specific embodiment, only two unit structures are shown (i.e., a first unit structure 70 including a first semiconductor chip 101, a second semiconductor chip 102, a third semiconductor chip 103, and a fourth semiconductor chip 104, and a second unit structure 71 including a fifth semiconductor chip 105, a sixth semiconductor chip 106, a seventh semiconductor chip 107, and an eighth semiconductor chip 108). The axes AA of any two adjacent unit structures (e.g., the first unit structure 70 and the second unit structure 71) in the stacked structure are aligned, and the axes AA of any two adjacent semiconductor chips (e.g., the first semiconductor chip 101 and the second semiconductor chip 102 in the first unit structure 70) in each unit structure (e.g., the first unit structure 70 or the second unit structure 71) are aligned, i.e., the axes AA of any two adjacent semiconductor chips in the stacked structure are aligned).

[0049] In this specific embodiment, a pair of signal via groups is formed symmetrically with respect to the axis AA, and each of the two signal via groups in each pair includes a plurality of signal vias arranged in a polygonal shape. This eliminates the need to modify the manufacturing process of each semiconductor chip when stacking multiple semiconductor chips on the substrate 110, thereby simplifying the semiconductor chip manufacturing process. Furthermore, in some examples of this specific embodiment, control signals are sequentially transmitted to multiple semiconductor chips in a semiconductor device via an interface circuit in the substrate. This eliminates the need to provide individual drivers and interface circuits for each semiconductor chip. This simplifies the driving operation of the semiconductor device, reduces the driving load of the semiconductor device, widens the data eye pattern, and reduces the power consumption of the semiconductor device. Furthermore, in some examples of this specific embodiment, the two signal via groups in one pair of signal via groups are independent of each other, eliminating the need to simultaneously drive the two signal via groups. That is, different control signals can be simultaneously transmitted to the two signal via groups in one pair of signal via groups via the interface circuit in the substrate. This improves the driving efficiency of the semiconductor device and simplifies the driving operation of the semiconductor device.

[0050] In some embodiments, the semiconductor device further comprises: The semiconductor device includes a plurality of signal transmission link groups, each of which corresponds one-to-one with a plurality of signal via groups in each semiconductor chip. The signal transmission link groups include a plurality of signal transmission links, and the signal transmission links in each signal transmission link group are independent of each other and all extend spirally along a third direction D3. The signal transmission links in each signal transmission link group correspond one-to-one with a plurality of signal vias in a corresponding signal via group in each semiconductor chip. Each signal transmission link includes one corresponding signal via in each semiconductor chip.

[0051] Specifically, the signal transmission link groups of the multiple pairs correspond one-to-one to the signal via groups in the semiconductor chips, and each signal transmission link group of the multiple pairs includes two signal transmission link groups that correspond one-to-one to the two signal via groups in each signal via group of the pair, and each signal transmission link group includes a plurality of signal transmission links that correspond one-to-one to the signal vias in the signal via groups, and each signal transmission link includes a corresponding signal via in each semiconductor chip. For example, as shown in Figure 4B, one signal transmission link includes the first signal via 201 in the first semiconductor chip 101, the eighth signal via 214 in the second semiconductor chip 102, the third signal via 203 in the third semiconductor chip 103, and the sixth signal via 212 in the fourth semiconductor chip 104. 4C , another signal transmission link includes the second signal via 202 in the first semiconductor chip 101, the seventh signal via 213 in the second semiconductor chip 102, the fourth signal via 204 in the third semiconductor chip 103, and the fifth signal via 211 in the fourth semiconductor chip 104. The multiple signal transmission links in the signal transmission link group are independent of each other and all extend spirally along the third direction D3 to avoid signal crosstalk between the signal transmission links.

[0052] In some embodiments, for two semiconductor chips stacked face-to-face, the projection of signal vias in the two semiconductor chips electrically connected to the same signal line transmission link onto the top surface of any base is a centrosymmetric distribution, and the center of symmetry is the projection of a polygon onto the top surface of the base. In one example, for any two signal transmission links in one signal transmission link group, an imaginary line between two signal vias connected to one signal transmission link and a center line of the stacked structure forms a first included angle, and an imaginary line between two signal vias connected to another signal transmission link and a center line of the stacked structure forms a second included angle, and the first included angle is equal to the second included angle.

[0053] In some embodiments, the signal transmission link group further comprises: The semiconductor device has a plurality of pairs of bonding pillar groups, which are located only between the semiconductor chips stacked face-to-face and correspond one-to-one to the plurality of pairs of signal via groups of the two semiconductor chips stacked face-to-face, and are used to realize signal transmission between the semiconductor chips stacked face-to-face, each bonding pillar group including a plurality of bonding pillars 80, each bonding pillar 80 corresponding one-to-one to the plurality of signal vias of the two semiconductor chips stacked face-to-face, the plurality of pairs of signal transmission link groups corresponding one-to-one to the plurality of pairs of bonding pillar groups between each of the two semiconductor chips stacked face-to-face, the plurality of signal transmission links in each signal transmission link group corresponding one-to-one to the plurality of bonding pillars 80 of the plurality of pairs of bonding pillar groups, and each signal transmission link including one corresponding bonding pillar 80 between the two semiconductor chips stacked face-to-face.

[0054] For example, as shown in FIG. 5, there is a bonding pillar group between a first semiconductor chip 101 and a second semiconductor chip 102 stacked face-to-face, and the four bonding pillars 80 of the bonding pillar group correspond one-to-one to the four signal vias in the first semiconductor chip 101 (i.e., the first signal via 201, the second signal via 202, the third signal via 203, and the fourth signal via 204), and also correspond one-to-one to the four signal vias in the second semiconductor chip 102 (i.e., the fifth signal via 211, the sixth signal via 212, the seventh signal via 213, and the eighth signal via 214). For example, in the structure shown in FIG. 5, one signal transmission link includes a first signal via 201 in the first semiconductor chip 101, an eighth signal via 214 in the second semiconductor chip 102, and a bonding pillar 80 for electrically connecting the first signal via 201 in the first semiconductor chip 101 and the eighth signal via 214 in the second semiconductor chip 102.

[0055] In some embodiments, in two semiconductor chips stacked back to back, a plurality of signal vias in one semiconductor chip correspond one-to-one to a plurality of signal vias in the other semiconductor chip and are electrically connected by direct contact.

[0056] 4B, in the second semiconductor chip 102 and the third semiconductor chip 103 stacked back to back, the eighth signal via 214 in the second semiconductor chip 102 is in direct contact with and electrically connected to the third signal via 203 in the third semiconductor chip 103. In another example, in the second semiconductor chip 102 and the third semiconductor chip 103 stacked back to back, as shown in FIG. 4C, the seventh signal via 213 in the second semiconductor chip 102 is in direct contact with and electrically connected to the fourth signal via 204 in the third semiconductor chip 103.

[0057] In some embodiments, each semiconductor chip comprises a plurality of top metal wiring structures, all of which are disposed on the top surface of the base 10, the plurality of top metal wiring structures being electrically connected to the plurality of signal via groups in one-to-one correspondence, each top metal wiring structure including a plurality of conductive paths being electrically connected to the plurality of signal vias in the corresponding signal via group in one-to-one correspondence, and each signal transmission link including one corresponding signal via and one corresponding conductive path in each semiconductor chip; the top layer metal wiring structure includes a first conductive layer, a second conductive layer, and a plurality of connection elements 35, the first conductive layer being located on the top surface of the base, the first conductive layer including a plurality of first conductive elements arranged at intervals, the plurality of first conductive elements being arranged in a polygonal shape, and the plurality of first conductive elements being electrically connected in one-to-one correspondence with the plurality of signal vias in the corresponding signal via group; the second conductive layer being located on the first conductive layer, the second conductive layer including a plurality of second conductive elements arranged at intervals and in one-to-one correspondence with the plurality of first conductive elements, the plurality of second conductive elements being arranged in a polygonal shape, and each second conductive element being partially overlapped with its corresponding first conductive element; the plurality of connection elements being in one-to-one correspondence with the plurality of first conductive elements and the plurality of second conductive elements, each connection element being used to electrically connect its corresponding first conductive element and second conductive element to form a conductive path; The first conductive element includes a first end and a second end distributed opposite each other along its extension direction, and the second conductive element includes a third end and a fourth end distributed opposite each other along its extension direction, the first ends of the multiple first conductive elements are electrically connected to the multiple signal vias in one-to-one correspondence, and for corresponding first conductive elements and second conductive elements, one end of the connection element 35 is electrically connected to the third end of the second conductive element, and the other end of the connection element is electrically connected to the second end of the first conductive element.

[0058] In some embodiments, for two semiconductor chips stacked face-to-face, each of the multiple pairs of bonding pillar groups corresponds one-to-one to the multiple top layer metal wiring structures of the two semiconductor chips, and one end of each bonding pillar 80 is electrically connected to the fourth end of a corresponding one of the second conductive elements in one semiconductor chip, and the other end of the bonding pillar 80 is bonded and electrically connected to the fourth end of a corresponding one of the second conductive elements in another semiconductor chip.

[0059] Specifically, because the four semiconductor chips in the unit structure (i.e., first semiconductor chip 101, second semiconductor chip 102, third semiconductor chip 103, and fourth semiconductor chip 104) all have the same structure, simply by rotating (e.g., flipping) the semiconductor chips can be bonded face-to-face. For example, the second conductive elements in first semiconductor chip 101 are bonded to the second conductive elements in second semiconductor chip 102 in one-to-one correspondence via bonding pillars 80. The signal vias in second semiconductor chip 102 are electrically connected to the signal vias in third semiconductor chip 103 in one-to-one correspondence and in direct contact with each other.

[0060] 4A and 5, the top metal wiring structure electrically connected to the first signal via group 20 in the first semiconductor chip 101 includes four conductive paths, namely, a first conductive path, a second conductive path, a third conductive path, and a fourth conductive path. Here, the first conductive path in the first semiconductor chip 101 includes, electrically connected in sequence, a left-side first conductive element 321, a connection element 35 electrically connecting the left-side first conductive element 321 and the left-side second conductive element 331, and a left-side second conductive element 331. The second conductive path in the first semiconductor chip 101 includes, electrically connected in sequence, a front-side first conductive element 322, a connection element 35 electrically connecting the front-side first conductive element 322 and the front-side second conductive element 332, and a front-side second conductive element 332. The third conductive path in the first semiconductor chip 101 includes, electrically connected in sequence, a right-side first conductive element 323, a connection element 35 electrically connecting the right-side first conductive element 323 and the right-side second conductive element 333, and a right-side second conductive element 333. The fourth conductive path in the first semiconductor chip 101 includes, electrically connected in sequence, a rear-side first conductive element 324, a connection element 35 electrically connecting the rear-side first conductive element 324 and the rear-side second conductive element 334, and a rear-side second conductive element 334. The top layer metal wiring structure electrically connected to the second signal via group 21 in the first semiconductor chip 101 also similarly includes four conductive paths (a first conductive path, a second conductive path, a third conductive path, and a fourth conductive path). In addition, the top layer metal wiring structure electrically connected to the first signal via group 20 in the first semiconductor chip 101 is the same as the top layer metal wiring structure electrically connected to the second signal via group 21, see Figures 4A and 6.

[0061] As shown in Figures 4A and 5, one signal transmission link includes a first signal via 201 in the first semiconductor chip 101, a first conductive path in the first semiconductor chip 101, a bonding pillar 80 electrically connecting the first conductive path in the first semiconductor chip 101 and a fourth conductive path in the second semiconductor chip 102, a fourth conductive path in the second semiconductor chip 102, and an eighth signal via 214 in the second semiconductor chip 102.

[0062] In some embodiments, each semiconductor chip further includes a plurality of internal circuits in one-to-one correspondence with the plurality of top metal wiring structures, each internal circuit electrically connected to one conductive path in the corresponding top metal wiring structure; and a plurality of lead wires 50 corresponding one-to-one to the plurality of internal circuits, one end of each lead wire 50 being electrically connected to one internal circuit and the other end being electrically connected to only one first conductive element of the corresponding top layer metal wiring structure.

[0063] In some embodiments, for each unit structure, one signal transmission link is electrically connected to only one lead of one semiconductor chip.

[0064] 4A and 5, the first semiconductor chip 101 includes a first conductive element 321 on the left side electrically connected to the first signal via group 20 and a first lead wire 50 electrically connected to the first conductive element 201 on the left side, where the first lead wire 50 is located in a first region P1 (see FIG. 1) of the first semiconductor chip 101. As shown in FIG. 6, the first semiconductor chip 101 further includes a first conductive element 321 on the left side electrically connected to the second signal via group 21 and a second lead wire 51 electrically connected to the first conductive element 201 on the left side, where the second lead wire 51 is located in a second region P2 (see FIG. 1) of the first semiconductor chip 101. The first lead wire 50 in the first semiconductor chip 101 is electrically connected to a first internal circuit (not shown) in the first semiconductor chip 101, and the second lead wire 51 in the first semiconductor chip 101 is electrically connected to a second internal circuit (not shown) in the first semiconductor chip 101.

[0065] In some embodiments, the semiconductor device further comprises: an interface circuit disposed within the substrate 110 and electrically connected to the plurality of pairs of signal transmission link groups, the interface circuit being used to transmit a plurality of control signals to the signal transmission link groups, each of which corresponds one-to-one with the plurality of signal transmission links within the signal transmission link groups, and each control signal being drawn from only one lead wire of one semiconductor chip within each unit structure; For each pair of signal via groups in one semiconductor chip, the interface circuit outputs a first control signal to a lead wire electrically connected to one signal via of one signal via group via one corresponding signal transmission link, and transmits a second control signal different from the first control signal to a lead wire electrically connected to one signal via of another signal via group via another corresponding signal transmission link.

[0066] For example, as shown in FIG. 7, for each pair of two signal transmission link groups, the interface circuit transmits to one signal transmission link group four first sub-control signals (i.e., CS_0 signal, CS_2 signal, WE_1 signal, WE_3 signal) that correspond one-to-one with the four signal transmission links of one signal transmission link group, and the interface circuit transmits to the other signal transmission link group four second sub-control signals (i.e., CS_1 signal, CS_3 signal, WE_0 signal, WE_2 signal) that correspond one-to-one with the four signal transmission links of another signal transmission link group. For one pair of signal via groups consisting of a first signal via group 20 and a second signal via group 21 in one semiconductor chip, the interface circuit outputs a CS_0 signal to a first lead wire in the semiconductor chip through the first signal via group 20, and the CS_0 signal is transmitted to a first internal circuit in the semiconductor chip, and the interface circuit outputs a WE_0 signal to a second lead wire 51 of the semiconductor chip through the second signal via group 21, and the WE_0 signal is transmitted to a second internal circuit in the semiconductor chip. As shown in Figures 4B and 7, the signal transmission link transmitting the CS_0 signal is electrically connected only to the first lead wire 50 of the first semiconductor chip 101 in the first unit structure 70.

[0067] 4A and 7, the CS_0 signal is transmitted to the first signal via 201 in the first semiconductor chip 101 in the first unit structure 70 via the interface circuit in the substrate, and is output to the first internal circuit in the first semiconductor chip 101 via the first conductive element 321 on the left side electrically connected to the first signal via 201 and the first lead wire 50. The WE_1 signal is transmitted to the first unit structure 70 via the interface circuit in the substrate, transmitted to the second semiconductor chip 102 via the first semiconductor chip 101 in the first unit structure 70, transmitted to the second semiconductor chip 102 via the fifth signal via in the second semiconductor chip 102 to the second lead wire 51 in the second semiconductor chip 102, and output to the second internal circuit in the second semiconductor chip 102 via the second lead wire 51. The CS_2 signal is transmitted to the first unit structure 70 via the interface circuit in the substrate, transmitted to the third semiconductor chip 103 via the first semiconductor chip 101 and the second semiconductor chip 102 in the first unit structure 70, transmitted to the first lead wire 50 in the third semiconductor chip 103 via the first signal via in the third semiconductor chip 103, and output to a first internal circuit in the third semiconductor chip 103 via the first lead wire 50. The WE_3 signal is transmitted to the first unit structure 70 via the interface circuit in the substrate, transmitted to the fourth semiconductor chip 104 via the first semiconductor chip 101, the second semiconductor chip 102, and the third semiconductor chip 103 in the first unit structure 70, transmitted to the second lead wire 51 in the fourth semiconductor chip 104 via the fifth signal via in the fourth semiconductor chip 104, and output to a second internal circuit in the fourth semiconductor chip 104 via the second lead wire 51. Similarly, the interface circuit in the substrate transmits corresponding first sub-control signals and second sub-control signals via signal transmission links to corresponding semiconductor chips in other unit structures in the stacked structure, for example, semiconductor chips 105 to 108 in the second unit structure 71 in Figure 7.

[0068] In the following, an example will be given in which a plurality of signal transmission links in a signal transmission link group are independent of each other and all extend spirally along the third direction D3.

[0069] Specifically, as shown in FIG. 4B , one signal transmission link in the stacked structure includes the first signal via 201 in the first semiconductor chip 101 in one unit structure, the first conductive element 321 on the left side in the first semiconductor chip 101, the connection element 35 that electrically connects the first conductive element 321 on the left side and the second conductive element 331 on the left side in the first semiconductor chip 101, the second conductive element 331 on the left side in the first semiconductor chip 101, the bonding pillar 80 between the first semiconductor chip 101 and the second semiconductor chip 102 that are stacked face to face, the second conductive element 334 on the rear side in the second semiconductor chip 102, the connection element 35 that electrically connects the second conductive element 334 on the rear side and the first conductive element 324 on the rear side in the second semiconductor chip 102, and the first conductive element 324 on the rear side in the second semiconductor chip 102. , an eighth signal via 214 in the second semiconductor chip 102, a third signal via 203 in the third semiconductor chip 103, a right-side first conductive element 323 in the third semiconductor chip 103, a connection element 35 electrically connecting the right-side first conductive element 323 and the right-side second conductive element 333 in the third semiconductor chip 103, a right-side second conductive element 333 in the third semiconductor chip 103, a bonding pillar 80 between the third semiconductor chip 103 and the fourth semiconductor chip 104, a front-side second conductive element 332 in the fourth semiconductor chip 104, a connection element 35 electrically connecting the front-side second conductive element 332 and the front-side first conductive element 322 in the fourth semiconductor chip 104, a front-side first conductive element 322 in the fourth semiconductor chip 104, and a sixth signal via 212 in the fourth semiconductor chip 104.

[0070] The stacked structure transmits one corresponding control signal between chips through each signal transmission link. Continuing with reference to FIGS. 4B and 7, the external CS_0 signal is transmitted through the interface circuit in the substrate 110 to the first signal via 201 in the first semiconductor chip 101 in one unit structure, then sequentially through the left first conductive element 321 electrically connected to the first signal via 201 in the first semiconductor chip 101, the connection element 35, and the left second conductive element 331 to the bonding pillar 80, and then through the bonding pillar 80 to the rear second conductive element 334 in the second semiconductor chip 102, and then sequentially through the connection element 35 and the rear first conductive element 324 in the second semiconductor chip 102. The signal is then transmitted to the eighth signal via 214 in the second semiconductor chip 102, then to the top metal wiring structure of the third semiconductor chip 103 via the third signal via 203 in the third semiconductor chip 103, which is electrically connected to the eighth signal via 214 in the second semiconductor chip 102, then to the bonding pillar 80 via the first right conductive element 323, the connecting element 35, and the second right conductive element 333 in the third semiconductor chip 103, then to the bonding pillar 80 to the fourth semiconductor chip 104, and then to the next unit structure within the fourth semiconductor chip 104 via the front second conductive element 332, the connecting element 35, the front first conductive element 322, and the sixth signal via 212. That is, the same type of control signal is transmitted spirally upward along one independent signal transmission path.

[0071] In another example, as shown in FIGS. 4C and 7 , another signal transmission link in the stacked structure includes the second signal via 202 in the first semiconductor chip 101 in one unit structure, the front-side first conductive element 322 in the first semiconductor chip 101, the connection element 35 electrically connecting the front-side first conductive element 322 and the front-side second conductive element 332 in the first semiconductor chip 101, the front-side second conductive element 332 in the first semiconductor chip 101, the bonding pillar 80 between the first semiconductor chip 101 and the second semiconductor chip 102, the right-side second conductive element 333 in the second semiconductor chip 102, the connection element 35 electrically connecting the right-side second conductive element 333 and the right-side first conductive element 323 in the second semiconductor chip 102, the right-side first conductive element 323 in the second semiconductor chip 102, and the The fourth semiconductor chip 104 includes a seventh signal via 213 in the second semiconductor chip 102, a fourth signal via 204 in the third semiconductor chip 103, a rear first conductive element 324 in the third semiconductor chip 103, a connection element 35 that electrically connects the rear first conductive element 324 and the right second conductive element 334 in the third semiconductor chip 103, the rear second conductive element 334 in the third semiconductor chip 103, a bonding pillar 80 between the third semiconductor chip 103 and the fourth semiconductor chip 104, a left second conductive element 331 in the fourth semiconductor chip 104, a connection element 35 that electrically connects the left second conductive element 331 and the left first conductive element 321 in the fourth semiconductor chip 104, the left first conductive element 321 in the fourth semiconductor chip 104, and a fifth signal via 211 in the fourth semiconductor chip 104.

[0072] 4C and 7, the external WE_1 signal is transmitted to the second signal via 202 in the first semiconductor chip 101 via the interface circuit in the substrate 110, then transmitted to the bonding pillar 80 via the front first conductive element 322 electrically connected to the second signal via 202 in the first semiconductor chip 101, the connection element 35, and the front second conductive element 332, and then transmitted to the bonding pillar 80 to the right second conductive element 333 in the second semiconductor chip 102, and then transmitted to the seventh signal via 213 in the second semiconductor chip 102 via the connection element 35 and the right first conductive element 323. Then, the signal is transmitted to the top metal wiring structure of the third semiconductor chip 103 via the fourth signal via 204 in the third semiconductor chip 103, which is electrically connected to the seventh signal via 213 in the second semiconductor chip 102, and then to the bonding pillar 80 via the rear first conductive element 324, the connecting element 35, and the rear second conductive element 334 in the third semiconductor chip 103, and then to the fourth semiconductor chip 104 via the bonding pillar 80, and then to the next unit structure within the fourth semiconductor chip 104 via the left second conductive element 331, the connecting element 35, the left first conductive element 321, and the fifth signal via 211. That is, the same type of control signal is transmitted spirally upward along an independent signal transmission path.

[0073] This specific embodiment further provides a method for forming a semiconductor device, and Figure 8 is a flowchart of the method for forming a semiconductor device in this specific embodiment. For the structure of the semiconductor device formed by this specific embodiment, please refer to Figures 1 to 7. As shown in Figures 1 to 8, the method for forming a semiconductor device includes the following steps:

[0074] In step S81, a substrate 110 is provided.

[0075] In step S82, a semiconductor chip is formed, the semiconductor chip including a base 10 and a plurality of pairs of signal via groups that are independent of each other, the base 10 including a top surface 31 and a bottom surface 30 opposite the top surface 31, each signal via group arranged at intervals within the base, the two signal via groups of each pair being distributed symmetrically with respect to an axis on the top surface of the base 10 and being distributed in a first region P1 and a second region P2 on both sides of the axis AA, respectively, the axis AA being parallel to the first direction D1 or the second direction D2, each signal via group including a plurality of signal vias 111 arranged in a polygonal shape, any two signal vias 111 in each signal via group being electrically isolated, and each signal via 111 penetrating the base 10 along a third direction D3, where the first direction D1 and the second direction D2 are perpendicular to each other and both parallel to the top surface 31, and the third direction D3 is a direction perpendicular to the top surface 31 of the base 10.

[0076] In step S83, a stacked structure is formed on the substrate 110 based on the plurality of semiconductor chips, the stacked structure including N unit structures sequentially stacked and electrically connected along a third direction D3, each unit structure including four semiconductor chips, the four semiconductor chips in the unit structure sequentially stacked along the third direction D3, the first semiconductor chip 101 located at the bottom layer and the second semiconductor chip 102 located thereon are stacked face-to-face, the second semiconductor chip 102 and the third semiconductor chip 103 located thereon are stacked back-to-back, and the third semiconductor chip 103 and the fourth semiconductor chip 104 located thereon are stacked face-to-face, N is a positive integer; The axes AA of any two adjacent semiconductor chips in the stacked structure are aligned, and the first region P1 of one semiconductor chip is aligned with the second region P2 of the other semiconductor chip; Here, face-to-face means that the top surfaces of two adjacent semiconductor chips face each other, and back-to-back means that the bottom surfaces of two adjacent semiconductor chips face each other.

[0077] In some embodiments, forming the semiconductor chip comprises: forming a base 10, and defining a first region P1 and a second region P2 located on either side of an axis AA in the base 10; forming a signal via group penetrating the base 10 along a third direction D2 in the first region P1 and the second region P2; The method includes forming a plurality of top metal wiring structures on the top surface 31 of the base 10, the plurality of top metal wiring structures being electrically connected in one-to-one correspondence with the plurality of signal via groups, and each top metal wiring structure including a plurality of conductive paths being electrically connected in one-to-one correspondence with the plurality of signal vias 111 in the corresponding signal via group.

[0078] In some embodiments, forming a top metallization structure on the top surface of the base comprises: Forming a first conductive layer on the top surface 31 of the base 10, the first conductive layer including a plurality of first conductive elements arranged at intervals, the plurality of first conductive elements being arranged in a polygonal shape, the first conductive elements including first ends and second ends distributed opposite to each other along the extending direction thereof, the first ends of the plurality of first conductive elements being electrically connected in one-to-one correspondence with a plurality of signal vias 111 in a corresponding signal via group; forming a second conductive layer on a first conductive layer, the second conductive layer including a plurality of second conductive elements arranged at intervals and corresponding one-to-one to the plurality of first conductive elements, the plurality of second conductive elements being arranged in a polygonal shape, the second conductive elements including third and fourth ends oppositely distributed along an extension direction thereof, and each second conductive element being arranged to partially overlap a corresponding first conductive element; and forming a connection element 35 between the first conductive layer and the second conductive layer, wherein for each corresponding first conductive element and second conductive element, one end of the connection element is electrically connected to a third end of the second conductive element and the other end of the connection element is electrically connected to a second end of the first conductive element to form a conductive path.

[0079] In some embodiments, forming a stacked structure on the substrate 110 based on a plurality of semiconductor chips includes: providing four semiconductor chips; disposing a first semiconductor chip on a substrate; stacking a second semiconductor chip 102 face-to-face on the first semiconductor chip; stacking a third semiconductor chip 103 back-to-back on the second semiconductor chip 102; stacking the fourth semiconductor chip 104 face-to-face on the third semiconductor chip 103 to form a unit structure including the first semiconductor chip 101, the second semiconductor chip 102, the third semiconductor chip 103, and the fourth semiconductor chip 104; and repeatedly performing the above process on the formed unit structure to sequentially form N unit structures stacked along a third direction D3; Here, the axes AA of any two adjacent semiconductor chips in the stacked structure are aligned, and the first region P1 of one semiconductor chip is aligned with the second region P2 of the other semiconductor chip.

[0080] In some embodiments, stacking the second semiconductor chip 102 face-to-face on the first semiconductor chip 101 includes: forming a bonding pillar group on a top metal wiring structure of the first semiconductor chip (101), the bonding pillar group including a plurality of bonding pillars (80), a lower end of the bonding pillar (80) being bonded to a fourth end of one second conductive element in the first semiconductor chip (101); The upper end of the bonding pillar is bonded to the top metal wiring structure of the second semiconductor chip 102, and the upper end of the bonding pillar is bonded to the fourth end of one of the second conductive elements in the second semiconductor chip 102.

[0081] In some embodiments, stacking the third semiconductor chip 103 back-to-back on the second semiconductor chip 102 includes: This includes making direct contact or direct electrical connection of a plurality of signal vias 111 located in the second semiconductor chip 102 with a corresponding plurality of signal vias 111 located in the third semiconductor chip 103 in a one-to-one manner.

[0082] In some embodiments, the semiconductor chip further comprises a plurality of internal circuits in one-to-one correspondence with the plurality of top metal interconnect structures, and the method of forming the semiconductor device comprises: The method further includes forming leads between the internal circuits and the corresponding top metal wiring structures, so that each internal circuit is electrically connected to one conductive path in the corresponding top metal wiring structure.

[0083] In some embodiments, the method further comprises: forming an interface circuit in the substrate 110; Electrically connecting any two adjacent semiconductor chips in the stacked structure to form a plurality of pairs of signal transmission link groups corresponding one-to-one to the plurality of pairs of signal via groups of each semiconductor chip, each signal transmission link group including a plurality of signal transmission links, each signal transmission link including one corresponding signal via in each semiconductor chip, one corresponding conductive path in each semiconductor chip, and one corresponding bonding pillar 80 between the two semiconductor chips stacked face-to-face; The method further includes electrically connecting the interface circuit to a plurality of pairs of signal via groups in a semiconductor chip located at the bottom layer of the stacked structure, and electrically connecting the interface circuit to a plurality of pairs of signal transmission link groups so as to transmit a plurality of control signals to the signal transmission link groups, each of which corresponds one-to-one to a plurality of signal transmission links in the signal transmission link groups, wherein each control signal is drawn to a corresponding internal circuit through only one lead wire in one semiconductor chip in each unit structure, and wherein, for each pair of signal via groups in one semiconductor chip, the interface circuit is further used to output a first control signal to a lead wire electrically connected to one signal via of one signal via group through one corresponding signal transmission link, and to transmit a second control signal different from the first control signal to a lead wire electrically connected to one signal via of another signal via group through another corresponding signal transmission link.

[0084] According to some examples of the semiconductor chip, semiconductor device and method for forming the same of this specific embodiment of the present invention, a plurality of pairs of signal via groups independent of each other are provided in the semiconductor chip, each signal via group is arranged at intervals in the base, and the two signal via groups of each pair are distributed symmetrically with respect to an axis on the top surface of the base, and are respectively distributed in a first region and a second region on both sides of the axis, so that when stacking multiple semiconductor chips, a simple rotation operation can be performed to achieve face-to-face stacking connection of the semiconductor chips, thereby ensuring that the same control signal in the semiconductor device propagates upward in one direction, reducing the number of masks required in the semiconductor device formation process, simplifying the operation of sequentially stacking multiple semiconductor chips, easing the difficulty of manufacturing semiconductor devices, and helping to improve the yield of the semiconductor devices.

[0085] It should be noted that the above are only preferred embodiments of the present invention, and those skilled in the art may make some improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered to fall within the protection scope of the present invention.

Claims

1. A semiconductor chip, a base including a top surface and a bottom surface opposite the top surface; a plurality of pairs of signal via groups independent of each other, each of the signal via groups arranged at intervals within the base, the two signal via groups of each pair being distributed symmetrically with respect to an axis on the top surface of the base, and being distributed in a first region and a second region on both sides of the axis, the axis being parallel to a first direction or a second direction, each of the signal via groups including a plurality of signal vias arranged in a polygonal shape, any two of the signal vias in each of the signal via groups being electrically insulated, each of the signal vias penetrating the base along a third direction, the first direction and the second direction being perpendicular to each other and both being parallel to the top surface, the third direction being perpendicular to the top surface of the base, each of the signal via groups including four of the signal vias, the four signal vias being arranged in a square or diamond shape; a plurality of top layer metal wiring structures, all of which are disposed on a top surface of the base, the plurality of top layer metal wiring structures being electrically connected to the plurality of signal via groups in one-to-one correspondence, and each of the top layer metal wiring structures including a plurality of conductive paths being electrically connected to the plurality of signal vias in the corresponding signal via group in one-to-one correspondence.

2. The top metal wiring structure comprises: a first conductive layer located on a top surface of the base, the first conductive layer including a plurality of first conductive elements arranged at intervals, the plurality of first conductive elements being arranged in the polygonal shape, and the plurality of first conductive elements being electrically connected in one-to-one correspondence with the plurality of signal vias in the corresponding signal via group; a second conductive layer located on the first conductive layer, the second conductive layer including a plurality of second conductive elements arranged at intervals and corresponding one-to-one to a plurality of the first conductive elements, the plurality of second conductive elements being arranged in the polygonal shape, and each of the second conductive elements being provided so as to partially overlap the corresponding first conductive element; a plurality of connection elements corresponding one-to-one to the plurality of first conductive elements and the plurality of second conductive elements, each of the connection elements being used to electrically connect the corresponding first conductive element and the corresponding second conductive element to form the conductive path; the first conductive element includes a first end and a second end that are distributed opposite to each other along the extension direction thereof, and the second conductive element includes a third end and a fourth end that are distributed opposite to each other along the extension direction thereof; the first ends of the plurality of first conductive elements are electrically connected to the plurality of signal vias in one-to-one correspondence; For the first conductive element and the second conductive element corresponding to each other, one end of the connection element is electrically connected to the third end of the second conductive element, and the other end of the connection element is electrically connected to the second end of the first conductive element; the semiconductor chip further comprises a plurality of internal circuits corresponding one-to-one to the plurality of top metal wiring structures, each of the internal circuits being electrically connected to the conductive path of one of the corresponding top metal wiring structures; the semiconductor chip further comprises a plurality of lead wires corresponding one-to-one to the plurality of internal circuits, one end of each of the lead wires being electrically connected to one of the internal circuits, and the other end of each of the lead wires being electrically connected to only one of the first conductive elements in the top layer metal wiring structure; The semiconductor chip according to claim 1 .

3. A semiconductor device comprising: A substrate; a stacked structure disposed on the substrate, the stacked structure including N unit structures sequentially stacked and electrically connected along a third direction, each unit structure including four semiconductor chips according to claim 1, where N is a positive integer; The four semiconductor chips in the unit structure are stacked sequentially along the third direction, with a first semiconductor chip located in the bottom layer and a second semiconductor chip located thereon stacked face-to-face, the second semiconductor chip and a third semiconductor chip located thereon stacked back-to-back, and the third semiconductor chip and a fourth semiconductor chip located thereon stacked face-to-face, the axes of any two adjacent semiconductor chips in the stacked structure are aligned, and the first region of one semiconductor chip is aligned with the second region of the other semiconductor chip; A semiconductor device in which face-to-face refers to the top surfaces of two adjacent semiconductor chips facing each other, and back-to-back refers to the bottom surfaces of two adjacent semiconductor chips facing each other.

4. The semiconductor device further comprises: the signal transmission link group includes a plurality of pairs of signal transmission link groups, each of the plurality of pairs of signal transmission link groups corresponding one-to-one to a plurality of pairs of signal via groups of each of the semiconductor chips, the signal transmission link group including a plurality of signal transmission links, the plurality of signal transmission links in the signal transmission link group being independent of one another and all extending spirally along the third direction, the plurality of signal transmission links in each of the signal transmission link groups corresponding one-to-one to a plurality of the signal vias in the corresponding signal via group in each of the semiconductor chips, and each of the signal transmission links including one corresponding signal via in each of the semiconductor chips; In the two semiconductor chips stacked back to back, the plurality of signal vias of one of the semiconductor chips correspond one-to-one to the plurality of signal vias of the other semiconductor chip, and are in direct contact with and electrically connected to each other. The semiconductor device of claim 3 .

5. The semiconductor device further comprises: a plurality of pairs of bonding pillar groups, the bonding pillar groups being located only between the semiconductor chips stacked face-to-face and corresponding one-to-one to the plurality of pairs of signal via groups of the two semiconductor chips stacked face-to-face, and used to realize signal transmission between the semiconductor chips stacked face-to-face, each of the bonding pillar groups including a plurality of bonding pillars, each of which corresponds one-to-one to the plurality of signal vias of the two semiconductor chips stacked face-to-face; a plurality of pairs of signal transmission link groups corresponding one-to-one to the plurality of pairs of bonding pillar groups between each of the two semiconductor chips stacked face-to-face, the plurality of signal transmission links in each of the signal transmission link groups corresponding one-to-one to the plurality of bonding pillars of the plurality of pairs of bonding pillar groups, and each of the signal transmission links including one corresponding bonding pillar between the two semiconductor chips stacked face-to-face; The semiconductor device of claim 4 .

6. each of the semiconductor chips comprises a plurality of top metal wiring structures, the plurality of top metal wiring structures are all disposed on the top surface of the base, the plurality of top metal wiring structures are electrically connected to the plurality of signal via groups in one-to-one correspondence, each of the top metal wiring structures includes a plurality of conductive paths electrically connected to the plurality of signal vias in the corresponding signal via group in one-to-one correspondence, and each of the signal transmission links includes one corresponding signal via in each of the semiconductor chips and one corresponding conductive path; the top metal wiring structure includes a first conductive layer, a second conductive layer, and a plurality of connection elements, the first conductive layer being located on the top surface of the base, the first conductive layer including a plurality of first conductive elements arranged at intervals, the plurality of first conductive elements being arranged in the polygonal shape, and the plurality of first conductive elements being electrically connected to a plurality of the signal vias in the corresponding signal via groups in one-to-one correspondence; the second conductive layer being located on the first conductive layer, the second conductive layer including a plurality of second conductive elements arranged at intervals and in one-to-one correspondence with the plurality of first conductive elements, the plurality of second conductive elements being arranged in the polygonal shape, and each of the second conductive elements being partially overlapped with the corresponding first conductive element; the plurality of connection elements being in one-to-one correspondence with the plurality of first conductive elements and the plurality of second conductive elements, respectively, and each of the connection elements being used to electrically connect the corresponding first conductive element and the second conductive element to form the conductive path; the first conductive elements include first and second ends that are distributed opposite to each other along the extension direction thereof, the second conductive elements include third and fourth ends that are distributed opposite to each other along the extension direction thereof, the first ends of the plurality of first conductive elements are electrically connected to the plurality of signal vias in one-to-one correspondence, and for the first conductive elements and the second conductive elements that correspond to each other, one end of the connection element is electrically connected to the third end of the second conductive element, and the other end of the connection element is electrically connected to the second end of the first conductive element; For the two semiconductor chips stacked face-to-face, each of the plurality of pairs of bonding pillar groups corresponds one-to-one to a plurality of top layer metal wiring structures of the two semiconductor chips, and one end of each of the bonding pillars is electrically connected to the fourth end of a corresponding one of the second conductive elements in one of the semiconductor chips, and the other end of each of the bonding pillars is electrically connected to the fourth end of a corresponding one of the second conductive elements in another of the semiconductor chips; Each of the semiconductor chips further comprises: a plurality of internal circuits corresponding one-to-one to the plurality of top metal wiring structures, each of the internal circuits being electrically connected to one conductive path in the corresponding top metal wiring structure; a plurality of lead wires corresponding one-to-one to the plurality of internal circuits, one end of each of the lead wires being electrically connected to one of the internal circuits and the other end being electrically connected to only one of the first conductive elements in the corresponding top layer metal wiring structure; For each of the unit structures, one of the signal transmission links is electrically connected to only one of the lead wires of one of the semiconductor chips; The semiconductor device further comprises: an interface circuit disposed within the substrate and electrically connected to the plurality of pairs of signal transmission link groups, the interface circuit being used to transmit a plurality of control signals to the signal transmission link groups, each of which corresponds one-to-one with a plurality of the signal transmission links within the signal transmission link groups, and each of the control signals being drawn from only one of the lead wires within one of the semiconductor chips within each of the unit structures; For each pair of the signal via groups in one of the semiconductor chips, the interface circuit outputs a first control signal to the lead wire electrically connected to one of the signal vias in one of the signal via groups via one corresponding signal transmission link, and transmits a second control signal different from the first control signal to the lead wire electrically connected to one of the signal vias in another of the signal via groups via another corresponding signal transmission link. The semiconductor device of claim 5 .

7. 1. A method of forming a semiconductor device, comprising: Providing a substrate; forming a semiconductor chip, the semiconductor chip including: a base; and a plurality of pairs of signal via groups independent of each other; the base including a top surface and a bottom surface opposite the top surface; each of the signal via groups being arranged at intervals within the base; two of the signal via groups of each pair being distributed symmetrically with respect to one axis on the top surface of the base, and being distributed in a first region and a second region on both sides of the axis, respectively; the axis being parallel to a first direction or a second direction; each of the signal via groups including a plurality of signal vias arranged in a polygonal shape; any two of the signal vias in each of the signal via groups being electrically insulated; each of the signal vias penetrating the base along a third direction; the first direction and the second direction being perpendicular to each other and both parallel to the top surface; forming a stacked structure on the substrate based on the plurality of semiconductor chips, the stacked structure including N unit structures stacked sequentially along the third direction and electrically connected, each of the unit structures including four of the semiconductor chips, the four semiconductor chips in the unit structure being stacked sequentially along the third direction, a first semiconductor chip located at the bottom layer and a second semiconductor chip located thereon being stacked face to face, the second semiconductor chip and a third semiconductor chip located thereon being stacked back to back, and the third semiconductor chip and a fourth semiconductor chip located thereon being stacked face to face, and N is a positive integer; the axes of any two adjacent semiconductor chips in the stacked structure are aligned, and the first region of one semiconductor chip is aligned with the second region of the other semiconductor chip; "Face-to-face" refers to the top surfaces of two adjacent semiconductor chips facing each other, and "back-to-back" refers to the bottom surfaces of two adjacent semiconductor chips facing each other; Forming a semiconductor chip includes: forming a base, the base defining the first region and the second region on opposite sides of the axis; forming the signal via group penetrating the base along the third direction in the first region and the second region; A method for forming a semiconductor device, comprising: forming a plurality of top metal wiring structures on a top surface of the base, the plurality of top metal wiring structures being electrically connected in one-to-one correspondence with a plurality of the signal via groups, and each of the top metal wiring structures including a plurality of conductive paths being electrically connected in one-to-one correspondence with a plurality of the signal vias in the corresponding signal via group.

8. forming a top metal wiring structure on the top surface of the base; forming a first conductive layer on the top surface of the base, the first conductive layer including a plurality of first conductive elements arranged at intervals, the plurality of first conductive elements being arranged in the polygonal shape, the first conductive elements including first end portions and second end portions oppositely distributed along an extension direction thereof, the first end portions of the plurality of first conductive elements being electrically connected in one-to-one correspondence with the plurality of signal vias in the corresponding signal via group; forming a second conductive layer on the first conductive layer, the second conductive layer including a plurality of second conductive elements arranged at intervals and corresponding one-to-one to a plurality of the first conductive elements, the plurality of second conductive elements being arranged in the polygonal shape, the second conductive elements including third and fourth ends distributed opposite to each other along an extension direction thereof, and each of the second conductive elements being provided so as to partially overlap the corresponding first conductive element; forming a connection element between the first conductive layer and the second conductive layer, wherein for each of the first conductive element and the second conductive element corresponding to each other, one end of the connection element is electrically connected to the third end of the second conductive element and the other end of the connection element is electrically connected to the second end of the first conductive element to form the conductive path; forming a stacked structure on the substrate based on the plurality of semiconductor chips, providing four of said semiconductor chips; disposing a first semiconductor chip on the substrate; stacking a second semiconductor chip face-to-face on the first semiconductor chip; stacking a third semiconductor chip back-to-back on the second semiconductor chip; stacking a fourth semiconductor chip face-to-face on the third semiconductor chip to form the unit structure including the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip; and repeatedly performing the above process on the formed unit structure to sequentially form N unit structures stacked along the third direction, the axes of any two adjacent semiconductor chips in the stacked structure are aligned, and the first region of one semiconductor chip is aligned with the second region of the other semiconductor chip; Stacking the second semiconductor chip face-to-face on the first semiconductor chip includes: forming a bonding pillar group on the top metal wiring structure of the first semiconductor chip, the bonding pillar group including a plurality of bonding pillars, a lower end of each of the bonding pillars being bonded to the fourth end of one of the second conductive elements in the first semiconductor chip; an upper end of the bonding pillar is bonded to the top metal wiring structure of the second semiconductor chip, and an upper end of the bonding pillar is bonded to the fourth end of one of the second conductive elements in the second semiconductor chip; Stacking a third semiconductor chip back-to-back on the second semiconductor chip includes: direct contact or direct electrical connection of a plurality of the signal vias located in the second semiconductor chip with a corresponding plurality of the signal vias located in the third semiconductor chip; The semiconductor chip further includes a plurality of internal circuits, the plurality of internal circuits corresponding one-to-one to the plurality of top layer metal wiring structures, and the method for forming the semiconductor device includes: forming leads between the internal circuits and the corresponding top metal wiring structure, such that each of the internal circuits is electrically connected to one conductive path in the corresponding top metal wiring structure; The method for forming a semiconductor device comprises: forming an interface circuit within the substrate; electrically connecting any two adjacent semiconductor chips in the stacked structure to form a plurality of pairs of signal transmission link groups corresponding one-to-one to the plurality of pairs of signal via groups of each of the semiconductor chips, each of the signal transmission link groups including a plurality of signal transmission links, each of the signal transmission links including one corresponding signal via in each of the semiconductor chips, one corresponding conductive path in each of the semiconductor chips, and one corresponding bonding pillar between two semiconductor chips stacked face-to-face; The method further includes electrically connecting the interface circuit to a plurality of pairs of signal via groups in the semiconductor chip located in the lowest layer of the stacked structure, and electrically connecting the interface circuit to a plurality of pairs of the signal transmission link groups to transmit a plurality of control signals to the signal transmission link groups, each of which corresponds one-to-one with a plurality of the signal transmission links in the signal transmission link groups, wherein each of the control signals is drawn to one corresponding internal circuit via only one of the lead wires in one of the semiconductor chips in each of the unit structures, and for each pair of the signal via groups in one of the semiconductor chips, the interface circuit is further used to output a first control signal to the lead wire electrically connected to one of the signal vias in one of the signal via groups via one corresponding signal transmission link, and to transmit a second control signal different from the first control signal to the lead wire electrically connected to one of the signal vias in another corresponding signal via link. The method for forming a semiconductor device according to claim 7.

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