Semiconductor Module

Abstract

To preferably reduce radiation noise of a semiconductor module.SOLUTION: A semiconductor module having a P-side arm circuit and an N-side arm circuit, comprises a plurality of wiring patterns in which high voltage-side P terminals and low voltage-side N terminals are separated from each other, and transistors and diodes connected in parallel in the P-side arm circuit and N-side arm circuit. The plurality of wiring patterns include a first wiring pattern, a second wiring pattern, and a third wiring pattern. The P terminals are connected to the first wiring pattern and the N terminals are connected to the second wiring pattern. Anode electrodes of the diodes of the N-side arm circuit are arranged above the second wiring pattern and connected to the second wiring pattern, and anode terminals of the diodes of the P-side arm circuit are arranged above the third wiring pattern and connected to the third wiring pattern.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module. [Background technology]

[0002] Conventionally, semiconductor modules incorporating semiconductor chips such as IGBTs (Insulated Gate Bipolar Transistors) have been plagued by the problem of high-frequency common-mode currents being generated due to imbalances in ground capacitance, resulting in radiation noise. Semiconductor modules that reduce radiation noise are known (see, for example, Patent Documents 1-3). It is also known that the parasitic components of semiconductor modules can be considered as bridge circuits (see, for example, References 1-3). Patent Document 1 Patent No. 6053668 Patent Document 2 Patent No. 6169250 Patent Document 3: Japanese Patent Application Laid-Open No. 2007-181351 Reference 1: Atsuhiro Takahashi and five others, "Common-mode noise reduction of power converters using impedance balance method," Institute of Electronics, Information and Communication Engineers, Environmental Electromagnetic Engineering Study Group, July 11, 2013, IEICE-113, no. 122, pp. 45-50 Reference 2: Chiharu Kyotani and six others, "A Study on Reduction of Common-Mode Conducted Noise in the MHz Band in a Synchronous Rectification DC-DC Buck Converter," Institute of Electrical Engineers of Japan, December 11, 2020, Vol. 2020, No. 57, pp. 73-78 Reference 3: Nishimoto, Taiki, and four others, "Common-mode noise reduction using impedance balancing method for asymmetric switching power supply circuits," IEICE Transactions on Electronics, Information and Communication Engineers, Vol. J102-B, No. 3, pp. 184-193, March 1, 2019 Summary of the Invention [Problem to be solved by the invention]

[0003] It is preferable to reduce radiation noise in a semiconductor module. [Means for solving the problem]

[0004] To solve the above problem, one aspect of the present invention provides a semiconductor module. The semiconductor module may have a P-side arm circuit and an N-side arm circuit. The semiconductor module may include a P-terminal on a high-voltage side. The semiconductor module may include an N-terminal on a low-voltage side. The semiconductor module may include multiple wiring patterns. The multiple wiring patterns may be separated from each other. The semiconductor module may include a transistor and a diode. The transistor and diode may be connected in parallel in the P-side arm circuit and the N-side arm circuit, respectively. The multiple wiring patterns may include a first wiring pattern, a second wiring pattern, and a third wiring pattern. The P-terminal may be connected to the first wiring pattern. The N-terminal may be connected to the second wiring pattern. The anode electrode of the diode in the N-side arm circuit may be arranged above the second wiring pattern and connected to the second wiring pattern. The anode electrode of the diode in the P-side arm circuit may be arranged above the third wiring pattern and connected to the third wiring pattern.

[0005] The collector electrode of the transistor in the P-side arm circuit may be disposed above the first wiring pattern and connected to the first wiring pattern.

[0006] The collector electrode of the transistor in the N-arm circuit may be disposed above a wiring pattern different from the first wiring pattern and connected to that wiring pattern.

[0007] The collector electrode of the transistor in the N-side arm circuit may be disposed above the third wiring pattern and connected to the third wiring pattern.

[0008] The semiconductor module may include a plurality of wires, one of which may connect the cathode electrode of the diode in the N-side arm circuit to the third wiring pattern.

[0009] The area of ​​the first wiring pattern in top view and the area of ​​the second wiring pattern in top view may be approximately equal.

[0010] The total number of transistor and diode chips provided in the first wiring pattern may be the same as the total number of transistor and diode chips provided in the second wiring pattern.

[0011] The total number of transistor and diode chips provided on the first wiring pattern may be 1. The total number of transistor and diode chips provided on the second wiring pattern may be 1.

[0012] One transistor may be provided on the first wiring pattern, and one diode may be provided on the second wiring pattern.

[0013] The semiconductor module may include a chip capacitor that may be provided across the first wiring pattern and the second wiring pattern.

[0014] The semiconductor module may include an output terminal, which may output a voltage to the outside, and which may be connected to the third wiring pattern.

[0015] The semiconductor module may include a base substrate. The base substrate may have one end edge and the other end edge facing each other. The semiconductor module may include two insulating substrates. The insulating substrate may be provided above the base substrate. The P terminal and the N terminal may be provided on one end edge. The output terminal may be provided on the other end edge. The second wiring pattern may include a fourth wiring pattern and a fifth wiring pattern. The fourth wiring pattern may be provided above the insulating substrate on the other end edge of the two insulating substrates. The fifth wiring pattern may be provided above the insulating substrate on one end edge of the two insulating substrates. The anode electrode of the diode in the N-side arm circuit may be disposed above the fourth wiring pattern and connected to the fourth wiring pattern. The fifth wiring pattern may be connected to the fourth wiring pattern and the N terminal.

[0016] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a diagram illustrating an example of a semiconductor module 100 according to a comparative example. [Figure 2] 1 is a diagram illustrating an example of a semiconductor module 100 as viewed from above. [Figure 3] 1 is a diagram illustrating an example of a circuit configuration of a semiconductor module 100. FIG. [Figure 4] 3 is a diagram illustrating an example of parasitic components of the semiconductor module 100. FIG. [Figure 5] 1 is a diagram illustrating an example of a semiconductor module 200 according to an embodiment. [Figure 6] 2 is a diagram illustrating an example of a semiconductor module 200 as viewed from above. FIG. [Figure 7] 1 is a diagram illustrating an example of a semiconductor module 300 according to an embodiment. [Figure 8] 1 is a diagram illustrating an example of a semiconductor module 400 according to an embodiment. [Figure 9]1 is a diagram illustrating an example of a semiconductor module 500 according to an embodiment. [Figure 10] FIG. 1 is a diagram illustrating an example of a semiconductor module 600 according to a comparative example. [Figure 11] 7 is a diagram illustrating an example of a semiconductor module 700 according to an embodiment. [Figure 12] 1 is a diagram illustrating an example of a semiconductor module 800 according to an embodiment. [Figure 13] 1 is a diagram illustrating an example of a semiconductor module 900 according to an embodiment. [Figure 14] 1 is a diagram illustrating an example of a semiconductor module 1000 according to an embodiment. [Figure 15] FIG. 1 illustrates an example of a semiconductor module 1100 according to an embodiment. [Figure 16] FIG. 1 illustrates an example of a semiconductor module 1200 according to an embodiment. [Figure 17] FIG. 6 is a diagram showing in detail the arrangement of the diodes 30 in FIG. 5. [Figure 18] FIG. 10 is a diagram showing in detail the arrangement of chip capacitors 94 in FIG. 9. DETAILED DESCRIPTION OF THE INVENTION

[0018] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification and drawings, elements having substantially the same function and configuration are designated by the same reference numerals to avoid redundant description, and elements not directly related to the present invention are not shown. Furthermore, in a single drawing, elements having the same function and configuration may be designated by the same reference numeral, and the reference numerals may be omitted for other elements.

[0019] In this specification, one side in a direction parallel to the depth direction of a semiconductor chip is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor module is mounted.

[0020] In this specification, technical matters may be described using orthogonal coordinate axes, i.e., the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit specific directions. For example, the Z-axis does not limit the height direction relative to the ground. The +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is referred to without specifying positive or negative, it means a direction parallel to the +Z-axis and the -Z-axis. In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor chip are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the top and bottom surfaces of the semiconductor chip is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor chip, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0021] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0022] Fig. 1 is a diagram showing an example of a semiconductor module 100 according to a comparative example. The semiconductor module 100 may function as a power conversion device such as an inverter. In Fig. 1, the semiconductor module 100 includes a base substrate 20, an insulating substrate 21, a plurality of wiring patterns 26, a plurality of wires 28, a plurality of diodes 30, a plurality of transistors 40, a P terminal 70, and an N terminal 80. In Fig. 1, the semiconductor module 100 is shown schematically.

[0023] The semiconductor module 100 includes one or more insulating substrates 21. A predetermined wiring pattern 26 is provided on one surface of the insulating substrate 21, and a base substrate 20 is provided on the other surface of the insulating substrate 21. The insulating substrate 21 is, for example, made of silicon nitride ceramics or aluminum nitride ceramics. The wiring pattern 26 is, for example, a copper plate or an aluminum plate. The wiring pattern 26 may be formed by bonding a plated copper plate or aluminum plate to the insulating substrate 21 directly or via a brazing layer. The base substrate 20 is, for example, a copper plate. A cooler may be provided on the underside of the base substrate 20.

[0024] A transistor 40 or a diode 30 is provided on the wiring pattern 26. The transistor 40 and the diode 30 are each an example of a semiconductor chip. The transistor 40 or the diode 30 is provided on the upper surface of the wiring pattern 26. A bonding material (not shown) such as solder may be provided between the transistor 40 or the diode 30 and the wiring pattern 26. The transistor 40 or the diode 30 may also be protected by a sealing resin (not shown).

[0025] In this example, the transistor 40 is an IGBT. The transistor 40 is a vertical chip. The transistor 40 has an emitter electrode 42 and a collector electrode 44. In FIG. 1, the emitter electrode 42 is formed on the top surface of the transistor 40. Also in FIG. 1, the collector electrode 44 is formed on the bottom surface of the transistor 40. The transistor 40 is connected to the wiring pattern 26 by an electrode formed on the bottom surface, and is connected to the wire wiring 28 by an electrode formed on the top surface. The transistor 40 may also be a MOS transistor. The wire wiring 28 may be formed by wire bonding. For example, the wire wiring 28 is made of copper, aluminum, or the like.

[0026] In this example, the diode 30 is a free wheel diode (FWD). The diode 30 is a vertical chip. The diode 30 has an anode electrode 32 and a cathode electrode 34. In FIG. 1, the anode electrode 32 is formed on the top surface of the diode 30. Also in FIG. 1, the cathode electrode 34 is formed on the bottom surface of the diode 30. The diode 30 is connected to the wiring pattern 26 by an electrode formed on the bottom surface, and is connected to the wire interconnection 28 by an electrode formed on the top surface.

[0027] The semiconductor module 100 includes a P terminal 70 and an N terminal 80. The P terminal 70 is a high-voltage side terminal. The P terminal 70 is provided on the wiring pattern 26. The N terminal 80 is a low-voltage side terminal. The N terminal 80 is provided on the wiring pattern 26. The P terminal 70 and the N terminal 80 may be made of a conductive material such as copper.

[0028] Fig. 2 is a diagram illustrating an example of a semiconductor module 100 as viewed from above. Fig. 2 illustrates the arrangement of a base substrate 20, an insulating substrate 21, a wiring pattern 26, wire interconnections 28, a diode 30, a transistor 40, a P terminal 70, an N terminal 80, and an output terminal 90 as viewed from above.

[0029] The wiring pattern 26 includes a plurality of wiring patterns that are separated from one another. In FIG. 2, the wiring pattern 26 includes a wiring pattern 26-1, a wiring pattern 26-2, and a wiring pattern 26-3. The wiring pattern 26-1 is an example of a first wiring pattern. The wiring pattern 26-2 is an example of a second wiring pattern. The wiring pattern 26-3 is an example of a third wiring pattern. The P terminal 70 is provided on the wiring pattern 26-1 and is connected to the wiring pattern 26-1. The N terminal 80 is provided on the wiring pattern 26-2 and is connected to the wiring pattern 26-2.

[0030] The semiconductor module 100 includes an output terminal 90. The semiconductor module 100 outputs a predetermined voltage to the outside via the output terminal 90. The output terminal 90 may output a voltage to the outside. The output terminal 90 is provided on the wiring pattern 26-3. The output terminal 90 is connected to the wiring pattern 26-3. The output terminal 90 may be a conductive material such as copper. Note that the output terminal 90 is omitted from FIG. 1.

[0031] In FIG. 2, the transistor 40 includes a transistor 40-1 and a transistor 40-2. The transistor 40-1 is provided above the wiring pattern 26-1. The transistor 40-1 may be provided on the wiring pattern 26-1. In this example, the collector electrode 44 of the transistor 40-1 is connected to the wiring pattern 26-1. Also, in this example, the emitter electrode 42 of the transistor 40-1 is exposed in a top view. In FIG. 2, the emitter electrode 42 of the transistor 40 is represented by "E." The emitter electrode 42 of the transistor 40-1 is connected to the wiring pattern 26-3 via the wire wiring 28. A plurality of transistors 40-1 may be provided.

[0032] The transistor 40-2 is provided above the wiring pattern 26-3. The transistor 40-2 may be provided on the wiring pattern 26-3. In this example, the collector electrode 44 of the transistor 40-2 is connected to the wiring pattern 26-3. In this example, the emitter electrode 42 of the transistor 40-2 is exposed in a top view. The emitter electrode 42 of the transistor 40-2 is connected to the wiring pattern 26-2 via the wire 28 and the anode electrode 32 of the diode 30-2. A plurality of transistors 40-2 may be provided.

[0033] A gate electrode may be provided on the upper surface of the transistor 40. The gate electrode of the transistor 40 may be connected to a gate terminal (not shown in FIGS. 1 and 2) via a wire interconnection 28 or the like.

[0034] In FIG. 2, the diode 30 includes a diode 30-1 and a diode 30-2. The diode 30-1 is provided above the wiring pattern 26-1. The diode 30-1 may be provided on the wiring pattern 26-1. In this example, the cathode electrode 34 of the diode 30-1 is connected to the wiring pattern 26-1. In this example, the anode electrode 32 of the diode 30-1 is exposed in a top view. In FIG. 2, the anode electrode 32 of the diode 30 is represented by "A." The anode electrode 32 of the diode 30-1 is connected to the wiring pattern 26-3 via the wire 28. A guard ring 96 is formed on the top surface of the diode 30. The guard ring 96 is provided to ensure a breakdown voltage. The guard ring 96 may be provided to surround the anode electrode 32. A plurality of diodes 30-1 may be provided.

[0035] The diode 30-2 is provided above the wiring pattern 26-3. The diode 30-2 may be provided on the wiring pattern 26-3. In this example, the cathode electrode 34 of the diode 30-2 is connected to the wiring pattern 26-3. In this example, the anode electrode 32 of the diode 30-2 is exposed in top view. The anode electrode 32 of the diode 30-2 is connected to the wiring pattern 26-2 via the wire 28. A plurality of diodes 30-2 may be provided.

[0036] FIG. 3 is a diagram showing an example of a circuit configuration of the semiconductor module 100. In FIG. 3, gate terminals 50 and 51 are shown as gate terminals. The semiconductor module 100 has a P-side arm circuit 72 and an N-side arm circuit 82. The P-side arm circuit 72 is an arm circuit provided on the P-terminal 70 side. The P-side arm circuit 72 is composed of a transistor 40-1 and a diode 30-1. The N-side arm circuit 82 is an arm circuit provided on the N-terminal 80 side. The N-side arm circuit 82 is composed of a transistor 40-2 and a diode 30-2. In each of the P-side arm circuit 72 and the N-side arm circuit 82, the transistor 40 and the diode 30 are connected in parallel.

[0037] The collector electrode 44 of the transistor 40-1 is connected to the P terminal 70. The emitter electrode 42 of the transistor 40-1 is connected to the output terminal 90. The gate electrode of the transistor 40-1 is connected to the gate terminal 50. A gate voltage is applied between the gate terminal 50 and the output terminal 90.

[0038] The collector electrode 44 of the transistor 40-2 is connected to the output terminal 90. The emitter electrode 42 of the transistor 40-2 is connected to the N terminal 80. The gate electrode of the transistor 40-2 is connected to the gate terminal 51. A gate voltage is applied between the gate terminal 51 and the N terminal 80.

[0039] The cathode electrode 34 of the diode 30-1 is connected to the P terminal 70. The anode electrode 32 of the diode 30-1 is connected to the output terminal 90.

[0040] The cathode electrode 34 of the diode 30-2 is connected to the output terminal 90. The anode electrode 32 of the diode 30-2 is connected to the N terminal 80.

[0041] FIG. 4 is a diagram showing an example of the parasitic components of the semiconductor module 100. As shown in FIG. 4, the parasitic components of the semiconductor module 100 can be considered as a bridge circuit (see References 1-3). The P terminal 70 and wiring pattern 26-1 are defined as the P line. The N terminal 80 and wiring pattern 26-2 are defined as the N line. The parasitic inductance of the P line is defined as Lp, and the stray capacitance between the P line and ground (such as the base substrate 20) is defined as Cp. The parasitic inductance of the N line is defined as Ln, and the stray capacitance between the N line and ground (such as the base substrate 20) is defined as Cn. The voltage when the transistor 40, etc. is switched is defined as Vn, and the stray capacitance of the transistor 40, etc. is defined as Coss. A predetermined impedance is defined as Z.

[0042] In this bridge circuit, a through current flows through the stray capacitance Coss with each switching operation. This through current generates a common-mode current that flows through the resistance component R. This common-mode current is a cause of radiated noise. When the bridge balance condition (Equation 1 below) is met, the generation of common-mode current is suppressed, and radiated noise can be reduced. (Number 1) Lp Cp = Ln Cn

[0043] While Lp and Ln are relatively easy to adjust, Cp and Cn are more difficult to adjust than Lp and Ln. In FIG. 2, the area of ​​wiring pattern 26-1 in top view is larger than the area of ​​wiring pattern 26-2 in top view. Therefore, Cp >> Cn is often the case, and it is difficult to hold true the formula 1. This makes it difficult to reduce the radiation noise.

[0044] Fig. 5 is a diagram showing an example of a semiconductor module 200 according to an embodiment, which differs from the semiconductor module 100 in Fig. 1 in that the anode electrode 32 of the diode 30 in Fig. 5 is formed on the bottom surface.

[0045] 5, the anode electrode 32 is formed on the bottom surface of the diode 30. Also in FIG. 5, the cathode electrode 34 is formed on the top surface of the diode 30. The diode 30 is connected to the wiring pattern 26 by the electrode formed on the bottom surface, and is connected to the wire 28 by the electrode formed on the top surface.

[0046] Fig. 6 is a diagram showing an example of a semiconductor module 200 as viewed from above. Fig. 6 shows the arrangement of a base substrate 20, an insulating substrate 21, a wiring pattern 26, wire interconnections 28, a diode 30, a transistor 40, a P terminal 70, an N terminal 80, and an output terminal 90 as viewed from above. Description of the same configuration in Fig. 6 as in Fig. 2 will be omitted.

[0047] The transistor 40-1 is provided above the wiring pattern 26-1. The transistor 40-1 may be provided on the wiring pattern 26-1. In this example, the collector electrode 44 of the transistor 40-1 is connected to the wiring pattern 26-1. In this example, the emitter electrode 42 of the transistor 40-1 is exposed in a top view. The emitter electrode 42 of the transistor 40-1 is connected to the wiring pattern 26-3 via the wire 28.

[0048] The transistor 40-2 is provided above the wiring pattern 26-3. The transistor 40-2 may be provided on the wiring pattern 26-3. In this example, the collector electrode 44 of the transistor 40-2 is connected to the wiring pattern 26-3. In this example, the emitter electrode 42 of the transistor 40-2 is exposed in a top view. The emitter electrode 42 of the transistor 40-2 is connected to the wiring pattern 26-2 via the wire 28.

[0049] The diode 30-1 is provided above the wiring pattern 26-3. The diode 30-1 may be provided on the wiring pattern 26-3. In this example, the anode electrode 32 of the diode 30-1 is connected to the wiring pattern 26-3. In this example, the cathode electrode 34 of the diode 30-1 is exposed in top view. In FIG. 6, the cathode electrode 34 of the diode 30-1 is represented by "K." The cathode electrode 34 of the diode 30-1 is connected to the wiring pattern 26-1 via the wire 28.

[0050] The diode 30-2 is provided above the wiring pattern 26-2. The diode 30-2 may be provided on the wiring pattern 26-2. In this example, the anode electrode 32 of the diode 30-2 is connected to the wiring pattern 26-2. In this example, the cathode electrode 34 of the diode 30-2 is exposed in top view. The cathode electrode 34 of the diode 30-2 is connected to the wiring pattern 26-3 via the wire 28.

[0051] The circuit configuration of the semiconductor module 200 is the same as the circuit configuration of the semiconductor module 100 in Fig. 3. That is, the semiconductor module 200 has a P-side arm circuit 72 and an N-side arm circuit 82. The P-side arm circuit 72 is configured with a transistor 40-1 and a diode 30-1. The N-side arm circuit 82 is configured with a transistor 40-2 and a diode 30-2.

[0052] In this example, the anode electrode 32 of the diode 30-2 in the N-arm circuit 82 is disposed above the wiring pattern 26-2 and connected to the wiring pattern 26-2. The anode electrode 32 of the diode 30-1 in the P-arm circuit 72 is disposed above the wiring pattern 26-3 and connected to the wiring pattern 26-3. This configuration allows the area of ​​the wiring pattern 26-1 and the area of ​​the wiring pattern 26-2 in the top view to be approximately equal. Therefore, Cp = Cn, and by adjusting Lp and Ln, Equation 1 can be established. This makes it possible to reduce radiated noise. Radiated noise can be reduced simply by replacing the diode 30, without installing additional components in the semiconductor module 200.

[0053] The collector electrode 44 of the transistor 40-1 in the P-arm circuit 72 may be arranged above the wiring pattern 26-1 and connected to the wiring pattern 26-1. The collector electrode 44 of the transistor 40-2 in the N-arm circuit 82 may be arranged above a wiring pattern different from the wiring pattern 26-1 and connected to that wiring pattern. In this example, the collector electrode 44 of the transistor 40-2 in the N-arm circuit 82 is arranged above the wiring pattern 26-3 and connected to the wiring pattern 26-3. By arranging the transistors 40-1 and 40-2 in this manner, the circuit configuration of the semiconductor module 200 can be made the same as that in FIG. 3.

[0054] The wire 28 may connect the cathode electrode 34 of the diode 30-2 in the N-arm circuit 82 to the wiring pattern 26-3. The wire 28 may connect the cathode electrode 34 of the diode 30-1 in the P-arm circuit 72 to the wiring pattern 26-1. By arranging the wire 28 in this manner, the circuit configuration of the semiconductor module 200 can be made the same as that shown in FIG.

[0055] The total number of transistor 40 and diode 30 chips provided on the wiring pattern 26-1 may be the same as the total number of transistor 40 and diode 30 chips provided on the wiring pattern 26-2. In this example, the total number of transistor 40 and diode 30 chips provided on the wiring pattern 26-1 is one. In FIG. 6, one transistor 40-1 is provided on the wiring pattern 26-1. Also, in this example, the total number of transistor 40 and diode 30 chips provided on the wiring pattern 26-2 is one. In FIG. 6, one diode 30-2 is provided on the wiring pattern 26-2. By making the total number of transistor 40 and diode 30 chips the same for the wiring pattern 26-1 and the wiring pattern 26-2, it becomes easy to make the area of ​​the wiring pattern 26-1 in a top view equal to the area of ​​the wiring pattern 26-2 in a top view.

[0056] FIG. 7 is a diagram illustrating an example of a semiconductor module 300 according to an embodiment. FIG. 7 illustrates the semiconductor module 300 in a top view. In FIG. 7, the semiconductor module 300 includes a resin case 10, an insulating substrate 21, a plurality of wiring patterns 26, a plurality of wires 28, a plurality of diodes 30, a plurality of transistors 40, a P terminal 70, an N terminal 80, and an output terminal 90. In the semiconductor module 300, descriptions of the same reference numerals as those in the semiconductor modules 100 and 200 are omitted. The circuit configuration of the semiconductor module 300 is the same as that of the semiconductor modules 100 and 200. A base substrate may be provided below the insulating substrate 21. In the semiconductor module 300, the total number of chips for the transistors 40 and the diodes 30 can be made the same for the wiring patterns 26-1 and 26-2, making it easy to make the area of ​​the wiring pattern 26-1 in a top view equal to the area of ​​the wiring pattern 26-2 in a top view.

[0057] Resin case 10 is provided to surround a space that houses transistor 40 or diode 30. Insulating substrate 21 may be provided below resin case 10. In this example, resin case 10 is molded from a resin such as a thermosetting resin that can be formed by injection molding or an ultraviolet-curing resin that can be formed by UV molding. The resin may include one or more polymer materials selected from, for example, polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, polyamide (PA) resin, acrylonitrile butadiene styrene (ABS) resin, and acrylic resin. Furthermore, P terminal 70, N terminal 80, and output terminal 90 are provided in resin case 10.

[0058] A capacitor 92 is provided outside the semiconductor module 300. The capacitor 92 is provided to protect the circuit of the semiconductor module 300. The capacitor 92 may be provided between the P terminal 70 and the N terminal 80. Considering the parasitic inductance in this case, the parasitic inductance component extends up to the position where the capacitor 92 is provided. Therefore, Lp and Ln in equation 1 may differ significantly, making it difficult to establish equation 1.

[0059] Fig. 8 is a diagram illustrating an example of a semiconductor module 400 according to an embodiment. The semiconductor module 400 in Fig. 8 differs from the semiconductor module 300 in Fig. 7 in that it includes a chip capacitor 94. Other configurations of the semiconductor module 400 in Fig. 8 may be the same as those of the semiconductor module 300 in Fig. 7.

[0060] The chip capacitor 94 is provided above the wiring pattern 26. The chip capacitor 94 may be provided above the wiring pattern 26-1. The chip capacitor 94 may be provided on the wiring pattern 26-1. The chip capacitor 94 may be provided above the wiring pattern 26-2. The chip capacitor 94 may be provided on the wiring pattern 26-2. The chip capacitor 94 may be provided across the wiring patterns 26-1 and 26-2. The chip capacitor 94 is provided to protect the circuit of the semiconductor module 400. Although omitted in FIG. 8, a capacitor 92 may be provided externally, as in FIG. 7.

[0061] It is preferable that the impedance of chip capacitor 94 be sufficiently smaller than the impedance of the circuit upstream of chip capacitor 94 in the radiated noise band. Therefore, the circuit upstream of chip capacitor 94 can be considered short-circuited at high frequencies, and the area that forms the bridge circuit can be limited to the area downstream of chip capacitor 94. This makes it easier to establish equation 1, making it possible to reduce radiated noise.

[0062] 9 is a diagram illustrating an example of a semiconductor module 500 according to an embodiment. The semiconductor module 500 in FIG. 9 differs from the semiconductor module 400 in FIG. 8 in the arrangement of chip capacitors 94. The semiconductor module 500 in FIG. 9 also differs from the semiconductor module 400 in FIG. 8 in the number of transistor 40 chips. Other configurations of the semiconductor module 500 in FIG. 9 may be the same as those of the semiconductor module 400 in FIG. 8.

[0063] The plurality of transistors 40-1 may be provided above the wiring pattern 26-1. In this example, two transistors 40-1 are provided above the wiring pattern 26-1. The two transistors 40-1 may be provided on the wiring pattern 26-1. In this example, the collector electrodes 44 of the two transistors 40-1 are connected to the wiring pattern 26-1. Also, in this example, the emitter electrodes 42 of the two transistors 40-1 are exposed in a top view. In FIG. 9, the emitter electrodes 42 of the two transistors 40-1 are connected to the wiring pattern 26-3 via one wire 28.

[0064] The plurality of transistors 40-2 may be provided above the wiring pattern 26-3. In this example, two transistors 40-2 are provided above the wiring pattern 26-3. The two transistors 40-2 may be provided on the wiring pattern 26-3. In this example, the collector electrodes 44 of the two transistors 40-2 are connected to the wiring pattern 26-3. Also, in this example, the emitter electrodes 42 of the two transistors 40-2 are exposed in a top view. In FIG. 9, the emitter electrodes 42 of the two transistors 40-2 are connected to the wiring pattern 26-2 via one wire 28.

[0065] The chip capacitor 94 may be provided above the wiring pattern 26-2. The chip capacitor 94 may be provided on the wiring pattern 26-2. The chip capacitor 94 does not have to be provided above the wiring pattern 26-1. The chip capacitor 94 may be connected to the wiring pattern 26-1 via the wire 28.

[0066] In this example, the total number of chips of the transistors 40, diodes 30, and chip capacitors 94 provided on the wiring pattern 26-1 is the same as the total number of chips of the transistors 40, diodes 30, and chip capacitors 94 provided on the wiring pattern 26-2. In this example, the total number of chips of the transistors 40, diodes 30, and chip capacitors 94 provided on the wiring pattern 26-1 is two. In FIG. 9, two transistors 40-1 are provided on the wiring pattern 26-1. In this example, the total number of chips of the transistors 40, diodes 30, and chip capacitors 94 provided on the wiring pattern 26-2 is also two. In FIG. 9, one diode 30-2 and one chip capacitor 94 are provided on the wiring pattern 26-2. By making the total number of chips of the transistors 40, diodes 30, and chip capacitors 94 the same for the wiring pattern 26-1 and the wiring pattern 26-2, it is easy to make the area of ​​the wiring pattern 26-1 in a top view equal to the area of ​​the wiring pattern 26-2 in a top view. 8, there may be one transistor 40 on wiring pattern 26-1 and one transistor on wiring pattern 26-3. In this case, there is one transistor 40 on wiring pattern 26-1, one transistor 40 and one diode 30 on wiring pattern 26-3, and one diode 30 and one chip capacitor 94 on wiring pattern 26-2. Since the planar area of ​​the diode 30 and the chip capacitor 94 is often smaller than that of the transistor 40, there is one element on wiring pattern 26-1 and two elements on wiring pattern 26-2, but this makes it easier to equalize the planar areas of wiring pattern 26-1 and wiring pattern 26-2.

[0067] Fig. 10 is a diagram illustrating an example of a semiconductor module 600 according to a comparative example. Fig. 10 illustrates the arrangement of a base substrate 20, an insulating substrate 21, wire interconnections 28, a diode 30, a wiring pattern 36, a transistor 40, a P-terminal 70, an N-terminal 80, and an output terminal 90 in a top view. The P-side arm circuit of the semiconductor module 600 is composed of three transistors 40-1 and three diodes 30-1. The N-side arm circuit of the semiconductor module 600 is composed of three transistors 40-2 and three diodes 30-2.

[0068] The base substrate 20 has an edge 22 in a top view. The base substrate 20 of this example has an edge 22-1 (an example of one edge) and an edge 22-2 (an example of the other edge) that face each other in a top view. In FIG. 1, the edge 22-1 and the edge 22-2 face each other in the Y-axis direction. The edge 22-1 is provided on the positive side of the Y-axis direction. On the other hand, the edge 22-2 is provided on the negative side of the Y-axis direction.

[0069] In this example, the semiconductor module 600 includes two insulating substrates 21 (insulating substrate 21-1, insulating substrate 21-2). A predetermined wiring pattern 36 is provided on one surface of each insulating substrate 21. A base substrate 20 is provided on the other surface of each insulating substrate 21. Each insulating substrate 21 may be provided above the base substrate 20. Of the two insulating substrates 21, insulating substrate 21-1 is provided on the edge 22-1 side. "Provided on the edge 22-1 side" means that the shortest distance between edge 22-1 and insulating substrate 21-1 is shorter than the shortest distance between edge 22-2 and insulating substrate 21-1. Of the two insulating substrates 21, insulating substrate 21-2 is provided on the edge 22-2 side. "Provided on the edge 22-2 side" means that the shortest distance between edge 22-2 and insulating substrate 21-2 is shorter than the shortest distance between edge 22-1 and insulating substrate 21-2. In this example, the transistor 40-1 and the diode 30-1 are provided above the insulating substrate 21-1, and the transistor 40-2 and the diode 30-2 are provided above the insulating substrate 21-2.

[0070] The wiring pattern 36 is provided with a transistor 40 or a diode 30. The transistor 40 or the diode 30 is provided on the upper surface of the wiring pattern 36. A bonding material (not shown) such as solder may be provided between the transistor 40 or the diode 30 and the wiring pattern 36.

[0071] The wiring pattern 36 includes a plurality of wiring patterns that are separated from one another. In FIG. 10, the wiring pattern 36 includes wiring pattern 36-1, wiring pattern 36-2, wiring pattern 36-3, wiring pattern 36-4, and wiring pattern 36-5. The wiring pattern 36-1 is an example of a first wiring pattern. The wiring patterns 36-4 and 36-5 are examples of a second wiring pattern. The wiring patterns 36-2 and 36-3 are examples of a third wiring pattern. The wiring pattern 36-2 is connected to the wiring pattern 36-3. The wiring pattern 36-4 is an example of a fourth wiring pattern. The wiring pattern 36-5 is an example of a fifth wiring pattern. The wiring pattern 36-4 is connected to the wiring pattern 36-5. In FIG. 10, the wiring patterns 36-1, 36-2, and 36-5 are provided above the insulating substrate 21-1. In FIG. 10, the wiring pattern 36-3 and the wiring pattern 36-4 are provided above the insulating substrate 21-2.

[0072] In this example, the P terminal 70, the N terminal 80, and the output terminal 90 are predetermined wiring patterns. The P terminal 70, the N terminal 80, and the output terminal 90 may be connected to other terminals, etc. The P terminal 70 is connected to the wiring pattern 36-1 via the wire wiring 28. The N terminal 80 is connected to the wiring pattern 36-5 via the wire wiring 28. The output terminal 90 is connected to the wiring pattern 36-3 via the wire wiring 28. In this example, the P terminal 70 and the N terminal 80 are provided on the side of the edge 22-1. Being provided on the side of the edge 22-1 means that the shortest distance between each terminal and the edge 22-1 is shorter than the shortest distance between each terminal and the edge 22-2. In this example, the output terminal 90 is provided on the side of the edge 22-2. Being provided on the side of the edge 22-2 means that the shortest distance between each terminal and the edge 22-2 is shorter than the shortest distance between each terminal and the edge 22-1.

[0073] In FIG. 10, the transistor 40 includes a transistor 40-1 and a transistor 40-2. The transistor 40-1 is provided above the wiring pattern 36-1. The transistor 40-1 may be provided on the wiring pattern 36-1. In this example, three transistors 40-1 are provided on the wiring pattern 36-1. In this example, the collector electrode 44 of the transistor 40-1 is connected to the wiring pattern 36-1. Also, in this example, the emitter electrode 42 of the transistor 40-1 is exposed in a top view. The emitter electrode 42 of the transistor 40-1 is connected to the wiring pattern 36-2 via the wire 28 or the anode electrode 32 of the diode 30-1.

[0074] The transistor 40-2 is provided above the wiring pattern 36-3. The transistor 40-2 may be provided on the wiring pattern 36-3. In this example, the collector electrode 44 of the transistor 40-2 is connected to the wiring pattern 36-3. In this example, three transistors 40-2 are provided on the wiring pattern 36-3. In this example, the emitter electrode 42 of the transistor 40-2 is exposed in a top view. The emitter electrode 42 of the transistor 40-2 is connected to the wiring pattern 36-4 via the wire 28 or the anode electrode 32 of the diode 30-2.

[0075] In FIG. 10, the diode 30 includes a diode 30-1 and a diode 30-2. The diode 30-1 is provided above the wiring pattern 36-1. The diode 30-1 may be provided on the wiring pattern 36-1. In this example, three diodes 30-1 are provided on the wiring pattern 36-1. In this example, the cathode electrode 34 of the diode 30-1 is connected to the wiring pattern 36-1. In this example, the anode electrode 32 of the diode 30-1 is exposed in a top view. The anode electrode 32 of the diode 30-1 is connected to the wiring pattern 36-2 via the wire 28 or the emitter electrode 42 of the transistor 40-1.

[0076] The diode 30-2 is provided above the wiring pattern 36-3. The diode 30-2 may be provided on the wiring pattern 36-3. In this example, the cathode electrode 34 of the diode 30-2 is connected to the wiring pattern 36-3. In this example, the anode electrode 32 of the diode 30-2 is exposed in a top view. The anode electrode 32 of the diode 30-2 is connected to the wiring pattern 36-4 via the wire 28 or the emitter electrode 42 of the transistor 40-2.

[0077] The transistors 40 and the diodes 30 may be provided alternately along a predetermined direction. The transistors 40 and the diodes 30 may be provided alternately along the X-axis direction. The transistors 40 and the diodes 30 may be provided alternately along the Y-axis direction.

[0078] 11 is a diagram illustrating an example of a semiconductor module 700 according to an embodiment. Description of the same configuration in FIG. 11 as in FIG.

[0079] The emitter electrode 42 of the transistor 40-1 is connected to the wiring pattern 36-2 via the wiring 28. The emitter electrode 42 of the transistor 40-2 is connected to the wiring pattern 36-4 via the wiring 28.

[0080] The diode 30-1 is provided above the wiring pattern 36-2. The diode 30-1 may be provided on the wiring pattern 36-2. In this example, three diodes 30-1 are provided on the wiring pattern 36-2. In this example, the anode electrode 32 of the diode 30-1 is connected to the wiring pattern 36-2. In this example, the cathode electrode 34 of the diode 30-1 is exposed in top view. The cathode electrode 34 of the diode 30-1 is connected to the wiring pattern 36-1 via the wire 28.

[0081] The diode 30-2 is provided above the wiring pattern 36-4. The diode 30-2 may be provided on the wiring pattern 36-4. In this example, three diodes 30-2 are provided on the wiring pattern 36-4. In this example, the anode electrode 32 of the diode 30-2 is connected to the wiring pattern 36-4. In this example, the cathode electrode 34 of the diode 30-2 is exposed in top view. The cathode electrode 34 of the diode 30-2 is connected to the wiring pattern 36-3 via the wire 28.

[0082] With the above configuration, the bridge balance condition can be easily established, which makes it possible to reduce the radiation noise. Therefore, the radiation noise can be reduced by simply replacing the diode 30 without mounting any additional components on the semiconductor module 700.

[0083] Furthermore, in this example, the width L1 of the wiring pattern 36-3 in the X-axis direction is larger than the width L2 of the wiring pattern 36-4 in the X-axis direction. The width L3 of the wiring pattern 36-1 in the X-axis direction may be larger than the width L2 of the wiring pattern 36-4 in the X-axis direction. The width of the wiring pattern 36 in the X-axis direction may be the width of the region of the wiring pattern 36 in which the transistor 40 or the diode 30 is provided. Because the area of ​​the transistor 40 in a top view is larger than the area of ​​the diode 30 in a top view, the width L2 of the wiring pattern 36-4 in the X-axis direction is smaller than the width L1 of the wiring pattern 36-3 in the X-axis direction and the width L3 of the wiring pattern 36-1 in the X-axis direction. This width of the wiring pattern 36 makes it easier to align the area of ​​the wiring pattern 36-1 in a top view with the sum of the areas of the wiring patterns 36-4 and 36-5 in a top view. This facilitates achieving the bridge balance condition.

[0084] Fig. 12 is a diagram illustrating an example of a semiconductor module 800 according to an embodiment. The semiconductor module 800 in Fig. 12 differs from the semiconductor module 700 in Fig. 11 in the number of transistor 40 chips and the number of diode 30 chips. Other configurations of the semiconductor module 800 in Fig. 12 may be the same as those of the semiconductor module 700 in Fig. 11.

[0085] The four transistors 40-1 may be provided above the wiring pattern 36-1. The four transistors 40-1 may be provided on the wiring pattern 36-1. In this example, the collector electrodes 44 of the four transistors 40-1 are connected to the wiring pattern 36-1. In this example, the emitter electrodes 42 of the four transistors 40-1 are exposed in a top view. The four transistors 40-1 are arranged in the Y-axis direction.

[0086] The four transistors 40-2 may be provided above the wiring pattern 36-3. The four transistors 40-2 may be provided on the wiring pattern 36-3. In this example, the collector electrodes 44 of the four transistors 40-2 are connected to the wiring pattern 36-3. In this example, the emitter electrodes 42 of the four transistors 40-2 are exposed in a top view. The four transistors 40-2 are arranged in the Y-axis direction.

[0087] The two diodes 30-1 may be provided above the wiring pattern 36-2. The two diodes 30-1 may be provided on the wiring pattern 36-2. In this example, the anode electrodes 32 of the two diodes 30-1 are connected to the wiring pattern 36-2. In this example, the cathode electrodes 34 of the two diodes 30-1 are exposed in top view. The two diodes 30-1 are arranged in the Y-axis direction.

[0088] The two diodes 30-2 may be provided above the wiring pattern 36-4. The two diodes 30-2 may be provided on the wiring pattern 36-4. In this example, the anode electrodes 32 of the two diodes 30-2 are connected to the wiring pattern 36-4. In this example, the cathode electrodes 34 of the two diodes 30-2 are exposed in top view. The two diodes 30-2 are arranged in the Y-axis direction.

[0089] In this way, the bridge balance condition can be easily established even if the number of transistor 40 chips and the number of diode 30 chips are changed, and therefore, radiation noise can be reduced.

[0090] Fig. 13 is a diagram illustrating an example of a semiconductor module 900 according to an embodiment. The semiconductor module 900 in Fig. 13 differs from the semiconductor module 800 in Fig. 12 in that diodes 30-3 and 30-4 are provided instead of diode 30-1. Other configurations of the semiconductor module 900 in Fig. 13 may be the same as those of the semiconductor module 800 in Fig. 12.

[0091] The diode 30-3 may be provided above the wiring pattern 36-1. The diode 30-3 may be provided on the wiring pattern 36-1. In this example, the cathode electrode 34 of the diode 30-3 is connected to the wiring pattern 36-1. In addition, in this example, the anode electrode 32 of the diode 30-3 is exposed in a top view. The anode electrode 32 of the diode 30-3 is connected to the wiring pattern 36-2 via the wire 28.

[0092] The diode 30-4 may be provided above the wiring pattern 36-2. The diode 30-4 may be provided on the wiring pattern 36-2. In this example, the anode electrode 32 of the diode 30-4 is connected to the wiring pattern 36-2. In this example, the cathode electrode 34 of the diode 30-4 is exposed in a top view. The cathode electrode 34 of the diode 30-4 is connected to the wiring pattern 36-1 via the wire 28.

[0093] Even if the diodes 30-3 and 30-4 are provided in this manner, the bridge balance condition can be easily established. Therefore, it is possible to reduce radiation noise. Furthermore, by providing the diodes 30-3 and 30-4, it is possible to adjust the area of ​​the wiring pattern 36-1 in a top view and the area of ​​the wiring pattern 36-2 in a top view.

[0094] Fig. 14 is a diagram illustrating an example of a semiconductor module 1000 according to an embodiment. The semiconductor module 1000 in Fig. 14 differs from the semiconductor module 700 in Fig. 11 in that diodes 30-3 and 30-4 are provided instead of diode 30-1 and diodes 30-5 and 30-6 are provided instead of diode 30-2. Other configurations of the semiconductor module 1000 in Fig. 14 may be the same as those of the semiconductor module 700 in Fig. 11.

[0095] The diode 30-3 may be provided above the wiring pattern 36-1. The diode 30-3 may be provided on the wiring pattern 36-1. In this example, one diode 30-3 is provided on the wiring pattern 36-1. In this example, the cathode electrode 34 of the diode 30-3 is connected to the wiring pattern 36-1. In addition, in this example, the anode electrode 32 of the diode 30-3 is exposed in a top view. The anode electrode 32 of the diode 30-3 is connected to the wiring pattern 36-2 via the wire 28.

[0096] The diode 30-4 may be provided above the wiring pattern 36-2. The diode 30-4 may be provided on the wiring pattern 36-2. In this example, two diodes 30-4 are provided on the wiring pattern 36-2. In this example, the anode electrode 32 of the diode 30-4 is connected to the wiring pattern 36-2. In this example, the cathode electrode 34 of the diode 30-4 is exposed in a top view. The cathode electrode 34 of the diode 30-4 is connected to the wiring pattern 36-1 via the wire 28.

[0097] The diode 30-5 may be provided above the wiring pattern 36-3. The diode 30-5 may be provided on the wiring pattern 36-3. In this example, one diode 30-5 is provided on the wiring pattern 36-3. In this example, the cathode electrode 34 of the diode 30-5 is connected to the wiring pattern 36-3. In this example, the anode electrode 32 of the diode 30-5 is exposed in a top view. The anode electrode 32 of the diode 30-5 is connected to the wiring pattern 36-4 via the wire 28.

[0098] The diode 30-6 may be provided above the wiring pattern 36-4. The diode 30-6 may be provided on the wiring pattern 36-4. In this example, two diodes 30-6 are provided on the wiring pattern 36-4. In this example, the anode electrode 32 of the diode 30-6 is connected to the wiring pattern 36-4. In this example, the cathode electrode 34 of the diode 30-6 is exposed in top view. The cathode electrode 34 of the diode 30-6 is connected to the wiring pattern 36-3 via the wire 28.

[0099] In this example, the total number of transistor 40 and diode 30 chips provided in wiring pattern 36-1 is different from the total number of transistor 40 and diode 30 chips provided in wiring pattern 36-4. Therefore, it is easy to align the area of ​​wiring pattern 36-1 in a top view with the sum of the area of ​​wiring pattern 36-4 in a top view and the area of ​​wiring pattern 36-5 in a top view. In this way, the total number of transistor 40 and diode 30 chips provided in wiring pattern 36 can be flexibly changed.

[0100] Fig. 15 is a diagram illustrating an example of a semiconductor module 1100 according to an embodiment. The semiconductor module 1100 in Fig. 15 differs from the semiconductor module 1000 in Fig. 14 in the number of chips for each of the diodes 30-1, 30-2, 30-3, and 30-4. Other configurations of the semiconductor module 1100 in Fig. 15 may be the same as those of the semiconductor module 1000 in Fig. 14.

[0101] In this example, two diodes 30-3 are provided on wiring pattern 36-1. Also in this example, one diode 30-4 is provided on wiring pattern 36-2. Similarly, two diodes 30-5 are provided on wiring pattern 36-3, and one diode 30-6 is provided on wiring pattern 36-4. In this way, similar to the semiconductor module 1000 of FIG. 14, the total number of transistor 40 and diode 30 chips provided on wiring pattern 36 can be flexibly changed.

[0102] The number of diode 30 chips provided on wiring pattern 36-1 may be different from the number of diode 30 chips provided on wiring pattern 36-3. For example, one diode 30 chip is provided on wiring pattern 36-1, and two diode 30 chips are provided on wiring pattern 36-3. In this case, two diode 30 chips are provided on wiring pattern 36-2, and one diode 30 chip is provided on wiring pattern 36-4. The number of diode 30 chips provided on wiring pattern 36 can be changed as appropriate.

[0103] Fig. 16 is a diagram illustrating an example of a semiconductor module 1200 according to an embodiment. The semiconductor module 1200 in Fig. 16 differs from the semiconductor module 800 in Fig. 12 in the arrangement of the transistors 40 and the diodes 30. Other configurations of the semiconductor module 1200 in Fig. 16 may be the same as those of the semiconductor module 800 in Fig. 12.

[0104] In this example, three transistors 40-1 are arranged in the Y-axis direction above insulating substrate 21-1. Also in this example, one transistor 40-1 and two diodes 30-1 are arranged in the Y-axis direction above insulating substrate 21-1. Also in this example, three transistors 40-2 are arranged in the Y-axis direction above insulating substrate 21-2. Also in this example, one transistor 40-2 and two diodes 30-2 are arranged in the Y-axis direction above insulating substrate 21-2. By changing the arrangement of the transistors 40 and diodes 30, the area of ​​wiring pattern 36 in a top view can be flexibly changed.

[0105] 17 is a diagram showing in detail the arrangement of the diode 30 in FIG. 5. A bonding material 38 is provided between the diode 30 and the wiring pattern 26. The bonding material 38 is, for example, solder. The anode electrode 32 of the diode 30 is connected to the wiring pattern 26 via the bonding material 38.

[0106] A guard ring 96 is provided on the anode electrode 32 side of the diode 30. Therefore, in order to ensure a withstand voltage between the diode 30 and the wiring pattern 26, it is preferable to provide an insulating film or the like on the guard ring 96. Therefore, the diode 30 in FIG. 5 has a different structure from the diode 30 in FIG. 1. In FIG. 5, the anode electrodes 32 of the two diodes 30 are provided on the bottom surface, so the two diodes 30 can have the same structure. This allows the number of parts to be reduced.

[0107] 18 is a diagram showing in detail the arrangement of the chip capacitor 94 in FIG. 9. The chip capacitor 94 is provided with an electrode 95. In this example, the electrode provided on the upper surface of the chip capacitor 94 is referred to as electrode 95-1, and the electrode provided on the lower surface of the chip capacitor 94 is referred to as electrode 95-2. In other words, the chip capacitor 94 is a vertical chip. The electrode 95-2 of the chip capacitor 94 is connected to the wiring pattern 26-2. The electrode 95-1 of the chip capacitor 94 is connected to the wiring pattern 26-1 via the wire 28.

[0108] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. [Explanation of symbols]

[0109] 10 Resin case, 20 Base substrate, 21 Insulating substrate, 22 Edge, 26 Wiring pattern, 28 Wire wiring, 30 Diode, 32 Anode electrode, 34 Cathode electrode, 36 Wiring pattern, 38 Bonding material, 40 Transistor, 42 Emitter electrode, 44 Collector electrode, 50 Gate terminal, 51 Gate terminal, 70 P terminal, 72 P-side arm circuit, 80 N terminal, 82 N-side arm circuit, 90 Output terminal, 92··Capacitor, 94··Chip capacitor, 95··Electrode, 96··Guard ring, 100··Semiconductor module, 200··Semiconductor module, 300··Semiconductor module, 400··Semiconductor module, 500··Semiconductor module, 600··Semiconductor module, 700··Semiconductor module, 800··Semiconductor module, 900··Semiconductor module, 1000··Semiconductor module, 1100··Semiconductor module, 1200··Semiconductor module

Claims

1. A semiconductor module having a P-side arm circuit and an N-side arm circuit, The P terminal on the high voltage side, N terminal on the low voltage side, A plurality of wiring patterns separated from each other; a transistor and a diode connected in parallel in each of the P-side arm circuit and the N-side arm circuit; Equipped with the plurality of wiring patterns include a first wiring pattern, a second wiring pattern, and a third wiring pattern; the P terminal is connected to the first wiring pattern; the N terminal is connected to the second wiring pattern; an anode electrode of the diode of the N-side arm circuit is disposed above the second wiring pattern and connected to the second wiring pattern; an anode electrode of the diode of the P-side arm circuit is disposed above the third wiring pattern and connected to the third wiring pattern; The area of ​​the first wiring pattern in top view and the area of ​​the second wiring pattern in top view are substantially equal. Semiconductor module.

2. The collector electrode of the transistor of the P-side arm circuit is disposed above the first wiring pattern and is connected to the first wiring pattern. The semiconductor module according to claim 1 .

3. The collector electrode of the transistor of the N-side arm circuit is disposed above a wiring pattern different from the first wiring pattern and is connected to the wiring pattern.

3. The semiconductor module according to claim 1.

4. The collector electrode of the transistor of the N-side arm circuit is disposed above the third wiring pattern and is connected to the third wiring pattern. The semiconductor module according to claim 3 .

5. A plurality of wires are provided, One of the plurality of wires connects the cathode electrode of the diode of the N-side arm circuit to a third wiring pattern. The semiconductor module according to claim 1 .

6. A plurality of wires are provided, One of the plurality of wires connects the cathode electrode of the diode of the P-side arm circuit to a first wiring pattern. The semiconductor module according to claim 5 .

7. The total number of the transistor and diode chips provided on the first wiring pattern is equal to the total number of the transistor and diode chips provided on the second wiring pattern. The semiconductor module according to claim 1 .

8. the total number of the transistor and diode chips provided on the first wiring pattern is one; The total number of the transistor and diode chips provided on the second wiring pattern is one. The semiconductor module according to claim 7 .

9. one of the transistors is provided on the first wiring pattern; One of the diodes is provided on the second wiring pattern. The semiconductor module according to claim 8 .

10. The semiconductor device further includes a chip capacitor provided across the first wiring pattern and the second wiring pattern. The semiconductor module according to claim 1 .

11. further comprising an output terminal for outputting a voltage to the outside; The output terminal is connected to the third wiring pattern. The semiconductor module according to claim 1 .

12. an output terminal for outputting a voltage to the outside; a base substrate having one end side and the other end side facing each other; two insulating substrates provided above the base substrate; Further provided with the output terminal is connected to the third wiring pattern; the P terminal and the N terminal are provided on the one end side, the output terminal is provided on the other end side, The second wiring pattern is a fourth wiring pattern provided above the insulating substrate on the other end side of the two insulating substrates; a fifth wiring pattern provided above the insulating substrate on the one end side of the two insulating substrates; Including, an anode electrode of the diode of the N-side arm circuit is disposed above the fourth wiring pattern and connected to the fourth wiring pattern; The fifth wiring pattern is connected to the fourth wiring pattern and the N terminal. The semiconductor module according to claim 1 .

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