Semiconductor Devices

Abstract

To provide a semiconductor element capable of suppressing characteristic deterioration.SOLUTION: An amplifier comprises an FET, an input matching circuit, and an output matching circuit. The FET comprises: a substrate 10; a source electrode 12; a drain electrode 16; a first gate electrode 14a; a second gate electrode 14b; a gate pad provided so as to sandwich the first gate electrode between the gate pad and the second gate electrode and electrically connected to the first gate electrode; a first gate line 18 provided above the source electrode and opposite to the substrate with respect to the source electrode, and extending in a first direction Y; a second gate line 19b provided above the source electrode and extending in a second direction X crossing the first direction Y, having a first end connected to the first gate line and a second end opposite the first end electrically connected to the second gate electrode outside the source electrode; and a first guard metal layer 21b provided between the second gate line and the drain electrode and at least a part thereof is provided closer to the drain electrode than the source electrode, and electrically connected to the source electrode.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] In a field effect transistor (FET) having finger-shaped source, gate and drain electrodes, it is known to arrange a plurality of unit FETs each having a source, gate and drain electrode in the direction in which the electrodes extend (for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-299351 [Patent Document 2] U.S. Patent No. 9,786,660 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Documents 1 and 2, by arranging multiple unit FETs in the electrode extension direction, the width of the gate electrode in each unit FET can be shortened. This reduces the gate resistance. However, the gate wiring that electrically connects the gate pad and the gate electrode that is distant from the gate pad is provided above the unit FET. Where the gate wiring approaches the drain electrode, the parasitic capacitance between the gate wiring and the drain electrode increases, degrading characteristics such as gain.

[0005] The present disclosure has been made in consideration of the above-mentioned problems, and aims to suppress deterioration of characteristics. [Means for solving the problem]

[0006] One embodiment of the present disclosure relates to a semiconductor device including a substrate, a source electrode extending in a first direction and provided on the substrate, a drain electrode extending in the first direction and provided on the substrate, a first gate electrode extending in the first direction and provided on the substrate between the source electrode and the drain electrode, a second gate electrode extending in the first direction and provided on a region of the substrate located in the first direction from the first gate electrode between the source electrode and the drain electrode, and a gate pad provided so as to sandwich the first gate electrode between the second gate electrode and electrically connected to the first gate electrode. a first gate wiring provided above the source electrode on a side opposite to the substrate and extending in the first direction; a second gate wiring provided above the source electrode and extending in a second direction intersecting the first direction, the second gate wiring having a first end connected to the first gate wiring and a second end opposite to the first end electrically connected to the second gate electrode outside the source electrode; and a first guard metal layer provided between the second gate wiring and the drain electrode, at least a portion of which is provided closer to the drain electrode than the source electrode and electrically connected to the source electrode. [Effects of the Invention]

[0007] According to the present disclosure, deterioration of characteristics can be suppressed. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of an amplifier using a FET according to the first embodiment. [Figure 2] FIG. 2 is a plan view of the FET according to the first embodiment. [Figure 3] FIG. 3 is an enlarged plan view of a range D in FIG. [Figure 4] FIG. 4 is an enlarged plan view of a range E in FIG. [Figure 5] FIG. 5 is a cross-sectional view taken along line AA in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along the line BB in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line CC in FIG. [Figure 8] FIG. 8 is a plan view of a semiconductor device according to a first comparative example. [Figure 9] FIG. 9 is an enlarged plan view of a range D in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along the line AA in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line BB in FIG. [Figure 12] FIG. 12 is an enlarged plan view of a semiconductor device according to a first modification of the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view of a semiconductor device according to a second modification of the first embodiment. [Figure 14] FIG. 14 is a plan view of the FET according to the second embodiment. [Figure 15] FIG. 15 is a plan view of the FET according to the second embodiment. [Figure 16] FIG. 16 is a cross-sectional view taken along the line AA in FIGS. [Figure 17] FIG. 17 is a cross-sectional view taken along the line BB in FIGS. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Details of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure relates to a semiconductor device including a substrate, a source electrode extending in a first direction and provided on the substrate, a drain electrode extending in the first direction and provided on the substrate, a first gate electrode extending in the first direction and provided on the substrate between the source electrode and the drain electrode, a second gate electrode extending in the first direction and provided on a region of the substrate between the source electrode and the drain electrode located in the first direction from the first gate electrode, and a gate electrode provided between the second gate electrode and the gate electrode and electrically connected to the first gate electrode. a first gate wiring provided above the source electrode on a side opposite to the substrate and extending in the first direction, a second gate wiring provided above the source electrode and extending in a second direction intersecting the first direction, the second gate wiring having a first end connected to the first gate wiring and a second end opposite to the first end electrically connected to the second gate electrode outside the source electrode, and a first guard metal layer provided between the second gate wiring and the drain electrode, at least a portion of which is provided closer to the drain electrode than the source electrode and electrically connected to the source electrode. This makes it possible to suppress gate-drain capacitance and thereby suppress deterioration of characteristics. (2) In (1) above, the first guard metal layer may be arranged to surround a portion of the second gate wiring located outside the source electrode from the first direction, the direction opposite to the first direction, and the second direction. (3) In the above (2), a first end of the first guard metal layer may be electrically connected to the source electrode in a region away from the second gate wiring in the first direction, and a second end of the first guard metal layer may be electrically connected to the source electrode in a region away from the second gate wiring in a direction opposite to the first direction. (4) In any of (1) to (3) above, a second guard metal layer may be provided between the first gate wiring and the drain electrode, extending in the first direction, at least a portion of which is provided above the source electrode and electrically connected to the source electrode. (5) In any of (1) to (4) above, an insulating film may be provided on the substrate so as to cover the source electrode, the drain electrode, the first gate electrode, and the second gate electrode, and the first gate wiring, the second gate wiring, and the first guard metal layer may be provided on the insulating film. (6) In the above (5), a first via wiring may be provided that penetrates the insulating film and electrically connects the source electrode and the first guard metal layer. (7) In the above (5) or (6), a second via wiring may be provided that penetrates the insulating film and electrically connects the second gate electrode and the second gate wiring. (8) In any of (1) to (7) above, a source wall may be provided, at least a portion of which is provided between the second gate electrode and the drain electrode and extending in the first direction, and the first guard metal layer may be electrically connected to the source wall outside the source electrode. (9) In any one of the above (1) to (8), the first gate electrode and the second gate electrode may be spaced apart in the first direction on the upper surface of the substrate. (10) In any of the above (1) to (9), the thickness of the source electrode and the drain electrode may be greater than the thickness of the first gate electrode and the second gate electrode in the normal direction to the upper surface of the substrate.

[0010] Specific examples of semiconductor devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0011] [Example 1] FIG. 1 is a block diagram of an amplifier using a FET according to a first embodiment. As shown in FIG. 1, the amplifier 100 includes an FET 55, an input matching circuit 52, and an output matching circuit 54. The source S of the FET 55 is connected to ground. A high-frequency signal input from an input terminal Tin is input to a gate G of the FET 55 via the input matching circuit 52. The high-frequency signal amplified by the FET 55 is output from an output terminal Tout via the output matching circuit 54. The input matching circuit 52 performs matching so that the input impedance of the input terminal Tin and the impedance of the input matching circuit 52 viewed from the gate G of the FET 55 are complex conjugates. The output matching circuit 54 performs matching so that the output impedance of the output terminal Tout and the impedance of the output matching circuit 54 viewed from the drain D of the FET 55 are complex conjugates. The amplifier 100 is, for example, a power amplifier for wireless communications, operating at a frequency of 0.5 GHz or higher and 10 GHz or lower (e.g., 3.5 GHz). The output power of the amplifier 100 is, for example, 30 dBm or higher and 56 dBm or lower.

[0012] Fig. 2 is a plan view of the FET in Example 1. Figs. 3 and 4 are enlarged plan views of ranges D and E in Fig. 2. Figs. 5 to 7 are cross-sectional views taken along lines AA, BB, and CC in Fig. 3, respectively. The normal direction to the top surface of substrate 10 is defined as the Z direction, the extension direction of each finger-shaped electrode is defined as the Y direction (first direction), and the arrangement direction of each electrode is defined as the X direction (second direction).

[0013] As shown in Figures 2 to 4, a source electrode 12, gate electrodes 14a, 14b, and 14c, a drain electrode 16, gate wirings 18, 19a, 19b, and 19c, guard metal layers 20a, 20b, 21b, and 21c, a source bus bar 32a, a source pad 32b, a gate wiring 34a, a gate pad 34b, and a drain pad 36 are provided on a substrate 10.

[0014] Active regions 11a, 11b, and 11c are provided on a substrate 10. The active regions 11a, 11b, and 11c are arranged in the Y direction and extend in the X direction. A plurality of unit FETs 35a, 35b, and 35c arranged in the X direction are provided in the active regions 11a, 11b, and 11c, respectively.

[0015] The multiple source electrodes 12 extend in the Y direction across the active regions 11a, 11b, and 11c. The multiple source electrodes 12 are electrically connected in common to a source bus bar 32a at the positive (+) ends of the source electrodes 12 in the Y direction and are shorted. The source bus bar 32a is electrically connected in common to a source pad 32b and is shorted. The multiple drain electrodes 16 extend in the Y direction across the active regions 11a, 11b, and 11c. The multiple drain electrodes 16 are electrically connected in common to a drain pad 36 at the negative (-) ends of the drain electrodes 16 in the Y direction and are shorted. The multiple source electrodes 12 and the multiple drain electrodes 16 are arranged alternately. Gate electrodes 14a, 14b, and 14c are arranged on the active regions 11a, 11b, and 11c, respectively, between one source electrode 12 and one drain electrode 16. The gate electrode 14b is arranged on the negative side of the gate electrode 14a in the Y direction. Gate electrode 14c is provided on the negative side of gate electrode 14b in the Y direction. The source electrode 12, gate electrode 14a, and drain electrode 16 form unit FET 35a, the source electrode 12, gate electrode 14b, and drain electrode 16 form unit FET 35b, and the source electrode 12, gate electrode 14c, and drain electrode 16 form unit FET 35c.

[0016] Pads 15a, 15b, and 15c are provided at the positive ends in the Y direction of the active regions 11a, 11b, and 11c of the gate electrodes 14a, 14b, and 14c, respectively. The pads 15a, 15b, and 15c are metal layers made of the same material as the gate electrodes 14a, 14b, and 14c. Gate wiring 18, 19a, 19b, and 19c, and guard metal layers 20a, 20b, 21b, and 21c are provided above the source electrode 12. The gate wiring 18 extends in the Y direction above the source electrode 12 and is electrically connected to and short-circuited with the gate wiring 34a or gate pad 34b at its positive end in the Y direction. The gate wiring 19a, 19b, and 19c electrically connect the gate wiring 18 to the pads 15a, 15b, and 15c via via wirings 23a, 23b, and 23c, respectively, thereby electrically shorting them.

[0017] The guard metal layers 20a and 20b are provided above the source electrode 12 in the active regions 11a and 11b, respectively, on both sides of the gate wiring 18 in the Y direction, and extend in the Y direction. The guard metal layer 20a is electrically connected to the source electrode 12 at its positive end in the Y direction via a via wiring 22a, and at its negative end in the Y direction via a via wiring 22b. The guard metal layer 20b is electrically connected to the source electrode 12 at its positive end in the Y direction via a via wiring 22c, and at its negative end in the Y direction via a via wiring 22d. As a result, the guard metal layers 20a and 20b are electrically short-circuited to the source electrode 12, and the guard metal layers 20a and 20b and the source electrode 12 have approximately the same potential.

[0018] The guard metal layer 21b is provided between the gate wiring 19b and the drain electrode 16. A first end of the guard metal layer 21b is electrically connected to the negative end of the guard metal layer 20a in the Y direction, and a second end of the guard metal layer 21b is electrically connected to the positive end of the guard metal layer 20b in the Y direction. The guard metal layer 21c is provided between the gate wiring 19c and the drain electrode 16. A first end of the guard metal layer 21c is electrically connected to the negative end of the guard metal layer 20b in the Y direction, and a second end of the guard metal layer 21c is electrically connected to the source electrode 12 via the via wiring 22e. As a result, the guard metal layers 21b and 21c are electrically short-circuited with the source electrode 12, and the guard metal layers 21b and 21c and the source electrode 12 have approximately the same potential.

[0019] As shown in FIGS. 5 to 7 , the substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. In an XY plane parallel to the X and Y directions, a region of the semiconductor layer 10b that has been inactivated by ion implantation or the like is an inactive region 13, and regions that have not been inactivated are active regions 11a, 11b, and 11c. An insulating film 24a is provided on the substrate 10 to cover the source electrode 12, the drain electrode 16, and the gate electrodes 14a, 14b, and 14c. Gate wirings 18, 19a, 19b, and 19c and guard metal layers 20a, 20b, 21b, and 21c are provided on the insulating film 24a. The gate wirings 18, 19a, 19b, and 19c and the guard metal layers 20a, 20b, 21b, and 21c are metal layers formed, for example, in the same manufacturing process, made of the same material, and have approximately the same thickness. An insulating film 24b is provided on the insulating film 24a so as to cover the gate wirings 18, 19a, 19b, and 19c and the guard metal layers 20a, 20b, 21b, and 21c. The insulating films 24a and 24b form an insulating film 24. The via wirings 22a, 22b, 22c, 22d, 22e, 23a, 23b, and 23c penetrate the insulating film 24a and extend in the Z direction.

[0020] 2 to 5, in the active regions 11a and 11b, the gate wiring 18 is provided above the center of the source electrode 12 in the X direction. The guard metal layers 20a and 20b are provided above the ends of the source electrode 12 in the X direction.

[0021] 2 to 4 and 6, when viewed from the +Z direction, guard metal layer 21b extends from guard metal layers 20a and 20b toward the outside of source electrode 12, and guard metal layer 21c extends from guard metal layers 20b and 20c toward the outside of source electrode 12. Guard metal layer 20a is electrically connected to source electrode 12 through via wirings 22a and 22b, and guard metal layer 20b is electrically connected to source electrode 12 through via wirings 22c and 22d.

[0022] 2 to 4 and 7, when viewed from the positive side in the Z direction, gate wirings 19b and 19c extend from gate wiring 18 toward the outside of source electrode 12 and are electrically connected to pads 15b and 15c, respectively, via via wirings 23b and 23c outside source electrode 12. Guard metal layers 21b and 21c are provided between gate wirings 19b and 19c, respectively, and drain electrode 16.

[0023] A source potential (e.g., a reference potential such as ground potential) is supplied to the source electrode 12 from the source pad 32b and the source bus bar 32a. A gate potential (e.g., a high-frequency signal and a gate bias voltage) is supplied to the gate electrodes 14a, 14b, and 14c from the gate pad 34b and the gate wiring 34a via the gate wirings 18, 19a, 19b, and 19c, respectively. A drain bias voltage is supplied to each drain electrode 16 from the drain pad 36. The high-frequency signal amplified in each unit FET 35a, 35b, and 35c is output from the drain electrode 16 to the drain pad 36.

[0024] In the unit FETs 35a, 35b, and 35c, a high-frequency signal is input from the positive ends in the Y direction of the gate electrodes 14a, 14b, and 14c, respectively. If a high-frequency signal is input to the gate electrode 14a from both the positive end and the negative end in the Y direction of the gate electrode 14a, the high-frequency characteristics of the unit FET 35a will deteriorate due to a phase difference, etc. The same applies to the unit FET 35b. In the first embodiment, the negative end in the Y direction of the gate electrode 14a is not connected to the positive end in the Y direction of the gate electrode 14b, and the negative end in the Y direction of the gate electrode 14b is not connected to the positive end in the Y direction of the gate electrode 14c, so that deterioration of the high-frequency characteristics of the unit FETs 35a and 35b can be suppressed.

[0025] If the semiconductor device is, for example, a nitride semiconductor device, the substrate 10a is, for example, a SiC substrate, a silicon substrate, a GaN substrate, or a sapphire substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a GaN layer, an AlGaN layer, and / or an InGaN layer. If the semiconductor device is, for example, a GaAs-based semiconductor device, the substrate 10a is, for example, a GaAs substrate. The semiconductor layer 10b includes, for example, an arsenide semiconductor layer such as a GaAs layer, an AlGaAs layer, and / or an InGaAs layer. The source electrode 12 and the drain electrode 16 are metal films, for example, titanium and aluminum films from the substrate 10 side. A gold film may be provided on the aluminum film. The gate electrodes 14a, 14b, and 14c and pads 15a, 15b, and 15c are metal films, for example, nickel and gold films from the substrate 10 side. The gate wiring 18, 19a, 19b, and 19c and the guard metal layers 20a, 20b, 21b, and 21c are, for example, gold, copper, or aluminum layers. The via wirings 22a, 22b, 22c, 22d, 22e, 23a, 23b, and 23c are metal layers, such as gold, copper, tungsten, or aluminum. The insulating film 24 is an organic insulating film made of, for example, polyimide resin or BCB (Benzocyclobutene). The insulating film 24 may also be an inorganic insulating film made of, for example, silicon nitride or silicon oxide. The dielectric constant of the insulating film 24 is, for example, 2.4 or more and 10 or less.

[0026] Referring to FIG. 5, the length L1 of the source electrode 12 in the X direction is, for example, 5 μm or more and 50 μm or less. The length L2 of the gate wiring 18 in the X direction is, for example, 3 μm or more and 45 μm or less. The distance L3 in the X direction between the source electrode 12 and the drain electrode 16 is, for example, 3 μm or more and 20 μm or less. The distance L4 in the X direction between the end of the gate wiring 18 and the end of the source electrode 12 is, for example, 1 μm or more and 10 μm or less. The length L5 in the X direction of the guard metal layers 20a and 20b is, for example, 0.5 μm or more and 3 μm or less. The thickness T1 of the source electrode 12 and the thickness T2 of the drain electrode 16 are, for example, 1 μm or more and 6 μm or less. The thickness T5 of the gate electrodes 14a, 14b, and 14c is, for example, 1 μm or less, which is smaller than the thicknesses T1 and T2. The thickness T3 of the insulating film 24a between the source electrode 12 and the gate wiring 18 is, for example, 0.5 μm or more and 10 μm or less. The thickness T4 of the gate wirings 18, 19a, 19b, 19c and the guard metal layers 20a, 20b, 21b, and 21c is, for example, 0.5 μm or more and 6 μm or less.

[0027] 7, the distance L8 in the X direction between the end of the source electrode 12 and the ends of the gate wirings 19a, 19b, and 19c is, for example, 1 μm or more and 20 μm or less. The distance L9 in the X direction between the gate wirings 19b and 19c and the guard metal layers 21b and 21c is, for example, 0.2 μm or more and 5 μm or less. The length L10 in the X direction of the guard metal layers 21a and 21b is, for example, 0.5 μm or more and 5 μm or less.

[0028] Fig. 8 is a plan view of a semiconductor device according to Comparative Example 1. Fig. 9 is an enlarged plan view of range D in Fig. 8, and Figs. 10 and 11 are a cross-sectional view taken along lines AA and BB in Fig. 9. As shown in Figs. 8 to 11, Comparative Example 1 does not include guard metal layers 20a, 20b, 21b, and 21c, and via wirings 22a, 22b, 22c, 22d, and 22e. The other configurations are the same as those of Example 1, and therefore description thereof will be omitted.

[0029] 10 , in the active region 11a, electric field lines 38a extend between the gate wiring 18 and the drain electrode 16, resulting in electric field coupling between the gate wiring 18 and the drain electrode 16. This generates a parasitic capacitance Cp_gda between the gate wiring 18 and the drain electrode 16.

[0030] 11, between the active regions 11a and 11b, electric field lines 38b extend between the gate wiring 19b and the drain electrode 16 and between the gate wiring 19b and the via wiring 23b and the drain electrode 16, thereby causing electric field coupling between the gate wiring 19b and the via wiring 23b and the drain electrode 16. This generates a parasitic capacitance Cp_gdb between the gate wiring 19b and the drain electrode 16 and between the gate wiring 19b and the via wiring 23b and the drain electrode 16.

[0031] The maximum oscillation frequency fmax of the FET is expressed by the following formula 1. fmax~√(ft / (8πRgCgd)) Equation 1 where ft is the cutoff frequency, Rg is the gate resistance, and Cgd is the gate-drain capacitance. As the parasitic capacitances Cp_gda and Cp_gdb increase, Cgd increases and fmax decreases.

[0032] One possible way to reduce the parasitic capacitances Cp_gda and Cp_gdb is to reduce the relative dielectric constant εr of the insulating film 24. However, reducing εr reduces the function of the insulating film 24 as a protective film, leading to a decrease in moisture resistance, dust resistance, and the like.

[0033] One way to reduce the parasitic capacitance Cp_gda is to lengthen L3+L4, which corresponds to the distance between the gate wiring 18 and the drain electrode 16. Reducing the length L2 of the gate wiring 18 increases the gate resistance. Therefore, one way to increase L3+L4 is to increase the length L1 of the source electrode 12. However, this increases the area of ​​the FET, resulting in an increase in the size of the semiconductor device.

[0034] Increasing the distance between the gate wiring 19b and the drain electrode 16 is one way to reduce the parasitic capacitance Cp_gdb. However, in order to electrically connect the gate wiring 19b to the pad 15b, the end of the gate wiring 19b is located between the source electrode 12 and the drain electrode 16 in the X direction. Therefore, if an attempt is made to increase the distance between the gate wiring 19b and the drain electrode 16, the distance L3 between the source electrode 12 and the drain electrode 16 must also be increased. Changing the distance L3 would change the characteristics of the unit FET 35a, so the distance L3 cannot be changed. As such, it is difficult to increase the distance between the gate wiring 19b and the drain electrode 16.

[0035] In Example 1, as shown in FIG. 7, a guard metal layer 21b shorted to the source electrode 12 is provided on the side of the gate wiring 19b. This blocks the electric field lines 38b (see FIG. 11 for Comparative Example 1) connecting the gate wiring 19b and the drain electrode 16. Although the electric field lines 38b connecting the via wiring 23b and the drain electrode 16 are not blocked, the parasitic capacitance Cp_gdb is reduced compared to Comparative Example 1. Instead of the electric field lines 38b blocked by the guard metal layer 21b, electric field lines 39b connecting the guard metal layer 21b and the drain electrode 16 are generated. This generates a parasitic capacitance Cp_dsb between the source electrode 12 and the drain electrode 16, increasing the drain-source capacitance Cds. However, as shown in Equation 1, Cds does not significantly affect fmax. While the gate-source capacitance Cgs significantly affects ft in Equation 1 due to the Miller effect, the drain-source capacitance Cds does not significantly affect ft. Therefore, even if the drain-source capacitance Cds increases in the first embodiment, the effect on the FET characteristics is small, and the gate-drain capacitance Cgd can be reduced, so that the FET characteristics such as fmax can be improved.

[0036] According to the first embodiment, the gate electrode 14a (first gate electrode) extends in the Y direction (first direction) and is provided on the substrate 10 between the source electrode 12 and the drain electrode 16. The gate electrode 14b (second gate electrode) extends in the Y direction and is provided on a region of the substrate 10 located negative in the Y direction from the gate electrode 14a between the source electrode 12 and the drain electrode 16. The gate electrode 14a is sandwiched between the gate pad 34b and the gate electrode 14b. The gate wiring 18 (first gate wiring) is provided above the substrate 10 on the opposite side to the source electrode 12 and extends in the Y direction. The gate wiring 19b (second gate wiring) is provided above the substrate 10 on the opposite side to the source electrode 12 and extends in the X direction (second direction intersecting the first direction), with a first end connected to the gate wiring 18 and a second end (the end opposite to the first end) electrically connected to the gate electrode 14b outside the source electrode 12. In this manner, the gate electrode 14b is electrically connected to the gate pad 34b by the gate wirings 18 and 19b.

[0037] 3, 4, and 7, guard metal layers 21b and 21c (first guard metal layers) are provided between gate wiring 19b and 19c and drain electrode 16, respectively, with at least a portion thereof being provided closer to drain electrode 16 than source electrode 12 and electrically connected to source electrode 12. As a result, as described in FIG. 7, guard metal layer 21b can shield electric field lines 38b between gate wiring 19b and drain electrode 16. This can reduce parasitic capacitance Cp_gdb, thereby improving characteristics such as fmax of the FET.

[0038] 3 and 4, the guard metal layers 21b and 21c are provided to surround the portions of the gate wirings 19b and 19c that are located outside the source electrode 12 from the positive direction in the Y direction (first direction), the negative direction in the Y direction (opposite the first direction), and the positive direction in the X direction (second direction). This allows the guard metal layers 21b and 21c to shield the electric field lines 38b that extend from the positive and negative directions in the Y direction of the gate wirings 19b and 19c to the drain electrode 16, as shown in FIG. 7. This further reduces the parasitic capacitance Cp_gdb, thereby further improving the characteristics of the FET.

[0039] 3 and 4, first ends of the guard metal layers 21b and 21c are electrically connected to the source electrode 12 via via wirings 22b and 22d, respectively, in regions spaced apart in the positive Y direction (first direction) from the gate wirings 19b and 19c, respectively. Second ends of the guard metal layers 21b and 21c are electrically connected to the source electrode 12 via via wirings 22c and 22e, respectively, in regions spaced apart in the negative Y direction (opposite the first direction) from the gate wirings 19b and 19c, respectively. This allows the guard metal layers 21b and 21c to be connected to the potential of the source electrode 12 (e.g., ground potential) at both ends of the guard metal layers 21b and 21c. This further increases the shielding effect of the guard metal layers 21b and 21c.

[0040] As shown in FIG. 7 , the end X7 of the guard metal layer 21b closest to the drain electrode 16 may be located closer to the source electrode 12 than the end X4 of the drain electrode 16 closest to the source electrode 12. However, if the end X7 is too close to the drain electrode 16, the parasitic capacitance Cp_ds increases. From this perspective, the end X7 of the guard metal layer 21b can be located closer to the source electrode 12 than the midpoint between the end X2 of the source electrode 12 and the end X4 of the drain electrode 16. Furthermore, the end X7 of the guard metal layer 21b can be located closer to the source electrode 12 than the end X8 of the pad 15b closest to the drain electrode 16. If the distance L9 between the gate wiring 19b and the guard metal layer 21b is small, the parasitic capacitance Cp_gs increases. From this perspective, the distance L9 can be set to at least half the width L10 of the guard metal layer 21b, and can be set to at least one time.

[0041] As shown in FIGS. 2 to 5 , guard metal layers 20a and 20b (second guard metal layers) are provided between the gate wiring 18 and the drain electrode 16, extending in the Y direction. At least a portion of the guard metal layer 20a is provided above the source electrode 12 and electrically connected to the source electrode 12. As described in FIG. 5 , the guard metal layer 20a can shield electric field lines 38a (see FIG. 10 for Comparative Example 1) between the gate wiring 18 and the drain electrode 16. This reduces the parasitic capacitance Cp_gda, thereby improving the FET's characteristics, such as fmax. Instead of the electric field lines 38a blocked by the guard metal layer 20a, electric field lines 39a are generated connecting the guard metal layer 20a and the drain electrode 16. This generates a parasitic capacitance Cp_dsb between the source electrode 12 and the drain electrode 16, increasing the drain-source capacitance Cds. However, as shown in Equation 1, Cds does not significantly affect fmax.

[0042] The insulating film 24a is provided to cover the source electrode 12, the drain electrode 16, and the gate electrodes 14a, 14b, and 14c. The gate wiring 18, the gate wirings 19a, 19b, and 19c, and the guard metal layers 20a, 20b, 21b, and 21c are provided on the insulating film 24a. This improves the moisture resistance and dust resistance of the unit FETs 35a, 35b, and 35c. Because the insulating film 24a has a higher dielectric constant than air, the parasitic capacitances Cp_gda and Cp_gdb between the gate wirings 18, 19b, and 19c and the drain electrode 16 become large. Therefore, the guard metal layers 20a, 20b, 21b, and 21c can be provided.

[0043] Via wirings 22b and 22c (first via wirings) penetrate the insulating film 24a and electrically connect the source electrode 12 and the guard metal layer 21b. Via wirings 22d and 22e penetrate the insulating film 24a and electrically connect the source electrode 12 and the guard metal layer 21c. This allows the guard metal layers 21b and 21c to have the same potential as the source electrode 12.

[0044] The via wiring 23b (second via wiring) penetrates the insulating film 24a and electrically connects an end of the gate electrode 14b to the gate wiring 19b. The via wiring 23c penetrates the insulating film 24a and electrically connects an end of the gate electrode 14c to the gate wiring 19c. This allows the gate electrodes 14b and 14c to be electrically connected to the gate wirings 19b and 19c, respectively, between the source electrode 12 and the drain electrode 16.

[0045] Gate electrodes 14a and 14b are spaced apart on the upper surface of substrate 10, and gate electrodes 14b and 14c are spaced apart on the upper surface of substrate 10. This makes it possible to suppress interference between gate electrodes 14a and 14b and between gate electrodes 14b and 14c, thereby improving high-frequency characteristics. Gate electrodes 14a and 14b may be connected to each other on the upper surface of substrate 10, and gate electrodes 14b and 14c may be connected to each other on the upper surface of substrate 10.

[0046] The source electrode 12 and the drain electrode 16 are thicker than the gate electrodes 14a, 14b, and 14c. In this case, the parasitic capacitance due to electric field coupling between the gate electrodes 14a, 14b, and 14c and the drain electrode 16 is small, and the parasitic capacitance Cp_gd due to electric field coupling between the gate wiring 18 and the drain electrode 16 in Comparative Example 1 becomes a problem. Therefore, guard metal layers 20a and 18b can be provided.

[0047] [Modification 1 of Example 1] FIG. 12 is an enlarged plan view of a semiconductor device according to Modification 1 of Example 1. FIG. 12 corresponds to an enlarged plan view of Range D in FIG. 2. As shown in FIG. 12, Modification 1 of Example 1 does not include guard metal layers 20a and 20b. The other configurations are the same as those of Example 1, and therefore, description thereof will be omitted. The gate wiring 19b (and 19c) is closer to the drain electrode 16 than the gate wiring 18. Therefore, the parasitic capacitance Cp_gdb between the gate wiring 19b (and 19c) and the drain electrode 16 may be more problematic than the parasitic capacitance Cp_gda between the gate wiring 18 and the drain electrode 16. In such a case, as in Modification 1 of Example 1, it is sufficient to include guard metal layer 21b even if guard metal layers 20a and 20b are not included.

[0048] [Modification 2 of Example 1] 13 is a cross-sectional view of a semiconductor device according to a second modification of the first embodiment. FIG. 13 shows a cross-sectional view of the first embodiment corresponding to the cross section taken along line AA in FIG. 3. As shown in FIG. 13, an end X1 of the guard metal layer 20a that is closer to the drain electrode 16 may be closer to the drain electrode 16 than an end X2 of the source electrode 12 that is closer to the drain electrode 16. The end X1 of the guard metal layer 20a that is closer to the drain electrode 16 may be positioned closer to the source electrode 12 than an end X4 of the drain electrode 16 that is closer to the source electrode 12. However, if the end X1 is too close to the drain electrode 16, the parasitic capacitances Cp_gs and Cp_ds increase. From this viewpoint, end X1 of guard metal layer 20a closer to drain electrode 16 can be aligned with end X5 of gate electrode 14a on the source electrode 12 side or closer to gate wiring 18 than end X5, can be aligned with the midpoint between ends X2 and X5 or closer to source electrode 12 than the midpoint between ends X2 and X5, and can be aligned with end X2 of source electrode 12 on the drain electrode 16 side or closer to gate wiring 18 than end X2. Distance L6 in the X direction between end X1 and end X2 is, for example, 0 μm to 5 μm.

[0049] The end X3 of the guard metal layer 20a closest to the gate wiring 18 may be closer to the drain electrode 16 than the end X6 of the gate wiring 18 closest to the drain electrode 16. However, if the end X3 is too close to the gate wiring 18, the parasitic capacitance Cp_gs increases. From this perspective, the distance L7 between the end X3 of the guard metal layer 20a closest to the gate wiring 18 and the end X6 of the gate wiring 18 closest to the drain electrode 16 can be set to at least one-third, and even at least one-half, of the distance L4. If the distance L7 is too large, the overlap between the end X3 of the guard metal layer 20a and the end X2 of the source electrode 12 becomes small, making it difficult to electrically connect the guard metal layer 20a and the source electrode 12 via the via wiring 22a. From this perspective, the distance L7 can be set to be shorter than the distance L4, and can be set to at most two-thirds of the distance L4. The other configurations are the same as those of the first embodiment, and therefore a description thereof will be omitted.

[0050] [Example 2] 14 and 15 are plan views of the FET in Example 2. Gate electrodes 14a, 14b and pad 15b are omitted from Fig. 14, and guard metal layers 20a, 20b, and 21b are omitted from Fig. 15, and gate electrodes 14a, 14b and pad 15b are indicated by dotted lines. Figs. 16 and 17 are cross-sectional views taken along lines AA and BB in Figs. 14 and 15, respectively.

[0051] 14 to 17, source walls 26a and 26b are provided from above the gate electrodes 14a and 14b toward the drain electrode 16. An insulating film 24a is provided between the source walls 26a and 26b and the gate electrodes 14a and 14b, and between the source walls 26a and 26b and the substrate 10. The source wall 26b is electrically connected to a pad 27b above the inactive region 13 at the end on the positive side in the Y direction. The pad 27b is provided above the pad 15b, and the insulating film 24a is provided between the pads 27b and 15b.

[0052] A via wiring 22f that penetrates the insulating film 24a electrically connects and shorts the guard metal layer 21b and the pad 27b. This causes the source walls 26a and 26b to have the same potential as the source electrode 12. The source walls 26a and 26b are provided to suppress the gate-drain parasitic capacitance between the gate electrodes 14a and 14b and the drain electrode 16. It is sufficient that at least a portion of the source walls 26a and 26b is provided between the gate electrodes 14a and 14b and the drain electrode 16. The other configurations are the same as those in the first embodiment, and therefore a description thereof will be omitted.

[0053] According to the second embodiment, at least a portion of the source wall 26b is provided between the gate electrode 14b and the drain electrode 16 and extends in the Y direction. The guard metal layer 21b is electrically connected to the source wall 26b outside the source electrode 12 through a via wiring 22f (third via wiring). This allows the source wall 26b and the source electrode 12 to be electrically connected without using additional wiring. This allows the semiconductor device to be miniaturized.

[0054] 15, the gate electrodes 14a and 14b are thinner than the source electrode 12 and the drain electrode 16, and therefore the upper surfaces of the source walls 26a and 26b are lower than the upper surfaces of the source electrode 12 and the drain electrode 16. Therefore, even if the source walls 26a and 26b are provided, it is difficult to suppress the parasitic capacitance Cp_gd between the gate wiring 18 and the drain electrode 16. Therefore, the guard metal layers 20a and 20b can be provided. In the first and second modifications of the first embodiment, the source wall 26b, the pad 27b, and the via wiring 22f may be provided.

[0055] In the first embodiment, its modifications, and the second embodiment, an example has been described in which six unit FETs 35a, 35b, and 35c are arranged in the X direction, but the number of unit FETs 35a, 35b, and 35c in the X direction can be designed as desired. Also, an example has been described in which three unit FETs 35a, 35b, and 35c are arranged in the Y direction, but the number of unit FETs 35a, 35b, and 35c in the Y direction can be designed as desired, provided that it is two or more.

[0056] Also, a via may be provided penetrating the substrate 10 in the Z direction, and the source electrode 12 may be electrically connected through the via to a metal layer provided on the underside of the substrate 10. By supplying a reference potential to the metal layer, the potentials of the source electrode 12 and the guard metal layers 20a, 20b, 21b, and 21c can be set to the ground potential.

[0057] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the meaning described above, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0058] 10, 10a board 10b Semiconductor layer 11a, 11b, 11c active area 12 Source electrode 13 Inactive area 14a gate electrode (first gate electrode) 14b gate electrode (second gate electrode) 14c Gate electrode 15a, 15b, 15c, 27b pads 16 Drain electrode 18 Gate wiring (first gate wiring) 19b Gate wiring (second gate wiring) 19a, 19c Gate wiring 20a, 20b: Guard metal layer (second guard wiring) 21b, 21c: Guard metal layer (first guard wiring) 22a, 22b, 22c, 22d, 22e Via wiring (first via wiring) 22f Via wiring (third via wiring) 23b, 23c Via wiring (second via wiring) 23a Via wiring 24, 24a, 24b insulating film 26a, 26b Source Wall 32a Source Busbar 32b Source Pad 34a Gate wiring 34b Gate Pad 35a, 35b, 35c Unit FET 36 Drain Pad 38a, 38b Electric field lines 52 Input matching circuit 54 Output matching circuit 100 Amplifier

Claims

1. A substrate; a source electrode extending in a first direction and disposed on the substrate; a drain electrode extending in the first direction and provided on the substrate; a first gate electrode extending in the first direction and provided on the substrate between the source electrode and the drain electrode; a second gate electrode extending in the first direction and provided on a region of the substrate located in the first direction from the first gate electrode between the source electrode and the drain electrode; a gate pad provided so as to sandwich the first gate electrode between the second gate electrode and the gate pad, the gate pad being electrically connected to the first gate electrode; a first gate wiring provided above the source electrode on the opposite side of the substrate and extending in the first direction; a second gate wiring provided above the source electrode, extending in a second direction intersecting the first direction, having a first end connected to the first gate wiring and a second end opposite to the first end electrically connected to the second gate electrode outside the source electrode; a first guard metal layer provided between the second gate wiring and the drain electrode, at least a portion of which is provided closer to the drain electrode than the source electrode, and electrically connected to the source electrode; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the first guard metal layer is provided to surround a portion of the second gate wiring located outside the source electrode from the first direction, a direction opposite to the first direction, and the second direction.

3. 3. The semiconductor device according to claim 2, wherein a first end of the first guard metal layer is electrically connected to the source electrode in a region away from the second gate wiring in the first direction, and a second end of the first guard metal layer is electrically connected to the source electrode in a region away from the second gate wiring in a direction opposite to the first direction.

4. 4. The semiconductor device according to claim 1, further comprising: a second guard metal layer provided between the first gate wiring and the drain electrode, extending in the first direction, at least a portion of which is provided above the source electrode, and electrically connected to the source electrode.

5. an insulating film provided on the substrate so as to cover the source electrode, the drain electrode, the first gate electrode, and the second gate electrode; 4. The semiconductor device according to claim 1, wherein the first gate wiring, the second gate wiring, and the first guard metal layer are provided on the insulating film.

6. The semiconductor device according to claim 5 , further comprising a first via wiring that penetrates the insulating film and electrically connects the source electrode and the first guard metal layer.

7. The semiconductor device according to claim 5 , further comprising a second via wiring that penetrates the insulating film and electrically connects the second gate electrode and the second gate wiring.

8. a source wall at least a portion of which is provided between the second gate electrode and the drain electrode and which extends in the first direction; 4. The semiconductor device according to claim 1, wherein the first guard metal layer is electrically connected to the source wall outside the source electrode.

9. 4. The semiconductor device according to claim 1, wherein the first gate electrode and the second gate electrode are spaced apart from each other in the first direction on the upper surface of the substrate.

10. 4. The semiconductor device according to claim 1, wherein the thickness of the source electrode and the drain electrode is greater than the thickness of the first gate electrode and the second gate electrode in a normal direction to the upper surface of the substrate.

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