Semiconductor Devices

Abstract

This semiconductor device comprises: a first semiconductor element, a first connecting member, and a first member. The first semiconductor element has a first element main surface and a first element back surface facing opposite sides in the thickness direction. Further, the first semiconductor element has a first electrode arranged on the main surface of the first element. The first connecting member conducts to the first electrode. The first member overlaps with the first electrode in the thickness direction, has a Vickers hardness smaller than the Vickers hardness of the first connecting member, and has conductivity.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Conventionally, aluminum (Al) wires have been bonded to electrodes of semiconductor elements. Recently, power semiconductor elements using semiconductor materials primarily composed of silicon carbide (SiC) have been developed. In such power semiconductor elements, because the current density flowing through the electrodes is high, Cu lead members or Cu wires are bonded to the electrodes instead of Al wires. Furthermore, when Cu wires are bonded, Cu plate members are bonded to the electrodes as buffer materials. In other words, in such power semiconductor elements, Cu connecting members are bonded to the electrodes. Patent Document 1 discloses a semiconductor device using sintered metal as a bonding material for bonding connecting members to the electrodes of a semiconductor element. In Patent Document 1, a sintering metal material (a sinterable silver film) is placed between a semiconductor element and a clip serving as a connecting member, and a sintering process is performed to turn the sintering metal material into sintered metal (sintered silver), and the clip is bonded to the semiconductor element. In the sintering process, a pressure member presses the clip against the semiconductor element, and the sintering metal material is compressed by this pressing force. Then, the sintering metal material is heated under pressure.

[0003] When multiple semiconductor elements are mounted on a single semiconductor device, the connection members are bonded to each semiconductor element simultaneously. Slight variations in the thickness of each semiconductor element and each connection member are permitted. Furthermore, the substrate on which each semiconductor element is mounted may also have slight warping. Furthermore, the thickness of the sintering metal material disposed between the electrodes of each semiconductor element and the connection member, and between the substrate and the semiconductor element, may also vary. As a result, the position (overall height) of the top surface (the surface facing away from the semiconductor element) of the connection member bonded to each semiconductor element may not be uniform. In this case, when each connection member is pressed with a single pressure member, the load applied to each semiconductor element is not uniform. Therefore, a semiconductor element subjected to a large load may be destroyed. Furthermore, multiple semiconductor devices are generally manufactured simultaneously. Therefore, even in a semiconductor device with only one semiconductor element mounted, the semiconductor element may be destroyed during a sintering process involving pressure application due to uneven load caused by uneven height. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2018-504788 Summary of the Invention [Problem to be solved by the invention]

[0005] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can prevent a biased load from being applied to a semiconductor element during a sintering process that involves pressure application. [Means for solving the problem]

[0006] The semiconductor device provided by the present disclosure includes a first semiconductor element, a first connection member, and a first member. The first semiconductor element has a first element main surface and a first element back surface facing opposite each other in a thickness direction, and has a first electrode disposed on the first element main surface. The first connection member is electrically connected to the first electrode. The first member overlaps the first electrode when viewed in the thickness direction, has a Vickers hardness lower than that of the first connection member, and is electrically conductive. [Effects of the Invention]

[0007] According to the above configuration, it is possible to prevent a biased load from being applied to the semiconductor element during the sintering process involving pressure application.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a perspective view showing the semiconductor device of FIG. 1, with the sealing resin omitted. [Figure 3] FIG. 2 is a plan view showing the semiconductor device of FIG. [Figure 4] FIG. 2 is a plan view showing the semiconductor device of FIG. 1, with the sealing resin omitted. [Figure 5] FIG. 5 is a partially enlarged view of a part of FIG. 4. [Figure 6] FIG. 2 is a front view showing the semiconductor device of FIG. [Figure 7] FIG. 2 is a bottom view showing the semiconductor device of FIG. [Figure 8] FIG. 2 is a left side view showing the semiconductor device of FIG. [Figure 9] FIG. 2 is a right side view showing the semiconductor device of FIG. [Figure 10] FIG. 5 is a cross-sectional view taken along line XX in FIG. 4. [Figure 11]FIG. 3 is a partially enlarged view of a part of FIG. 2. [Figure 12] FIG. 5 is a partially enlarged view of a part of FIG. 4. [Figure 13] FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. [Figure 14] FIG. 5 is a partially enlarged view of a part of FIG. 4. [Figure 15] FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. [Figure 16A] FIG. 10 is a schematic diagram for explaining a pressurizing and heating step, showing the state before the two buffer members are deformed. [Figure 16B] 10 is a schematic diagram for explaining a pressurizing and heating step, showing a state in which one of the buffer members is deformed. FIG. [Figure 17] FIG. 10 is a partially enlarged plan view showing a semiconductor device according to a second embodiment of the present disclosure. [Figure 18] FIG. 18 is a partially enlarged cross-sectional view showing the semiconductor device of FIG. [Figure 19] FIG. 10 is a partially enlarged perspective view showing a semiconductor device according to a third embodiment of the present disclosure. [Figure 20] FIG. 20 is a partially enlarged cross-sectional view showing the semiconductor device of FIG. 19. [Figure 21] FIG. 10 is a partially enlarged cross-sectional view showing a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 22] FIG. 10 is a partially enlarged cross-sectional view showing a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 23] FIG. 10 is a partially enlarged cross-sectional view showing a semiconductor device according to a sixth embodiment of the present disclosure. [Figure 24] FIG. 12 is a partially enlarged cross-sectional view showing a semiconductor device according to a seventh embodiment of the present disclosure. [Figure 25] FIG. 13 is a partially enlarged cross-sectional view showing a semiconductor device according to an eighth embodiment of the present disclosure. [Figure 26] FIG. 13 is a perspective view showing a semiconductor device according to a ninth embodiment of the present disclosure. [Figure 27] FIG. 27 is a cross-sectional view taken along line XXVII-XXVII in FIG. 26. [Figure 28A]27 is a schematic diagram for explaining a pressurizing and heating step in the manufacturing process of the semiconductor device of FIG. 26, showing the state before each buffer member is deformed. FIG. [Figure 28B] 27 is a schematic diagram for explaining a pressurizing and heating step in the manufacturing process of the semiconductor device of FIG. 26, showing a state in which one of the buffer members is deformed. DETAILED DESCRIPTION OF THE INVENTION

[0010] Preferred embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0011] In this disclosure, unless otherwise specified, the terms "a certain object A is formed on an object B" and "a certain object A is formed on an object B" include "a certain object A is formed directly on an object B" and "a certain object A is formed on an object B with another object interposed between the objects A and B." Similarly, the terms "a certain object A is disposed on an object B" and "a certain object A is disposed on an object B" include "a certain object A is disposed directly on an object B" and "a certain object A is disposed on an object B with another object interposed between the objects A and B," unless otherwise specified. Similarly, the term "a certain object A is located on an object B" includes "a certain object A is located on an object B in contact with the object B" and "a certain object A is located on an object B with another object interposed between the objects A and B," unless otherwise specified. Additionally, unless otherwise specified, "something A overlaps something B when viewed from a certain direction" includes "something A overlaps the entirety of something B" and "something A overlaps part of something B."

[0012] 1 to 15, a semiconductor device A1 according to a first embodiment of the present disclosure will be described. The semiconductor device A1 includes a plurality of semiconductor elements 10, a support substrate 20, a plurality of conductive bonding layers 3, input terminals 41 and 42, an output terminal 43, a pair of gate terminals 44A and 44B, a pair of detection terminals 45A and 45B, a plurality of dummy terminals 46, a pair of side terminals 47A and 47B, an insulating member 49, a plurality of lead members 51, a plurality of buffer members 8, a plurality of wires 6, and a sealing resin 7. Note that the input terminals 41 and 42, the output terminal 43, the pair of gate terminals 44A and 44B, the pair of detection terminals 45A and 45B, the plurality of dummy terminals 46, and the pair of side terminals 47A and 47B may be collectively referred to as terminals 40.

[0013] FIG. 1 is a perspective view of the semiconductor device A1. FIG. 2 is a perspective view of the semiconductor device A1, with the sealing resin 7 omitted. FIG. 3 is a plan view of the semiconductor device A1. FIG. 4 is a plan view of the semiconductor device A1, with the sealing resin 7 omitted. In FIG. 4, the sealing resin 7 is indicated by an imaginary line (two-dot chain line). FIG. 5 is a partial enlarged view of a portion of FIG. 4. FIG. 6 is a front view of the semiconductor device A1. FIG. 7 is a bottom view of the semiconductor device A1. FIG. 8 is a left side view of the semiconductor device A1. FIG. 9 is a right side view of the semiconductor device A1. FIG. 10 is a cross-sectional view taken along line XX in FIG. 4. FIG. 11 is a partial enlarged view of a portion including a lead member 51 in the perspective view of FIG. 2. In FIG. 11, the wires 6 are omitted. FIG. 12 is a partial enlarged view of a portion including a semiconductor element 10A (described later) in the plan view of FIG. 4. In FIG. 12, lead members 51 are shown in perspective with imaginary lines (two-dot chain lines). FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 12. FIG. 14 is a partially enlarged view of a portion including a semiconductor element 10B (described later) in the plan view shown in FIG. 4. In FIG. 14, input terminals 42 are shown in perspective with imaginary lines (two-dot chain lines). FIG. 15 is a cross-sectional view taken along line XV-XV in FIG.

[0014] The semiconductor device A1 has a rectangular shape when viewed in the thickness direction (plan view). For convenience of explanation, the thickness direction (plan view) of the semiconductor device A1 is defined as the z direction, the direction along one side of the semiconductor device A1 perpendicular to the z direction (the left-right direction in FIGS. 3 and 4) is defined as the x direction, and the direction perpendicular to the z direction and the x direction (the up-down direction in FIGS. 3 and 4) is defined as the y direction. Furthermore, one side of the z direction (the lower side in FIGS. 6, 8, and 9) is defined as the z1 side, and the other side (the upper side in FIGS. 6, 8, and 9) is defined as the z2 side. One side of the x direction (the left side in FIGS. 3 and 4) is defined as the x1 side, and the other side (the right side in FIGS. 3 and 4) is defined as the x2 side. One side of the y direction (the lower side in FIGS. 3 and 4) is defined as the y1 side, and the other side (the upper side in FIGS. 3 and 4) is defined as the y2 side. The z direction is an example of a "thickness direction." Dimensions of the semiconductor device A1 are not limited.

[0015] Each of the multiple semiconductor elements 10 is made of a semiconductor material primarily composed of SiC (silicon carbide). The semiconductor material is not limited to SiC and may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or the like. In this embodiment, each semiconductor element 10 is a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Each semiconductor element 10 is not limited to a MOSFET and may be a field-effect transistor including a MISFET (Metal-Insulator-Semiconductor FET), an IGBT (Insulated Gate Bipolar Transistor), a bipolar transistor, or an IC chip such as an LSI. In this embodiment, each semiconductor element 10 is the same element and is an n-channel MOSFET. Each semiconductor element 10 has a rectangular shape when viewed in the z direction (plan view). In this embodiment, the thickness (z-direction dimension) of each semiconductor element 10 is approximately 350 to 370 μm, but may be approximately 100 μm. The shape and dimensions of each semiconductor element 10 are not limited.

[0016] As shown in FIGS. 10, 13, and 15, each semiconductor element 10 has an element main surface 101 and an element back surface 102. In each semiconductor element 10, the element main surface 101 and the element back surface 102 are spaced apart in the z direction and face opposite each other. In this embodiment, the element main surface 101 faces the z2 side in the z direction, and the element back surface 102 faces the z1 side in the z direction. Each semiconductor element 10 is an example of a "first semiconductor element" or a "second semiconductor element."

[0017] As shown in FIGS. 5 and 11 to 15, each semiconductor element 10 includes a source electrode 111, a gate electrode 112, a drain electrode 113, and an insulating film 13.

[0018] The source electrode 111 and the gate electrode 112 are disposed on the main surface 101 of the device. The source electrode 111 is larger than the gate electrode 112. Although the present embodiment illustrates a case in which the source electrode 111 is configured as a single region, it may be divided into multiple regions. The drain electrode 113 is disposed on the rear surface 102 of the device. In the present embodiment, the drain electrode 113 is formed over almost the entire rear surface 102 of the device. As shown in FIGS. 13 and 15 , a plating layer 115 is formed on the surfaces of the source electrode 111, the gate electrode 112, and the drain electrode 113. In the present embodiment, the plating layer 115 is formed of multiple metal plating layers, for example, Ni, Pd, and Au, stacked in this order. The configuration of the plating layer 115 is not limited. The plating layer 115 may have a metal layer formed on its outermost surface that is metallically bonded to the conductive bonding layer 3. The source electrode 111 is an example of a "first electrode" or a "second electrode."

[0019] The insulating film 13 is provided on the element principal surface 101. The insulating film 13 has electrical insulation properties. The insulating film 13 surrounds the source electrode 111 and the gate electrode 112 when viewed in the z direction. The insulating film 13 is formed by laminating, for example, a SiO2 (silicon dioxide) layer, a SiN4 (silicon nitride) layer, and a polybenzoxazole layer in this order from the element principal surface 101. Note that the insulating film 13 may be formed by laminating a polyimide layer instead of the polybenzoxazole layer.

[0020] The multiple semiconductor elements 10 include multiple semiconductor elements 10A and multiple semiconductor elements 10B. In this embodiment, the semiconductor device A1 configures a half-bridge switching circuit. The multiple semiconductor elements 10A configure an upper arm circuit in this switching circuit, and the multiple semiconductor elements 10B configure a lower arm circuit in this switching circuit. As shown in FIGS. 2 and 4, the semiconductor device A1 includes four semiconductor elements 10A and four semiconductor elements 10B. Note that the number of semiconductor elements 10 is not limited to this configuration and can be freely set depending on the performance required of the semiconductor device A1.

[0021] As shown in FIGS. 2, 4, 5, and 11 to 13, each of the multiple semiconductor elements 10A is mounted on a support substrate 20 (conductive member 22A, which will be described later). In this embodiment, the multiple semiconductor elements 10A are aligned at equal intervals in the y direction and spaced apart from one another. When each semiconductor element 10A is mounted on the conductive member 22A, the element back surface 102 faces the conductive member 22A. As shown in FIGS. 4, 5, and 11 to 13, each semiconductor element 10A is conductively bonded to the support substrate 20 (conductive member 22A) via a conductive bonding layer 3 (element bonding layer 31A, which will be described later).

[0022] As shown in FIGS. 2, 4, 5, 14, and 15, each of the multiple semiconductor elements 10B is mounted on a support substrate 20 (a conductive member 22B described later). In this embodiment, the multiple semiconductor elements 10B are aligned at equal intervals in the y direction and spaced apart from one another. When each semiconductor element 10B is mounted on the conductive member 22B, the element back surface 102 faces the conductive member 22B. As shown in FIGS. 4, 5, 10, 14, and 15, each semiconductor element 10B is conductively bonded to the support substrate 20 (the conductive member 22B) via a conductive bonding layer 3 (an element bonding layer 31B described later).

[0023] The support substrate 20 is a support member that supports a plurality of semiconductor elements 10. The support substrate 20 includes an insulating substrate 21, a plurality of conductive members 22, a pair of insulating layers 23A and 23B, a pair of gate layers 24A and 24B, and a pair of detection layers 25A and 25B.

[0024] As shown in Fig. 10, insulating substrate 21 has a plurality of conductive members 22 arranged thereon. Insulating substrate 21 has electrical insulation properties. The constituent material of insulating substrate 21 is, for example, ceramics with excellent thermal conductivity. Examples of such ceramics include AlN (aluminum nitride), SiN (silicon nitride), and Al2O3 (aluminum oxide). In this embodiment, insulating substrate 21 has a rectangular shape when viewed in the z direction.

[0025] As shown in FIG. 10 , the insulating substrate 21 has a main surface 211 and a back surface 212. The main surface 211 and the back surface 212 are spaced apart in the z direction and face opposite directions. The main surface 211 faces the z2 side in the z direction, and has a plurality of conductive members 22 arranged thereon. The main surface 211, along with the plurality of conductive members 22 and the plurality of semiconductor elements 10, is covered with the sealing resin 7. The back surface 212 faces the z1 side in the z direction, and is exposed from the sealing resin 7 as shown in FIGS. 7 and 10 . For example, a heat sink or the like (not shown) is connected to the back surface 212. Note that the configuration of the insulating substrate 21 is not limited to that described above. For example, the insulating substrate 21 may be provided individually for each of the plurality of conductive members 22.

[0026] Each of the plurality of conductive members 22 is a metal plate. The metal plate is made of Cu or a Cu alloy. The plurality of conductive members 22, together with the plurality of terminals 40, form a conductive path with the plurality of semiconductor elements 10. The plurality of conductive members 22 are spaced apart from one another and are disposed on the main surface 211 of the insulating substrate 21. Each conductive member 22 is bonded to the main surface 211 of the insulating substrate 21 with a bonding material such as silver paste or solder. The bonding material may be a conductive material or an insulating material. In this embodiment, the dimension of the conductive member 22 in the z direction is approximately 0.4 to 3.0 mm, but is not limited thereto. In this embodiment, as shown in FIGS. 13 and 15 , a plating layer 222 is formed on the surface of each conductive member 22. The plating layer 222 is formed in contact with the surface of each conductive member 22 and covers at least the portion on which the semiconductor element 10 is mounted. The plating layer 222 may cover the entire surface of each conductive member 22. In this embodiment, the plating layer 222 contains, for example, Ag. The material of the plating layer 222 is not limited, and may be any metal material that can be metal-bonded to the conductive bonding layer 3.

[0027] The plurality of conductive members 22 include conductive member 22A and conductive member 22B. In this embodiment, the conductive members 22A and 22B are aligned in the x direction on the insulating substrate 21. As shown in FIGS. 2, 4, and 10, the conductive member 22A is disposed on the x2 side in the x direction relative to the conductive member 22B. The conductive member 22A has a main surface 221A facing the z2 side in the z direction, and a plurality of semiconductor elements 10A are mounted on the main surface 221A. The conductive member 22B has a main surface 221B facing the z2 side in the z direction, and a plurality of semiconductor elements 10B are mounted on the main surface 221B. In this embodiment, both conductive members 22A and 22B are rectangular when viewed in the z direction. The configuration of the plurality of conductive members 22 is not limited to the above and can be changed as appropriate based on the number and arrangement of the plurality of semiconductor elements 10. The conductive members 22A and 22B are examples of "conductors."

[0028] The pair of insulating layers 23A, 23B have electrical insulation properties and are made of, for example, glass epoxy resin. As shown in FIGS. 2 and 4, the pair of insulating layers 23A, 23B are each strip-shaped and extend in the y direction. The insulating layer 23A is bonded to the main surface 221A of the conductive member 22A. The insulating layer 23A is located on the x2 side of the multiple semiconductor elements 10A in the x direction. The insulating layer 23B is bonded to the main surface 221B of the conductive member 22B. The insulating layer 23B is located on the x1 side of the semiconductor elements 10B in the x direction.

[0029] The pair of gate layers 24A, 24B are conductive and are made of, for example, Cu. As shown in FIGS. 2 and 4, the pair of gate layers 24A, 24B are each strip-shaped extending in the y direction. The gate layer 24A is disposed on the insulating layer 23A. The gate layer 24A is electrically connected to the gate electrodes 112 of each semiconductor element 10A via wires 6 (gate wires 61, which will be described later). The gate layer 24B is disposed on the insulating layer 23B. The gate layer 24B is electrically connected to the gate electrodes 112 of each semiconductor element 10B via wires 6 (gate wires 61, which will be described later).

[0030] The pair of detection layers 25A, 25B are conductive and made of, for example, Cu. As shown in FIGS. 2 and 4, each of the pair of detection layers 25A, 25B has a strip shape extending in the y direction. The detection layer 25A is disposed on the insulating layer 23A together with the gate layer 24A. The detection layer 25A is located adjacent to the gate layer 24A on the insulating layer 23A and is spaced apart from the gate layer 24A. In this embodiment, the detection layer 25A is disposed closer to the semiconductor elements 10A in the x direction than the gate layer 24A. Therefore, the detection layer 25A is located on the x1 side of the gate layer 24A in the x direction. Note that the positions of the gate layer 24A and the detection layer 25A in the x direction may be reversed. The detection layer 25A is electrically connected to the source electrode 111 of each semiconductor element 10A via a wire 6 (a detection wire 62, described later). The detection layer 25B is disposed on the insulating layer 23B together with the gate layer 24B. The detection layer 25B is located next to the gate layer 24B on the insulating layer 23B and is spaced apart from the gate layer 24B. In this embodiment, the detection layer 25B is disposed closer to the semiconductor elements 10B in the x direction than the gate layer 24B. Therefore, the detection layer 25B is located on the x2 side of the gate layer 24B in the x direction. Note that the positions of the gate layer 24B and the detection layer 25B in the x direction may be reversed. The detection layer 25B is electrically connected to the source electrode 111 of each semiconductor element 10B via a wire 6 (a detection wire 62 described later).

[0031] Each of the base portions 29 has electrical insulation properties and is made of, for example, ceramics. As shown in FIGS. 2 and 10 , each base portion 29 is joined to the main surface 221A of the conductive member 22A. In this embodiment, each base portion 29 is rectangular when viewed in the z direction. The base portions 29 are arranged at equal intervals in the y direction and are spaced apart from one another. The dimension of each base portion 29 in the z direction is approximately the same as the sum of the dimension of the input terminal 41 in the z direction and the dimension of the insulating member 49 in the z direction. A portion of the input terminal 42 is joined to each base portion 29, supporting the input terminal 42 and stabilizing the position of the input terminal 42. Note that the semiconductor device A1 does not necessarily have to include multiple base portions 29.

[0032] The input terminals 41 and 42 are each a metal plate. The metal plate is made of Cu or a Cu alloy. In this embodiment, the z-direction dimension of each of the input terminals 41 and 42 is approximately 0.8 mm, but is not limited to this. As shown in FIGS. 4 and 10, each of the input terminals 41 and 42 is located near the x2 side of the semiconductor device A1 in the x-direction. A power supply voltage, for example, is applied between the input terminals 41 and 42. The power supply voltage may be applied to the input terminals 41 and 42 directly from a power supply (not shown). Alternatively, a bus bar (not shown) may be connected to sandwich the input terminals 41 and 42, and the power supply voltage may be applied via the bus bar. A snubber circuit or the like may be connected in parallel between the input terminals 41 and 42. The input terminal 41 is a positive terminal (P terminal), and the input terminal 42 is a negative terminal (N terminal). The input terminal 42 is disposed apart from both the input terminal 41 and the conductive member 22A in the z direction.

[0033] The input terminal 41 is electrically connected to the drain electrodes 113 of the semiconductor elements 10A via the conductive member 22A. The input terminal 41 includes a pad portion 411 and a terminal portion 412, as shown in FIGS.

[0034] The pad portion 411 is a portion of the input terminal 41 that is covered with the sealing resin 7. The end of the pad portion 411 on the x-direction x1 side is comb-shaped and includes a plurality of comb teeth 411a. Each of the plurality of comb teeth 411a is conductively joined to the main surface 221A of the conductive member 22A. The joining method may be laser welding using a laser beam, ultrasonic joining, or joining using a conductive joining material.

[0035] The terminal portion 412 is a portion of the input terminal 41 that is exposed from the sealing resin 7. As shown in FIGS. 7, 9, and 10, the terminal portion 412 extends from the sealing resin 7 to the x2 side in the x direction when viewed in the z direction.

[0036] The input terminal 42 is electrically connected to each of the source electrodes 111 of the semiconductor elements 10B. The input terminal 42 includes a pad portion 421 and a terminal portion 422, as shown in FIGS.

[0037] The pad portion 421 is a portion of the input terminal 42 that is covered with the sealing resin 7. The pad portion 421 includes a connecting portion 421a, multiple extending portions 421b, and multiple protruding portions 421c. The connecting portion 421a is strip-shaped and extends in the y direction. The connecting portion 421a is connected to the terminal portion 422. The multiple extending portions 421b are strip-shaped and extend from the connecting portion 421a toward the x1 side in the x direction. In this embodiment, each extending portion 421b extends from the connecting portion 421a until it overlaps with the semiconductor element 10B as viewed in the z direction. The multiple extending portions 421b are aligned in the y direction and spaced apart from one another as viewed in the z direction. A portion of the surface of each extending portion 421b facing the z1 side in the z direction is in contact with each base portion 29, and the extending portion 421b is supported by the conductive member 22A via the base portion 29. The multiple protrusions 421c are portions of the tip portion (end portion on the x1 side in the x-direction) of each extension portion 421b that protrude from the extension portion 421b toward the z1 side in the z-direction. Each protrusion 421c eliminates the difference in height in the z-direction between the extension portion 421b and the semiconductor element 10B. Each protrusion 421c is electrically connected to the source electrode 111 of the semiconductor element 10B via the buffer member 8 and the conductive bonding layer 3 (terminal bonding layer 33, described later). When viewed in the z-direction, the protrusion 421c overlaps the source electrode 111 of the semiconductor element 10B. In this embodiment, as shown in FIG. 15 , a plating layer 421d is formed on the surface of each protrusion 421c facing the semiconductor element 10B. The plating layer 421d may also cover other surfaces of the input terminal 42, or may cover the entire surface. In this embodiment, the plating layer 421d is made of, for example, Ag. The material of the plating layer 421d is not limited.

[0038] The terminal portion 422 is a portion of the input terminal 42 that is exposed from the sealing resin 7. As shown in FIGS. 4 and 10, the terminal portion 422 extends from the sealing resin 7 toward the x2 side in the x direction when viewed in the z direction. The terminal portion 422 has a rectangular shape when viewed in the z direction. As shown in FIGS. 4 and 10, the terminal portion 422 overlaps with the terminal portion 412 of the input terminal 41 when viewed in the z direction. The terminal portion 422 is spaced apart from the terminal portion 412 on the z2 side in the z direction. In this embodiment, the shape of the terminal portion 422 is the same as the shape of the terminal portion 412. The input terminal 42 is an example of a "first connecting member."

[0039] The output terminal 43 is a metal plate. The metal plate is made of, for example, Cu or a Cu alloy. As shown in FIGS. 2 and 4, the output terminal 43 is located on the x1 side of the semiconductor device A1 in the x-direction. The output terminal 43 is electrically connected to the drain electrodes 113 of the semiconductor elements 10B via the conductive member 22B. The output terminal 43 is also electrically connected to the source electrodes 111 of the semiconductor elements 10A via the conductive member 22B and the lead member 51. A voltage converted by turning on and off the semiconductor elements 10A is output from the output terminal 43. As shown in FIGS. 2 and 4, the output terminal 43 includes a pad portion 431 and a terminal portion 432.

[0040] The pad portion 431 is a portion of the output terminal 43 that is covered with the sealing resin 7. A portion of the pad portion 431 on the x2 side in the x-direction is comb-shaped and includes a plurality of comb-tooth portions 431a. Each of the plurality of comb-tooth portions 431a is conductively joined to the main surface 221B of the conductive member 22B. The joining method may be laser welding using a laser beam, ultrasonic joining, or joining using a conductive joining material.

[0041] The terminal portion 432 is a portion of the output terminal 43 that is exposed from the sealing resin 7. As shown in FIGS. 3, 6, 7, 8, and 10, the terminal portion 432 extends from the sealing resin 7 to the x-direction x1 side.

[0042] 1 to 7, the pair of gate terminals 44A, 44B are located adjacent to the respective conductive members 22A, 22B in the y direction. A gate voltage for driving the plurality of semiconductor elements 10A is applied to the gate terminal 44A. A gate voltage for driving the plurality of semiconductor elements 10B is applied to the gate terminal 44B.

[0043] As shown in FIGS. 4 and 5, each of the pair of gate terminals 44A, 44B includes a pad portion 441 and a terminal portion 442. In each of the gate terminals 44A, 44B, the pad portion 441 is covered with the sealing resin 7. As a result, each of the gate terminals 44A, 44B is supported by the sealing resin 7. The surface of the pad portion 441 may be plated with silver, for example. The terminal portion 442 is connected to the pad portion 441 and is exposed from the sealing resin 7. The terminal portion 442 is L-shaped when viewed in the x direction.

[0044] 1 to 7, the pair of detection terminals 45A, 45B are located adjacent to the pair of gate terminals 44A, 44B in the x direction. The detection terminal 45A detects the voltage applied to each source electrode 111 of the multiple semiconductor elements 10A. The detection terminal 45B detects the voltage applied to each source electrode 111 of the multiple semiconductor elements 10B.

[0045] As shown in FIGS. 4 and 5, each of the pair of detection terminals 45A, 45B includes a pad portion 451 and a terminal portion 452. In each of the detection terminals 45A, 45B, the pad portion 451 is covered with the sealing resin 7. As a result, each of the detection terminals 45A, 45B is supported by the sealing resin 7. The surface of the pad portion 451 may be plated with silver, for example. The terminal portion 452 is connected to the pad portion 451 and is exposed from the sealing resin 7. The terminal portion 452 is L-shaped when viewed in the x direction.

[0046] As shown in FIGS. 1 to 7, the multiple dummy terminals 46 are located on the opposite side of the pair of gate terminals 44A, 44B in the x direction from the pair of detection terminals 45A, 45B. In this embodiment, there are six dummy terminals 46. Three of the dummy terminals 46 are located on one side in the x direction (x2 side in the x direction). The remaining three dummy terminals 46 are located on the other side in the x direction (x1 side in the x direction). The multiple dummy terminals 46 are not limited to the configuration described above. Furthermore, the semiconductor device A1 may be configured without the multiple dummy terminals 46.

[0047] As shown in FIGS. 4 and 5 , each of the multiple dummy terminals 46 includes a pad portion 461 and a terminal portion 462. In each dummy terminal 46, the pad portion 461 is covered with the sealing resin 7. As a result, the multiple dummy terminals 46 are supported by the sealing resin 7. The surface of the pad portion 461 may be plated with silver, for example. The terminal portion 462 is connected to the pad portion 461 and is exposed from the sealing resin 7. The terminal portion 462 is L-shaped when viewed in the x direction. The shape of the terminal portion 462 is the same as the shape of each terminal portion 442 of the pair of gate terminals 44A, 44B and the shape of each terminal portion 452 of the pair of detection terminals 45A, 45B.

[0048] As shown in FIG. 4 , the pair of side terminals 47A, 47B overlap an end of the sealing resin 7 on the y1 side in the y direction when viewed in the z direction. The side terminal 47A overlaps an end of the sealing resin 7 on the x2 side in the x direction, and the side terminal 47B overlaps an end of the sealing resin 7 on the x1 side in the x direction. The side terminal 47A is joined to the conductive member 22A and is covered with the sealing resin 7 except for an end face facing the x2 side in the x direction. The side terminal 47B is joined to the conductive member 22B and is covered with the sealing resin 7 except for an end face facing the x1 side in the x direction. In this embodiment, the entire side terminals 47A, 47B overlap the sealing resin 7 when viewed in the z direction. The side terminals 47A, 47B may be joined by laser welding, ultrasonic bonding, or bonding using a conductive bonding material. Each of the side terminals 47A, 47B has a portion bent in the z direction as viewed in the z direction, and another portion bent in the z direction. Note that the configuration of each of the side terminals 47A, 47B is not limited to this. For example, each of the side terminals 47A, 47B may extend to protrude from the sealing resin 7 as viewed in the z direction. Also, the semiconductor device A1 may not include each of the side terminals 47A, 47B.

[0049] 1 to 7, the pair of gate terminals 44A, 44B, the pair of detection terminals 45A, 45B, and the plurality of dummy terminals 46 are arranged along the x direction when viewed in the z direction. In the semiconductor device A1, the pair of gate terminals 44A, 44B, the pair of detection terminals 45A, 45B, the plurality of dummy terminals 46, and the pair of side terminals 47A, 47B are all formed from the same lead frame.

[0050] The insulating member 49 has electrical insulation properties and is made of, for example, insulating paper. A portion of the insulating member 49 is a flat plate, and as shown in FIGS. 6, 9, and 10, is sandwiched in the z direction between the terminal portion 412 of the input terminal 41 and the terminal portion 422 of the input terminal 42. When viewed in the z direction, the entire input terminal 41 overlaps the insulating member 49. When viewed in the z direction, a portion of the pad portion 421 and the entire terminal portion 422 of the input terminal 42 overlap the insulating member 49. The two input terminals 41 and 42 are insulated from each other by the insulating member 49. A portion of the insulating member 49 (the portion on the x1 side in the x direction) is covered with the sealing resin 7.

[0051] 10 , insulating member 49 includes intervening portion 491 and extending portion 492. Intervening portion 491 is interposed in the z direction between terminal portion 412 of input terminal 41 and terminal portion 422 of input terminal 42. Intervening portion 491 is entirely sandwiched between terminal portion 412 and terminal portion 422. Extended portion 492 extends from intervening portion 491 toward the x2 side in the x direction, further than terminal portion 412 and terminal portion 422.

[0052] The multiple lead members 51 are each electrically connected to the source electrodes 111 of different semiconductor elements 10A. Each lead member 51 electrically connects the source electrode 111 of the semiconductor element 10A to the conductive member 22B. When viewed in the z direction, each lead member 51 has a rectangular shape extending in the x direction. Each lead member 51 is a plate-shaped connecting member. Each lead member 51 has a first joint portion 511, a second joint portion 512, and a connecting portion 513.

[0053] The first bonding portion 511 is a portion that is electrically connected to the source electrode 111 of the semiconductor element 10A via the buffer member 8 and the conductive bonding layer 3 (the lead bonding layer 321 described later). The first bonding portion 511 overlaps the source electrode 111 of the semiconductor element 10A when viewed in the z direction. In this embodiment, as shown in FIG. 13 , a plating layer 515 is formed on the surface of the first bonding portion 511 that faces the semiconductor element 10A. The plating layer 515 may also cover other surfaces of the lead member 51, or may cover the entire surface. In this embodiment, the plating layer 515 is made of, for example, Ag. The material of the plating layer 515 is not limited. In this embodiment, the dimension (thickness) of the first bonding portion 511 in the z direction is approximately 160 to 200 μm. The thickness of the first bonding portion 511 is not limited to this.

[0054] The second bonding portion 512 is a portion bonded to the conductive member 22B via a conductive bonding layer 3 (a lead bonding layer 322 described later). In this embodiment, a plating layer 515 is also formed on the surface of the second bonding portion 512 facing the conductive member 22B. The thickness of the second bonding portion 512 is greater than the thickness of the first bonding portion 511. In this embodiment, the dimension (thickness) of the second bonding portion 512 in the z direction is approximately 500 to 700 μm. However, the thickness of the second bonding portion 512 is not limited to this.

[0055] The connecting portion 513 is a portion that connects the first bonding portion 511 and the second bonding portion 512. The surface of the connecting portion 513 facing the z-direction z1 contacts the sealing resin 7. The thickness of the connecting portion 513 is the same as the thickness of the first bonding portion 511, and is approximately 160 to 200 μm. However, the thickness of the connecting portion 513 is not limited to this. The lead member 51 is an example of a "first connecting member" or a "second connecting member."

[0056] The multiple buffer members 8 deform themselves during the pressurizing and heating process described below so as to distribute the load on each semiconductor element 10 evenly. The multiple buffer members 8 include multiple buffer members 81 and multiple buffer members 82. As shown in FIGS. 12 and 13 , the multiple buffer members 81 are each interposed between the source electrode 111 of the semiconductor element 10A and the first bonding portion 511 of the lead member 51. When viewed in the z direction, the multiple buffer members 81 overlap the source electrode 111 of the semiconductor element 10A. As shown in FIGS. 14 and 15 , the multiple buffer members 82 are each interposed between the source electrode 111 of the semiconductor element 10B and each protrusion 421c of the input terminal 42. When viewed in the z direction, the multiple buffer members 82 overlap the source electrode 111 of the semiconductor element 10B. When the buffer members 81 and 82 are not distinguished from each other, they are referred to as buffer members 8.

[0057] As shown in FIGS. 13 and 15 , each buffer member 8 has a main surface 801 and a back surface 802. The main surface 801 and the back surface 802 are spaced apart in the z direction and face opposite each other. In this embodiment, the main surface 801 faces the z2 side in the z direction and faces the first joint portion 511 of the lead member 51 or each protrusion 421c of the input terminal 41. The back surface 802 faces the z1 side in the z direction and faces the source electrode 111 of the semiconductor element 10. A plating layer 85 is formed on the entire surfaces of the main surface 801 and the back surface 802. The plating layer 85 is formed in contact with the main surface 801 or the back surface 802. In this embodiment, the plating layer 85 is made of, for example, Ag. As shown in FIG. 13, the buffer member 81 and the first bonding portion 511 of the lead member 51 are bonded by solid-state diffusion bonding between a plating layer 85 (Ag) formed on the main surface 801 of the buffer member 81 and a plating layer 515 (Ag) formed on the first bonding portion 511. Also, as shown in FIG. 15, the buffer member 82 and the protruding portion 421c of the input terminal 42 are bonded by solid-state diffusion bonding between a plating layer 85 (Ag) formed on the main surface 801 of the buffer member 82 and a plating layer 421d (Ag) formed on the protruding portion 421c. Also, as shown in FIGS. 13 and 15, the buffer member 8 and the source electrode 111 of the semiconductor element 10 are bonded by a conductive bonding layer 3. The buffer member 8 may also be bonded to the first bonding portion 511 or the protruding portion 421c by the conductive bonding layer 3. The material of the plating layer 85 is not limited.

[0058] Each buffer member 8 has a lower Vickers hardness than each lead member 51 and input terminal 41 and is conductive. In this embodiment, since each lead member 51 and input terminal 41 are made of Cu, each buffer member 8 is made of Al, a material with a lower Vickers hardness than Cu. Here, Vickers hardness (unit: HV) is a measure of hardness and is calculated by pressing a pyramidal diamond indenter into the material surface with a test load and dividing the test load by the surface area of ​​the indentation formed. Note that the material of each buffer member 8 is not limited, and any material may be used as long as it has a lower Vickers hardness than each lead member 51 and input terminal 41. The Vickers hardness of each buffer member 8 is preferably 1HV or more but not more than 50HV, and may be, for example, Sn, In, or Zn. When each lead member 51 or input terminal 42 is pressed against the semiconductor element 10 during the pressurizing and heating process, each buffer member 8 deforms itself to prevent uneven load from being applied to the semiconductor element 10.

[0059] 16A and 16B are schematic diagrams illustrating how the buffer members 8 deform themselves during the pressurizing and heating process to evenly distribute the load on each semiconductor element 10. FIG. 16A shows two semiconductor elements 10A mounted on a conductive member 22A, lead members 51 electrically connected to each semiconductor element 10A, and buffer members 81 disposed between the semiconductor elements 10A and the lead members 51. None of the buffer members 81 has yet deformed at this stage. The semiconductor element 10A on the left is thicker than the semiconductor element 10A on the right, and the conductive bonding layer 3 disposed between the left and right semiconductor elements 10A and the conductive member 22A is also thicker. Therefore, the height from the main surface 221A of the conductive member 22A to the top surface of the lead member 51 (the surface facing away from the semiconductor elements 10A) is higher on the left side than on the right side.

[0060] 16B shows a state in which pressure member 90 presses and applies pressure to each lead member 51. Buffer member 81, which is disposed on semiconductor element 10A on the left side, is deformed by the pressure and assumes a crushed shape. As a result, the thickness of buffer member 81 is reduced, and the height from main surface 221A of conductive member 22A to the upper surface of lead member 51 is approximately the same on the right and left sides. As a result, the load applied to semiconductor element 10A on the left side and the load applied to semiconductor element 10A on the right side are approximately the same, and the load is applied evenly to the two semiconductor elements 10A.

[0061] In some cases, none of the multiple buffer members 8 are deformed and maintain their shape prior to the pressurizing and heating process. On the other hand, in some cases, one of the multiple buffer members 8 is deformed during the pressurizing and heating process. FIGS. 12 and 13 show a deformed buffer member 81. In this embodiment, the buffer member 81 before deformation is rectangular and approximately the same size as the first bonding portion 511 of the lead member 51 as viewed in the z direction. As shown in FIG. 12, the buffer member 81 has a shape that has been crushed by pressure and has a curved, bulging portion as viewed in the z direction. Furthermore, as shown in FIG. 13, both ends of the cross section perpendicular to the z direction protrude outward in an arc shape. As shown in FIGS. 12 and 13, the buffer member 81 includes a first portion 81a and a second portion 81b. The first portion 81a overlaps the lead member 51 as viewed in the z direction. The second portion 81b is connected to the first portion 81a and protrudes from the lead member 51 as viewed in the z direction. The second portion 81b is hatched in Figures 11 and 12. In Figure 13, the boundary between the first portion 81a and the second portion 81b is indicated by a broken line.

[0062] 14 and 15 show a deformed buffer member 82. In this embodiment, when viewed in the z direction, the buffer member 82 before deformation has a rectangular shape approximately the same size as each protrusion 421c of the input terminal 41. As shown in FIG. 14, when viewed in the z direction, the buffer member 82 has a shape that has been crushed by pressure and has a curved, bulging portion. Also, as shown in FIG. 15, the cross section has a shape in which both ends in a direction perpendicular to the z direction protrude outward in an arc shape. As shown in FIGS. 14 and 15, the buffer member 82 has a first portion 82a and a second portion 82b. When viewed in the z direction, the first portion 82a is a portion that overlaps with the input terminal 42. The second portion 82b is connected to the first portion 82a and protrudes from the input terminal 42 when viewed in the z direction. In FIG. 14, the second portion 82b is hatched. In FIG. 15, the boundary between the first portion 82a and the second portion 82b is indicated by a dashed line.

[0063] As shown in FIGS. 13 and 15, the thickness T1 (dimension in the z-direction) of the buffer member 8 is 10% to 30% of the thickness T2 (dimension in the z-direction) of the semiconductor element 10. The thickness T1 of the buffer member 8 that is not deformed (before deformation) is also 10% to 30% of the thickness T2. If the thickness T1 is too small, the load cannot be equalized by deformation. On the other hand, from the viewpoint of reducing the amount of material required, it is not necessary to make the thickness T1 too large. In this embodiment, the thickness T2 is approximately 350 to 370 μm, so the thickness T1 of the buffer member 8 that is not deformed (before deformation) is approximately 50 to 100 μm. Note that the thickness T1 is not limited and can be set appropriately. Since the thickness T1 needs to be large to a certain extent, when the thickness T2 is small (for example, approximately 100 μm), the thickness T1 is set to approximately 50 to 100% of the thickness T2. Each buffer member 8 is an example of a "first member" or a "second member."

[0064] Each of the multiple conductive bonding layers 3 is made of sintered metal formed by a sintering process. In this embodiment, the constituent material of each conductive bonding layer 3 is, for example, sintered silver. However, the constituent material of each conductive bonding layer 3 is not limited to this and may be other sintered metals such as sintered copper. Each conductive bonding layer 3 is porous with numerous micropores. In this embodiment, the micropores are assumed to be voids, but the micropores may be filled with, for example, epoxy resin. That is, each conductive bonding layer 3 may be sintered metal containing epoxy resin. However, since a high epoxy resin content reduces the conductivity of the conductive bonding layer 3, the epoxy resin content is set taking into account the amount of current in the semiconductor device A1. The conductive bonding layer 3 is formed by sintering a sintered metal material. In this embodiment, each conductive bonding layer 3 has a rectangular cross section, as shown in, for example, FIGS. 13 and 15 . However, it may also be trapezoidal, have curved sides, or have a fillet.

[0065] In this embodiment, the plurality of conductive bonding layers 3 include a plurality of element bonding layers 31A and 31B, a plurality of lead bonding layers 321 and 322, and a plurality of terminal bonding layers 33.

[0066] Each of the plurality of element bonding layers 31A is for bonding a corresponding semiconductor element 10A to the conductive member 22A. As shown in FIG. 13, each element bonding layer 31A is interposed between the element back surface 102 of each semiconductor element 10A and the conductive member 22A, and electrically connects the drain electrode 113 of the semiconductor element 10A to the conductive member 22A. Each element bonding layer 31A has a thickness of approximately 30 to 100 μm. However, the thickness of each element bonding layer 31A is not limited to this.

[0067] Each of the plurality of element bonding layers 31B is for bonding a corresponding semiconductor element 10B to the conductive member 22B. As shown in FIG. 15, each element bonding layer 31B is interposed between the element back surface 102 of each semiconductor element 10B and the conductive member 22B, and electrically connects the drain electrode 113 of the semiconductor element 10B to the conductive member 22B. Each element bonding layer 31B has a thickness of about 30 to 100 μm, similar to each element bonding layer 31A. However, the thickness of each element bonding layer 31B is not limited to this. The element bonding layers 31A and 31B are an example of a "second conductive bonding layer."

[0068] Each of the plurality of lead bonding layers 321 and 322 is for bonding a corresponding lead member 51.

[0069] As shown in FIGS. 11 to 13, each of the plurality of lead bonding layers 321 serves to bond the buffer member 81 bonded to the first bonding portion 511 of each lead member 51 to the source electrode 111 of each semiconductor element 10A. Each lead bonding layer 321 is interposed between the source electrode 111 of each semiconductor element 10A and the first bonding portion 511 of each lead member 51, and provides electrical continuity between the source electrode 111 of the semiconductor element 10A and the lead member 51. Each lead bonding layer 321 has a thickness of approximately 30 to 100 μm. However, the thickness of each lead bonding layer 321 is not limited to this. The lead bonding layer 321 is an example of a "conductive bonding layer."

[0070] 11, each of the plurality of lead bonding layers 322 serves to bond the second bonding portion 512 of each lead member 51 to the conductive member 22B. Each lead bonding layer 322 is interposed between the second bonding portion 512 of each lead member 51 and a portion of the conductive member 22B, and provides electrical continuity between the lead member 51 and the conductive member 22B. Each lead bonding layer 322 has a thickness of approximately 30 to 100 μm. However, the thickness of each lead bonding layer 322 is not limited to this.

[0071] As shown in FIGS. 14 and 15, each of the plurality of terminal bonding layers 33 serves to bond the buffer member 82 bonded to each protrusion 421c of the input terminal 42 to the source electrode 111 of each semiconductor element 10B. Each terminal bonding layer 33 is interposed between the source electrode 111 of each semiconductor element 10B and each protrusion 421c of the input terminal 42, and provides electrical continuity between the source electrode 111 of the semiconductor element 10B and the input terminal 42. Each terminal bonding layer 33 has a thickness of approximately 30 to 100 μm. However, the thickness of each terminal bonding layer 33 is not limited to this. The terminal bonding layer 33 is an example of a "conductive bonding layer."

[0072] Each of the plurality of wires 6 is a so-called bonding wire. Each wire 6 is electrically conductive and is made of, for example, aluminum (Al), gold (Au), or copper (Cu). In this embodiment, the plurality of wires 6 includes a plurality of gate wires 61, a plurality of detection wires 62, a pair of first connecting wires 63, and a pair of second connecting wires 64, as shown in FIGS. 4 and 5 .

[0073] 4 and 5, one end of each of the plurality of gate wires 61 is joined to the gate electrode 112 of each semiconductor element 10, and the other end is joined to one of the pair of gate layers 24A, 24B. The plurality of gate wires 61 include those that connect the gate electrode 112 of each semiconductor element 10A to the gate layer 24A, and those that connect the gate electrode 112 of each semiconductor element 10B to the gate layer 24B.

[0074] 4 and 5, one end of each of the plurality of detection wires 62 is joined to the source electrode 111 of each semiconductor element 10, and the other end is joined to one of the pair of detection layers 25A, 25B. The plurality of detection wires 62 include those that connect the source electrode 111 of each semiconductor element 10A to the detection layer 25A, and those that connect the source electrode 111 of each semiconductor element 10B to the detection layer 25B.

[0075] 4 and 5, one of the pair of first connecting wires 63 connects the gate layer 24A and the gate terminal 44A, and the other connects the gate layer 24B and the gate terminal 44B. One of the first connecting wires 63 has one end bonded to the gate layer 24A and the other end bonded to the pad portion 441 of the gate terminal 44A, thereby providing electrical continuity between the gate layer 24A and the gate terminal 44A. The other first connecting wire 63 has one end bonded to the gate layer 24B and the other end bonded to the pad portion 441 of the gate terminal 44B, thereby providing electrical continuity between the gate layer 24B and the gate terminal 44B.

[0076] 4 and 5, one of the pair of second connecting wires 64 connects the detection layer 25A and the detection terminal 45A, and the other connects the detection layer 25B and the detection terminal 45B. One second connecting wire 64 has one end joined to the detection layer 25A and the other end joined to the pad portion 451 of the detection terminal 45A, thereby providing electrical continuity between the detection layer 25A and the detection terminal 45A. The other second connecting wire 64 has one end joined to the detection layer 25B and the other end joined to the pad portion 451 of the detection terminal 45B, thereby providing electrical continuity between the detection layer 25B and the detection terminal 45B.

[0077] 1, 3, 4, and 6 to 10, the sealing resin 7 covers the semiconductor elements 10, a portion of the support substrate 20, the conductive bonding layers 3, a portion of each terminal 40, the lead members 51, and the wires 6. The sealing resin 7 is made of, for example, epoxy resin. As shown in FIGS. 1, 3, 4, and 6 to 10, the sealing resin 7 has a resin main surface 71, a resin back surface 72, and resin side surfaces 731 to 734.

[0078] The resin main surface 71 and the resin back surface 72 are spaced apart in the z direction and face opposite directions from each other. The resin main surface 71 faces the z2 side in the z direction, and the resin back surface 72 faces the z1 side in the z direction. As shown in FIG. 7 , the resin back surface 72 has a frame shape surrounding the back surface 212 of the insulating substrate 21 when viewed in the z direction. The back surface 212 of the insulating substrate 21 is exposed from the resin back surface 72. Each of the multiple resin side surfaces 731 to 734 is connected to both the resin main surface 71 and the resin back surface 72 and is sandwiched between them in the z direction. In this embodiment, the resin side surfaces 731 and 732 are spaced apart in the x direction and face opposite directions from each other. The resin side surface 731 faces the x2 side in the x direction, and the resin side surface 732 faces the x1 side in the x direction. Furthermore, the resin side surfaces 733 and 734 are spaced apart in the y direction and face opposite directions from each other. The resin side surface 733 faces the y2 side in the y direction, and the resin side surface 734 faces the y1 side in the y direction.

[0079] In this embodiment, as shown in Figures 6, 7, and 10, the sealing resin 7 has a plurality of recesses 75 that are recessed in the z direction from the resin back surface 72. Note that the sealing resin 7 does not necessarily have to have these recesses 75. Each of the plurality of recesses 75 extends in the y direction and is connected from the edge of the resin back surface 72 on the y1 side in the y direction to the edge on the y2 side in the y direction as viewed in the z direction. In this embodiment, the plurality of recesses 75 are formed three by three in the x direction, sandwiching the back surface 212 of the insulating substrate 21 between them as viewed in the z direction.

[0080] Next, a method for manufacturing the semiconductor device A1 according to the first embodiment will be described.

[0081] First, the support substrate 20 is prepared. In the step of preparing the support substrate 20 (support substrate preparation step), a plurality of conductive members 22 (conductive members 22A, 22B) are bonded to an insulating substrate 21 at a distance from each other. Then, a pair of insulating layers 23A, 23B, a pair of gate layers 24A, 24B, a pair of detection layers 25A, 25B, and a plurality of base portions 29 are bonded to the conductive members 22A, 22B.

[0082] Next, a plurality of lead members 51 are prepared. In the step of preparing the lead members 51 (lead preparation step), the lead members 51 are formed by performing metal processing, such as rolling, on a metal plate whose constituent material is Cu or a Cu alloy. Next, a plating layer 515 is formed on each lead member 51. Then, a buffer member 81 having a plating layer 85 formed thereon is joined to the first joint portion 511 of each lead member 51. This joining is performed by solid-state diffusion bonding between the plating layer 85 (Ag) formed on the main surface 801 of the buffer member 81 and the plating layer 515 (Ag) formed on the first joint portion 511.

[0083] Next, a plurality of sintering metal materials 301 are formed. Each sintering metal material 301 serves as the base for the element bonding layers 31A and 31B. In this embodiment, a sintering silver paste is used as each sintering metal material 301. This sintering silver paste is a mixture of micro- or nano-sized silver particles in a solvent. In this embodiment, the solvent for the sintering silver does not contain (or contains very little) epoxy resin. In the step of forming the sintering metal materials 301 (first sintering metal material forming step), each sintering metal material 301 is applied to the conductive members 22A and 22B by, for example, screen printing using a mask. Note that each sintering metal material 301 applied to the conductive member 22A will later become the element bonding layer 31A of the semiconductor device A1, and each sintering metal material 301 applied to the conductive member 22B will later become the element bonding layer 31B of the semiconductor device A1. The method of forming the plurality of sintering metal materials 301 is not limited to the above-described screen printing. For example, a dispenser may be used to apply the sintering metal material 301. The thickness of the applied sintering metal material 301 is about 50 to 110 μm.

[0084] Next, a drying process is performed on the plurality of sintering metal materials 301. In this drying process (drying step), each sintering metal material 301 is heated at a temperature of approximately 130°C for approximately 20 minutes. Note that the heating conditions are not limited to these. This causes the solvent in each sintering metal material 301 to evaporate.

[0085] Next, one of the semiconductor elements 10A and 10B is mounted on each of the sintering metal materials 301. Specifically, one semiconductor element 10A is mounted on each of the sintering metal materials 301 formed on the conductive member 22A, and one semiconductor element 10B is mounted on each of the sintering metal materials 301 formed on the conductive member 22B. In the step of mounting the semiconductor elements 10A and 10B (mounting step), each semiconductor element 10A is mounted on the conductive member 22A with the conductive member 22A and the back surface 102 of the semiconductor element 10A facing each other. Furthermore, each semiconductor element 10B is mounted on the conductive member 22B with the conductive member 22B and the back surface 102 of the semiconductor element 10B facing each other.

[0086] Next, a sintering metal material 302 is formed on each of the source electrodes 111 and conductive members 22B of the semiconductor elements 10A and 10B. The sintering metal material 302 serves as the base for the lead bonding layers 321 and 322 and the terminal bonding layer 33. In this embodiment, a preformed sintering silver is used as each of the sintering metal materials 302. This preformed sintering silver is obtained by, for example, drying the above-mentioned paste-like sintering silver and then molding it into a predetermined shape. Note that the preformed sintering silver may also be obtained by molding it into a predetermined shape and then drying it. In the step of forming the sintering metal material 302 (second sintering metal material forming step), one piece of each of the sintering metal materials 302 is placed on each of the source electrodes 111 and conductive members 22B of the semiconductor elements 10A and 10B. Each sintering metal material 302 formed on the source electrode 111 of each semiconductor element 10A will later become the lead bonding layer 321 of the semiconductor device A1, and each sintering metal material 302 formed on the conductive member 22B will later become the lead bonding layer 322 of the semiconductor device A1. Also, each sintering metal material 302 formed on the source electrode 111 of each semiconductor element 10B will later become the terminal bonding layer 33 of the semiconductor device A1. The thickness of the sintering metal material 302 to be placed is approximately 50 to 110 μm.

[0087] Next, each semiconductor element 10A is connected to the conductive member 22B using the lead members 51 prepared in the lead preparation step, with the buffer member 81 bonded to the first bonding portion 511. In the step of connecting using the lead members 51 (connecting step), the lead members 51 are arranged so that, as viewed in the z direction, the first bonding portion 511 and the buffer member 81 overlap the sintering metal material 302 formed on the source electrode 111 of the semiconductor element 10A, and the second bonding portion 512 overlaps the sintering metal material 302 formed on the conductive member 22B.

[0088] Next, the multiple terminals 40 are joined. When joining the input terminal 41, the comb-tooth portion 411a is joined to the main surface 221A of the conductive member 22A. This joining may be done by laser welding or ultrasonic bonding. When joining the output terminal 43, the comb-tooth portion 431a is joined to the main surface 221B of the conductive member 22B. This joining may be done by laser welding or ultrasonic bonding. The pair of gate terminals 44A, 44B, the pair of detection terminals 45A, 45B, the multiple dummy terminals 46, and the pair of side terminals 47A, 47B are formed on a single lead frame and are connected to each other. Then, portions of the lead frame corresponding to the side terminals 47A, 47B are joined to the main surface 221A of the conductive member 22A and the main surface 221B of the conductive member 22B, respectively. This joining may be done by laser welding or ultrasonic bonding.

[0089] Next, the input terminal 42 is connected to each semiconductor element 10B. A plating layer 421d is formed on each protrusion 421c of the input terminal 42, and a buffer member 82 is joined thereto. The protrusion 421c and the buffer member 82 are joined by solid-state diffusion bonding between the plating layer 85 (Ag) formed on the main surface 801 of the buffer member 82 and the plating layer 421d (Ag) formed on the protrusion 421c. The input terminal 42 is placed on the input terminal 41 with the insulating member 49 sandwiched therebetween. At this time, the input terminal 42 is placed so that each of the multiple protrusions 421c and the buffer member 82 overlaps the sintering metal material 302 formed on the source electrode 111 of the semiconductor element 10B when viewed in the z direction.

[0090] Next, a pressure and heat treatment is performed to convert the sintering metal materials 301, 302 into sintered metal. In this pressure and heat treatment process (pressure and heat treatment process), as shown in FIGS. 16A and 16B, a pressure member 90 presses each lead member 51, thereby applying pressure to the plurality of sintering metal materials 301, 302. At this time, some of the buffer members 81 deform so that the positions of the upper surfaces of the lead members 51 in the z direction are equalized (see FIG. 16B). This uniforms the load applied to each semiconductor element 10A. At the same time, the input terminals 42 are pressed by the pressure member 90 or a pressure member different from the pressure member 90, thereby applying pressure to the plurality of sintering metal materials 301, 302. At this time, some of the buffer members 82 deform so that the positions of the upper surfaces of the protrusions 421c of the input terminals 42 (the surfaces facing away from the semiconductor element 10B) in the z direction are equalized. This uniforms the load applied to each semiconductor element 10B. The sintering metal materials 301, 302 pressed through the lead member 51 and the sintering metal materials 301, 302 pressed through the input terminal 42 are heated, for example, at a temperature of approximately 250°C for approximately 90 seconds. The heating conditions are not limited to these. As a result, the silver particles in each of the sintering metal materials 301, 302 bond to each other to form a sintered metal. The sintered metal between the semiconductor element 10A and the conductive member 22A is the element bonding layer 31A of the semiconductor device A1, and the sintered metal between the semiconductor element 10B and the conductive member 22B is the element bonding layer 31B of the semiconductor device A1. The sintered metal between the first bonding portion 511 of the lead member 51 and the semiconductor element 10A is the lead bonding layer 321 of the semiconductor device A1. The sintered metal between the second bonding portion 512 of the lead member 51 and the conductive member 22B is the lead bonding layer 322 of the semiconductor device A1. The sintered metal interposed between each protrusion 421c of the input terminal 42 and the semiconductor element 10B is the terminal bonding layer 33 of the semiconductor device A1.

[0091] Next, a plurality of wires 6 are formed. In the step of forming the wires 6 (wire forming step), for example, a well-known wire bonder is used. In the wire forming step, a plurality of gate wires 61 are formed, connecting the gate electrode 112 of each semiconductor element 10A to the gate layer 24A, and a plurality of gate wires 61 are formed, connecting the gate electrode 112 of each semiconductor element 10B to the gate layer 24B. In addition, a plurality of detection wires 62 are formed, connecting the source electrode 111 of each semiconductor element 10A to the detection layer 25A, and a plurality of detection wires 62 are formed, connecting the source electrode 111 of each semiconductor element 10B to the detection layer 25B. Furthermore, a first connection wire 63 is formed, connecting the gate layer 24A to the gate terminal 44A, and a first connection wire 63 is formed, connecting the gate layer 24B to the gate terminal 44B. Then, a second connection wire 64 is formed, connecting the detection layer 25A to the detection terminal 45A, and a second connection wire 64 is formed, connecting the detection layer 25B to the detection terminal 45B. The order in which the wires 6 are formed is not particularly limited.

[0092] Next, the sealing resin 7 is formed. The process of forming the sealing resin 7 (resin forming process) is performed by, for example, transfer molding. The sealing resin 7 is, for example, an epoxy resin. In this embodiment, the sealing resin 7 is formed so as to cover the plurality of semiconductor elements 10, part of the support substrate 20, the plurality of conductive bonding layers 3, parts of the plurality of terminals 40, the plurality of lead members 51, and the plurality of wires 6. A part of each terminal 40 and a part of the support substrate 20 (specifically, the back surface 212 of the insulating substrate 21) are exposed from the formed sealing resin 7.

[0093] 1 to 15 is manufactured by cutting unnecessary portions of the terminals 40 (for example, parts of the lead frame) and bending the terminals 40. Note that the manufacturing method described above is an example and is not limited thereto, and the order of steps may be changed as appropriate.

[0094] Next, the effects of the semiconductor device A1 will be described.

[0095] According to this embodiment, a buffer member 81 is interposed between each first joint portion 511 of each lead member 51 and the source electrode 111 of the semiconductor element 10A. The buffer member 81 is made of Al and has a lower Vickers hardness than the lead member 51 made of Cu. Therefore, when the pressure member 90 presses and applies pressure to each lead member 51 during the pressure and heating process, some of the buffer members 81 are crushed and thinned by the pressure, so that the positions in the z direction of the upper surfaces of each lead member 51 (the height from the main surface 221A of the conductive member 22A to the upper surface of each lead member 51) become approximately the same. This ensures that the load is applied evenly to each semiconductor element 10A, thereby preventing a biased load from being applied to some of the semiconductor elements 10A. Furthermore, according to this embodiment, a buffer member 82 is interposed between each protrusion 421c of the input terminal 42 and the source electrode 111 of the semiconductor element 10B. The buffer member 82 is made of Al and has a lower Vickers hardness than the input terminal 42 made of Cu. Therefore, in the pressurizing and heating step, when pressure member 90 presses input terminal 42 and applies pressure, part of buffer member 82 is crushed and thinned by the pressure, so that the position in the z direction of the upper surface of each protrusion 421c (the height from main surface 221B of conductive member 22B to the upper surface of each protrusion 421c) becomes approximately the same. As a result, the load is applied evenly to each semiconductor element 10B, and it is possible to prevent a biased load from being applied to some semiconductor elements 10B.

[0096] According to this embodiment, a plating layer 85 made of Ag is formed on the entire main surface 801 and the back surface 802 of each buffer member 8. A plating layer 515 made of Ag is formed on the first bonding portion 511 of each lead member 51, and a plating layer 421d made of Ag is formed on each protruding portion 421c of the input terminal 42. This allows each buffer member 8 to be bonded to the first bonding portion 511 of the lead member 51 or the protruding portion 421c of the input terminal 42 by Ag solid-state diffusion bonding. Furthermore, a plating layer 115 having an Au layer laminated on the outermost surface is formed on the source electrode 111 of each semiconductor element 10. This allows each buffer member 8 to be firmly bonded to the source electrode 111 of the semiconductor element 10 by the conductive bonding layer 3 made of sintered silver. Each buffer member 8 can also be firmly bonded to the first bonding portion 511 or the protruding portion 421c by the conductive bonding layer 3.

[0097] Furthermore, according to this embodiment, the sintering metal material 301 formed under each semiconductor element 10A and the sintering metal material 302 formed on each semiconductor element 10A are simultaneously subjected to pressure and heat treatment. That is, the element bonding layer 31A and the lead bonding layer 321 are simultaneously sintered. The element bonding layer 31A and the lead bonding layer 321 are formed from these sintering metal materials 301, 302 by a single pressure and heat treatment, thereby improving the productivity of the semiconductor device A1. Furthermore, according to this embodiment, the sintering metal material 301 formed under each semiconductor element 10B and the sintering metal material 302 formed on each semiconductor element 10B are simultaneously subjected to pressure and heat treatment. That is, the element bonding layer 31B and the terminal bonding layer 33 are simultaneously sintered. The element bonding layer 31B and the terminal bonding layer 33 are formed from these sintering metal materials 301, 302 by a single pressure and heat treatment, thereby improving the productivity of the semiconductor device A1.

[0098] Furthermore, according to this embodiment, the element bonding layers 31A, 31B are formed from a sintering metal material 301, which is a sintering silver paste. The sintering silver paste is less expensive than the sintering silver preform. Therefore, the manufacturing cost of the semiconductor device A1 can be reduced. Note that in this embodiment, the element bonding layers 31A, 31B may be formed from the sintering silver preform. That is, the sintering silver preform may be used as the sintering metal material 301. In this case, the step of drying the sintering silver paste is not required, thereby improving productivity.

[0099] In this embodiment, the case where the sintering metal material 301 formed under each semiconductor element 10 and the sintering metal material 302 formed on each semiconductor element 10 are simultaneously subjected to pressure and heat treatment has been described, but this is not limited to this. The pressure and heat treatment of the sintering metal material 301 formed under each semiconductor element 10 and the pressure and heat treatment of the sintering metal material 302 formed on each semiconductor element 10 may be performed separately.

[0100] In this embodiment, the conductive bonding layer 3 is made of a sintered metal, but the present invention is not limited to this. The conductive bonding layer 3 may be made of, for example, silver paste.

[0101] 17 to 28B show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are denoted by the same reference numerals as those in the above embodiment.

[0102] 17 and 18 are diagrams illustrating a semiconductor device A2 according to a second embodiment of the present disclosure. Fig. 17 is a partially enlarged plan view showing the semiconductor device A2, and corresponds to Fig. 12. In Fig. 17, the lead members 51 are shown with an imaginary line (two-dot chain line). Fig. 18 is a partially enlarged cross-sectional view showing the semiconductor device A2, and corresponds to Fig. 13. The semiconductor device A2 according to this embodiment differs from the semiconductor device A1 according to the first embodiment in that the size of the buffer member 8 is smaller when viewed in the z direction.

[0103] Each buffer member 8 according to the second embodiment is smaller in size in the z direction than the semiconductor device A1 according to the first embodiment. Before deformation, the buffer member 8 is sized to be enclosed within the first bonding portion 511 of the lead member 51 or the protruding portion 421c of the input terminal 41 as viewed in the z direction, and remains enclosed even after deformation. The shape of the buffer member 8 is the same as that of the first embodiment, and is compressed by pressure as viewed in the z direction, resulting in a curved, bulging outline. As shown in FIG. 17 , both ends of the cross section perpendicular to the z direction protrude outward in an arc shape. Meanwhile, the buffer member 8 does not protrude beyond the first bonding portion 511 or the protruding portion 421c as viewed in the z direction, and does not have a portion corresponding to the second portion 81b (82b) in the first embodiment.

[0104] In this embodiment as well, a buffer member 81 is interposed between each first joint portion 511 of each lead member 51 and the source electrode 111 of the semiconductor element 10A. This makes it possible to prevent a load from being biased toward some of the semiconductor elements 10A. Furthermore, a buffer member 82 is interposed between each protrusion 421c of the input terminal 42 and the source electrode 111 of the semiconductor element 10B. This makes it possible to prevent a load from being biased toward some of the semiconductor elements 10B. Furthermore, the semiconductor device A2 has a common configuration with the semiconductor device A1, and thereby achieves the same effects as the semiconductor device A1.

[0105] 19 and 20 are diagrams for explaining a semiconductor device A3 according to a third embodiment of the present disclosure. FIG. 19 is a partially enlarged perspective view showing the semiconductor device A3, and corresponds to FIG. 11. Note that the gate wires 61 and the detection wires 62 are omitted in FIG. 19. FIG. 20 is a partially enlarged cross-sectional view showing the semiconductor device A3, and corresponds to FIG. 13. The semiconductor device A3 according to this embodiment differs from the semiconductor device A1 according to the first embodiment in that it includes a source wire 65 instead of the lead member 51.

[0106] The semiconductor device A3 according to the third embodiment does not include multiple lead members 51, but further includes multiple source wires 65 and multiple plate members 55. In the semiconductor device A3, the source electrode 111 of the semiconductor element 10A and the conductive member 22B are electrically connected by the source wire 65 instead of the lead member 51.

[0107] Each source wire 65 is a so-called bonding wire. Each source wire 65 electrically connects the source electrode 111 of the semiconductor element 10A to the conductive member 22B. Each source wire 65 is made of, for example, Cu so that it can withstand a large current. One end of each source wire 65 is joined to the plate member 55, which is electrically connected to the source electrode 111 of the semiconductor element 10A, and the other end is joined to the conductive member 22B.

[0108] The plate member 55 is a buffer material for protecting the source electrode 111 of the semiconductor element 10A from impact when the source wire 65 is bonded, and is made of, for example, Cu. The plate member 55 is rectangular when viewed in the z direction and overlaps the source electrode 111 of the semiconductor element 10A. In this embodiment, a plating layer 515 is formed on the surface of the plate member 55 facing the semiconductor element 10A. The plating layer 515 is made of, for example, Ag, similar to the first embodiment. The material of the plating layer 515 is not limited. In this embodiment, the dimension (thickness) of the plate member 55 in the z direction is approximately 100 to 200 μm. The thickness of the plate member 55 is not limited to this. The buffer member 81 is similar to the first embodiment and is interposed between the source electrode 111 of the semiconductor element 10A and the plate member 55. Some of the buffer members 81 deform when the pressing member 90 presses each plate member 55 during the pressurizing and heating process. In this embodiment, the plate member 55 is an example of a "first connecting member" or a "second connecting member."

[0109] According to the present embodiment, a buffer member 81 is interposed between each plate member 55 and the source electrode 111 of the semiconductor element 10A. This prevents a load from being biased onto some of the semiconductor elements 10A. Furthermore, a buffer member 82 is interposed between each protrusion 421c of the input terminal 42 and the source electrode 111 of the semiconductor element 10B. This prevents a load from being biased onto some of the semiconductor elements 10B. Furthermore, the semiconductor device A3 has a configuration in common with the semiconductor device A1, and thereby achieves the same effects as the semiconductor device A1.

[0110] Fig. 21 is a partially enlarged cross-sectional view showing a semiconductor device A4 according to a fourth embodiment of the present disclosure, and is a view corresponding to Fig. 13. The semiconductor device A4 according to this embodiment differs from the semiconductor device A1 according to the first embodiment in that it does not include a lead bonding layer 321 and a terminal bonding layer 33.

[0111] The plating layer 85 formed on the buffer member 8 according to the fourth embodiment is made of Au. Furthermore, the plating layer 515 formed on the first joint portion 511 of the lead member 51 and the plating layer 421d formed on the protruding portion 421c of the input terminal 42 are also made of Au. The buffer member 81 and the first joint portion 511 of the lead member 51 are bonded by solid-state diffusion bonding between the plating layer 85 (Au) and the plating layer 515 (Au). Furthermore, the buffer member 82 and each protruding portion 421c of the input terminal 42 are bonded by solid-state diffusion bonding between the plating layer 85 (Au) and the plating layer 421d (Au).

[0112] The buffer member 81 bonded to the first bonding portion 511 of the lead member 51 and the source electrode 111 of the semiconductor element 10A are bonded by solid-state diffusion bonding between the plating layer 85 (Au) and the plating layer 115 (the outermost layer is Au). The buffer member 82 bonded to each protrusion 421c of the input terminal 42 and the source electrode 111 of the semiconductor element 10B are bonded by solid-state diffusion bonding between the plating layer 85 (Au) and the plating layer 115 (the outermost layer is Au).

[0113] In this embodiment, a buffer member 81 is interposed between each first bonding portion 511 of each lead member 51 and the source electrode 111 of the semiconductor element 10A. This prevents a load from being biased toward some of the semiconductor elements 10A. A buffer member 82 is interposed between each protrusion 421c of the input terminal 42 and the source electrode 111 of the semiconductor element 10B. This prevents a load from being biased toward some of the semiconductor elements 10B. The semiconductor device A4 has a configuration common to the semiconductor device A1, thereby achieving the same effects as the semiconductor device A1. Furthermore, in the semiconductor device A4, the buffer member 8 and the source electrode 111 of the semiconductor element 10 are bonded by solid-state diffusion bonding between the plating layer 85 (Au) and the plating layer 115 (the outermost layer of which is Au). This eliminates the need for the lead bonding layer 321 and the terminal bonding layer 33.

[0114] In this embodiment, the outermost layer of plating layer 115, plating layer 515, plating layer 421d, and plating layer 85 are each made of Au, but this is not limiting. The outermost layer of plating layer 115, plating layer 515, plating layer 421d, and plating layer 85 may each be made of Ag. In this case, they are bonded by solid-state diffusion bonding of Ag.

[0115] Fig. 22 is a partially enlarged cross-sectional view showing a semiconductor device A5 according to a fifth embodiment of the present disclosure, and is a view corresponding to Fig. 13. The semiconductor device A5 according to this embodiment differs from the semiconductor device A1 according to the first embodiment in the position where the buffer member 81 is arranged.

[0116] In the semiconductor device A5 according to the fifth embodiment, the buffer member 81 is disposed on the opposite side (z2 side in the z direction) of the first bonding portion 511 of the lead member 51 from the semiconductor element 10A. The first bonding portion 511 of the lead member 51 is bonded to the source electrode 111 of the semiconductor element 10A via a lead bonding layer 321. Similarly, the buffer member 82 may be disposed on the opposite side (z2 side in the z direction) of the protrusion 421c of the input terminal 41 from the semiconductor element 10B.

[0117] According to this embodiment, the buffer members 81 are disposed on the z2 side of the first bonding portions 511 of each lead member 51 in the z direction. Therefore, when the pressure member 90 presses and applies pressure to the buffer members 81 bonded to each lead member 51 in the pressurizing and heating process, some of the buffer members 81 are crushed and thinned by the pressure, so that the positions in the z direction (heights from the main surface 221A of the conductive member 22A to the top surfaces of the buffer members 81) (surfaces facing away from the semiconductor element 10A) of the buffer members 81 become approximately the same. This allows the load to be applied evenly to each semiconductor element 10A, thereby preventing a disproportionate load from being applied to some of the semiconductor elements 10A. Furthermore, the semiconductor device A5 has a configuration in common with the semiconductor device A1, thereby achieving the same effects as the semiconductor device A1.

[0118] Fig. 23 is a partially enlarged cross-sectional view showing a semiconductor device A6 according to a sixth embodiment of the present disclosure, and is a view corresponding to Fig. 13. The semiconductor device A6 according to this embodiment differs from the semiconductor device A1 according to the first embodiment in that buffer members 81 are arranged on both sides of the first bonding portion 511 of the lead member 51 in the z direction.

[0119] In the semiconductor device A6 according to the sixth embodiment, buffer members 81 are disposed on both sides in the z direction of a first bonding portion 511 of a lead member 51. In this embodiment, a clad material in which plate members made of Al are bonded to both sides of a plate member made of Cu is used as the material of the lead member. The plate members made of Cu of the clad material are the lead member 51, and the plate members made of Al are the buffer members 81. A plating layer 85 is formed on both sides of the clad material (corresponding to the outer surfaces of each buffer member 81). Note that buffer members 82 may also be disposed on both sides in the z direction of a protrusion 421c of an input terminal 41.

[0120] According to this embodiment, buffer members 81 are disposed on both sides of the first bonding portion 511 of each lead member 51 in the z direction. Therefore, in the pressurizing and heating process, when the pressing member 90 presses and applies pressure to the buffer members 81 (hereinafter referred to as "upper buffer members 81") bonded to the surface of each lead member 51 on the z2 side in the z direction, some of the buffer members 81 are crushed and thinned by the pressure. As a result, the positions in the z direction of the upper surfaces of the upper buffer members 81 (surfaces facing away from the semiconductor element 10A) (heights from the main surface 221A of the conductive member 22A to the upper surfaces of the upper buffer members 81) become approximately the same. This allows the load to be applied evenly to each semiconductor element 10A, thereby preventing a biased load from being applied to some of the semiconductor elements 10A. Furthermore, the semiconductor device A6, having a configuration common to the semiconductor device A1, achieves the same effects as the semiconductor device A1.

[0121] Fig. 24 is a partially enlarged cross-sectional view showing a semiconductor device A7 according to the seventh embodiment of the present disclosure, and is a view corresponding to Fig. 13. The semiconductor device A7 according to this embodiment differs from the semiconductor device A1 according to the first embodiment in the material of the lead members 51.

[0122] The semiconductor device A7 according to the seventh embodiment does not include a buffer member 81, and the lead member 51 functions as a buffer member. The lead member 51 according to the seventh embodiment is made of a conductive material, such as Al, with a Vickers hardness lower than that of Cu. Similar to the first embodiment, a plating layer 515 (Ag) is formed on the surface of the first bonding portion 511 of the lead member 51 facing the semiconductor element 10A. The first bonding portion 511 of the lead member 51 and the source electrode 111 of the semiconductor element 10A are bonded by a lead bonding layer 321. The first bonding portion 511 of some of the lead members 51 is deformed during the pressurizing and heating process, and has a shape in which, when viewed in the z direction, it is crushed by the pressure and has a curved, bulging outline. Furthermore, as shown in FIG. 24 , both ends of the cross section perpendicular to the z direction protrude outward in an arc shape. In this embodiment, the lead member 51 is an example of a “first connecting member.” Similarly, the input terminal 41 may be made of Al, for example.

[0123] According to this embodiment, each lead member 51 is made of Al, which has a Vickers hardness lower than that of Cu. Therefore, when the pressure member 90 presses and applies pressure to each lead member 51 during the pressure and heating process, the first bonding portions 511 of some of the lead members 51 are crushed and thinned by the pressure, so that the positions in the z direction (heights from the main surface 221A of the conductive member 22A to the upper surfaces of each first bonding portion 511) (surfaces facing away from the semiconductor element 10A) of each first bonding portion 511 become approximately the same. This allows the load to be applied evenly to each semiconductor element 10A, preventing a biased load from being applied to some of the semiconductor elements 10A. Furthermore, the semiconductor device A7 has a configuration common to the semiconductor device A1, thereby achieving the same effects as the semiconductor device A1.

[0124] Fig. 25 is a partially enlarged cross-sectional view showing a semiconductor device A8 according to an eighth embodiment of the present disclosure, and is a view corresponding to Fig. 13. The semiconductor device A8 according to this embodiment differs from the semiconductor device A1 according to the first embodiment in the position where the buffer member 81 is arranged.

[0125] In a semiconductor device A8 according to the eighth embodiment, a buffer member 81 is interposed between a conductive member 22A and a semiconductor element 10A. The buffer member 81 and the conductive member 22A are bonded by solid-state diffusion bonding between a plating layer 85 (Ag) formed on a main surface 801 of the buffer member 81 and a plating layer 222 (Ag) formed on a main surface 221A of the conductive member 22A. The buffer member 81 and the semiconductor element 10 are bonded by an element bonding layer 31A. A portion of the buffer member 81 is deformed during the pressurizing and heating process, and has a shape in which the outer shape is compressed by the pressure and bulges in a curved shape when viewed in the z direction. Similarly, a buffer member 82 may be interposed between the conductive member 22B and the semiconductor element 10B. The buffer member 81 may be interposed between the element bonding layer 31A and the semiconductor element 10A, or the buffer member 82 may be interposed between the element bonding layer 31B and the semiconductor element 10B.

[0126] According to this embodiment, buffer members 81 are interposed between the conductive member 22A and the semiconductor element 10A. Therefore, when the pressure member 90 presses and applies pressure to the lead members 51 in the pressure-heating process, some of the buffer members 81 are crushed and thinned by the pressure, so that the positions in the z direction of the upper surfaces of the lead members 51 (the heights from the main surface 221A of the conductive member 22A to the upper surfaces of the lead members 51) become approximately the same. This allows the load to be applied evenly to the semiconductor elements 10A, preventing a biased load from being applied to some of the semiconductor elements 10A. Furthermore, the semiconductor device A8 has a configuration in common with the semiconductor device A1, and thereby achieves the same effects as the semiconductor device A1.

[0127] 26 to 28B are diagrams illustrating a semiconductor device A9 according to a ninth embodiment of the present disclosure. FIG. 26 is a perspective view showing the semiconductor device A9, with the sealing resin 7 indicated by an imaginary line (two-dot chain line). FIG. 27 is a cross-sectional view taken along line XXVII-XXVII in FIG. 26. Note that the plating layers are omitted in FIG. 27. FIGS. 28A and 18B are schematic diagrams illustrating a pressurizing and heating step in the manufacturing process of the semiconductor device A9. The semiconductor device A9 according to this embodiment differs from the semiconductor device A1 according to the first embodiment in that it includes only one semiconductor element 10A.

[0128] The semiconductor device A9 according to the ninth embodiment has a so-called lead frame structure and includes a lead frame 92, as shown in FIG. 26 . The material of the lead frame 92 is not particularly limited, but may be, for example, Cu or a Cu alloy. The lead frame 92 includes a die pad portion 921 and a terminal portion 922. The die pad portion 921 is a portion on which a semiconductor element 10A is mounted. In this embodiment, one semiconductor element 10A is mounted on the die pad portion 921, and the semiconductor element 10A is bonded to the die pad portion 921 via an element bonding layer 31. The die pad portion 921 is electrically connected to the drain electrode 113 of the semiconductor element 10A. In this embodiment, the die pad portion 921 is an example of an “electrical conductor.” A portion of the terminal portion 922 is exposed from the sealing resin 7. The terminal portion 922 is electrically connected to the source electrode 111 of the semiconductor element 10A via a lead member 51.

[0129] The first bonding portion 511 of the lead member 51 according to the ninth embodiment is electrically connected to the source electrode 111 of the semiconductor element 10A via the buffer member 81 and the lead bonding layer 321. The second bonding portion 512 is bonded to the terminal portion 922 via the lead bonding layer 322.

[0130] The buffer member 81 is interposed between the source electrode 111 of the semiconductor element 10A and the first bonding portion 511 of the lead member 51. As shown in Figures 28A and 28B, in the pressure and heat step of the manufacturing process of the semiconductor device A9, the pressure and heat treatment is performed on a plurality of semiconductor devices A9 at once.

[0131] FIG. 28A shows two lead frames 92, semiconductor elements 10A mounted on each lead frame, lead members 51 electrically connected to each semiconductor element 10A, and buffer members 81 disposed between the semiconductor elements 10A and the lead members 51. The height from the bottom surface of the lead frame 92 to the top surface of the lead members 51 is higher on the left side than on the right side. FIG. 28B shows a state in which a pressure member 90 presses down on each lead member 51. The buffer member 81 disposed on the left semiconductor element 10A is deformed and crushed by the pressure. This reduces the thickness of the buffer member 81, and the height from the bottom surface of the lead frame 92 to the top surface of the lead members 51 is approximately the same on both sides. This causes the load applied to the left semiconductor element 10A and the right semiconductor element 10A to be approximately the same, resulting in equal loads being applied to the two semiconductor elements 10A.

[0132] The buffer member 81 of any of the multiple semiconductor devices A9 manufactured simultaneously deforms during the pressurizing and heating process, thereby evenly distributing the load on each semiconductor element 10A. The semiconductor device A9 shown in FIGS. 26 and 27 shows the buffer member 81 deformed during the pressurizing and heating process. When viewed in the z direction, the buffer member 81 has a shape with a curved, bulging portion due to pressure. Furthermore, both ends of the cross section perpendicular to the z direction protrude outward in an arc shape. In FIG. 26, the second portion 81b is hatched. In FIG. 27, the boundary between the first portion 81a and the second portion 81b is indicated by a dashed line. Note that some semiconductor devices A9 have undeformed buffer members 81 that retain their rectangular parallelepiped shape.

[0133] According to this embodiment, a buffer member 81 is interposed between the first bonding portion 511 of the lead member 51 and the source electrode 111 of the semiconductor element 10A. Therefore, during the pressure and heat process for simultaneously manufacturing a plurality of semiconductor devices A9, it is possible to prevent a biased load from being applied to some of the semiconductor elements 10A. Furthermore, by adopting a configuration common to the semiconductor device A1, the semiconductor device A9 achieves the same effects as the semiconductor device A1. While this embodiment has been described with reference to a case in which the semiconductor device A9 includes the semiconductor element 10A, this is not limiting. The semiconductor device A9 may include another semiconductor element, such as a diode or an IC, instead of the semiconductor element 10A.

[0134] The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways. The present disclosure includes the embodiments described in the following appendices.

[0135] Appendix 1. a first semiconductor element having a first element main surface and a first element back surface facing opposite to each other in a thickness direction, and a first electrode disposed on the first element main surface; a first connection member electrically connected to the first electrode; a first member overlapping the first electrode as viewed in the thickness direction, having a Vickers hardness lower than that of the first connection member, and having electrical conductivity; The semiconductor device comprises: Appendix 2. 2. The semiconductor device according to claim 1, wherein the first member has a portion whose outline is curved and bulges when viewed in the thickness direction. Appendix 3. 3. The semiconductor device according to claim 1, wherein the Vickers hardness of the first member is lower than the Vickers hardness of Cu. Appendix 4. 4. The semiconductor device according to claim 3, wherein the first member has a Vickers hardness of 1 HV or more and 50 HV or less. Appendix 5. 5. The semiconductor device according to claim 4, wherein the first member is made of Al. Appendix 6. 6. The semiconductor device according to claim 1, wherein the first member is interposed between the first electrode and the first connection member. Appendix 7. 7. The semiconductor device according to claim 6, further comprising a conductive bonding layer interposed between the first member and the first electrode. Appendix 8. 8. The semiconductor device according to claim 7, wherein the conductive bonding layer is made of a sintered metal. Appendix 9. 9. The semiconductor device according to claim 8, wherein the sintered metal is sintered silver. Appendix 10. 10. The semiconductor device according to any one of claims 6 to 9, further comprising a plating layer interposed between the first member and the first electrode and in contact with the first member. Appendix 11. 11. The semiconductor device according to any one of claims 6 to 10, wherein the first member has a first portion that overlaps the first connection member when viewed in the thickness direction, and a second portion that is connected to the first portion and protrudes from the first connection member when viewed in the thickness direction. Appendix 12. a second semiconductor element having a second element main surface and a second element back surface facing opposite to each other in the thickness direction, and a second electrode disposed on the second element main surface; a second member overlapping the second electrode as viewed in the thickness direction, having a Vickers hardness lower than that of the first connection member, and having electrical conductivity; 12. The semiconductor device according to any one of claims 6 to 11, further comprising: Appendix 13. 13. The semiconductor device according to claim 12, further comprising a second connection member electrically connected to the second electrode via the second member. Appendix 14. 13. The semiconductor device according to claim 12, wherein the first connection member is electrically connected to the second electrode via the second member. Appendix 15. 15. The semiconductor device according to any one of claims 1 to 14, wherein the dimension of the first member in the thickness direction is 10% to 30% of the dimension of the first semiconductor element in the thickness direction. Appendix 16. a first semiconductor element having a first element main surface and a first element back surface facing opposite to each other in a thickness direction, and a first electrode disposed on the first element main surface; a first connection member that overlaps the first electrode when viewed in the thickness direction and is electrically connected to the first electrode; Equipped with The semiconductor device, wherein the first connecting member has a Vickers hardness lower than the Vickers hardness of Cu and is conductive. Appendix 17. a conductor on which the first semiconductor element is mounted; a second conductive bonding layer interposed between the first semiconductor element and the conductor; Furthermore, 17. The semiconductor device according to any one of claims 1 to 16, wherein the second conductive bonding layer is made of sintered silver. Appendix 18. 18. The semiconductor device according to any one of claims 1 to 17, further comprising a wire joined to the first connection member. Appendix 19. 19. The semiconductor device according to any one of claims 1 to 18, wherein the first semiconductor element is a power MOSFET. [Explanation of symbols]

[0136] A1 to A9: Semiconductor device 10, 10A, 10B: Semiconductor element 101: element main surface 102: element back surface 111: Source electrode 112: Gate electrode 113: Drain electrode 115: Plating layer 13: insulating film 20: supporting substrate 21: insulating substrate 211: main surface 212: Back surface 22, 22A, 22B: Conductive member 221A, 221B: Main surface 222: Plating layer 23A, 23B: Insulation layer 24A, 24B: Gate layer 25A, 25B: detection layer 29: base 3: Conductive bonding layer 301, 302: Metal material for sintering 31, 31A, 31B: element bonding layer 321, 322: Lead bonding layer 33: Terminal bonding layer 40: Terminal 41: Input terminal 411: Pad section 411a: Comb tooth part 412: Terminal part 42: Input terminal 421: Pad section 421a: Connecting part 421b: Extension part 421c: Protrusion 421d: Plating layer 422: Terminal section 43: Output terminal 431: Pad portion 431a: Comb teeth portion 432: Terminal section 44A, 44B: Gate terminal 441: Pad section 442: Terminal section 45A, 45B: Detection terminals 451: Pad section 452: Terminal section 46: Dummy terminal 461: Pad section 462: Terminal section 47A, 47B: Side terminals 49: Insulating member 491: Intervening part 492: Extending part 51: Lead member 511: First joint 512: Second joint 513: Connection 515: plating layer 55: plate member 6: Wire 61: Gate wire 62: Detection wire 63: First connecting wire 64: Second connecting wire 65: Source wire 7: Sealing resin 71: Resin main surface 72: Resin back surface 731~734: Resin side surface 75: Recess 8, 81, 82: Cushioning member 801: Main surface 802: Back surface 81a, 82a: Part 1 81b, 82b: Part 2 85: Plating layer 90: Pressure member 92: Lead frame 921: Die pad 922:Terminal section

Claims

1. a first semiconductor element having a first element main surface and a first element back surface facing opposite to each other in a thickness direction, and a first electrode disposed on the first element main surface; a first connection member electrically connected to the first electrode; a first member overlapping the first electrode as viewed in the thickness direction, having a Vickers hardness lower than that of the first connection member, and having electrical conductivity; a plating layer in contact with the first member; Equipped with the first member is interposed between the first electrode and the first connection member, The plating layer is interposed between the first member and the first electrode. Semiconductor device.

2. a first semiconductor element having a first element main surface and a first element back surface facing opposite to each other in a thickness direction, and a first electrode disposed on the first element main surface; a first connection member electrically connected to the first electrode; a first member overlapping the first electrode as viewed in the thickness direction, having a Vickers hardness lower than that of the first connection member, and having electrical conductivity; a conductive bonding layer made of sintered metal; Equipped with the first member is interposed between the first electrode and the first connection member, the conductive adhesive layer is interposed between the first member and the first electrode; Semiconductor device.

3. 3. The semiconductor device according to claim 2, wherein the sintered metal is sintered silver.

4. The semiconductor device according to claim 1 , wherein the first member has a portion whose outline is curved and bulges when viewed in the thickness direction.

5. 5. The semiconductor device according to claim 1, wherein the Vickers hardness of said first member is lower than the Vickers hardness of Cu.

6. The semiconductor device according to claim 5 , wherein the first member has a Vickers hardness of 1 HV or more and 50 HV or less.

7. The semiconductor device according to claim 6 , wherein the first member is made of Al.

8. 8. The semiconductor device according to claim 1, wherein the first member has a first portion that overlaps the first connection member when viewed in the thickness direction, and a second portion that is connected to the first portion and protrudes from the first connection member when viewed in the thickness direction.

9. a second semiconductor element having a second element main surface and a second element back surface facing opposite to each other in the thickness direction, and a second electrode disposed on the second element main surface; a second member overlapping the second electrode as viewed in the thickness direction, having a Vickers hardness lower than that of the first connection member, and having electrical conductivity; 9. The semiconductor device according to claim 1, further comprising:

10. The semiconductor device according to claim 9 , further comprising a second connection member electrically connected to said second electrode via said second member.

11. The semiconductor device according to claim 9 , wherein the first connection member is electrically connected to the second electrode via the second member.

12. 12. The semiconductor device according to claim 1, wherein the dimension of the first member in the thickness direction is 10% to 30% of the dimension of the first semiconductor element in the thickness direction.

13. a conductor on which the first semiconductor element is mounted; a second conductive bonding layer interposed between the first semiconductor element and the conductor; Furthermore, 13. The semiconductor device according to claim 1, wherein said second conductive bonding layer is made of sintered silver.

14. 14. The semiconductor device according to claim 1, further comprising a wire joined to said first connection member.

15. 15. The semiconductor device according to claim 1, wherein the first semiconductor element is a power MOSFET.

Images