Power conversion device and motor module

Abstract

The power conversion device converts DC power into n-phase AC power. The power conversion device, when a first voltage and a second voltage lower than the first voltage are applied thereto, outputs an n-phase output voltage on the basis of a modulation factor. Here, n is an odd number of 3 or more and indicates the number of phases of an AC output. At a low modulation factor equal to or lower than a first modulation factor, the output voltage becomes a sine wave output. At a second modulation factor higher than the first modulation factor, the output voltage is switched between a phase fixed to the highest voltage and a phase fixed to the lowest voltage, at each electrical angle π / n.

Description

[Technical Field]

[0001] The present invention relates to a power conversion device and a motor module. [Background technology]

[0002] The power conversion device described in Patent Document 1 includes a power conversion unit and a control unit. The control unit has an intermediate value generation unit, a superposition amount generation unit, a voltage value command value calculation unit, and PWM control means. The intermediate value generation unit successively compares the magnitudes of AC output voltage command values ​​of the three-phase power converter to generate an intermediate value. The superposition amount generation unit outputs a superposition amount that changes depending on the amplitude value of the three-phase AC voltage command value. The voltage value command value calculation unit adds the superposition amount to each of the three-phase AC voltage command values ​​to create new three-phase AC voltage command values. The PWM control means compares the voltage command value with a carrier wave and outputs a PWM signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-45846 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the power conversion device described in Patent Document 1, when the modulation factor is near its maximum (for example, when the modulation factor is 2 / √3), the amplitude of the neutral point potential becomes large, resulting in increased harmonic components. The neutral point potential is the average waveform of the three phases. Furthermore, the output voltage waveform of each phase contains non-smooth, non-differentiable points, and therefore contains many high-order harmonics. This may result in noise. When a motor is driven by the power conversion device, this may cause torque fluctuations.

[0005] The present invention has been made in view of the above-mentioned problems, and its object is to provide a power conversion device and a motor module that can suppress noise by suppressing high-order harmonics. [Means for solving the problem]

[0006] An exemplary power conversion device of the present invention converts DC power into n-phase AC power. The power conversion device receives a first voltage and a second voltage lower than the first voltage, and outputs n-phase output voltages based on a modulation factor, where n is the number of phases of the AC output and is an odd number equal to or greater than 3. At a low modulation factor equal to or less than the first modulation factor, the output voltage is a sinusoidal wave output. At a second modulation factor higher than the first modulation factor, the output voltage switches between a phase fixed at a maximum voltage and a phase fixed at a minimum voltage every electrical angle π / n.

[0007] An exemplary power conversion device of the present invention converts DC power into n-phase AC power. The power conversion device outputs n-phase output voltages based on a modulation factor. n is the number of phases of the AC output and is an odd number equal to or greater than 3. The waveform of the output voltage for each phase is a waveform obtained by subtracting a common offset wave from a sine wave waveform. The waveform of the offset wave corresponds to the waveform obtained by connecting the maximum and minimum waveforms of the sine wave waveforms, shifting them in the amplitude value direction, and multiplying them by a coefficient. The maximum waveform represents the maximum waveform of the sine wave waveforms of all phases. The minimum waveform represents the minimum waveform of the sine wave waveforms of all phases.

[0008] An exemplary motor module of the present invention includes the above-described power conversion device and a motor, the motor receiving the output of the power conversion device. [Effects of the Invention]

[0009] In accordance with the exemplary invention, noise can be suppressed by suppressing higher order harmonics. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram of a motor module according to an embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram showing the inverter unit. [Figure 3A] FIG. 3A is a diagram showing a sinusoidal waveform, a primary offset wave, and an offset wave. [Figure 3B] FIG. 3B shows the output voltage after modulation. [Figure 4A] FIG. 4A is a diagram showing a sinusoidal waveform. [Figure 4B] FIG. 4B is an enlarged view of the vicinity of an electrical angle of 60 degrees. [Figure 5A] FIG. 5A is a diagram showing the modulated output voltage and offset wave. [Figure 5B] FIG. 5B is a diagram showing the modulated output voltage and offset wave. [Figure 6A] FIG. 6A is a diagram showing the modulated output voltage and offset wave. [Figure 6B] FIG. 6B is a diagram showing the modulated output voltage and offset wave. [Figure 7] FIG. 7 is a diagram showing the modulated output voltage and offset wave. [Figure 8A] 8A is a diagram showing the output voltage and offset wave of a comparative example. [Figure 8B] FIG. 8B is a diagram showing the output voltage and offset wave of the comparative example. [Figure 9A] FIG. 9A is a diagram showing an output voltage and an offset wave in a comparative example. [Figure 9B] FIG. 9B is a diagram showing the output voltage and offset wave of the comparative example. [Figure 10A] FIG. 10A is a diagram showing an output voltage and an offset wave in a comparative example. [Figure 10B] FIG. 10B is a diagram showing the output voltage and offset wave of the present invention. [Figure 11] FIG. 11 is a diagram showing the amplitude of the offset wave in the voltage direction as a peak-to-peak voltage. [Figure 12A] FIG. 12A is a diagram showing a sine wave waveform and an offset wave. [Figure 12B] FIG. 12B is a diagram showing the output voltage after modulation. [Figure 13]FIG. 13 is an enlarged view of the vicinity of an electrical angle of 90 degrees. [Figure 14A] FIG. 14A is a diagram showing the modulated output voltage and offset wave. [Figure 14B] FIG. 14B is a diagram showing the modulated output voltage and offset wave. [Figure 14C] FIG. 14C shows the modulated output voltage and offset wave. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference characters and description thereof will not be repeated.

[0012] A motor module 200 according to an embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a block diagram of the motor module 200 according to an embodiment of the present invention. Figure 2 is a circuit diagram showing the inverter unit 110.

[0013] As shown in FIG. 1, the motor module 200 includes a motor drive circuit 100 and a three-phase motor M. The three-phase motor M is driven by the motor drive circuit 100. The three-phase motor M is, for example, a brushless DC motor. The three-phase motor M has a U phase, a V phase, and a W phase. The output of the motor drive circuit 100 is input to the three-phase motor M. The motor drive circuit 100 corresponds to an example of a "power conversion device."

[0014] The motor drive circuit 100 controls the driving of the three-phase motor M. The motor drive circuit 100 includes an inverter unit 110 and a signal generation unit 120.

[0015] The motor drive circuit 100 converts DC power into n-phase AC power. n is the number of phases of the AC output and is an integer equal to or greater than 3. In this embodiment, the motor drive circuit 100 converts DC power into three-phase AC power. The motor drive circuit 100 has n output terminals 102. In this embodiment, the motor drive circuit 100 has three output terminals 102. The three output terminals 102 include an output terminal 102u, an output terminal 102v, and an output terminal 102w. The n output terminals 102 output n-phase output voltages and n-phase output currents. In this embodiment, the three output terminals 102 output the three-phase output voltages and three-phase output currents to the three-phase motor M. More specifically, the output terminal 102u outputs a U-phase output voltage Vu and a U-phase output current Iu to the three-phase motor M. The output terminal 102v outputs a V-phase output voltage Vv and a V-phase output current Iv to the three-phase motor M. The output terminal 102w outputs a W-phase output voltage Vw and a W-phase output current Iw to the three-phase motor M.

[0016] As shown in FIG. 2 , the motor drive circuit 100 includes a first power supply terminal P, a second power supply terminal N, a capacitor C, and n series bodies 112. In this embodiment, the motor drive circuit 100 includes a first power supply terminal P, a second power supply terminal N, a capacitor C, and three series bodies 112. More specifically, in this embodiment, the motor drive circuit 100 includes an inverter unit 110, which includes a first power supply terminal P, a second power supply terminal N, a capacitor C, and three series bodies 112. The inverter unit 110 further includes a DC voltage source B. Note that the DC voltage source B may be external to the inverter unit 110.

[0017] A first voltage V1 is applied to a first power supply terminal P. The first power supply terminal P is connected to a DC voltage source B.

[0018] A second voltage V2 is applied to the second power supply terminal N. The second power supply terminal N is connected to a DC voltage source B. The second voltage V2 is lower than the first voltage V1.

[0019] The capacitor C is connected between the first power supply terminal P and the second power supply terminal N.

[0020] Two semiconductor switching elements are connected in series to the three series bodies 112. The semiconductor switching elements are, for example, IGBTs (insulated gate bipolar transistors). The semiconductor switching elements may also be other transistors such as field-effect transistors. The three series bodies 112 include a series body 112u, a series body 112v, and a series body 112w. The three series bodies 112 are connected in parallel to one another. One end of each of the three series bodies 112 is connected to a first power supply terminal P. The other end of each of the three series bodies 112 is connected to a second power supply terminal N. A rectifying element D is connected in parallel to each of these semiconductor switching elements, with the first power supply terminal P side (upper side of the drawing) serving as the cathode and the second power supply terminal N side (lower side of the drawing) serving as the anode. When field-effect transistors are used as the semiconductor switching elements, a parasitic diode may be used as the rectifying element.

[0021] Each of the three series bodies 112 has a first semiconductor switching element and a second semiconductor switching element. Specifically, the series body 112u has a first semiconductor switching element Up and a second semiconductor switching element Un. The series body 112v has a first semiconductor switching element Vp and a second semiconductor switching element Vn. The series body 112w has a first semiconductor switching element Wp and a second semiconductor switching element Wn.

[0022] The first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are connected to the first power supply terminal P. In other words, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are semiconductor switching elements on the high-voltage side.

[0023] The second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are connected to the second power supply terminal N. In other words, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are semiconductor switching elements on the low-voltage side.

[0024] The first semiconductor switching element and the second semiconductor switching element are connected at a connection point 114. More specifically, the first semiconductor switching element Up and the second semiconductor switching element Un are connected at a connection point 114u. The first semiconductor switching element Vp and the second semiconductor switching element Vn are connected at a connection point 114v. The first semiconductor switching element Wp and the second semiconductor switching element Wn are connected at a connection point 114w.

[0025] Connection point 114 in each of the three series bodies 112 is connected to three output terminals 102. Specifically, connection point 114u in series body 112u is connected to output terminal 102u. Connection point 114v in series body 112v is connected to output terminal 102v. Connection point 114w in series body 112w is connected to output terminal 102w.

[0026] PWM signals are input to the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp. The PWM signals are output from the signal generating unit 120. Hereinafter, in this specification, the PWM signal input to the first semiconductor switching element Up may be referred to as the "UpPWM signal." The PWM signal input to the first semiconductor switching element Vp may be referred to as the "VpPWM signal." The PWM signal input to the first semiconductor switching element Wp may be referred to as the "WpPWM signal." The first semiconductor switching elements Up, Vp, and Wp are switched on and off at a frequency higher than the frequency of the AC output. For example, the first semiconductor switching elements Up, Vp, and Wp are turned on when the UpPWM signal, VpPWM signal, and WpPWM signal are at a HIGH level, respectively. On the other hand, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are turned off when the UpPWM signal, the VpPWM signal, and the WpPWM signal are at a low level, respectively.

[0027] PWM signals are input to the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn. The PWM signals are output from the signal generating unit 120. Hereinafter, in this specification, the PWM signal input to the second semiconductor switching element Un may be referred to as the "UnPWM signal." The PWM signal input to the second semiconductor switching element Vn may be referred to as the "VnPWM signal." The PWM signal input to the second semiconductor switching element Wn may be referred to as the "WnPWM signal." The second semiconductor switching elements Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are switched on and off at a frequency higher than the frequency of the AC output. For example, the second semiconductor switching elements Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned on when the UnPWM signal, the VnPWM signal, and the WnPWM signal are at a HIGH level, respectively. On the other hand, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned off when the UnPWM signal, the VnPWM signal, and the WnPWM signal are at a low level, respectively.

[0028] 1, the signal generating unit 120 includes a carrier generating unit 122, a voltage command value generating unit 124, and a comparing unit 126. The signal generating unit 120 is a hardware circuit configured with a processor such as a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), and the like. The processor of the signal generating unit 120 functions as the carrier generating unit 122, the voltage command value generating unit 124, and the comparing unit 126 by executing a computer program stored in a storage device.

[0029] The signal generating unit 120 controls the inverter unit 110. Specifically, the signal generating unit 120 generates a PWM signal and outputs the PWM signal to control the inverter unit 110. More specifically, the signal generating unit 120 generates a PWM signal to be input to each of the three series bodies 112.

[0030] The carrier generating unit 122 generates a carrier signal. The carrier signal is, for example, a triangular wave. Alternatively, the carrier signal may be a sawtooth wave.

[0031] The voltage command value generation unit 124 generates a voltage command value. The voltage command value corresponds to a voltage value output from the motor drive circuit 100. That is, the voltage command value generation unit 124 generates voltage values ​​according to the output voltage Vu, the output voltage Vv, and the output voltage Vw as voltage command values.

[0032] The comparison unit 126 generates a PWM signal by comparing the carrier signal with the voltage command value.

[0033] The signal generating unit 120 modulates the sine wave based on the modulation factor. More specifically, in this embodiment, the voltage command value generating unit 124 modulates the sine wave based on the modulation factor. In the following description, the modulation factor is defined as 1 when the amplitude of the sine wave is 1 / (√3).

[0034] Next, a sine wave modulation method will be described with reference to FIGS. 3A and 3B. FIG. 3A shows sine wave waveforms Vub, Vvb, Vwb, primary offset wave OW1, and offset wave OW2. FIG. 3B shows modulated output voltages Vu, Vv, and Vw. In FIG. 3A, the sine wave waveform Vub is shown by a solid line, the sine wave waveform Vvb is shown by a dashed line, and the sine wave waveform Vwb is shown by a dashed line. In FIG. 3B, the output voltage Vu is shown by a solid line, the output voltage Vv is shown by a dashed line, and the output voltage Vw is shown by a dashed line. The vertical axis in FIGS. 3A and 3B represents the voltage value normalized by the input voltage V1-V2, and the output voltage of each phase ranges from 0 to 1. This value also represents the duty cycle, which is the ratio of the on-time of the first semiconductor switching element of each phase to the PWM period. When the second semiconductor switching element is switched, the ratio of the on-time of the second semiconductor switching element to the PWM period is calculated by subtracting the value on the vertical axis from 1. When both the first and second semiconductor switching elements are switched, an appropriate dead time is provided to prevent them from being turned on simultaneously, and the switching is performed complementarily. The horizontal axis in Figures 3A and 3B represents the electrical rotation angle of the motor, measured in degrees.

[0035] As shown in Figure 3A, the sine wave waveforms Vub, Vvb, and Vwb are sinusoidal. The sine wave waveform Vvb is 120 degrees out of phase with the sine wave waveform Vub. The sine wave waveform Vwb is 120 degrees out of phase with the sine wave waveform Vvb. The sine wave waveform Vub is 120 degrees out of phase with the sine wave waveform Vwb.

[0036] As shown in (1) of FIG. 3A, the signal generator 120 generates the first offset wave OW1 by switching between the maximum waveform among the sinusoidal waveforms of all phases and the minimum waveform among the sinusoidal waveforms of all phases every 60 degrees, moving them in the amplitude value direction, and connecting them on the Y-axis. In this specification, the "maximum waveform among the sinusoidal waveforms of all phases" may be referred to as the "maximum waveform." Also, in this specification, the "minimum waveform among the sinusoidal waveforms of all phases" may be referred to as the "minimum waveform."

[0037] Specifically, the signal generating unit 120 shifts the maximum waveform in the amplitude direction at electrical angles between 60 and 120 degrees, between 180 and 240 degrees, and between 300 and 360 degrees. If the amplitude of the sine wave is A, the shift amount is A×(√3) / 2.

[0038] The signal generating unit 120 shifts the minimum waveform in the amplitude value direction at electrical angles of 0 to 60 degrees, 120 to 180 degrees, and 240 to 360 degrees. If the amplitude of the sine wave is A, the shift amount is A×(√3) / 2.

[0039] Next, as shown in (2) of FIG. 3A, the signal generating unit 120 generates an offset wave OW2 by multiplying the amplitude of the primary offset wave OW1 by K. The coefficient K is K=(A-0.5) / A{1-(√3) / 2}. Note that when A≦0.5, K=0. When A=1 / √3, i.e., when the modulation factor is 1, K=1. When A>1 / √3 (overmodulation), K is fixed at, for example, K=1.

[0040] Next, by subtracting the offset wave OW2 from the sine wave waveform of each phase (sine wave waveform Vub, sine wave waveform Vvb, sine wave waveform Vwb), a modulated waveform that is tangent to ±0.5 is obtained, as shown in Figure 3B. In other words, the waveform of the output voltage of each phase is a waveform obtained by subtracting the common offset wave OW2 from the sine wave waveform (sine wave waveform Vub, sine wave waveform Vvb, sine wave waveform Vwb).

[0041] As described above with reference to Figures 3A and 3B, the waveform of the output voltage of each phase is a waveform obtained by subtracting a common offset wave OW2 from the sinusoidal waveforms (sinusoidal waveform Vub, sinusoidal waveform Vvb, sinusoidal waveform Vwb). The waveform of the offset wave OW2 corresponds to the waveform obtained by shifting the maximum and minimum waveforms of the sinusoidal waveforms (sinusoidal waveform Vub, sinusoidal waveform Vvb, sinusoidal waveform Vwb) in the amplitude direction, connecting them, and multiplying them by a coefficient. The maximum waveform represents the maximum waveform of the sinusoidal waveforms of all phases. The minimum waveform represents the minimum waveform of the sinusoidal waveforms of all phases. Therefore, noise can be suppressed by suppressing high-order harmonics. Furthermore, calculation of the offset wave becomes easier.

[0042] Next, the coefficient K will be further described with reference to Figures 4A and 4B. Figure 4A is a diagram showing the sine wave waveforms Vub, Vvb, and Vwb. Figure 4B is an enlarged view of the vicinity of an electrical angle of 60 degrees.

[0043] As shown in FIG. 4A, when focusing on an electrical angle of 60 degrees, the gradients of the minimum waveform (V phase) and the maximum waveform (U phase) match, so the extracted waveforms can be smoothly connected.

[0044] Here, consider generating an offset wave (b) using waveform (a) extracted from a sine wave waveform Vub between 60 and 120 electrical degrees to obtain a modulated waveform (c) (peak = ±0.5). If the amplitude of the sine wave waveform Vub is A, and the point A(√3) / 2 at 60 electrical degrees is used as the reference point, subtracting (b) from (a), which has a height AA(√3) / 2, to obtain (c), which has a height of 0.5 - A(√3) / 2. Therefore, the height of (b) is A - 0.5. When generating (b) by multiplying (a) by K, K is the height ratio, i.e., K = (A - 0.5) / A{1 - (√3) / 2}.

[0045] Next, the output voltage when the modulation factor is changed will be described with reference to Figs. 5A to 7. Figs. 5A to 7 are diagrams showing the modulated output voltage Vu, output voltage Vv, output voltage Vw, and offset wave OW2. Fig. 5A shows the output voltage when the modulation factor is 0.8. Fig. 5B shows the output voltage when the modulation factor is (√3) / 2. Fig. 6A shows the output voltage when the modulation factor is 0.9. Fig. 6B shows the output voltage when the modulation factor is 0.95. Fig. 7 shows the output voltage when the modulation factor is 1.

[0046] As shown in FIG. 5A, at a modulation rate of 0.8, the output voltages (output voltage Vu, output voltage Vv, and output voltage Vw) are sinusoidal waves.

[0047] 5B, at a modulation rate of (√3) / 2, the output voltages (output voltage Vu, output voltage Vv, and output voltage Vw) become sine waves. At a modulation rate of (√3) / 2, the sine waves have their maximum amplitude.

[0048] As shown in Figures 5A and 5B, when the modulation factor is low, that is, (√3) / 2 or less, the output voltage is a sine wave output. The modulation factor (√3) / 2 is an example of a "first modulation factor." In other words, when the modulation factor is low, that is, less than the first modulation factor, the output voltage is a sine wave output.

[0049] As shown in FIG. 6A, at a modulation factor of 0.9, the output voltages (output voltage Vu, output voltage Vv, and output voltage Vw) are transformed from a sine wave so that they fall between the maximum voltage (+0.5) and the minimum voltage (-0.5). For example, at an electrical angle of 30 degrees, the output voltage Vv reaches its minimum voltage. At an electrical angle of 90 degrees, the output voltage Vu reaches its maximum voltage. At an electrical angle of 150 degrees, the output voltage Vw reaches its minimum voltage. At an electrical angle of 210 degrees, the output voltage Vu reaches its maximum voltage. At an electrical angle of 270 degrees, the output voltage Vu reaches its minimum voltage. At an electrical angle of 330 degrees, the output voltage Vu reaches its maximum voltage.

[0050] As shown in FIG. 6B, at a modulation factor of 0.95, the output voltages (output voltage Vu, output voltage Vv, and output voltage Vw) are deformed from a sine wave so that they fall between a maximum voltage (+0.5) and a minimum voltage (-0.5). For example, at an electrical angle of 30 degrees, the output voltage Vv reaches its minimum voltage. At an electrical angle of 90 degrees, the output voltage Vu reaches its maximum voltage. At an electrical angle of 150 degrees, the output voltage Vw reaches its minimum voltage. At an electrical angle of 210 degrees, the output voltage Vu reaches its maximum voltage. At an electrical angle of 270 degrees, the output voltage Vu reaches its minimum voltage. At an electrical angle of 330 degrees, the output voltage Vu reaches its maximum voltage. With the output voltage at a modulation factor of 0.95 shown in FIG. 6B, the curvature of the output voltage waveform near the maximum voltage (+0.5) and the minimum voltage (-0.5) is smaller than with the output voltage at a modulation factor of 0.9 shown in FIG. 6A.

[0051] As shown in FIG. 7, at a modulation factor of 1, the output voltages (output voltage Vu, output voltage Vv, and output voltage Vw) are fixed so that part of the sine wave is at the maximum voltage (+0.5) or part of the sine wave is at the minimum voltage (-0.5). For example, from an electrical angle of 0 to 60 degrees, the output voltage Vu is fixed to the minimum voltage. From an electrical angle of 60 to 120 degrees, the output voltage Vu is fixed to the maximum voltage. From an electrical angle of 120 to 180 degrees, the output voltage Vw is fixed to the minimum voltage. From an electrical angle of 180 to 240 degrees, the output voltage Vv is fixed to the maximum voltage. From an electrical angle of 240 to 300 degrees, the output voltage Vu is fixed to the minimum voltage. From an electrical angle of 300 to 360 degrees, the output voltage Vw is fixed to the maximum voltage. Thus, at a modulation factor of 1, the output voltage switches between a phase fixed at the maximum voltage and a phase fixed at the minimum voltage every 90 electrical degrees (π / n). Modulation factor 1 is an example of a "second modulation factor." The second modulation factor is greater than the first modulation factor. In other words, at the second modulation factor, the output voltage switches between a phase fixed at the maximum voltage and a phase fixed at the minimum voltage every π / n electrical angle. Therefore, noise can be suppressed by suppressing higher-order harmonics.

[0052] Furthermore, the maximum voltage is substantially equal to the first voltage. At this time, during the period when the output voltage is the maximum voltage output, the first semiconductor switching element of the phase that produces the maximum voltage output can be fixed to ON. Therefore, switching loss can be reduced.

[0053] Furthermore, the minimum voltage is substantially equal to the second voltage. At this time, during the period when the output voltage is the minimum voltage output, the second semiconductor switching element of the phase that produces the minimum voltage output can be fixed to ON. Therefore, switching loss can be suppressed.

[0054] 5A to 7, as the modulation rate increases, the output voltage changes continuously from a first state (the state shown in FIGS. 5A and 5B) in which the output voltage is a sine wave output to a second state (the state shown in FIG. 7) in which the phase in which the output voltage is fixed to the maximum voltage and the phase in which the output voltage is fixed to the minimum voltage switch every electrical angle π / n. Therefore, noise can be suppressed by suppressing high-order harmonics.

[0055] Next, the peak-to-peak voltage of the offset wave will be described with reference to FIGS. 8A to 11. FIGS. 8A to 10A are diagrams showing the output voltage and offset wave of a comparative example. Specifically, FIG. 8A shows the output voltage and offset wave of a Min-type two-phase modulation. FIG. 8B shows the output voltage and offset wave of a MinMax-type two-phase modulation. FIG. 9A shows the output voltage and offset wave of space vector modulation (SVM). FIG. 9B shows the output voltage and offset wave of a conventional method using a linear equation. The conventional method using a linear equation multiplies the median value of the three-phase output voltage by 0.5, then multiplies it by a superposition amount according to the modulation rate, and subtracts the result from the output voltage of each phase. The relationship between the modulation rate and the superposition amount is such that the superposition amount is 0 for modulation rates of (√3) / 2 or less, and the superposition amount is proportional to the value obtained by subtracting (√3) / 2 from the modulation rate for modulation rates of (√3) / 2 to 1. FIG. 10A shows the output voltage and offset wave superimposed with a third harmonic. FIG. 10B is a diagram showing the output voltage and offset wave of the present invention.

[0056] Figure 11 shows the amplitude of the offset wave in the voltage direction as peak-to-peak voltage. In Figure 11, the horizontal axis represents the modulation rate, and the vertical axis represents the peak-to-peak voltage. In a non-overmodulation state, the offset wave corresponds to the average output voltage of all phases, i.e., it represents the output common voltage. Therefore, the smaller the peak-to-peak voltage on the vertical axis, the smaller the fluctuation in the output common potential, and the more effectively noise caused by fluctuations in the output common potential is suppressed.

[0057] As shown in FIG. 11, at modulation rates of 0.91 to 0.98, the MinMax type two-phase modulation shown in FIG. 8B and the third harmonic superposition shown in FIG. 10A are equivalent to the present invention shown in FIG. 10B. However, with the MinMax type two-phase modulation, the peak-to-peak voltage deteriorates at low modulation rates. Furthermore, with the third harmonic superposition, the peak-to-peak voltage of the offset wave deteriorates at high modulation rates. With the conventional method using a linear equation, the peak-to-peak voltage of the offset wave deteriorates more than with the MinMax type two-phase modulation and the third harmonic superposition, and as the modulation rate increases, the increase in the peak-to-peak voltage of the offset wave becomes more pronounced. With the Min type two-phase modulation and space vector modulation (SVM), the peak-to-peak voltage of the offset wave deteriorates more than with the linear equation of JP 2005-45846 A. As such, with the present invention, the peak-to-peak voltage of the offset wave can be suppressed across the entire range.

[0058] 1 to 11, the number of phases of the AC output is three, but the number of phases of the AC output may be an odd number equal to or greater than five. For example, the number of phases of the AC output may be five.

[0059] Next, a method for modulating a sine wave will be described with reference to Figures 12A and 12B. Figure 12A is a diagram showing sine wave waveforms Vub, Vvb, Vwb, Vxb, Vyb, and an offset wave OW2. Figure 12B is a diagram showing the modulated output voltages Vu, Vv, Vw, Vx, Vy, and offset wave OW2. In Figure 12A, the sine wave waveform Vub is shown with a solid line, the sine wave waveform Vvb is shown with a dashed line, the sine wave waveform Vwb is shown with a dashed line, the sine wave waveform Vxb is shown with a large-pitched dashed line, and the sine wave waveform Vyb is shown with a small-pitched dashed line. In Figure 12B, the output voltage Vu is shown by a solid line, the output voltage Vv is shown by a dashed line, the output voltage Vw is shown by a dashed line, the output voltage Vx is shown by a dashed line with a large pitch, and the output voltage Vy is shown by a dashed line with a small pitch. The vertical axis in Figures 12A and 12B represents the voltage value normalized by the input voltage V1-V2, and the output voltage of each phase ranges from 0 to 1. This value also represents the duty value, which is the ratio of the on-time of the first semiconductor switching element of each phase to the PWM period. When the second semiconductor switching element is switched, the value on the vertical axis is subtracted from 1 to obtain the ratio of the on-time of the second semiconductor switching element to the PWM period. When both the first and second semiconductor switching elements are switched, an appropriate dead time is provided to prevent them from being turned on simultaneously, and the switching is performed complementarily. The horizontal axis in Figures 12A and 12B represents the electrical rotation angle of the motor, in degrees.

[0060] 12A, the number of phases of the AC output is 5. That is, the motor drive circuit 100 controls the drive of the motor M having five phases.

[0061] As shown in FIG. 12A, the sine wave waveform Vub, the sine wave waveform Vvb, the sine wave waveform Vwb, the sine wave waveform Vxb, and the sine wave waveform Vyb are sinusoidal. The sine wave waveform Vvb is out of phase with the sine wave waveform Vub by 72 degrees (2π / n). The sine wave waveform Vwb is out of phase with the sine wave waveform Vvb by 72 degrees (2π / n). The sine wave waveform Vub is out of phase with the sine wave waveform Vyb by 72 degrees (2π / n). The sine wave waveform Vxb is out of phase with the sine wave waveform Vwb by 72 degrees (2π / n). The sine wave waveform Vyb is out of phase with the sine wave waveform Vxb by 72 degrees (2π / n).

[0062] The slopes of the maximum and minimum waveforms match at the dashed line in Figure 12A. For example, at an electrical angle of 36 degrees (π / n), the slopes of the maximum waveform (Y phase) and the minimum waveform (W phase) match. Therefore, the extracted waveforms can be smoothly connected.

[0063] The offset wave OW2 corresponds to the maximum and minimum waveforms of the sine wave waveforms (sine wave waveform Vub, sine wave waveform Vvb, sine wave waveform Vwb, sine wave waveform Vxb, and sine wave waveform Vyb) shifted in the amplitude value direction, connected, and multiplied by a coefficient.

[0064] When the central potential of the output voltage is used as the reference, the maximum voltage is Dmax, the minimum voltage is -Dmax, and the amplitude of the sine wave is A, the amount of movement in the amplitude direction for the maximum waveform is -Asin{(n-1)π / (2n)} and for the minimum waveform is Asin{(n-1)π / (2n)}. This makes it easy to calculate the offset wave OW2.

[0065] By subtracting the offset wave OW2 from the sinusoidal waveform of each phase (sinusoidal waveform Vub, sinusoidal waveform Vvb, sinusoidal waveform Vwb, sinusoidal waveform Vxb, and sinusoidal waveform Vyb), a modulated waveform that is in contact with ±Dmax is obtained, as shown in Figure 12B. Therefore, the modulated waveform is a smooth waveform that falls within the range of ±Dmax.

[0066] The coefficient K will be further described with reference to Figures 12A and 13. Figure 13 is an enlarged view of the vicinity of an electrical angle of 90 degrees.

[0067] As shown in Figure 13, suppose that waveform (c) with a peak value of Dmax is obtained by subtracting an offset wave (b) from waveform (a) with amplitude A. Using the value Asin{(n-1)π / n} of (a) at the slope coincidence point (n-1)π / n as a reference, the peak height of (a) is A-Asin{(n-1)π / 2n}. Subtracting the offset wave (b) from this waveform yields waveform (c), whose peak height is Dmax-Asin{(n-1)π / n}. Therefore, the peak height of offset wave (b) is A-Dmax. To generate offset wave (b) from waveform (a) with amplitude A, the portion of waveform (a) with amplitude A that exceeds Asin{(n-1)π / n} can be multiplied by a coefficient K = (A-Dmax) / [A-Asin{(n-1)π / 2n}]. In other words, if the original sine wave waveform is shifted by Asin{(n-1)π / 2n} and then connected and multiplied by the coefficient K, the offset wave OW2 shown in Fig. 12A is obtained. Note that when the amplitude A is A≦Dmax, K=0.

[0068] As described above with reference to Figures 12A and 13, the waveform of the offset wave OW2 corresponds to the maximum and minimum waveforms of a sine wave, shifted in the amplitude direction, connected, and multiplied by a coefficient. Taking the central potential of the output voltage as the reference, if the maximum voltage is Dmax, the minimum voltage is -Dmax, and the amplitude of the sine wave is A, the amount of shift in the amplitude direction for the maximum waveform is -Asin{(n-1)π / (2n)}, and for the minimum waveform is Asin{(n-1)π / (2n)}. This makes it easy to calculate the offset wave OW2.

[0069] Furthermore, the coefficient K is (A-Dmax) / [A-Asin{(n-1)π / (2n)}]. Therefore, the offset wave OW2 can be easily calculated.

[0070] The output voltage when the modulation factor is changed will be described with reference to Figures 14A to 14C. Figures 14A to 14C are diagrams showing the modulated output voltage Vu, output voltage Vv, output voltage Vw, and offset wave OW2. Figure 14A shows the output voltage when the modulation factor is 0.95. Figure 14B shows the output voltage when the modulation factor is 1.0. Figure 14C shows the output voltage when the modulation factor is 1.02.

[0071] 14C, when the modulation factor exceeds the second modulation factor (for example, modulation factor 1), the coefficient K is 1. This makes it easy to calculate the offset wave OW2. Furthermore, when the modulation factor exceeds the second modulation factor, the offset wave OW2 is subtracted from the sinusoidal waveforms of each phase (sinusoidal waveform Vub, sinusoidal waveform Vvb, sinusoidal waveform Vwb, sinusoidal waveform Vxb, and sinusoidal waveform Vyb), and then the portions below -Dmax are fixed to -Dmax, and the portions above Dmax are fixed to Dmax, thereby obtaining the waveforms of the output voltages (output voltage Vu, output voltage Vv, and output voltage Vw).

[0072] Furthermore, when the modulation factor exceeds a second modulation factor (e.g., a modulation factor of 1), at least one of the time period fixed at the maximum voltage and the time period fixed at the minimum voltage increases as the modulation factor increases. Therefore, the transition from a non-overmodulation state (e.g., a modulation factor of 1 or less) to an overmodulation state (e.g., a modulation factor exceeding 1) can be performed continuously without changing the waveform shape. As a result, it is possible to prevent problems such as speed steps from occurring when transitioning from a non-overmodulation state (e.g., a modulation factor of 1 or less) to an overmodulation state (e.g., a modulation factor exceeding 1). [Industrial Applicability]

[0073] The present invention can be suitably used in a power conversion device and a motor module. [Explanation of symbols]

[0074] 100 Motor drive circuit (power conversion device) 102, 102u, 102v, 102w output terminal 112, 112u, 112v, 112w series body 200 Motor Module A amplitude K factor Medium motor N 2nd power supply terminal OW2 offset wave P 1st power supply terminal Un, Vn, Wn Second semiconductor switching element Up, Vp, Wp First semiconductor switching element V1 First voltage V2 Second voltage Vu, Vv, Vw, Vx, Vy output voltage Vub, Vvb, Vwb, Vxb, Vyb Sine wave waveform

Claims

1. A power conversion device that converts DC power into n-phase AC power, outputting n-phase output voltages based on the modulation rate; n is the number of phases of the AC output, and is an odd number equal to or greater than 3, The waveform of the output voltage of each phase is a waveform obtained by subtracting a common offset wave from a sine wave waveform, the waveform of the offset wave corresponds to a waveform obtained by shifting the maximum and minimum waveforms of the sine wave waveform in the amplitude value direction, connecting the waveforms, and multiplying the waveform by a coefficient; the maximum waveform indicates the maximum waveform among the sinusoidal waveforms of all phases, The minimum waveform represents the minimum waveform among the sinusoidal waveforms of all phases.

2. When the central potential of the output voltage is used as a reference, the maximum voltage is Dmax, the minimum voltage is −Dmax, and the amplitude of the sine wave waveform is A, the amount of movement in the amplitude value direction is −A sin {(n−1)π / (2n)}, and the minimum waveform is A sin {(n−1)π / (2n)}. The power conversion device according to claim 1.

3. 3. The power conversion device according to claim 1, wherein the coefficient is (A-Dmax) / [A-A sin{(n-1)π / (2n)}].

4. A power conversion device described in any one of claims 1 to 3, wherein at a second modulation rate greater than a predetermined modulation rate, the output voltage switches between a phase fixed to a maximum voltage and a phase fixed to a minimum voltage every electrical angle π / n.

5. The power conversion device according to claim 4 , wherein the coefficient is 1 when the modulation rate exceeds the predetermined modulation rate.

6. 6. The power conversion device according to claim 4, wherein when the modulation rate exceeds the predetermined modulation rate, at least one of a time period during which the voltage is fixed at the maximum voltage and a time period during which the voltage is fixed at the minimum voltage increases in accordance with an increase in the modulation rate.

7. The power conversion device according to any one of claims 1 to 6; a motor to which the output of the power conversion device is input.

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