Diffusion barrier for germanium

Abstract

An example of the present technique includes a semiconductor processing method for forming a diffusion barrier for germanium in a semiconductor structure. The method may include forming a semiconductor layer stack from a silicon / silicon germanium layer pair. The silicon / silicon germanium layer pair may be formed by forming a silicon layer and then forming a germanium barrier layer on the silicon layer. In some embodiments, the germanium barrier layer may be about 20 Å or less. A silicon germanium layer may be formed on the germanium barrier layer to complete the formation of the silicon / silicon germanium layer pair. In some embodiments, the silicon layer may be an amorphous silicon layer, and the silicon germanium layer may be characterized by about 5 atomic % or more than about 5 atomic % germanium. An example of the present technique may also include a semiconductor structure including a silicon germanium layer, a germanium barrier layer, and a silicon layer.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. patent application Ser. No. 17 / 004,262, filed Aug. 27, 2020, entitled "Diffusion Barriers for Germanium," the entire contents of which are incorporated herein by reference.

[0002]

[0002] The present technology relates to methods and systems for semiconductor processing, and more particularly to systems and methods for creating diffusion barriers for germanium in semiconductor structures. [Background technology]

[0003]

[0003] Integrated circuits are realized by processes that create intricately patterned layers of material on a substrate surface. Creating patterned materials on a substrate requires controlled methods for forming and removing material. As device sizes continue to shrink, film properties can have a greater impact on device performance. The materials used to form the layers of material can affect the operating characteristics of the resulting device. As material thicknesses continue to decrease, the as-deposited properties of the film can have a greater impact on device performance.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to create high quality devices and structures. The present technology addresses these and other needs. Summary of the Invention

[0005] Embodiments of the present technology include semiconductor processing methods for forming diffusion barriers for germanium on a substrate. These diffusion barriers prevent germanium from diffusing from a germanium-containing layer (e.g., a silicon germanium (SiGe) layer) into an adjacent layer (e.g., a silicon (Si) layer) where germanium may form undesired crystals during annealing operations. The technology can be used to fabricate semiconductor devices such as 3D NAND, including forming and annealing multiple pairs of silicon / silicon germanium layers with few defects due to germanium crystallization in the annealed layers. In some embodiments, the method can include forming a semiconductor layer stack from silicon / silicon germanium layer pairs. The silicon / silicon germanium layer pairs can be formed by forming a silicon layer and then forming a germanium barrier layer on the silicon layer. In some embodiments, the germanium barrier layer can be about 20 Å or less. A silicon germanium layer can be formed on the germanium barrier layer to complete the formation of the silicon / silicon germanium layer pairs. In some embodiments, the silicon layer may be an amorphous silicon layer, and the silicon germanium layer may be characterized by about 5 atomic % or greater than about 5 atomic % germanium.

[0006] In exemplary embodiments, the germanium barrier layer may be made of one or more materials, such as silicon oxide, silicon nitride, silicon oxynitride, germanium oxide, germanium nitride, or germanium oxynitride. In some embodiments, the germanium barrier layer may be a silicon oxide layer formed by exposing the silicon layer to an oxidizing plasma generated from an oxidizing precursor including molecular oxygen (O). In further embodiments, the oxidizing precursor may include one or more of ozone (O), water (H2O), and nitrous oxide (N2O). The silicon layer may be exposed to the oxidizing plasma for about 5 seconds or less to form a silicon oxide layer that functions as a germanium barrier layer. In some embodiments, a second germanium barrier layer may be formed on the silicon germanium layer before another silicon / silicon germanium layer pair is formed. In these embodiments, a germanium barrier layer is formed between each silicon layer and silicon germanium layer in the semiconductor layer stack. In some embodiments, the semiconductor layer stack can have about 50 pairs or more than about 50 pairs of silicon / silicon germanium layer pairs.

[0007] In a further exemplary embodiment, the germanium barrier layer may be a silicon nitride layer formed by exposing the silicon layer to a nitrogen-containing plasma generated from a nitrogen-containing precursor. In embodiments, the nitrogen-containing precursor may include one or more of molecular nitrogen (N), a combination of N and H, and ammonium (NH), among other nitrogen-containing precursors. In a further embodiment, the nitrogen-containing precursor may be oxygen-free.

[0008] A germanium diffusion barrier formed in the semiconductor layer stack slows the diffusion of germanium atoms from the silicon germanium layer into the silicon layer during annealing operations. In some embodiments, these annealing operations can include exposing the semiconductor layer stack to temperatures at or above about 800° C. An exemplary embodiment of the annealing operation can include a rapid thermal anneal that rapidly heats the semiconductor layer stack to temperatures at or above about 1000° C.

[0009]

[0009] Embodiments of the present technology may also include a semiconductor processing method that forms a silicon layer on a substrate and exposes the silicon layer to an oxidizing plasma. The oxidizing plasma may be generated from an O2-containing oxygen precursor that treats the silicon layer for about 5 seconds or less to form a silicon oxide layer on the exposed silicon layer. In some embodiments, the silicon oxide layer may be characterized by a thickness of about 20 Å or less than about 20 Å. The method may further include depositing a silicon germanium layer on the silicon oxide layer. The substrate including the silicon germanium layer may be annealed at a temperature of about 800°C or greater than about 800°C.

[0010] In exemplary embodiments, an O2-containing oxygen precursor can be delivered to a substrate processing chamber holding a substrate, and the chamber can be characterized by a pressure of about 5 Torr or greater than about 5 Torr during generation of an oxidizing plasma. In some embodiments, a plasma power of about 500 Watts or less than about 500 Watts can be delivered to the O2-containing precursor to generate the oxidizing plasma. In further embodiments, the O2-containing precursor can include an additional gas, such as argon.

[0011]

[0011] Embodiments of the present technology further include a semiconductor structure. In some embodiments, the semiconductor structure can include a silicon germanium layer, a germanium barrier layer, and a silicon layer. The germanium barrier layer can be in direct contact with the silicon layer and the silicon germanium layer and can be characterized by a thickness of about 20 Å or less than about 20 Å. In some embodiments, the germanium barrier layer can be a silicon oxide layer. The silicon layer can be characterized by about 0.01 wt % or less than about 0.01 wt % germanium, and in some embodiments, the germanium present in the silicon layer can include crystalline germanium.

[0012] In exemplary embodiments of the semiconductor structure, the silicon germanium layer may be characterized by about 5 atomic % or more than about 5 atomic % germanium, and the silicon layer may include crystallized silicon. In further embodiments, at least one of the silicon germanium layer and the silicon layer may be characterized by a thickness of about 20 nm or more than about 20 nm. In further exemplary embodiments, the semiconductor structure may include a semiconductor layer stack characterized by silicon / silicon germanium layer pairs, the silicon layer and the silicon germanium layer separated by a germanium barrier layer. In some of these embodiments, a second germanium barrier layer may contact the silicon germanium layer. In exemplary embodiments, the semiconductor structure may include a semiconductor layer stack having about 50 pairs or more than about 50 pairs of silicon / silicon germanium layer pairs.

[0013] Such techniques may offer numerous benefits over semiconductor processing methods and structures lacking a germanium barrier layer between silicon / silicon germanium layers. The germanium barrier layer may reduce or prevent germanium diffusion from the silicon germanium layer into the silicon layer. Because the amount of germanium diffusion into the silicon layer is reduced, a high level of etch selectivity is maintained for removing the silicon germanium layer between silicon layers during fabrication processes, such as forming silicon memory channels in 3D NAND devices. Reducing germanium diffusion in the silicon layer also results in fewer germanium-containing crystals forming in the silicon layer. These crystals create defects in the silicon layer that can harm device performance, such as reducing the breakdown voltage of memory cells fabricated from the silicon layer. These and other embodiments, along with their many advantages and features, are described in more detail below and in the accompanying drawings.

[0014] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the following portions of this specification and the drawings. [Brief explanation of the drawings]

[0015] [Figure 1]

[0015] FIG. 1 is a top view of an exemplary processing system, in accordance with some embodiments of the present technique. [Figure 2A]

[0016] 1 is a schematic cross-sectional view of an exemplary semiconductor processing chamber, in accordance with some embodiments of the present technique; [Figure 2B]

[0017] 1 is a schematic cross-sectional view of a further exemplary semiconductor processing chamber, in accordance with some embodiments of the present technique; [Figure 3]

[0018] 1 is a schematic cross-sectional view of an exemplary substrate support and electrostatic chuck, in accordance with some embodiments of the present technique; [Figure 4]

[0019] 1 illustrates operations in a semiconductor processing method, according to some embodiments of the present technique. [Figures 5A-5C]

[0020] 1 is a cross-sectional view of an exemplary semiconductor structure, in accordance with some embodiments of the present technique. DETAILED DESCRIPTION OF THE INVENTION

[0016]

[0021] Some drawings are included as schematics. It is understood that the drawings are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Furthermore, as schematics, the drawings are provided to aid in understanding and may not include all aspects or information compared to realistic depictions and may include exaggerated material for illustrative purposes.

[0017]

[0022] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same kind may be distinguished according to the reference numerals by a letter that distinguishes between the similar components. When only a first reference numeral is used in this specification, the description is applicable to any one of the similar components having the same first reference numeral, regardless of the letter.

[0018]

[0023] The present technology includes semiconductor processing systems, methods, and structures that form a barrier layer for germanium between two adjacent layers of semiconductor material, one of which contains germanium. Embodiments of the present technology address the problem of germanium diffusion from a germanium-containing layer, such as a silicon germanium layer, to an adjacent layer that is not formed of germanium, such as a silicon layer. Germanium that penetrates adjacent layers often forms germanium crystals when these layers undergo thermal treatments, such as rapid thermal annealing. The germanium crystals create defects in these previously germanium-free layers that can degrade the performance of semiconductor devices that include these layers. For example, germanium crystals in an annealed silicon layer can increase the layer's electronic conductivity, requiring semiconductor devices fabricated with these layers to operate at higher voltages and generate more heat. Contamination of the germanium crystals can further reduce the breakdown voltage of semiconductor devices, resulting in increased charge leakage rates and degraded performance in memory storage applications. Thus, in many conventional technologies, even layers intended to be germanium-free may actually contain germanium contamination significantly exceeding 1.0%.

[0019]

[0024] One conventional approach to reducing germanium levels in adjacent layers is to reduce the amount of germanium in the germanium-containing layer. For example, when the germanium-containing layer is a silicon-germanium layer, reducing the molar or weight ratio of germanium to silicon in the layer can result in reduced germanium diffusion into the adjacent layer. However, reducing the molar or weight ratio of germanium to silicon also reduces the etch selectivity of the silicon-germanium layer relative to the adjacent layer (e.g., silicon layer). In device structures such as 3D NAND, selective removal of a silicon-germanium layer over an adjacent silicon layer is a major driver for pursuing these materials over materials made with conventional materials, such as alternating layers of silicon oxide and silicon nitride. Therefore, reducing the molar or weight ratio of germanium to silicon in the silicon-germanium layer makes these materials less essential as a replacement for conventional silicon oxide / silicon nitride in 3D NAND fabrication.

[0020]

[0025] Another conventional approach to reducing germanium levels in adjacent layers is to increase the thickness of the adjacent layers so that the penetrating germanium is less concentrated within the layer. For example, an adjacent silicon layer can be made thicker to reduce the concentration of germanium in the layer that diffuses from the silicon-germanium layer. However, increasing the thickness of the silicon layers can also increase their deposition time as well as the time required to etch semiconductor features, such as contact holes, that penetrate the layers. For device structures such as 3D NAND devices, which may include hundreds of silicon layers, even a small increase in silicon layer thickness can result in a significant increase in the formation and etching time of the layer stack.

[0021]

[0026] The present technology addresses these problems by providing, among other things, semiconductor processing systems, methods, and structures that form a thin barrier layer for germanium to reduce or prevent the diffusion of germanium into adjacent layers that were initially formed germanium-free. In some embodiments, the germanium barrier layer can be formed as a silicon- or germanium-containing dielectric layer about 20 Å or less in thickness. This thin barrier layer has been found to be effective in reducing or preventing the diffusion of germanium into adjacent layers. Because the barrier layers are thin, they can be deposited in a short time (e.g., about 5 seconds or less). They also add a relatively small thickness to layer stacks that may include about 50 or more pairs of germanium-containing layers and adjacent layers that were initially formed germanium-free. In some embodiments, the present technology enables faster and thinner formation of silicon / silicon germanium layer stacks with few post-anneal defects for applications such as 3D NAND device formation.

[0022]

[0027] While the remainder of the disclosure routinely identifies particular deposition processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to other deposition and treatment processes that may occur in the described chambers or any other chambers. Thus, the present technology should not be considered limited to use with these particular deposition processes or chambers alone. This disclosure describes one possible system and chamber that may be used in carrying out processing methods according to some embodiments of the present technology, before describing additional modifications and adjustments to this system according to embodiments of the present technology.

[0023]

[0028] FIG. 1 illustrates a top view of one embodiment of a semiconductor processing system 100 with a deposition chamber, an etch chamber, a bake chamber, and a cure chamber, according to an embodiment. In the figure, a pair of front-opening unified pods 102 deliver substrates of various sizes that are received by a robot arm 104 and placed in a low-pressure holding area 106 before being placed in one of the substrate processing chambers 108a-108f positioned in tandem sections 109a-109c. A second robot arm 110 may be used to transfer substrate wafers from the holding area 106 to and from the substrate processing chambers 108a-108f. Each substrate processing chamber 108a-f may be equipped to perform several substrate processing operations, including the formation of stacks of semiconductor materials described herein, in addition to other substrate processes, including plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and annealing, etc.

[0024]

[0029] The substrate processing chambers 108a-f may include one or more system components for depositing, forming, annealing, and / or etching silicon-containing layers (e.g., silicon layers) and germanium-containing layers (e.g., silicon germanium layers) on a substrate. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit silicon-containing and silicon germanium-containing materials on a substrate and form germanium barrier layers between each silicon-containing and germanium-containing layer. A third pair of processing chambers (e.g., 108a-b) may be used to anneal and etch the deposited / formed layers. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured for substrate deposition of a semiconductor layer stack featuring alternating silicon and silicon germanium layers separated by germanium barrier layers. Any one or more of the described processes may be performed in chambers separate from the fabrication systems shown in various embodiments. It will be understood that additional configurations of deposition chambers, forming chambers, annealing chambers, and etching chambers for these layers are contemplated by system 100.

[0025]

[0030] 2A and 2B show schematic cross-sectional views of exemplary semiconductor processing systems 232 and 280, in accordance with some embodiments of the present technology. The figures may provide an overview of systems that may be specifically configured to incorporate one or more aspects of the present technology and / or perform one or more operations in accordance with embodiments of the present technology. Further details of systems 232 and 280, as well as the methods performed therein, may be described further below. Systems 232 and 280 may be utilized to form one or more pairs of silicon-containing layers (e.g., silicon layers) and germanium-containing layers (e.g., silicon germanium layers), which may be separated by a germanium barrier layer, in accordance with some embodiments of the present technology, although it should be understood that the methods may similarly be performed in any system in which layer formation may occur.

[0026]

[0031] 2A , a semiconductor processing system 232 includes a semiconductor processing chamber 200 that may include a top wall 224, a sidewall 201, and a bottom wall 222 that define a substrate processing region 226. A gas panel 230 and a controller 210 may be coupled to the processing chamber 200. A substrate support assembly 246 may be provided within the substrate processing region 226 of the processing chamber 200.

[0027]

[0032] The substrate support assembly 246 may include an electrostatic chuck 250 supported by a stem 260. The electrostatic chuck 250 may be fabricated from aluminum, ceramic, and other suitable materials, such as stainless steel. The electrostatic chuck 250 may be moved vertically within the processing chamber 200 using a displacement mechanism (not shown). A temperature sensor 272, such as a thermocouple, may be embedded in the electrostatic chuck 250 to monitor the temperature of the electrostatic chuck 250. The controller 210 may use the measured temperature to control the power supplied to the heater element 270 to maintain the substrate at a desired temperature.

[0028]

[0033] A vacuum pump 202 may be coupled to a port formed in the bottom of the processing chamber 200. The vacuum pump 202 may be used to maintain a desired gas pressure within the processing chamber 200. The vacuum pump 202 also evacuates post-processing gases and process by-products from the processing chamber 200.

[0029]

[0034] A gas distribution assembly 220 having a plurality of apertures 228 may be disposed on top of the processing chamber 200 above the electrostatic chuck 250. The apertures 228 of the gas distribution assembly 220 are utilized to introduce processing gases (e.g., deposition precursors or oxidation precursors) into the processing chamber 200. The apertures 228 may have various sizes, numbers, distributions, shapes, designs, and diameters to facilitate the flow of various processing gases for various process requirements. The gas distribution assembly 220 is connected to a gas panel 230, which allows various gases to flow into the processing space 226 during processing. A plasma is formed from the processing gas mixture exiting the gas distribution assembly 220 to enhance thermal decomposition and / or ionization of the processing gases, resulting in the deposition or formation of material on an upper surface 291 of a substrate 290 positioned on the electrostatic chuck 250.

[0030]

[0035] The gas distribution assembly 220 and the electrostatic chuck 250 may form a spaced-apart electrode pair within the process space 226. To facilitate plasma generation between the gas distribution assembly 220 and the electrostatic chuck 250, one or more RF power sources 240 provide a bias potential to the gas distribution assembly 220 through a matching network 238 (which is optional). Alternatively, the RF power sources 240 and the matching network 238 may be coupled to the gas distribution assembly 220, the electrostatic chuck 250, or both the gas distribution assembly 220 and the electrostatic chuck 250, or may be coupled to an antenna (not shown) disposed outside the process chamber 200. In some embodiments, RF power source 240 can produce power at frequencies of about or greater than about 100 KHz, about or greater than about 500 KHz, about or greater than about 500 KHz, about or greater than about 1 MHz, about or greater than about 10 MHz, about or greater than about 20 MHz, about or greater than about 50 MHz, and about or greater than about 100 MHz, among other frequency ranges. Specific examples of frequencies of power produced by RF power source 240 include 350 KHz, 2 MHz, 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, 100 MHz, and 162 MHz, among other frequencies.

[0031]

[0036] The controller 210 includes a central processing unit (CPU) 212, memory 216, and support circuits 214, which are utilized to control processing sequences and regulate gas flow from the gas panel 230. The CPU 212 may be any form of general-purpose computer processor that may be used in an industrial setting. Software routines may be stored in the memory 216, such as random access memory, read-only memory, a floppy or hard disk drive, or other form of digital storage. The support circuits 214 are coupled to the CPU 212 and may include cache, clock circuits, input / output systems, power supplies, etc. Bidirectional communication between the controller 210 and the various components of the substrate processing system 232 is handled through a number of signal cables (collectively referred to as a signal bus 218, some of which are shown in FIG. 2A ).

[0032]

[0037] 2B shows a schematic cross-sectional view of another substrate processing system 280 that can be used to implement embodiments described herein. The substrate processing system 280 is similar to the substrate processing system 232 of FIG. 2A, except that the substrate processing system 280 is configured to flow process gas radially from the gas panel 230 through the sidewall 201 across the top surface 291 of the substrate 290. In addition, the gas distribution assembly 220 shown in FIG. 2A has been replaced with an electrode 282. The electrode 282 can be configured for secondary electron generation. In one embodiment, the electrode 282 is a silicon-containing electrode.

[0033]

[0038] 3 shows a schematic cross-sectional view of a substrate support assembly 346 that may be used in embodiments of the system. The substrate support assembly 346 may include an electrostatic chuck 350, which may include a heater element 370 suitable for controlling the temperature of a substrate 390 supported on an upper surface 392 of the electrostatic chuck 350. The heater element 370 may be embedded in the electrostatic chuck 350. The electrostatic chuck 350 may be resistively heated by applying a current from a heater power supply 306 to the heater element 370. The heater power supply 306 may be coupled through an RF filter 316 to protect the heater power supply 306 from RF energy. The current supplied by the heater power supply 306 is regulated by a controller 310 to control the heat generated by the heater element 370 and thus maintain the substrate 390 and electrostatic chuck 350 at a substantially constant temperature during film deposition. The supply current may be adjusted to selectively control the temperature of the electrostatic chuck 350 to about 100° C. or greater during deposition, oxidation, and / or thermal annealing operations.

[0034]

[0039] In some embodiments, the electrostatic chuck 350 includes a chucking electrode 410, which may be a mesh of conductive material. The chucking electrode 410 may be embedded in the electrostatic chuck 350. The chucking electrode 410 is coupled to a chucking power supply 412. The chucking power supply 412, when energized, electrostatically clamps the substrate 390 to the upper surface 392 of the electrostatic chuck 350.

[0035]

[0040] The chuck electrode 310 may be configured as a monopolar or bipolar electrode, or may have another suitable configuration. The chuck electrode 410 may be coupled to a chuck power supply 412 through an RF filter 414. The chuck power supply 412 provides direct current (DC) power to electrostatically clamp the substrate 390 to the upper surface 392 of the electrostatic chuck 350. The RF filter 414 prevents RF power utilized to form a plasma within the processing chamber from damaging electrical equipment. The electrostatic chuck 350 may be fabricated from a ceramic material such as AlN or Al2O3.

[0036]

[0041] A power application system 420 is coupled to the substrate support assembly 346. The power application system 420 may include a heater power supply 306, a chuck power supply 412, a first radio frequency (RF) power supply 430, and a second RF power supply 440. An embodiment of the power application system 420 may further include a controller 310, a sensor device 450 in communication with the controller 310, and both the first RF power supply 430 and the second RF power supply 440. The controller 310 may also be utilized to control a plasma from the process gas by applying RF power from the first RF power supply 430 and the second RF power supply 440 to deposit a layer of material on the substrate 390.

[0037]

[0042] As described above, the electrostatic chuck 350 includes a chucking electrode 410, which in one embodiment functions to chuck the substrate 390 and also functions as a first RF electrode. The electrostatic chuck 350 may also include a second RF electrode 460, which, in conjunction with the chucking electrode 410, may apply RF power to regulate the plasma. The first RF power source 430 may be coupled to the second RF electrode 460, while the second RF power source 440 may be coupled to the chucking electrode 410. A first matching network and a second matching network may be provided for the first RF power source 430 and the second RF power source 440, respectively. The second RF electrode 460 may be a solid metal plate of a conductive material or a mesh of a conductive material.

[0038]

[0043] The first RF power source 430 and the second RF power source 440 can produce power at the same frequency or at different frequencies. In some embodiments, one or both of the first RF power source 430 and the second RF power source 440 can independently produce power at frequencies of about or greater than about 100 KHz, about or greater than about 500 KHz, about or greater than about 500 KHz, about or greater than about 1 MHz, about or greater than about 10 MHz, about or greater than about 20 MHz, about or greater than about 50 MHz, and about or greater than about 100 MHz, among other frequency ranges. Specific examples of frequencies of power independently produced by the RF power sources 430, 440 include 350 KHz, 2 MHz, 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, 100 MHz, and 162 MHz, among other frequencies. The RF power from one or both of the first RF power source 430 and the second RF power source 440 can be varied to tailor the plasma.

[0039]

[0044] FIG. 4 illustrates exemplary operations of a processing method 400 according to some embodiments of the present technology. In some embodiments, the method 400 may include forming a layer stack on a substrate. The layer stack may include alternating pairs of germanium-free and germanium-containing layers separated by a germanium barrier layer. In some embodiments, the number of alternating pairs of layers may be about 50 pairs or more than about 50 pairs of layers. Embodiments of the layer stack formed on the substrate can be used to fabricate memory devices, such as 3D NAND devices. The germanium barrier layers between the alternating pairs of germanium-free and germanium-containing layers in the layer stack reduce or prevent germanium crystal growth in the germanium-free layer as a result of processing operations, such as annealing one or more alternating pairs or annealing the fully formed layer stack. The reduction or elimination of germanium crystals in the germanium-free layer increases the conductivity of the layer, among other improvements in device performance.

[0040]

[0045] The processing method 400 can be performed in a variety of processing chambers, including the processing systems 232, 280, and 118 described above. The method 400 can include one or more operations prior to the initiation of the specified method operations, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed before the described operations. The method can also include several optional operations that may or may not be specifically associated with methods in accordance with the present technology, as shown in the drawings. For example, many of the operations are described to provide a broader scope of semiconductor processing, but are not critical to the technology and may be performed by alternative methods, as discussed further below.

[0041]

[0046] Method 400 may involve optional operations to develop the semiconductor structure into specific fabrication operations. In some embodiments, method 400 may be performed on a base structure, but in some embodiments, the method may be performed subsequent to other material formation or removal operations. For example, any number of deposition, formation, or removal operations may be performed to create any number of structural features on a substrate. Operations creating underlying structures may be performed in the same chamber in which aspects of method 400 may be performed, or one or more operations may also be performed in one or more chambers on the same platform as the chamber in which operations of method 400 may be performed or on a different platform.

[0042]

[0047] The method 400 may include forming a germanium-free layer on a substrate 406. The substrate may be positioned in a substrate processing region of a substrate processing chamber. In embodiments, the substrate is a semiconductor wafer. In further embodiments, the substrate may be made of one or more of silicon, silicon oxide, silicon nitride, strained silicon, silicon-on-insulator, carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, and sapphire. In still further embodiments, the substrate may be made of one or more conductive materials, such as elemental metals, metal alloys, and metal nitrides, among other conductive materials. In some embodiments, the substrate may undergo pretreatment operations prior to the initial deposition of the germanium-free layer. Exemplary pretreatment operations may include one or more of polishing, etching, reducing, oxidizing, hydroxylating, nitriding, annealing, and baking the substrate prior to the initial deposition. In further embodiments, the substrate pretreatment operations may also include forming one or more layers of material on the substrate prior to the initial deposition of the germanium-free layer.

[0043]

[0048] In embodiments, the one or more layers of material may include a semiconductor layer (e.g., a polysilicon layer) formed on the substrate. In further embodiments, the one or more layers may optionally include a sacrificial layer formed on the semiconductor layer. The sacrificial layer may be made of a material that can be selectively removed relative to adjacent layers (e.g., the semiconductor layer and the germanium-free layer). In still further embodiments, the one or more layers of material may include a wetting layer formed on the semiconductor layer or, if present, the sacrificial layer. The wetting layer may be formed from the same material as the germanium-free layer but is characterized by a deposition rate that may be slower than the deposition rate for forming the germanium-free layer. In embodiments, the wetting layer may act as a nucleation layer to assist in the deposition of the germanium-free layer. Exemplary substrates may take various shapes, such as circular, rectangular, or square, and may have dimensions, for example, of 200 mm, 300 mm, or 450 mm in diameter, side, or diagonal. In yet another embodiment, the substrate preparation operation may further include forming substrate features in the substrate. Examples of these substrate features may include one or more of steps, holes, doped regions, or trenches, among other substrate features, which may be formed in the substrate. In yet another embodiment, the substrate preparation operations may further include forming substrate features in one or more layers of material formed on the substrate.

[0044]

[0049] In some embodiments, forming a germanium-free layer on a substrate can include delivering deposition precursors to a substrate processing region, where they can be activated to form an as-deposited germanium-free layer on the substrate. In further embodiments, the deposition precursors can be activated by supplying plasma power to the precursors to generate a deposition plasma that deposits the germanium-free layer on the substrate. The as-deposited germanium-free layer can be characterized by a thickness of about or greater than about 20 nm, about or greater than about 25 nm, about or greater than about 30 nm, about or greater than about 35 nm, about or greater than about 40 nm, about or greater than about 45 nm, about or greater than about 50 nm, or greater than about 50 nm.

[0045]

[0050] In some embodiments, the germanium-free layer may be a silicon-containing layer formed with a deposition plasma formed from a silicon-containing deposition precursor. Embodiments of the silicon-containing deposition precursor include silane (SiH), disilane (SiH), and tetrasilane (SiH), among other silicon-containing precursors. 10 ), In some embodiments, the deposition precursor may also include one or more co-precursors such as hydrogen (H), helium (He), argon (Ar), and nitrogen (N), among other co-precursors. Embodiments of silicon-containing layers deposited by silicon-containing deposition precursors may include amorphous silicon layers, semi-crystalline silicon layers, or polysilicon layers, among other types of silicon layers. Embodiments of as-deposited germanium-free silicon layers may be characterized by about or less than about 2 atomic % germanium, about or less than about 1.5 atomic % germanium, about or less than about 1 atomic % germanium, about or less than about 0.5 atomic % germanium, about or less than about 0.25 atomic % germanium, about or less than about 0.1 atomic % germanium, about or less than about 0.1 atomic % germanium, or about or less than about 0.05 atomic % germanium, or less. The reduced germanium content in the germanium-free layer increases the etch selectivity of the germanium-containing layer relative to the germanium-free layer. The reduced germanium content in the germanium-free layer also reduces the number and size of germanium-containing crystals that form in the layer during high-temperature annealing operations. Germanium-free layers with fewer and smaller germanium-containing crystals can be formed in semiconductor device components (e.g., memory cells) that have, among other features, lower electrical resistance and higher breakdown voltages.

[0046]

[0051] In further embodiments, the operation of forming a germanium-free layer on the substrate 406 may further be characterized by maintaining a plasma deposition temperature in a substrate processing region. In some embodiments, during the formation of the germanium-free layer, the plasma processing region may be characterized by a temperature of about or less than 450°C, about or less than 425°C, about or less than 400°C, about or less than 375°C, about or less than 350°C, about or less than 325°C, about or less than 300°C, or less than 300°C. In embodiments, a higher temperature in the plasma processing region may form a germanium-free layer that is denser and etches more slowly than a layer formed at a lower temperature. On the other hand, a higher temperature in the plasma processing region may increase the amount of germanium diffusing from an adjacent germanium-containing layer into the germanium-free layer being formed. By placing a germanium barrier layer between the germanium-free layer and an adjacent germanium-containing layer, embodiments of the present technology enable the formation of a germanium-free layer at higher temperatures in the plasma processing region without proportionally increasing the germanium level in the layer.

[0047]

[0052] In embodiments of the present technology, method 400 may further include forming a germanium barrier layer on germanium-free layer 411. In some embodiments, the germanium barrier layer may be formed by exposing the germanium-free layer to a gas or plasma that reacts with the germanium-free layer to form the barrier layer. In further embodiments, the barrier layer may be formed by exposing the germanium-free layer to a deposition gas or plasma that deposits the barrier layer on the germanium-free layer. Embodiments may include forming a germanium barrier layer made from one or more dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, germanium oxide, germanium nitride, or germanium oxynitride, among other dielectric materials. The barrier layer may have a thickness of about 20 Å or less, about 17.5 Å or less, about 15 Å or less, about 12.5 Å or less, about 10 Å or less, or less. The germanium barrier layer can be formed in about 5 seconds or less, about 4 seconds or less, about 3 seconds or less, about 2 seconds or less, about 1 second or less, or less. In embodiments, a thinner germanium barrier layer produces less material from which holes, vias, channels, etc. can be etched in process methods for forming semiconductor devices, such as 3D NAND memory devices. A thinner germanium barrier layer can also be formed in a shorter time, increasing process efficiency. The reduction in etched barrier layer material and formation time is multiplied by the number of barrier layers formed in a stack layer made from multiple sets of germanium-free layers, germanium barrier layers, germanium-containing layers, and optionally additional barrier layers. In some embodiments, the stack layer can include about 50 sets or more of these layers.

[0048]

[0053] In some embodiments, the germanium barrier layer may include silicon oxide, which may be formed by exposing an underlying silicon layer to an oxidizing plasma. In embodiments, the silicon layer may be exposed to the oxidizing plasma for about 5 seconds or less. In further embodiments, the oxidizing plasma may be generated from an oxidizing precursor including oxygen (O) gas. In still further embodiments, the oxidizing precursor may include one or more of ozone (O), water (H2O), and nitrous oxide (N2O). In still further embodiments, the oxidizing precursor may include one or more co-precursors, such as helium or argon, among other co-precursors. The oxidizing precursor may be delivered to a substrate processing region of a substrate processing chamber, where the chamber may be characterized by a pressure of about 5 Torr or greater than about 5 Torr during formation of the barrier layer. The oxidizing plasma may be generated by delivering plasma power to the oxidizing precursor in the substrate processing region of the substrate processing chamber. In some embodiments, the plasma power delivered to the oxidizing precursor can be about or less than 1000 Watts, about or less than 750 Watts, about or less than 500 Watts, about or less than 400 Watts, or about or less than 300 Watts. In further embodiments, during the formation of the germanium barrier layer, the plasma treatment region can be characterized by a temperature of about or less than 500°C, about or less than 450°C, about or less than 425°C, about or less than 400°C, about or less than 375°C, about or less than 350°C, about or less than 325°C, or about or less than 300°C.

[0049]

[0054] In further embodiments, the germanium barrier layer may include silicon nitride, which may be formed by exposing an underlying silicon layer to a nitrogen-containing plasma. In further embodiments, the nitrogen-containing plasma may be oxygen-free. In embodiments, the silicon layer may be exposed to the nitrogen-containing plasma for about 5 seconds or less. In still further embodiments, the nitrogen-containing plasma may be generated from a nitrogen-containing precursor including nitrogen (O) gas. In still further embodiments, the nitrogen-containing precursor may include one or more of a combination of nitrogen (N) and hydrogen (H), and ammonia (NH), among other nitrogen-containing precursors. In still further embodiments, the nitrogen-containing precursor may include one or more co-precursors, such as helium or argon, among other co-precursors. The nitrogen-containing precursor may be delivered to a substrate processing region of a substrate processing chamber, where the chamber may be characterized by a pressure of about 5 Torr or greater than about 5 Torr during the formation of the silicon nitride barrier layer. The nitrogen-containing plasma may be generated by delivering plasma power to the nitrogen-containing precursor in the substrate processing region of the substrate processing chamber. In some embodiments, the plasma power delivered to the nitrogen-containing precursor can be about or less than 1000 Watts, about or less than 750 Watts, about or less than 500 Watts, about or less than 400 Watts, or about or less than 300 Watts. In further embodiments, during the formation of the germanium barrier layer, the plasma treatment region can be characterized by a temperature of about or less than 500°C, about or less than 450°C, about or less than 425°C, about or less than 400°C, about or less than 375°C, about or less than 350°C, about or less than 325°C, or about or less than 300°C.

[0050]

[0055] In some embodiments, the as-deposited germanium barrier layer is germanium-free and reduces or prevents germanium diffusion into the germanium-free layer during processing operations such as furnace annealing or rapid thermal annealing, among other operations that raise the temperature of the substrate to about 500°C or greater. The reduced germanium diffusion maintains etch selectivity between the germanium-free layer and adjacent germanium-containing layers. The high etch selectivity between layers allows for faster and more precise removal of the germanium-containing layer when forming memory cells spaced apart from the germanium-free layer in manufactured memory devices, such as 3D NAND devices. The reduced germanium diffusion in the germanium-free layer also results in fewer germanium-containing crystals forming in these layers. These crystals create defects in the germanium-free layer that can harm device performance, such as reducing the breakdown voltage of memory cells fabricated with the germanium-free layer.

[0051]

[0056] In embodiments of the present technique, the method 400 may further include forming a germanium-containing layer on the germanium barrier layer 416. In some embodiments, the germanium-containing layer may be formed using a deposition plasma formed from a germanium-containing deposition precursor, such as germane (GeH). In further embodiments, the germanium-containing deposition precursor may be silane (SiH), disilane (SiH), and tetrasilane (SiH), among other silicon-containing precursors. 10In these embodiments, the deposited germanium-containing layer may be a silicon germanium (SiGe) layer, and the amount of germanium in the as-deposited silicon germanium layer may be about or greater than about 4 atomic %, about or greater than about 5 atomic %, about or greater than about 10 atomic %, about or greater than about 15 atomic %, about or greater than about 20 atomic %, about or greater than about 25 atomic %, about or greater than about 30 atomic %, about or greater than about 35 atomic %, about or greater than about 40 atomic %, or more. In further embodiments, the germanium-containing precursor may include one or more co-precursors such as hydrogen (H), helium (He), argon (Ar), and nitrogen (N), among other co-precursors.

[0052]

[0057] In some embodiments of the present technology, the method 400 may optionally include forming an additional barrier layer on the germanium-containing layer 421. The additional barrier layer may prevent diffusion of germanium from the germanium-containing layer into an adjacent germanium-free layer. In some embodiments, the additional barrier layer may be formed by exposing the germanium-containing layer to a gas or plasma that reacts with the germanium-containing layer to form the barrier layer. In further embodiments, the additional barrier layer may be formed by exposing the germanium-containing layer to a deposition gas or plasma that deposits the additional barrier layer on the germanium-containing layer. Embodiments may include forming the additional barrier layer made from one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, germanium oxide, germanium nitride, or germanium oxynitride, among other dielectric materials. The additional barrier layer may have a thickness of about or less than about 20 Å, about or less than about 17.5 Å, about or less than about 15 Å, about or less than about 12.5 Å, about or less than about 12.5 Å, about or less than about 10 Å, or less. The additional barrier layer may be formed in about or less than about 5 seconds, about or less than about 4 seconds, about or less than about 3 seconds, about or less than about 2 seconds, or about or less than about 1 second, or less.

[0053]

[0058] In some embodiments, method 400 can include two or more cycles of forming a germanium-free layer, a germanium barrier layer, a germanium-containing layer, and optionally an additional barrier layer to create a layer stack on a substrate. In further embodiments, method 400 can include about or more than 50 cycles, about or more than 100 cycles, about or more than 150 cycles, about or more than 200 cycles, about or more than 250 cycles, or about or more than 300 cycles to create a layer stack on a substrate. In further embodiments, the germanium-free layer can be a silicon layer, the germanium barrier layer and the additional layer can be silicon oxide layers, and the germanium-containing layer can be a silicon germanium layer. In these embodiments, the layer stack can be created from two or more pairs of silicon / silicon germanium layers. For example, the layer stack can be created from about or more than 50 pairs of silicon / silicon germanium layers.

[0054]

[0059] In embodiments of the present technique, method 400 may also include annealing the substrate having at least one pair of germanium-free and germanium-containing layers with a germanium barrier layer positioned between layers 426. In some embodiments, the anneal may be characterized as a rapid thermal anneal. In further embodiments, the anneal may be characterized as a furnace anneal. In embodiments, the annealing temperature may be about or greater than 800°C, about or greater than 850°C, about or greater than 900°C, about or greater than 950°C, about or greater than 1000°C, about or greater than 1050°C, or greater than 1050°C. In furnace annealing embodiments, the annealing time may be about or greater than 30 minutes, about or greater than 1 hour, about or greater than 2 hours, or greater than 2 hours. In rapid thermal annealing embodiments, the annealing time can be about 10 minutes or less, about 5 minutes or less, about 1 minute or less, about 30 seconds or less, or less.

[0055]

[0060] In some embodiments, the annealing operation may be performed on a substrate having a stack of two or more pairs of germanium-free and germanium-containing layers, a germanium barrier layer positioned between the layers, and, optionally, an additional barrier layer formed on the germanium-containing layer. In further embodiments, the stack of layers may include two or more pairs of silicon and silicon-germanium layers, where the silicon layer may be a germanium-free layer and the silicon-germanium layer may be a germanium-containing layer. In these embodiments, a thin dielectric layer, such as a silicon oxide layer, may act as the germanium barrier layer between the silicon and silicon-germanium layers and as the additional barrier layer formed on the germanium-containing layer.

[0056]

[0061] In embodiments, the dielectric barrier layer in the stack layer may slow or prevent the diffusion of germanium from the silicon germanium layer into the silicon layer. For example, after an annealing operation, at least one silicon layer in the stack layer may be characterized by a germanium content of about 2 atomic % or less, about 1 atomic % or less, about 0.5 atomic % or less, about 0.1 atomic % or less, or less. The low level of germanium in the annealed silicon layer of the stack layer reduces the amount of germanium crystallization in the silicon layer. In some embodiments, the annealed silicon layer in the stack layer may be characterized by a weight of germanium-containing crystals of about 1 weight % or less, about 0.5 weight % or less, about 0.1 weight % or less, about 0.05 weight % or less, or less. The dielectric barrier layer may reduce or eliminate germanium-containing crystals in the annealed silicon layer or layer stack, but does not prevent the formation of silicon crystals in the silicon layer. In some embodiments, the silicon layers in the annealed stack of layers may be characterized by a high level of silicon crystallization compared to the as-deposited amorphous silicon layer. In embodiments, one or more of the annealed silicon layers may be characterized as a polysilicon layer or a crystalline silicon layer.

[0057]

[0062] It should also be understood that the dielectric barrier layer does not prevent the formation of germanium-containing crystals in the annealed germanium-containing layer. In embodiments where the layered stack includes a pair of a silicon layer and a silicon germanium layer, the germanium crystals in the germanium-containing layer do not substantially reduce etch selectivity relative to the silicon layer, and in some embodiments may even increase etch selectivity. In embodiments, the etch rate ratio of the silicon germanium layer to the silicon layer may be about 10:1 or greater, about 20:1 or greater, about 30:1 or greater, about 40:1 or greater, about 50:1 or greater, or even greater. The dielectric barrier layer also maintains high etch selectivity of the silicon germanium layer relative to the silicon layer by reducing the amount of germanium in the silicon layer after annealing. Increasing the difference in germanium levels between the silicon layer and the silicon germanium layer may also increase the etch rate ratio of the silicon germanium layer to the silicon layer.

[0058]

[0063] In embodiments, the high etch selectivity of the germanium-containing layer relative to the germanium-free layer allows for faster and more precise formation of isolated germanium-free layers following an etching operation. For example, in the fabrication of 3D NAND devices, the higher etch selectivity of the silicon-germanium layer relative to the silicon layer allows for faster and more precise removal of the silicon-germanium layer, leaving isolated silicon layers for forming memory cells. In some embodiments, the spaces left by the removed silicon-germanium layer can be replaced with a conductive material, such as tungsten, to form word lines in the 3D NAND memory device.

[0059]

[0064] 5A-C illustrate cross-sectional views of exemplary semiconductor structures that may be fabricated using processing methods according to some embodiments of the present technique. FIG. 5A illustrates one embodiment of a structure 500 including a germanium-containing layer 502 adjacent to a germanium barrier layer 504, which is adjacent to a germanium-free layer 506. In the illustrated embodiment, the germanium-free layer 506 is also adjacent to an optional sacrificial layer 508 and a semiconductor layer 510 formed on a substrate layer 512. In some embodiments, the germanium barrier layer 504 may be characterized by a thickness of about 20 Å or less. In further embodiments, the germanium-containing layer 502 may be characterized by a thickness of about 20 nm or greater than about 20 nm, and the germanium-free layer 506 may be characterized by a thickness of about 20 nm or greater than about 20 nm. In further embodiments, the thickness ratio of at least one of the germanium-containing layer 502 or the germanium-free layer 506 to the germanium barrier layer 504 may be about 10:1 or greater than about 10:1. The large difference in thickness between the germanium-containing / germanium-free layers 502, 506 and the germanium barrier layer 504 reflects the effectiveness of the barrier layer 504 in reducing or stopping the diffusion of germanium from the germanium-containing layer 502 to the germanium-free layer 506. In embodiments, an effective germanium barrier layer 504 may be characterized by a reduction in the amount of germanium in the germanium-free layer 506 after annealing of at or greater than about 50 atomic %, at or greater than about 75 atomic %, at or greater than about 90 atomic %, or more, compared to a germanium-containing / germanium-free layer pair lacking the germanium barrier layer.

[0060]

[0065] In some embodiments, the germanium-containing layer 502 may be a silicon germanium layer (SiGe layer) and the germanium-free layer 506 may be a silicon layer (Si layer). In embodiments, the germanium-containing layer 502 may be characterized as having an amount of germanium of about or greater than about 5% by weight, about or greater than about 10% by weight, about or greater than about 15% by weight, about or greater than about 20% by weight, about or greater than about 25% by weight, about or greater than about 30% by weight, about or greater than about 35% by weight, about or greater than about 40% by weight, or more. In some embodiments, after the annealing operation, for example, the germanium-free layer 506 may be characterized as containing about or less than 1.0 wt.% germanium, about or less than 0.5 wt.% germanium, about or less than 0.3 wt.% germanium, about or less than 0.1 wt.% germanium, about or less than 0.07 wt.% germanium, about or less than 0.05 wt.% germanium, about or less than 0.03 wt.% germanium, about or less than 0.01 wt.% germanium, or less, and in some embodiments the layer may be substantially or essentially free of germanium. In embodiments, the germanium-containing layer 502 may be an annealed layer comprising germanium crystals. In further embodiments, the germanium-free silicon layer 506 may include one or more of amorphous silicon, polysilicon, and crystalline silicon.

[0061]

[0066] In further embodiments, germanium barrier layer 504 may be a dielectric layer made from one or more of silicon oxide, silicon nitride, silicon oxynitride, germanium oxide, germanium nitride, and germanium oxynitride. In further embodiments, optional sacrificial layer 508 may be made from a material that can be more easily selectively removed than adjacent layers (e.g., germanium-free layer 506 and semiconductor layer 510). In still further embodiments, semiconductor layer 510 may be made from polysilicon, and substrate layer 512 may be made from one or more of silicon, silicon oxide, silicon nitride, strained silicon, silicon-on-insulator, carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, and sapphire.

[0062]

[0067] 5B illustrates one embodiment of the structure 500 having an additional barrier layer 514 formed on the germanium-containing layer 502. In an embodiment, the additional barrier layer 514 may function to reduce or prevent diffusion of germanium from the germanium-containing layer 502 to an additional germanium-free layer (not shown) formed on the germanium-containing layer 502. In an embodiment, the additional barrier layer 514 may be formed or deposited on the germanium-containing layer and may have a thickness of about 20 Å or less than about 20 Å. In further embodiments, the additional barrier layer may be made of one or more materials such as silicon oxide, silicon nitride, silicon oxynitride, germanium oxide, germanium nitride, and germanium oxynitride.

[0063]

[0068] 5C illustrates one embodiment of a layer stack 550 including layer pairs 552a-b of germanium-containing layers 502a-b and germanium-free layers 506a-b separated by germanium barrier layers 504a-b. In the illustrated embodiment, the layer stack 550 also includes additional barrier layers 514a-b separating the germanium-containing layers 502a-b of adjacent layer pairs 552a-b from the germanium-free layers 506a-b. In embodiments of the present technology, additional layer pairs (not shown) may be formed on the layer pairs 552a-b. In some embodiments, the layer stack may include about 50 or more layer pairs.

[0064]

[0069] Embodiments of the present technology, illustrated in the device structures of Figures 5A-C, can be used to form various semiconductor devices, such as 3D NAND memory devices. The germanium barrier layer between the germanium-free layer and the germanium-containing layer allows the layers to be annealed without significant germanium diffusion into the germanium-free layer, which could reduce etch selectivity for the removal of the germanium-containing layer during subsequent operations in device fabrication. Reduced germanium diffusion also prevents significant formation of germanium-containing crystals in the germanium-free layer, which could impair device performance. Additionally, the thin germanium barrier layer relative to the germanium-free and germanium-containing layers allows for faster and more precise etching of vertical holes and channels through the layers, since there is less material to etch. For layer stacks containing about 50 or more layer pairs, the cumulative reduction in material allows for substantially faster and more precise vertical etching through the layer stack.

[0065]

[0070] Although the above description, for purposes of explanation, sets forth numerous details in order to provide an understanding of various embodiments of the present technology, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0066]

[0071] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents may be used without departing from the essence of the embodiments. In addition, some well-known processes and elements have not been described to avoid unnecessarily obscuring the technology. Therefore, the above description should not be construed as limiting the scope of the technology.

[0067]

[0072] Where a range of values ​​is provided, each intervening value between the upper and lower limit of that range is also understood to be specifically disclosed, to the smallest unit of the lower limit (unless the context clearly dictates otherwise). Narrower ranges between any stated or unstated intervening values ​​in a stated range, and any other stated or intervening value in that stated range, are encompassed. The upper and lower limits of any such narrower range may independently be included in or excluded from the range. Each range where either, neither, or both limits are included in the narrower range is also encompassed within the technology, provided that there may be specifically excluded limits within the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0068]

[0073] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include the plural (unless the context clearly dictates otherwise). Thus, for example, a reference to "a precursor" includes a plurality of such precursors, a reference to "the layer" includes a reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0069]

[0074] Furthermore, the words "comprise(s) / comprising", "contain(s) / containing", and "include(s) / including", when used in this specification and the following claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, acts, or groups.

Claims

1. 1. A semiconductor processing method comprising: forming a semiconductor layer stack from a silicon / silicon germanium layer pair, the silicon / silicon germanium layer pair comprising: forming a silicon layer; forming a germanium barrier layer on the silicon layer to a thickness of 20 Å or less, the germanium barrier layer comprising O ２ forming a germanium barrier layer comprising a silicon oxide layer formed by exposing the silicon layer to an oxidation plasma generated from an oxidation precursor comprising: forming a silicon germanium layer on the germanium barrier layer; A semiconductor processing method comprising:

2. 1. A semiconductor processing method comprising: forming a semiconductor layer; forming a sacrificial layer on the semiconductor layer; and forming a semiconductor layer stack from a silicon / silicon germanium layer pair on the sacrificial layer, the silicon / silicon germanium layer pair comprising: forming a silicon layer; forming a germanium barrier layer on the silicon layer to a thickness of 20 Å or less; and forming a silicon germanium layer on the germanium barrier layer; A semiconductor processing method comprising:

3. 3. The semiconductor processing method of claim 2, wherein the germanium barrier layer comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, germanium oxide, germanium nitride, or germanium oxynitride.

4. 3. The semiconductor processing method of claim 1 or 2, wherein the silicon layer is exposed to an oxidizing plasma for 5 seconds or less.

5. 3. The semiconductor processing method of claim 1, wherein the silicon germanium layer comprises 5 atomic percent or more of germanium.

6. 3. The semiconductor processing method of claim 1, further comprising forming a second germanium barrier layer on said silicon germanium layer, said second germanium barrier layer being 20 Å or less in thickness.

7. The semiconductor processing method of claim 1 or 2, further comprising annealing the semiconductor layer stack at a temperature of 800°C or higher.

8. The semiconductor processing method of claim 1 or 2, further comprising subjecting the semiconductor layer stack to a rapid thermal anneal at a temperature of 1000°C or greater.

9. 3. The semiconductor processing method of claim 1 or 2, wherein the semiconductor layer stack comprises 50 or more pairs of the silicon / silicon germanium layers.

10. 1. A semiconductor processing method comprising: forming a silicon layer on a substrate; O ２ exposing the silicon layer to an oxidizing plasma generated from an oxidizing precursor comprising: depositing a silicon germanium layer on the silicon oxide layer; annealing the substrate including the silicon germanium layer at a temperature of 800° C. or greater; A semiconductor processing method comprising:

11. 1. A semiconductor processing method comprising: forming a semiconductor layer on a substrate; forming a sacrificial layer on the semiconductor layer; forming a silicon layer on the sacrificial layer; O ２ exposing the silicon layer to an oxidizing plasma generated from an oxidizing precursor comprising: depositing a silicon germanium layer on the silicon oxide layer; annealing the substrate including the silicon germanium layer at a temperature of 800° C. or greater; A semiconductor processing method comprising:

12. 12. The semiconductor processing method of claim 10 or 11, wherein the oxidizing precursor further comprises argon.

13. 12. The semiconductor processing method of claim 10 or 11, wherein plasma power is delivered to the oxidizing precursor to generate the oxidizing plasma, and the plasma power delivered to the oxidizing precursor is 500 watts or less.

14. 12. The semiconductor processing method of claim 10 or 11, wherein the oxidizing plasma is generated in a substrate processing chamber holding the substrate, the substrate processing chamber being characterized by a pressure of 5 Torr or greater during generation of the oxidizing plasma.

15. 12. The semiconductor processing method of claim 10 or 11, wherein the silicon oxide layer is characterized by a thickness of 20 Å or less.

16. 1. A semiconductor structure comprising: a silicon germanium layer; a silicon layer containing 0.1 wt % or less germanium; a germanium barrier layer characterized by a thickness of 20 Å or less and being silicon oxide, silicon oxynitride, germanium oxide, germanium nitride, or germanium oxynitride; wherein the germanium barrier layer is in direct contact with and positioned between the silicon layer and the silicon germanium layer.

17. 1. A semiconductor structure comprising: a semiconductor layer; A sacrificial layer; a silicon germanium layer; a silicon layer containing 0.1 wt % or less germanium; a germanium barrier layer characterized by a thickness of 20 Å or less; the germanium barrier layer is in direct contact with and positioned between the silicon layer and the silicon germanium layer, and the silicon layer, the silicon germanium layer, and the germanium barrier layer are positioned on the sacrificial layer on the semiconductor layer.

18. 18. The semiconductor structure of claim 16 or 17 wherein said 0.1 wt. % or less germanium in said silicon layer comprises crystalline germanium.

19. 18. The semiconductor structure of claim 16 or 17, wherein said structure further comprises a second germanium barrier layer in contact with said silicon germanium layer, said second germanium barrier layer being 20 Å or less in thickness.

20. 18. The semiconductor structure of claim 16 or 17, wherein at least one of said silicon germanium layer and said silicon layer is characterized by a thickness of 20 nm or greater.

21. 20. The semiconductor structure of claim 17 wherein said germanium barrier layer comprises silicon oxide.

22. 18. The semiconductor structure of claim 16 or 17 wherein said silicon germanium layer is characterized by 5 atomic % or greater germanium.

23. 18. The semiconductor structure of claim 16 or 17 wherein said silicon layer comprises crystallized silicon.

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