Error correction hardware with defect detection

Abstract

Reduced ECC logic requirements and semiconductor chip area savings in lockstep ECC circuit hardware. [Solution] The ECC memory circuit 400 includes a write GEN ECC logic 115b and a check ECC block 120b coupled to the ECC output of the memory circuit 130. A first MUX 115a receives write data and is in series with the input to the write GEN ECC logic, and a second MUX 120e receives read data from the memory circuit 130 in series with the input to the read GEN ECC logic. Cross-coupling connectors 150, 150' couple the read data from the memory circuit to the second input of the first MUX or couple the write data to the second input of the second MUX. An ECC bit comparator 135 compares the output of the write GEN ECC logic 120b1 with the read GEN ECC logic output.

Description

[Technical Field]

[0001] The present invention relates generally to error correcting codes (ECC), and more particularly to hardware for defect detection in ECC logic circuitry. [Background technology]

[0002] Error correcting code (ECC) memory is a type of computer data storage that can detect and correct most conventional types of internal data corruption. ECC memory circuits can be used in computers where data corruption is generally unacceptable, such as for automotive memory for safety-critical advanced driver assistance systems (ADAS) that must comply with scientific or functional safety requirements.

[0003] Implementing ECC in memory (e.g., static random access memory (SRAM), read-only memory (ROM), or flash memory) is a standard safety mechanism used in safety-critical applications to ensure data integrity within the memory. Traditionally, ECC redundancy bits (e.g., Hamming code) are added to the memory data contents by write path ECC logic circuitry and written together in the same cycle to provide a check on the data stored in the memory when the memory is read by read path ECC logic circuitry. ECC as used herein generally refers to single-bit error correction for single-bit errors and multi-bit error detection for multi-bit errors (e.g., double-bit errors) using Hamming code redundancy bits.

[0004] Conventionally, generate ECC hardware units are provided in the write path and in the read path, with a generate ECC unit in the write path and a check ECC block containing another generate ECC unit in the read path. The write path circuitry and the read path circuitry have no cross-coupled connections and therefore operate independently of each other. During a memory read operation, the ECC is recalculated by the check ECC block, and the ECC is compared to the stored ECC by an XOR circuit. The result (output) of this XOR circuit is called the syndrome. If the syndrome is zero, no error has occurred. If the syndrome is non-zero, it can be used to index a "syndrome decode" table to determine which bit is in error in the case of single-bit error correction (SEC), or the error is uncorrectable in the case of double-bit error detection (DED). Thus, conventional ECC memory can generally keep a memory system virtually free of most bit errors. Summary of the Invention

[0005] In a described example, lockstep ECC circuit hardware includes error correction circuitry that uses cross-coupled connections between write path circuitry and read path circuitry, allowing reuse of ECC generation logic on one side of a memory circuit to check errors on the other side, thereby reducing ECC logic requirements and saving significant semiconductor chip area. The described example includes a method of defect detection for ECC circuitry for a memory circuit having write generation (Gen) ECC logic in the write path circuitry and check ECC logic in the read path circuitry, including read Gen ECC logic. The outputs of the read Gen ECC logic and the write Gen ECC logic are operated on by digital comparators to check whether the respective bit strings match. When the bit strings do not match, a defect in the write Gen ECC logic or the read Gen ECC logic is detected. In the event of a lockstep error (mismatch in the comparator outputs) during a write operation, the write operation can be repeated. In the event of a lockstep error during a read operation, a single-bit error can be corrected and a multi-bit error interrupt signal can be sent. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a block diagram of an example ECC memory circuit with the described lockstep ECC circuit hardware for defect detection in read-side ECC logic having a multiplexer with a first input for receiving write data in series with an input to ECC generation logic, where write data is selected during normal write operations and read data is selected during read operations, according to one example embodiment.

[0007] [Figure 2]FIG. 10 is a block diagram of another example ECC memory circuit having the described lockstep ECC circuit hardware for defect detection in write-side ECC logic having a multiplexer with a first input for receiving read data from the memory circuit in series with an input of Gen ECC logic for defect detection in the ECC logic, in accordance with one example embodiment.

[0008] [Figure 3] 4 is a flowchart illustrating steps in an exemplary method of defect detection for ECC circuitry, in accordance with one exemplary embodiment.

[0009] [Figure 4] 1 is an exemplary ECC memory circuit including the described ECC hardware for defect detection in its read and write paths, essentially combining the read-side and write-side error checking embodiments described above in connection with FIGS. 1 and 2, according to one exemplary embodiment.

[0010] [Figure 5] FIG. 5 is a system diagram of an example ADAS system including two instances of the illustrated ECC memory circuit shown in FIG. 4 as a processor memory with the illustrated lockstep ECC circuit hardware for defect detection in the ECC logic in its read and write paths, according to one example embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] The drawings are not necessarily drawn to scale. In the drawings, like reference numerals indicate like or equivalent elements. Some illustrated acts or events may occur in different orders and / or concurrently with other acts or events. Also, some illustrated acts or events are optional for implementing a methodology according to an illustrative embodiment.

[0012] As used herein without further limitation, the terms "coupled to" or "coupled with" (and the like) describe an indirect or direct electrical connection. Thus, when a first device "couples" to a second device, the connection may be through a direct electrical connection with only parasitics in the path, or through an indirect electrical connection through intermediaries, including other devices and connections. In the case of an indirect coupling, the intermediaries generally do not alter the information in the signal, but may adjust its current level, voltage level, and / or power level.

[0013] A transient or permanent error may exist in the ECC logic hardware of an ECC memory circuit on the write side, which may result in incorrect ECC bits being written to memory during a write operation. A transient or permanent error in the ECC logic hardware on the read side of an ECC memory circuit may result in corruption of memory read data, or may result in the memory read data being erroneously flagged as corrupted when in fact it is not corrupted. Detection of transient / permanent errors in the ECC logic of an ECC memory circuit may be possible if the write path circuitry and the read path circuitry operate independently, but implementing such detection may require significant additional logic, including extra ECC generation logic on both sides of the ECC memory circuit.

[0014] 1 shows an ECC memory circuit 100 including a memory circuit 130 (e.g., an SRAM, ROM, or flash memory chip) and the described "lockstep" ECC hardware 110 with defect detection in its ECC logic circuitry configured to verify the bit output of read path Gen ECC 120b1 in read path circuitry 120. Memory circuit 130 includes a single-port memory, in which only one operation (read or write) can be performed for a given clock pulse. This single-port memory feature allows the bit output from one side of the ECC GEN logic (the side that is not active at a particular time / clock, write inactive as shown in FIG. 1 and read inactive as shown in FIG. 2) to be used as a reference to enable the described lockstep error detection.

[0015] The memory circuit 130 includes a common substrate 105 having at least a semiconductor surface. For example, the substrate 105 may include a bulk silicon substrate or an epitaxial layer on a bulk silicon substrate.

[0016] The memory circuit 130 has a separate data output and a separate ECC output. Data, designated as k bits, is stored with ECC bits, designated as r bits. For example, if a non-ECC memory stores 64 bits of data, an ECC memory can store the same 64 bits of data with 8 extra bits of ECC. Thus, 64+8 bits are written and 64+8 bits are read. The 8 ECC bits are used to validate the 64 data bits and go to an XOR logic in the check ECC.

[0017] Write path circuitry 115 includes write generate (Gen) ECC logic 115b, and check ECC logic 120b includes read Gen ECC logic 120b1 in read path circuitry 120. While operating in write mode (the write mode is active in FIG. 2 described below), data bits (e.g., 64 bits, shown as WR Data) and corresponding computed ECC bits (e.g., 8 bits) from write ECCGen logic 115b are each written to memory circuit 100 in the same clock cycle. In FIGS. 1 and 2, the data width for memory circuit 130 may be 72 bits (72-bit wide memory) including 64 bits (data) + 8 bits (ECC) in one example, which may be implemented as two separate memories, one 64 bits wide and one 8 bits wide, or may be a single 72-bit wide memory.

[0018] As mentioned above, 64 information / data bits and 8 ECC bits are just examples. The actual number of ECC bits may be based on the corresponding bit width for the data (information), such as that given in the example below. TIFF0007769181000001.tif55105

[0019] A multiplexer (Mux) 115a is provided at the input of write GEN ECC logic 115b for multiplexing in cross-coupled read data provided by cross-coupled connection 150, generally shown as k bits, from memory circuit 130 with write (wr) data from a processor. The processor may include a microprocessor, digital signal processor (DSP), or microcontroller unit (MCU). MUX 115a is shown with a select line indicated based on whether memory circuit 130 is in read mode from the processor, which is used to select between input lines containing rd data from memory on one line and wr data on the other line to send to the output of Mux 115a. When in read mode, rd data is selected by MUX 115a, and when in write mode, wr data is selected.

[0020] Digital comparator 135 is coupled to receive at one input the output from write Gen ECC logic 115b (as a reference, inactive during reads) and at its other output the output of read path Gen ECC 120b1. Digital comparator 135 therefore reuses the output from write Gen ECC logic 115b to verify the bit output of read path Gen ECC 120b1, both of which are shown as 8 bits by way of example only. Read Gen ECC 120b1, along with XOR circuit 120b2, comprise check ECC block 120b. The output of XOR circuit 120b2 provides a "syndrome" signal to syndrome decode block 120c. If the syndrome is zero, no error has occurred. If the syndrome is non-zero, syndrome decode block 120c determines which bit is in error (SEC) or that the error is uncorrectable (e.g., the error is a double-bit error). The single bit error is provided to SEC block 120d, which outputs corrected read data, denoted as rd data.

[0021] In ECC hardware 110, the output of digital comparator 135 is connected as enable to multi-bit (two or more) error interrupt generation and as enable to SEC block 120d. Therefore, the SEC of memory read data by SEC block 120d and the multi-bit error flag using the syndrome calculation provided by syndrome decode 120c are both enabled by the enable signal from digital comparator 135 if and only if the ECC calculation in the write path and the ECC calculation in the read path match each other (shown as the same r bit in FIG. 1). If the ECC calculation in the write path and the ECC calculation in the read path do not match each other, there is a lockstep error during the read operation, and a single-bit error can be corrected, and in the case of a multi-bit error, such as a double-bit error, a bit error interrupt (disable) signal can be sent.

[0022] 2 shows an example ECC memory circuit 200 including the described ECC hardware 110′ for defect detection in its write path, including write Gen ECC logic 115b. Here, a MUX 120e is added in read path circuitry 120′, and a cross-couple connection 150′ is added from write path circuitry 115′ to MUX 120e in read path circuitry 120′ for multiplexing with write data read from memory circuit 130. Here, the described lockstep ECC hardware 110 with defect detection in its ECC logic circuitry is configured to verify the bit output of write Gen ECC logic 115b while a write mode is active. A control input labeled “memory write” is a control signal that controls the input select node of MUX 120e. When in write mode, wr data is selected by MUX 120e, and when in read mode, rd data is selected.

[0023] The ECC bit output by read Gen ECC logic 120b1 is used by digital comparator 135 to verify the operation of write Gen ECC logic 115b, which compares the ECC bits generated by each of Gen ECC logic 115b and 120b1. The generated output of digital comparator 135 is used as an interrupt to a processor (e.g., a microprocessor, digital signal processor (DSP), or microcontroller unit (MCU)) to repeat the write process. If an error is flagged by digital comparator 135 during a write operation, the write operation can be repeated to ensure that the data written to memory circuit 130 is not erroneous. If the error is a transient defect, repeating the write can generally fix the hardware error problem. In the case of a permanent defect, digital comparator 135 continues to generate an error again, in which case the processor can take appropriate action, such as indicating to application software that a permanent defect has occurred in the system. This same defect response applies to read operations.

[0024] 3 is a flowchart illustrating steps in an example method 300 of defect detection for ECC circuitry associated with a single-port memory circuit, according to one illustrative embodiment. Step 301 includes comparing the output of the Read Gen ECC logic (120b1 in FIGS. 1 and 2) with the output of the Write Gen ECC logic (115b in FIGS. 1 and 2). Step 302 includes detecting a defect in the Write Gen ECC logic or in the Read Gen ECC logic if the comparison output from this comparison determines that the value of the output of the Write Gen ECC logic is not equal to the value of the output of the Read Gen ECC logic 120b1.

[0025] Step 303 includes correcting the single-bit error if the defect is a single-bit error during a read operation, and sending a multi-bit error interrupt signal if the defect is a multi-bit error during a read operation. When the defect is an error during a write operation, the write is repeated. As described above for the memory circuit 100 of FIG. 1 implementing read-side defect detection, the single-bit error is provided to SEC block 120d, which outputs corrected read data, shown as rd data. As described above for the memory circuit 200 of FIG. 2 implementing write-side defect detection, the write operation can be repeated to ensure that the data written to the memory chip is not erroneous.

[0026] The embodiments described above in connection with Figures 1 (write-side error checking) and 2 (read-side error checking) may be implemented independently (one without the other) to detect errors on one side of memory circuit 130. Alternatively, the read-side and write-side error checking embodiments described above in connection with Figures 1 and 2 may be combined together to enable error checking on both sides of memory circuit 130.

[0027] FIG. 4 is an example ECC memory circuit 400 including the described ECC hardware 110'' for defect detection in both its read and write paths, essentially combining the read-side and write-side error checking embodiments described above in connection with FIGS. 1 and 2. In addition to MUX 115a, ECC memory circuit 400 includes a second MUX 120e having a first input for receiving read data from an input of memory circuit 400, in series with Read Gen ECC logic 120b1, and a cross-coupled connection 150' for coupling write data to a second input of second MUX 120e. Here, digital comparator 135 is involved in both read-side and write-side error checking.

[0028] In contrast to the ECC memory circuits described herein, conventional ECC logic is used only to detect and correct internal memory (e.g., RAM) errors. In an ECC memory circuit with the ECC logic described herein, in addition to detecting and correcting internal memory errors, defect detection in the ECC logic is achieved, where any temporary or permanent errors in the ECC calculation and generation logic are also detected, allowing corrective action to be taken. As described above, in the case of a lockstep error in Read Gen ECC 120b1 (see FIG. 1), this single-bit error can be corrected and a multi-bit error interrupt signal can be generated. In the case of an error in Write Gen ECC logic 115b (see FIG. 2), the lockstep logic repeats the write operation. Additionally, the described lockstep ECC circuit hardware is non-intrusive and can operate continuously (on the fly, every clock cycle) to check the memory ECC logic, with only the penalty of limited area for additional Muxes and comparators.

[0029] The described embodiments are further illustrated in the following example. FIG. 5 is a system diagram of an example ADAS system 500 including two instances of the described ECC memory circuit shown in FIG. 4, shown as 4001 and 4002, including processor memories 1301 (shown as Processor Memory 1) and 1302 (shown as Processor Memory N). The ECC memory circuit has the described lockstep ECC circuit hardware, shown as ECC logic 1101 and 1102, for defect detection in the processor memory read and write paths. An image sensor 505 (e.g., a CMOS color camera) generates image data from a scene (e.g., from a rear view from a vehicle). The image data is coupled to an image recognition system 515 by a camera interface 510. The image recognition system 515 is shown to include a video recognition processor 515a, a flash memory 515b, an external DDR memory 515c, and a controller area network (CAN) bus Tx / Rx (transceiver) 515d.

[0030] Image recognition system 515 is coupled by CAN bus 520 to processor block 530, which includes processor core 530a. Processor core 530a is shown coupled by bus interface 535 to use processor memories 1301 and 1302 of ECC memory circuits 4001 and 4002. As noted above, during operation of ADAS system 500, ECC memory circuits 4001 and 4002 use the described lockstep ECC circuit hardware with cross-coupled connections between write path and read path circuitry, which allows the reuse of ECC generation logic to check errors on one side of processor memory and the other, which reduces ECC logic requirements and saves significant semiconductor chip area.

[0031] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the claims of the invention.

Claims

1. 1. A method comprising: comparing an output of read-generated error correction code (ECC) logic in read path circuitry for a memory circuit with an output of write-generated ECC logic in write path circuitry for said memory circuit; detecting a defect in the write generated ECC logic or in the read generated ECC logic when an output of the write generated ECC logic is not equal to an output of the read generated ECC logic based on the comparing; When the defect is an error during a write operation, determining a temporary or permanent error in the read or write generated ECC logic by repeatedly providing write data to the read and write generated ECC logic and comparing the output of the read and write generated ECC logic; Including, The method, wherein the temporary error is determined based on defects that are not detected again during the repeating, and the permanent error is determined based on defects that are detected again during the repeating.

2. 10. The method of claim 1, The method, wherein the comparing and detecting are performed continuously every clock cycle.

3. 10. The method of claim 1, The method, wherein the memory circuit comprises a static random access memory (SRAM), a read-only memory (ROM), or a flash memory.

4. 10. The method of claim 1, The method, wherein the memory circuit is a memory for a processor of an advanced driver assistance system (ADAS).

5. 10. The method of claim 1, The method, wherein the multi-bit error comprises a difference of at least two bits between the output of the read generate ECC logic and the output of the write generate ECC logic.

6. 10. The method of claim 1, The method further includes providing read data from the memory circuit to the read generation ECC logic and the write generation ECC logic.

7. 1. An apparatus comprising: circuitry that compares the output of write-generated error correction code (ECC) logic in write path circuitry of the memory circuit with the output of read-generated ECC logic in read path circuitry of said memory circuit; circuitry for detecting a defect in the write generated ECC logic or the read generated ECC logic when a comparison output from the comparing circuitry determines that the value of the output of the write generated ECC logic is not equal to the value of the output of the read generated ECC logic; circuitry for determining a temporary or permanent error in the read or write generated ECC logic by repeatedly providing write data to the read and write generated ECC logic when the defect is an error during a write operation and comparing the output of the read and write generated ECC logic with the output of the write generated ECC logic; Including, The apparatus wherein the temporary error is determined based on defects that are not detected again during the repeating, and the permanent error is determined based on defects that are detected again during the repeating.

8. 8. The apparatus of claim 7, the read path circuitry includes an XOR circuit having a first input coupled to an output of the read generation ECC logic, a second input coupled to an ECC output of the memory circuit, and an output providing a syndrome output to a syndrome decode block; the syndrome decode block is coupled to a single-bit error correction (SEC) block and to multi-bit error generation circuitry; The device, a circuit element that provides the comparison output as an enable input to a multi-bit error detection (MED) circuit element, and that provides the comparison output as an enable input to the SEC block; The apparatus further comprises:

9. 8. The apparatus of claim 7, The apparatus, wherein the comparing and detecting are performed continuously every clock cycle.

10. 8. The apparatus of claim 7, The apparatus, wherein the memory circuit is a static random access memory (SRAM), a read-only memory (ROM), or a flash memory.

11. 8. The apparatus of claim 7, The apparatus, wherein the memory circuit is memory for a processor of an advanced driver assistance system (ADAS).

12. 8. The apparatus of claim 7, The apparatus, wherein the comparing circuitry is a digital comparator.

13. 8. The apparatus of claim 7, The apparatus further includes circuitry that provides read data from the memory circuit to the read generation ECC logic and the write generation ECC logic.

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