Field effect transistor with repair access region - Patent Application 20070122997

Abstract

The transistor device comprises a semiconductor epitaxial layer structure comprising a channel layer and a barrier layer on the channel layer, the barrier layer having a bandgap larger than that of the channel layer. A repair access region is provided on an upper surface of the barrier layer opposite the channel layer. The repair access region comprises a material having a surface barrier height lower than that of the barrier layer. A source contact and a drain contact are formed on the barrier layer, and a gate contact is formed between the source contact and the drain contact. The repair access region can comprise a plurality of selective repair access regions on an upper surface of the barrier layer opposite the channel layer. The plurality of selective repair access regions are spaced apart along the length of the gate contact on the barrier layer.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. patent application Ser. No. 17 / 325,643, entitled "FIELD EFFECT TRANSITOR WITH SELECTIVE MODIFIED ACCESS REGIONS," filed May 20, 2021, and U.S. patent application Ser. No. 17 / 325,635, entitled "FIELD EFFECT TRANSITORS WITH MODIFIED ACCESS REGIONS," filed May 20, 2021, the disclosures and contents of which are incorporated herein in their entireties.

[0002] The present disclosure relates to transistor structures, and in particular to high electron mobility transistors. [Background technology]

[0003] Narrow bandgap semiconductor materials such as silicon (Si) and gallium arsenide (GaAs) are widely used in semiconductor devices for low-power and, in the case of Si, low-frequency applications. However, these semiconductor materials may be less suitable for high-power and / or high-frequency applications due, for example, to their relatively narrow bandgaps (1.12 eV for Si and 1.42 eV for GaAs at room temperature) and relatively low breakdown voltages.

[0004] Interest in high-power, high-temperature, and / or high-frequency applications and devices has focused on wide-bandgap semiconductor materials, such as silicon carbide (3.2 eV at room temperature for 4H-SiC) and Group III nitrides (e.g., 3.36 eV at room temperature for GaN). These materials can have higher electric field breakdown strengths and higher electron saturation velocities than GaAs and Si.

[0005] A device of particular interest for high-power and / or high-frequency applications is the high electron mobility transistor (HEMT), also known as the modulation doped field effect transistor (MODFET). In a HEMT device, a two-dimensional electron gas (2DEG) can form at the heterojunction of two semiconductor materials with different bandgap energies, where the narrower bandgap material has a higher electron affinity than the wider bandgap material. The 2DEG is an accumulation layer within the undoped narrower bandgap material, e.g., 10 13 Carrier / cm 2 HEMTs can contain a relatively high sheet electron concentration, exceeding 1000 kJ / cm. Furthermore, electrons generated in wider bandgap semiconductors can migrate to the 2DEG, allowing for relatively high electron mobility due to reduced scattering of ionized impurities. This combination of relatively high carrier concentration and carrier mobility allows HEMTs to achieve a relatively large transconductance, potentially outperforming metal-semiconductor field effect transistors (MESFETs) in high-frequency applications.

[0006] HEMTs fabricated in the gallium nitride / aluminum gallium nitride (GaN / AlGaN) material system can generate large RF power due to a combination of material properties such as a relatively large breakdown field, a relatively wide bandgap, a relatively large conduction band offset, and / or a relatively large saturated electron drift velocity. A large proportion of the electrons in the 2DEG can be contributed by polarization in the AlGaN.

[0007] FIG. 1A shows a conventional gallium nitride-based HEMT structure. The structure includes a substrate 10, which may be a semi-insulating 4H silicon carbide (SiC) substrate. Optional buffer, nucleation, and / or transition layers (not shown) may be provided on the substrate 10. A channel layer 20 is provided on the substrate 10. The channel layer 20 may be a III-nitride, such as GaN. A barrier layer 22 is provided on the channel layer 20. The barrier layer 22 may have a bandgap larger than that of the channel layer 20, which may have a larger electron affinity than the barrier layer 22. The barrier layer 22 may be AlN, AlInN, AlGaN, or AlInGaN, and has a sufficient thickness and a sufficiently high Al content and doping to induce a significant carrier concentration at the interface between the channel layer 20 and the barrier layer 22. This induced carrier concentration forms a two-dimensional electron gas (2DEG), which provides a conductive channel within the device. The conductivity of the 2DEG channel can be adjusted by applying a voltage to a gate contact 32 formed on the barrier layer 22 .

[0008] 1A further shows a cap layer 24 on the barrier layer 22, with a gate contact 32 in a recess 36 through the cap layer 24. The cap layer 24 physically distances the top (external) surface of the device from the channel, thereby reducing the device's surface effect. The cap layer 24 may be blanket deposited on the barrier layer 22 and may be formed by epitaxial growth and / or deposition. The cap layer 24 may typically have a thickness of about 2 nm to about 500 nm.

[0009] 1A, ohmic source / drain contacts 30 are provided on the barrier layer 22, and a gate recess is provided through the cap layer 24 to expose a portion of the barrier layer 22. A gate contact 32 is formed in the recess and contacts the exposed portion of the barrier layer 22. The gate contact 32 may be a "T" gate as shown in FIG. 1A.

[0010] A passivation layer (not shown) can also be provided on the structure of Figure 1A. For example, referring to Figure 1B, a SiN layer 52 can be formed in situ on the device surface. The structure of Figure 1B with the passivation layer can be annealed in a nitrogen ambient to improve process parameters.

[0011] Even with the presence of the cap layer 24 and annealing of the structure, conventional HEMT structures can trap charge in the barrier or channel layers of the device, which can cause distortion of signals passing through the device. The trapped charge can, for example, cause output delay, which can undesirably slow the switching speed and therefore bandwidth of the device. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] U.S. Patent No. 6,849,882 [Patent Document 2] U.S. Patent No. 7,230,284 [Patent Document 3] U.S. Patent No. 7,501,669 [Patent Document 4] U.S. Patent No. 7,126,426 [Patent Document 5] U.S. Patent No. 7,550,783 [Patent Document 6] U.S. Patent No. 7,573,078 [Patent Document 7] U.S. Patent Application Publication No. 2005 / 0253167 [Patent Document 8] U.S. Patent Application Publication No. 2006 / 0202272 [Patent Document 9] U.S. Patent Application Publication No. 2008 / 0128752 [Patent Document 10] U.S. Patent Application Publication No. 2010 / 0276698 [Patent Document 11] U.S. Patent Application Publication No. 2012 / 0049973 [Patent Document 12] U.S. Patent Application Publication No. 2012 / 0194276 [Patent Document 13] U.S. Patent No. 9,847,411 Summary of the Invention [Means for solving the problem]

[0013] A transistor device according to some embodiments includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, the barrier layer having a larger bandgap than the channel layer, and a repair access region on an upper surface of the barrier layer opposite the channel layer. The repair access region includes a material having a surface barrier height lower than that of the barrier layer. Source and drain contacts are formed on the barrier layer, and a gate contact is formed between the source and drain contacts.

[0014] The gate contact may form a Schottky contact to the repair access region in some embodiments, while the gate contact may not contact the repair access region in other embodiments.

[0015] The transistor device may further comprise a doped source region in the barrier layer, the source contact contacting the source region, and a doped drain region in the barrier layer, the drain contact contacting the drain region, the source and drain regions defining an active area of ​​the device between the source and drain regions, and a repair access region on the barrier layer spanning the active area of ​​the device.

[0016] The repair access region, in some embodiments, comprises an enhanced electrical conductivity region on an upper surface of the barrier layer opposite the channel layer.

[0017] The repair access region, in some embodiments, comprises an implanted region containing dopants implanted into the top surface of the barrier layer opposite the channel layer.

[0018] The repair access region, in some embodiments, has a thickness of about 0.1 nm to about 40 nm and a width of about 1E14 cm -3 Approximately 1E17cm -3 The repair access region, in some embodiments, has a thickness of about 0.5 nm to about 10 nm.

[0019] The repair access region, in some embodiments, comprises an epitaxial semiconductor layer of a material having a smaller bandgap than the barrier layer. The barrier layer, in some embodiments, comprises AlGaN, and the repair access region comprises AlGaN having a lower Al concentration than the barrier layer. In some embodiments, the barrier layer comprises AlGaN, and the repair access region comprises GaN. The repair access region may be doped with an n-type dopant.

[0020] The repair access region may be provided with a charge ejection path that allows charge carriers present on the upper surface of the barrier layer opposite the channel layer to be conducted toward the drain contact.

[0021] In some embodiments, the repair access region is not located in the region between the source contact and the gate contact. In some embodiments, the repair access region is located in the region between the gate contact and the drain contact, but does not extend all the way from the source contact to the drain contact. The gate contact may not contact the repair access region.

[0022] The transistor device may further comprise a doped drain region in the barrier layer, the drain contact contacting the drain region and the repair access region contacting the drain region.

[0023] A method of forming a transistor device according to some embodiments includes providing a semiconductor epitaxial layer structure comprising a channel layer and a barrier layer on the channel layer, the barrier layer having a larger bandgap than the channel layer, forming a repair access region on an upper surface of the barrier layer opposite the channel layer, forming source and drain contacts on the barrier layer, and forming a gate contact between the source and drain contacts. The repair access region includes a material having a surface barrier height lower than that of the barrier layer.

[0024] Forming the repair access region, in some embodiments, includes forming a sacrificial dielectric layer on the barrier layer, annealing the sacrificial dielectric layer and the barrier layer, and removing the sacrificial dielectric layer. The sacrificial dielectric layer can include SiN, SiOx, AlN, AlO, and / or HfO.

[0025] Forming the repair access region, in some embodiments, includes forming an epitaxial layer on the barrier layer of a material having a smaller bandgap than the barrier layer, and the epitaxial layer may be doped with an n-type dopant.

[0026] Forming the repair access region, in some embodiments, includes implanting an n-type dopant into a top surface of the barrier layer opposite the channel layer.

[0027] The repair access region, in some embodiments, is in the region between the gate and drain contacts, and does not extend all the way between the source and drain contacts.

[0028] The gate contact may not be in contact with the repair access region.

[0029] The method may further include forming a doped drain region in the barrier layer, the drain contact contacting the drain region, and the modification access region contacting the drain region.

[0030] A transistor device according to a further embodiment includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, the barrier layer having a larger bandgap than the channel layer, source and drain contacts on the barrier layer, and a gate contact on the barrier layer between the source and drain contacts. The device further includes a plurality of selective repair access regions on an upper surface of the barrier layer opposite the channel layer. The selective repair access regions include a material having a surface barrier height lower than that of the barrier layer, and the plurality of selective repair access regions are spaced apart on the barrier layer along the length of the gate contact.

[0031] The transistor device may further comprise a doped drain region in the barrier layer, the drain contact contacting the drain region, and the selective modification access region on the barrier layer between the gate contact and the drain contact.

[0032] The selective repair access region, in some embodiments, comprises an enhanced conductivity region on an upper surface of the barrier layer opposite the channel layer. The selective repair access region can comprise an implanted region, the implanted region including a dopant implanted in the upper surface of the barrier layer opposite the channel layer.

[0033] The selective repair access region, in some embodiments, has a thickness of about 0.1 nm to about 40 nm and a width of about 1E14 cm -3 Approximately 1E17cm -3 and a doping concentration of

[0034] The selective repair access region, in some embodiments, comprises an epitaxial semiconductor layer of a material having a smaller bandgap than the barrier layer. The barrier layer can include AlGaN, and the selective repair access region includes AlGaN having a lower Al concentration than the barrier layer. In some embodiments, the barrier layer includes AlGaN, and the selective repair access region includes GaN.

[0035] The selective repair access region may be doped with an n-type dopant.

[0036] The selective repair access region, in some embodiments, has a thickness of about 0.1 nm to about 40 nm and a width of about 1E14 cm -3 Approximately 1E17cm -3 and a doping concentration of

[0037] The selective repair access region may be provided with a charge ejection path that allows charge carriers present on the upper surface of the barrier layer opposite the channel layer to be conducted toward the drain contact.

[0038] The gate contact may not be in contact with the selective repair access region.

[0039] The selective repair access regions, in some embodiments, have a first width d1 and are spaced apart on the barrier layer along the length of the gate contact by a second width d2, where the first width d1 may be between about 1 micron and 100 microns and the second width d2 may be between about 1 micron and 100 microns.

[0040] A method of forming a transistor device according to some embodiments includes providing a semiconductor epitaxial layer structure comprising a channel layer and a barrier layer on the channel layer, the barrier layer having a larger bandgap than the channel layer, forming source and drain contacts on the barrier layer, forming a gate contact on the barrier layer between the source and drain contacts, and forming a plurality of selective repair access regions on an upper surface of the barrier layer opposite the channel layer, the selective repair access regions comprising a material having a surface barrier height lower than that of the barrier layer and spaced apart along the length of the gate contacts.

[0041] Forming the selective modification access region, in some embodiments, includes forming a mask on the barrier layer, the mask having a plurality of openings exposing respective portions of an upper surface of the barrier layer, and forming the selective modification access region in the portions of the upper surface of the barrier layer exposed by the openings.

[0042] Forming the charge cap emission region may include forming a sacrificial dielectric layer over the mask and the barrier layer, wherein the sacrificial dielectric layer extends into the opening and contacts the barrier layer at a portion of the top surface of the barrier layer exposed by the opening; annealing the sacrificial dielectric layer and the barrier layer; and removing the sacrificial dielectric layer.

[0043] The sacrificial dielectric layer, in some embodiments, includes SiN, SiOx, AlN, AlO, and / or HfO.

[0044] Forming the selective modification access region, in some embodiments, includes selectively forming an epitaxial layer on the portion of the top surface of the barrier layer exposed by the opening, the epitaxial layer including a material having a smaller bandgap than the barrier layer, and the epitaxial layer may be doped with an n-type dopant.

[0045] Forming the selective repair access region, in some embodiments, includes implanting an n-type dopant into the portion of the top surface of the barrier layer exposed by the opening.

[0046] The gate contact may or may not be in contact with the selective repair access region.

[0047] The method may further include forming a doped drain region in the barrier layer, the drain contact contacting the drain region, and the selective modification access region contacting the drain region.

[0048] The selective repair access regions can have a first width d1 and can be spaced apart on the barrier layer along the length of the gate contact by a second width d2, where the first width d1 can be between about 1 micron and 100 microns and the second width d2 can be between about 1 micron and 100 microns. [Brief explanation of the drawings]

[0049] [Figure 1A] FIG. 1 is a cross-sectional view of a conventional transistor device with a field plate. [Figure 1B] 1 is a cross-sectional view of an intermediate structure of a conventional transistor device. [Figure 2] 1 is a schematic plan view of a HEMT device, according to some embodiments. [Figure 3A] 1A-1D are cross-sectional views illustrating steps in forming a HEMT device structure, according to various embodiments. [Figure 3B]1A-1D are cross-sectional views illustrating steps in forming a HEMT device structure, according to various embodiments. [Figure 3C] 1A-1D are cross-sectional views illustrating steps in forming a HEMT device structure, according to various embodiments. [Figure 3D] 1A-1D are cross-sectional views illustrating steps in forming a HEMT device structure, according to various embodiments. [Figure 4A] FIG. 1 shows results on a test setup with a conventional GaN HEMT and a GaN HEMT with a modified access region. [Figure 4B] 1 is a chart comparing the Schottky barrier height of a conventional transistor with the Schottky barrier height of a transistor with a charge-emission capping layer. [Figure 4C] FIG. 1 is a band diagram showing the surface barrier height of a HEMT. [Figure 5A] 10 is a cross-sectional view of a HEMT device structure according to a further embodiment. [Figure 5B] 10 is a cross-sectional view of a HEMT device structure according to a further embodiment. [Figure 5C] 10 is a cross-sectional view of a HEMT device structure according to a further embodiment. [Figure 5D] 10 is a cross-sectional view of a HEMT device structure according to a further embodiment. [Figure 6A] 10A-10C show results on a test setup comprising a conventional GaN HEMT and a GaN HEMT with a selective repair access region according to various embodiments. [Figure 6B] 1 is a chart comparing the Schottky barrier height of a conventional transistor with the Schottky barrier height of a transistor with a selective repair access region according to various embodiments. [Figure 7A] 1A-1D are cross-sectional views illustrating steps in forming a HEMT device structure, according to various embodiments. [Figure 7B] 1A-1D are cross-sectional views illustrating steps in forming a HEMT device structure, according to various embodiments. [Figure 7C]1A-1D are cross-sectional views illustrating steps in forming a HEMT device structure, according to various embodiments. [Figure 7D] 1 is a block diagram illustrating a process for forming a transistor device according to some embodiments. [Figure 8A] 5A-5C are cross-sectional views illustrating steps in forming a HEMT device structure according to a further embodiment. [Figure 8B] 5A-5C are cross-sectional views illustrating steps in forming a HEMT device structure according to a further embodiment. [Figure 8C] 5A-5C are cross-sectional views illustrating steps in forming a HEMT device structure according to a further embodiment. [Figure 8D] 5A-5C are cross-sectional views illustrating steps in forming a HEMT device structure according to a further embodiment. [Figure 8E] 5A-5C are cross-sectional views illustrating steps in forming a HEMT device structure according to a further embodiment. [Figure 8F] 5A-5C are cross-sectional views illustrating steps in forming a HEMT device structure according to a further embodiment. [Figure 8G-1] 5A-5C are cross-sectional views illustrating steps in forming a HEMT device structure according to a further embodiment. [Figure 8G-2] 5A-5C are cross-sectional views illustrating steps in forming a HEMT device structure according to a further embodiment. [Figure 8G-3] 5A-5C are cross-sectional views illustrating steps in forming a HEMT device structure according to a further embodiment. [Figure 8H] 1 is a block diagram illustrating a process for forming a transistor device according to some embodiments. [Figure 9A] 1 is a schematic block diagram of a multiple amplifier circuit in which an RF transistor amplifier incorporating a transistor device according to an embodiment may be used. [Figure 9B] 1 is a schematic block diagram of a multiple amplifier circuit in which an RF transistor amplifier incorporating a transistor device according to an embodiment may be used. [Figure 9C]1 is a schematic block diagram of a multiple amplifier circuit in which an RF transistor amplifier incorporating a transistor device according to an embodiment may be used. [Figure 10] 1 is a schematic diagram of an MMIC amplifier comprising HEMT transistors, according to some embodiments. [Figure 11A] 1 is a schematic cross-sectional view illustrating an exemplary package for an RF transistor amplifier die, according to some embodiments. [Figure 11B] 1 is a schematic cross-sectional view illustrating an exemplary package for an RF transistor amplifier die, according to some embodiments. [Figure 12] 1 is a schematic diagram of the band gap and lattice constant of InAlGaN materials with various different compositions. DETAILED DESCRIPTION OF THE INVENTION

[0050] Embodiments of the inventive concepts will now be described in conjunction with the accompanying drawings. Some embodiments described herein provide transistor devices with a field plate that is self-aligned and, in some embodiments, laterally spaced from the gate such that the field plate does not vertically overlap the gate. The field plate, in some embodiments, is recessed toward the barrier layer in a recessed region. The field plate, in yet other embodiments, can be connected to the source outside the active area of ​​the device, with a connection that does not extend beyond the gate of the device.

[0051] It should also be understood that terms indicating order, such as first, second, third, etc., may be used herein to describe various elements, but such elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present disclosure.

[0052] Additionally, relationship terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figures. It should be understood that the relationship terms are intended to encompass various orientations of the device in addition to the orientation depicted in the figures. For example, if a device in one of the figures is turned over, features described as being on the "lower" side of an element would be oriented on the "upper" side of that element. Thus, the exemplary term "lower" can describe both a "down" and an "up" orientation, depending on the particular orientation of the device. Similarly, if a device in one of the figures is turned over, elements described as being "down" or "below" other elements would then be oriented "above" such other elements. Thus, the exemplary terms "below" or "below" can describe both an up and down orientation.

[0053] The terminology used in describing the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. When used in the description of this disclosure and the appended claims, the singular forms "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. The term "and / or," as used herein, is also understood to refer to and encompass any and all possible combinations of one or more of the associated listed items. It will be further understood that, as used in this specification, the terms "comprises" and "comprising" specify the presence of stated steps, operations, features, elements, and / or components, but do not exclude the presence or addition of one or more other steps, operations, features, elements, components, and / or groups thereof.

[0054] Embodiments of the present disclosure are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments of the present disclosure. As such, variations from the shapes of the illustrations that are a result, for example, of manufacturing techniques and / or tolerances, are to be expected. The embodiments of the present disclosure, therefore, should not be construed as limited to the particular shapes of regions illustrated herein and are to include, for example, shape variations due to manufacturing. The regions illustrated in the drawings are schematic in nature, and the shapes of the regions are not intended to represent the actual shape of a region of a device, and are not intended to limit the scope of the present disclosure unless otherwise specified. Additionally, for graphical reasons, lines depicted as straight, horizontal, or vertical in the drawings below will often be slanted, curved, non-horizontal, or non-vertical. Additionally, thicknesses of elements are intended to be graphical in nature.

[0055] All terms used in disclosing the embodiments of the present disclosure, including technical and scientific terms, unless otherwise defined, have the same meaning as commonly understood by those skilled in the relevant art and are not necessarily limited to the specific definitions known at the time of this disclosure. Accordingly, such terms may include equivalent terms subsequently created. It is further understood that terms as defined in commonly used dictionaries should be interpreted to have a meaning consistent with the meaning of the term in the context of this specification and the related art.

[0056] Trapped charge in semiconductor devices, such as GaN HEMT devices, can cause nonlinear distortion in the output signal generated by the device. To reduce such distortion, it is desirable to reduce the presence of trapped charge in the barrier layer of a HEMT device. While not wishing to be limited to a particular theory, it is currently believed that charge can be injected from the device's gate contact into the barrier layer and / or channel layer of a HEMT device, where such charge can be trapped in the barrier layer, and the trapped charge can adversely affect the switching characteristics of the device. In some embodiments, a repair access region having a low surface barrier height (SBH) is provided on or above the top surface of the barrier layer, forming a charge ejection path that allows some charge that would otherwise be injected into the barrier layer and / or channel layer to instead be conducted along the top surface of the barrier layer to the drain contact of the device. The repair access region comprises a material that has a lower surface barrier height relative to the gate contact than the barrier layer of the HEMT. By reducing the number of charges that can be trapped in the barrier layer and / or channel layer, the switching characteristics of the device can be improved.

[0057] A GaN HEMT structure 100 according to some embodiments is shown in Figure 2. The structure, as shown in Figure 2, includes a substrate 110 having a channel layer 120 formed thereon. A barrier layer 122 is formed on the channel layer. Doped source and drain regions 123, 125 are formed in the barrier layer 122 and may extend into the channel layer 120, and source and drain ohmic contacts 124, 126 are formed on the source and drain regions 123, 125, respectively.

[0058] 2, a repair access region 140 having a low surface barrier height (SBH) is formed on the top surface of the barrier layer 122 opposite the channel layer 120, in the active region of the device between the source region 123 and the drain region 125. A gate contact 130 is formed on the repair access region 140.

[0059] While not wishing to be bound by any particular theory, it is believed that the presence of the modified access region 140 provides a charge evacuation path that allows charges present at the surface of the barrier layer 122, such as charges that may be funneled from the gate contact 130, which may affect the charge transport characteristics of the device, to flow to the drain region 125 rather than being trapped in the barrier layer 122 and / or the channel layer 120.

[0060] A passivation film 128, such as a dielectric film, is formed over the structure, and a gate contact 130 is formed on the passivation film 128. The gate contact 130 extends through an opening in the passivation film 128 and contacts a repair access region 140.

[0061] The substrate 110 may be a semi-insulating silicon carbide (SiC) substrate, which may be, for example, silicon carbide of the 4H polytype. Other candidate polytypes of silicon carbide include the 3C, 6H, and 15R polytypes. In a specific embodiment of the inventive concept, a bulk crystal of silicon carbide has a density of about 1×10 at room temperature. 5 It has a resistivity of Ω·cm or greater. Optional buffer, nucleation, and / or transition layers (not shown) may be provided on the substrate 110. For example, an AlN buffer layer may be provided to provide a suitable crystal structure transition between the silicon carbide substrate and the remainder of the device.

[0062] Silicon carbide may be used as the substrate material, although some embodiments may utilize any suitable substrate, such as sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP, etc.

[0063] 2, the channel layer 120 may be deposited on the substrate 110 using buffer, transition, and / or nucleation layers as described above. The channel, buffer, nucleation, and / or transition layers may also be deposited by MOCVD or other techniques known to those skilled in the art, such as MBE or HVPE.

[0064] In some embodiments, the channel layer 120 is a III-nitride such as AlxGa1-xN, where 0≦x<1, provided that the conduction band edge energy of the channel layer 120 is less than the conduction band edge energy of the barrier layer 122 at the interface between the channel layer and the barrier layer. In some embodiments, x=0, indicating that the channel layer 120 is GaN. The channel layer 120 may also be other III-nitrides, such as InGaN or AlInGaN. The channel layer 120 may be undoped (“unintentionally doped”) and may be grown to a thickness greater than about 20 Å. The channel layer 120 may also be a multi-layer structure, such as a superlattice or a combination of GaN, AlGaN, etc.

[0065] The channel layer 120 can have a bandgap smaller than that of the barrier layer 122, and the channel layer 120 can also have a higher electron affinity than the barrier layer 122. The barrier layer 122, in some embodiments, is AlN, AlInN, AlGaN, or AlInGaN, having a thickness between about 0.1 nm and about 40 nm. The barrier layer 122, in particular embodiments, is thick enough and has a sufficiently high Al content and doping to induce a significant carrier concentration at the interface between the channel layer 120 and the barrier layer 122.

[0066] The barrier layer 122 is, in some embodiments, AlGaN, AlInGaN, and / or AlN, or a combination of these layers. The barrier layer 122 may be, for example, from about 0.1 nm to about 40 nm thick, but not so thick as to cause cracking or substantial defect formation within the barrier layer. The barrier layer 122 is, in some embodiments, undoped or doped with an n-type dopant to a concentration of less than about 10 19 cm -3 −1. The barrier layer 122 is, in some embodiments of the concepts of the present invention, AlxGa1-xN, where 0 < x ≦ 1. In certain embodiments, the aluminum concentration is about 25%. However, the barrier layer 122 includes AlGaN having an aluminum concentration between about 5% and about 100% in other embodiments of the concepts of the present invention. The aluminum concentration is greater than about 10% in certain embodiments of the concepts of the present invention.

[0067] The gate contact 130 can be a "T" - shaped gate as shown in FIG. 2 and can be fabricated using conventional manufacturing techniques. The gate contact 130 can be fabricated using conventional manufacturing techniques. Suitable gate materials can vary depending on the composition of the barrier layer. In some embodiments, conventional materials such as Ni, Pt, NiSiX, Cu, Pd, Cr, W, and / or WSiN, which can make a Schottky contact with nitride - based semiconductor materials, can be used.

[0068] The passivation layer 128 can be a SiN layer. Optionally, a structure comprising the passivation layer can be annealed at a temperature from 100°C to 1200°C in a nitrogen environment to activate the implanted dopants.

[0069] The repair access region 140 can be formed in a variety of ways. Some options for forming the repair access region 140 are illustrated, for example, in FIGS. 3A-3D . Referring to FIG. 3A , in some embodiments, after forming a barrier layer 122 on the channel layer 120, a sacrificial film 152 is formed on the barrier layer 122. The sacrificial film 152 can be a dielectric film having a different stoichiometry than the barrier layer 122. In certain embodiments, the sacrificial film 152 can include a dielectric material such as SiN, SiOx, AlN, AlO, or HfO. The sacrificial film 152 can be doped or undoped and can have a thickness of about 10 nm to about 200 nm.

[0070] With the sacrificial film 152 in place, the structure is annealed by exposing it to heat 154. The structure can be annealed at a temperature of about 100° C. to about 1200° C. for about 10 seconds to about 1 hour. Annealing can be performed in an atmosphere such as nitrogen, argon, or another inert gas.

[0071] During annealing, repair access regions 140 are formed in the surface of barrier layer 122. The repair access regions 140 can extend from about 0.1 nm to about 40 nm into barrier layer 122. In particular embodiments, the repair access regions can extend from about 0.5 nm to about 10 nm into barrier layer 122.

[0072] The sacrificial film 152 is then stripped, for example using an HF etch or other stripping process, to clean the surface of the barrier layer 122 and leave the repair access region 140 in place. The remaining steps of device fabrication (e.g., formation of source / drain regions 123, 125, source / drain contacts 124, 126, passivation layer 128, gate 130, and other dielectric / metallization layers) are then performed.

[0073] 3B, the repair access region 140 may, in some embodiments, be formed as an epitaxial layer on the barrier layer 122. The repair access region 140 may, for example, be formed as a thin epitaxial layer of a III-nitride based material having a smaller bandgap than the barrier layer 122. The repair access region 140 may, in particular embodiments, be formed as an epitaxial layer of InAlGaN, with relative concentrations of In, Al, and Ga such that the repair access region 140 has a smaller bandgap than the barrier layer 122. The relationship between the concentrations of In, Al, and Ga in an InAlGaN material and the bandgap of the material is shown, for example, in FIG. 12, which is a schematic diagram of the bandgap and lattice constant of InAlGaN materials having various different compositions (i.e., different relative levels of In, Al, and Ga). As can be seen from FIG. 12, the bandgap of the material increases as the percentage of Al in the material increases, generally to above 6 eV for AlN, while the bandgap of the material decreases as the percentage of In in the material increases, to below 2 eV for InN.

[0074] The repair access region 140, in some embodiments, can comprise GaN or InGaN. The repair access region 140 may have a thickness of about 0.1 nm to about 40 nm, in some embodiments about 0.5 nm to about 10 nm, and may be doped or undoped. In some embodiments, the repair access region 140 is made of heavily doped AlGaN (e.g., about 1E14 cm -3 In yet another embodiment, the charge emission cap layer 140 may comprise an n-type dopant, such as silicon, at a doping concentration of about 1E14 cm -3 From 1E17cm -3 and may have the same or similar bandgap as barrier layer 122.

[0075] 3C, the repair access region 140 can be formed by implanting dopant ions 156 into the barrier layer 122. For example, the repair access region 140 can be formed by implanting an n-type dopant 156, such as silicon, into the surface of the barrier layer 122 to form an enhanced conductive region at the surface of the barrier layer 122. When formed as an implanted region in the barrier layer 122, the repair access region 140 has a depth of approximately 1E14 cm -3 Approximately 1E17cm -3 and may have a thickness of about 0.1 nm to about 40 nm.

[0076] A preferred charge emission cap layer 140 implants silicon ions into the barrier layer 122 at an implant energy of about 10 keV to about 100 keV at a rate of 1E14 cm -3 Approximately 1E17cm -3 The doping concentration of the CrN layer 122 can be formed in the barrier layer 122 by implanting the CrN layer 122 in an amount suitable to form a layer with a doping concentration of CrN.

[0077] According to some embodiments, the switching speed of a transistor can be improved by the presence of the modified access region 140. For example, Figure 4A shows results from a test setup including a conventional GaN HEMT transistor and a GaN HEMT transistor with the modified access region 140 described herein, while Figure 4B compares the Schottky barrier height of the conventional transistor with the Schottky barrier height of a transistor with the modified access region 140 described herein.

[0078] Referring to Figure 4A, RF pulses were applied to a device without modified access region 140 (top graph) and a device with modified access region 140 (bottom graph). Specifically, the input and output matching network circuits and loads were set under appropriate bias conditions, and RF pulses were applied to the gate terminals of each device to test the transient behavior of the devices. The resulting output waveforms are shown on the right.

[0079] The device without the repair access region 140 exhibited a significant drain current drop (delay before recovery) at the onset of the applied RF pulse signal, which is believed to be affected by defect-related trapped charge. Specifically, the device without the charge release cap layer 140 exhibited a recovery time constant (τ) of several milliseconds, while the device with the charge release cap layer 140 exhibited a significantly shorter recovery time constant (τ) of several microseconds. However, as can be seen in FIG. 4A, the device with the repair access region 140 also exhibited some undesirable overshoot in the output signal.

[0080] 4B, devices with modified access region 140 have a lower average Schottky barrier height than devices without modified access region 140, which may be undesirable. For example, the reduced Schottky barrier height may be the cause of the overshoot evident in FIG. 4A.

[0081] FIG. 4C shows the Fermi level E F and conduction band E C4C illustrates the surface barrier height of a HEMT device, which is the energy barrier between the gate contact and the drain contact. As seen in FIG. 4C, by lowering the surface barrier height of the device, carriers that would otherwise be trapped in the barrier layer 122 may be able to move to the 2DEG region between the barrier layer 122 and the channel layer 120, where they may be conducted to the drain of the device. To eliminate this effect, some embodiments provide selective repair access regions in only select portions of the device active region between the source region 123 and the drain region 125 of the device. Specifically, some embodiments overcome this drawback by localizing the charge emission path provided by the repair access region 140 to the region between the gate contact and the drain contact. Referring to FIG. 5A, a GaN HEMT device 200 is provided with a localized charge emission path by a selective repair access region 240 provided only in the region between the gate contact 130 and the drain region 125 (denoted as the GD region in FIG. 5A). The selective repair access region 240 may not extend under the gate contact 130 in certain embodiments, such that the gate contact 130 directly contacts the barrier layer 122 .

[0082] The selective repair access region 240 can have a reduced surface barrier height compared to the portions of the barrier layer 122 beneath the gate contact 130 and between the gate contact 130 and the source region 123. Selective provision of the selective repair access region 240 can improve the Schottky barrier height of the device as well as the transient behavior of the device. The selective repair access region 240 can, in some embodiments, be formed by masking and selective epitaxial growth of the low SBH epitaxial layer 140, similar to the embodiment shown in FIG. 3B.

[0083] Referring to FIG. 5B, in some embodiments, a selective modification access region 242 can be provided in the barrier layer 122 between the gate contact 130 and the drain region 125. The selective modification access region 242 can be formed by selectively forming a selective sacrificial film 162 (as shown in FIG. 3D) prior to annealing, for example, by masking and etching the sacrificial film 152 of FIG. 3A to form the selective sacrificial film 162 of FIG. 3D prior to annealing. A protective film 164 can be formed on the selective sacrificial film 162 prior to annealing. In a further embodiment, referring to FIG. 3C, the selective modification access region 242 can be formed by masking and selectively implanting ions 156 into the barrier layer 122.

[0084] Referring to FIG. 5C , a GaN HEMT structure 200C according to a further embodiment is shown. In the GaN HEMT structure 200C, a modified access region 244 having a reduced surface barrier height is provided only in the SG region between the source region 123 and the gate contact 130 (not below the gate contact 130). Thus, the device shown in FIG. 5C can have a reduced surface barrier height in the region between the source contact 124 and the gate contact 130 while maintaining a high Schottky barrier between the gate contact 130 and the barrier layer 122. Although not shown in FIG. 5C , it will be understood that the modified access region 244 may be formed as a surface region in the barrier layer 122, as described above with respect to FIG. 5B .

[0085] 5D , a further embodiment of a GaN HEMT structure 200D is shown. In the GaN HEMT structure 200C, a first modified access region 246 having a reduced surface barrier height is provided in the SG region between the source region 123 and the gate contact 130 (but not below the gate contact 130), and a second modified access region 248 having a reduced surface barrier height is provided in the GD region between the gate contact 130 and the drain region 125 (but not below the gate contact 130). Thus, the device shown in FIG. 5D can have reduced surface barrier heights in the region between the source contact 124 and the gate contact 130 and the region between the gate contact 130 and the drain contact 126, while maintaining a high Schottky barrier between the gate contact 130 and the barrier layer 122. Although not shown in FIG. 5D, it will be appreciated that one or both of the first modification access region 246 and the second modification access region 248 may be formed as surface regions within the barrier layer 122, as described above with respect to FIG. 5B.

[0086] The presence of selective repair access region 240 or region 242 in the GD region can increase the switching speed of transistors according to some embodiments without causing undesirable overshoot in the drain current. For example, Figure 6A shows results from a test setup including a conventional GaN HEMT transistor, a GaN HEMT transistor with repair access region 140 across the entire active region between source region 123 and drain region 125, and a GaN HEMT transistor with selective repair access region 240 only in the GD region. Figure 6B compares the Schottky barrier height of the conventional transistor with the Schottky barrier height of a transistor with repair access region 140 and a transistor with selective repair access region 240 only in the GD region as described herein.

[0087] Referring to Figure 6A, RF pulses were applied to a device without a repair access region (top graph), a device with a full repair access region 140 (middle graph), and a device with a selective repair access region 240 (bottom graph). Specifically, the input and output matching network circuits and loads were set under appropriate bias conditions, and an RF pulse was applied to the gate terminal of each device to test the transient behavior of the device. The resulting output waveforms are shown on the right.

[0088] The device with the partial selective repair access region 240 exhibited a recovery time constant (τ) of approximately several microseconds, which is comparable to the performance of the device with the full repair access region 140. However, as can be seen in FIG. 6A, the device with the partial selective repair access region 240 did not exhibit any obvious overshoot in the output signal. Furthermore, referring to FIG. 6B, the device with the selective repair access region 240 had a Schottky barrier height similar to that of the device without the repair access region.

[0089] The selective formation of selective repair access regions 240, 242 is illustrated in Figures 7A-7C. For example, referring to Figure 7A, after forming channel layer 120 and barrier layer 122 on substrate 110, an epitaxial growth mask 702 can be selectively formed on the top surface of barrier layer 122 in areas corresponding to the SG regions of the device (Figure 5A). The epitaxial growth mask 702 exposes a portion of the surface of the barrier layer corresponding to the GD regions of the device. An epitaxial layer is then selectively formed on the exposed portions of barrier layer 122 to form selective repair access regions 240.

[0090] 7B, in some embodiments, an implant mask 704 is selectively formed on the top surface of barrier layer 122 in areas corresponding to the SG regions of the device. The implant mask 704 exposes a portion of the surface of the barrier layer corresponding to the GD regions of the device. Dopant ions 756 are then implanted into the exposed surface of barrier layer 122 to form selective repair access regions 240.

[0091] 7C, in some embodiments, a sacrificial layer 708 is selectively formed on the top surface of the barrier layer 122 in areas corresponding to the GD regions of the device. An implant mask 704 exposes a portion of the surface of the barrier layer corresponding to the SG regions of the device. The structure is then annealed 754 to form the selective repair access regions 242. A surface protection layer (not shown) may be formed on the sacrificial layer prior to annealing to prevent surface desorption of the barrier layer during annealing. The sacrificial layer is then removed, for example by etching.

[0092] The selective repair access region 240, in some embodiments, may not fill the entire GD region between the gate contact 130 and the drain region 125. For example, multiple repair access regions may be formed on the top surface of the barrier layer 122 and spaced apart along the length of the gate. The use of multiple repair access regions can provide a mechanism for controlling the conductivity of charge egress from the surface of the barrier layer 122 to the drain region 125, depending on the sizing and placement of the regions.

[0093] 7D illustrates a method of forming a transistor device. The method includes providing a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, the barrier layer having a larger bandgap than the channel layer (block 722). A repair access region is formed on an upper surface of the barrier layer opposite the channel layer (block 724). Source and drain contacts are formed on the barrier layer (block 726), and a gate contact is formed between the source and drain contacts (block 728). The repair access region includes a material having a lower surface barrier height for the gate contact than the barrier layer.

[0094] Forming the repair access region can include forming a sacrificial dielectric layer on the barrier layer, annealing the sacrificial dielectric layer and the barrier layer, and removing the sacrificial dielectric layer. The sacrificial dielectric layer can include SiN, SiOx, AlN, AlO, and / or HfO.

[0095] Forming the repair access region can include forming an epitaxial layer on the barrier layer of a material having a smaller bandgap than the barrier layer. The epitaxial layer can be doped with an n-type dopant.

[0096] Forming the repair access region, in some embodiments, includes implanting an n-type dopant into a top surface of the barrier layer opposite the channel layer.

[0097] The repair access region, in some embodiments, is in the region between the gate contact and the drain contact, but does not extend all the way between the source contact and the drain contact. The gate contact, in some embodiments, forms a non-ohmic contact to the barrier layer and does not contact the repair access region.

[0098] The method may further include forming a doped drain region in the barrier layer, the drain contact contacting the drain region and the modification access region contacting the drain region.

[0099] 8A-8F illustrate processes for forming a HEMT device according to various further embodiments. While FIGURES 8A-8F illustrate processes for forming repair access regions in the GD region of a HEMT device structure, it will be appreciated that similar processes can be performed to form repair access regions in the SG region, as shown in FIGURE 5C, or in both the SG and GD regions of a HEMT device structure, as shown in FIGURE 5D.

[0100] FIG. 8A is a cross-sectional view of a precursor structure for a GaN HEMT device, including a substrate 110, a channel layer 120, and a barrier layer 122, taken along line AA in FIG. 8B, which is a plan view of the structure of FIG. 8A. A mask 803 is formed on the top surface of the barrier layer 122 to expose multiple regions 122A on the surface of the barrier layer 122. The regions 122A extend across the GD region of the precursor structure. The regions 122A have widths d1 and d2, respectively, which may be between 1 micron and 100 microns. The number of regions 122A, along with the overall gate width of the device, may vary depending on the values ​​of d1 and d2. While the regions 122A are shown as rectangles in FIG. 8B, it will be understood that they may have any desired shape.

[0101] 8C and 8D, a sacrificial film 805 is formed over the mask layer and in regions 122A on the barrier layer. The sacrificial film 805 may have a composition similar to that of the sacrificial film 152 described above in connection with FIG. 3A. The structure is then annealed 854 in a manner similar to that described above in connection with FIG. 3A to form a plurality of regions 842 in the exposed regions 122A on the surface of the barrier layer 122.

[0102] Referring to FIG. 8E, in some embodiments, region 842 can be formed by implanting ions 856 into exposed region 122 A of the surface of barrier layer 122 .

[0103] Referring to FIG. 8F, in some embodiments, region 842 can be formed by selective epitaxial growth on the barrier layer in exposed region 122A.

[0104] Referring to FIG. 8G-1, in some embodiments, region 122B can be formed to cover the entire length between the source and drain contacts, thereby forming selective repair access region 842 in the SG region as well as the GD region of the device.

[0105] Referring to FIG. 8G-2, in some embodiments, region 122B can be formed between the source contact and the gate contact, thereby forming a selective repair access region 842 in the SG region of the device.

[0106] Referring to FIG. 8G-3, in some embodiments, region 122B can be formed between the source and drain contacts, but not under the gate contact, such that selective repair access region 842 is formed in the SG and GD regions of the device, but not under the gate contact.

[0107] 8H illustrates a method of forming a transistor device. The method includes providing a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, the barrier layer having a larger bandgap than the channel layer (block 802). The method further includes forming source and drain contacts on the barrier layer (block 804) and forming a gate contact on the barrier layer between the source and drain contacts (block 806). The method further includes forming a plurality of selective repair access regions on an upper surface of the barrier layer opposite the channel layer (block 808). The selective repair access regions include a material with a lower surface barrier height relative to the gate contact than the barrier layer, and a plurality of charge release cap regions are spaced along the length of the gate contact.

[0108] Forming the selective modification access region may include forming a mask on the barrier layer, the mask having a plurality of openings exposing respective portions of an upper surface of the barrier layer, and forming the selective modification access region in the portions of the upper surface of the barrier layer exposed by the openings.

[0109] Forming the selective repair access region can include forming a sacrificial dielectric layer over the mask and the barrier layer, where the sacrificial dielectric layer extends into the opening and contacts the barrier layer at a portion of the top surface of the barrier layer exposed by the opening, annealing the sacrificial dielectric layer and the barrier layer, and removing the sacrificial dielectric layer. The sacrificial dielectric layer can include SiN, SiOx, AlN, AlO, and / or HfO.

[0110] Forming the selective modification access region, in some embodiments, can include selectively forming an epitaxial layer on the portion of the top surface of the barrier layer exposed by the opening, the epitaxial layer comprising a material having a smaller bandgap than the barrier layer, and the epitaxial layer can be doped with an n-type dopant.

[0111] Forming the selective repair access region, in some embodiments, includes implanting an n-type dopant into the portion of the top surface of the barrier layer exposed by the opening.

[0112] The gate contact, in some embodiments, forms a non-ohmic contact to the barrier layer and does not contact the charge emission cap region.

[0113] The method may further include forming a doped drain region in the barrier layer, the drain contact contacting the drain region, and the charge emission cap region contacting the drain region.

[0114] The selective repair access regions may have a first width d1 and may be spaced apart by a second width d2 along the length of the gate contact on the barrier layer.

[0115] The first width d1 may be between approximately 1 micron and 100 microns, and the second width d2 may be between approximately 1 micron and 100 microns.

[0116] The transistor devices with selectively modifiable access regions described herein can be used in amplifiers operating in a variety of different frequency bands. In some embodiments, an RF transistor amplifier incorporating a transistor device as described herein can be configured to operate at frequencies greater than 1 GHz. In other embodiments, an RF transistor amplifier can be configured to operate at frequencies greater than 2.5 GHz. In still other embodiments, an RF transistor amplifier can be configured to operate at frequencies greater than 3.1 GHz. In still additional embodiments, an RF transistor amplifier can be configured to operate at frequencies greater than 5 GHz. In some embodiments, an RF transistor amplifier can be configured to operate in at least one of the following frequency bands: 2.5-2.7 GHz, 3.4-4.2 GHz, 5.1-5.8 GHz, 12-18 GHz, 18-27 GHz, 27-40 GHz, or 40-75 GHz, or portions of these frequency bands.

[0117] Although embodiments of the inventive concepts have been discussed above with respect to HEMT devices, it will be appreciated that the inventive concepts described herein may also be applied to other types of semiconductor devices, such as MOSFETs, DMOS transistors, and / or laterally diffused MOS (LDMOS) transistors.

[0118] RF transistor amplifiers incorporating the transistor devices described herein can be used in stand-alone RF transistor amplifiers and / or multiple RF transistor amplifiers. Examples of how RF transistor amplifiers according to some embodiments can be used in multiple amplifier applications will be discussed with reference to Figures 9A-9C.

[0119] Referring to FIG. 9A , a schematic diagram of an RF transistor amplifier 1000A is shown, which includes a preamplifier 1010 and a main amplifier 1030 electrically connected in series. As shown in FIG. 9A , the RF transistor amplifier 1000A includes an RF input 1001, a preamplifier 1010, an inter-stage impedance matching network 1020, a main amplifier 1030, and an RF output 1002. The inter-stage impedance matching network 1020 may include, for example, inductors and / or capacitors arranged in any suitable configuration to form a circuit that improves impedance matching between the output of the preamplifier 1010 and the input of the main amplifier 1030. Although not shown in FIG. 9A , the RF transistor amplifier 1000A may further include an input matching network inserted between the RF input 1001 and the preamplifier 1010 and / or an output matching network inserted between the main amplifier 1030 and the RF output 1002. An RF transistor amplifier according to an embodiment can be used to implement either or both of the preamplifier 1010 and the main amplifier 1030.

[0120] 9B, there is shown a schematic diagram of an RF transistor amplifier 1000B comprising an RF input 1001, a pair of preamplifiers 1010-1 and 1010-2, a pair of interstage impedance matching networks 1020-1 and 1020-2, a pair of main amplifiers 1030-1 and 1030-2, and an RF output 1002. A divider 1003 and a combiner 1004 are also provided. The preamplifier 1010-1 and main amplifier 1030-1 (electrically connected in series) are arranged electrically in parallel with the preamplifier 1010-2 and main amplifier 1030-2 (electrically connected in series). The RF transistor amplifier 1000B, like the RF transistor amplifier 1000A of FIG. 9A, may further include an input matching network inserted between the RF input 1001 and the preamplifiers 1010-1, 1010-2, and / or an output matching network inserted between the main amplifiers 1030-1, 1030-2 and the RF output 1002.

[0121] As shown in FIG. 9C , an RF transistor amplifier according to some embodiments can also be used to implement a Doherty amplifier. A Doherty amplifier circuit, as known in the art, includes first and second (or more) power combining amplifiers. The first amplifier is referred to as the “main” or “carrier” amplifier, and the second amplifier is referred to as the “peaking” amplifier. The two amplifiers can be biased separately. For example, in one common Doherty amplifier implementation, the main amplifier can include a Class AB or Class B amplifier, while the peaking amplifier can be a Class C amplifier. Doherty amplifiers can operate more efficiently than balanced amplifiers when operating at power levels backed off from the saturation level. The RF signal input to the Doherty amplifier is split (e.g., using a quadrature combiner) and the outputs of the two amplifiers are combined. Because the main amplifier is configured to turn on first (i.e., at the lower input power level), only the main amplifier operates at the lower power level. As the input power level increases towards the saturation level, the peaking amplifier turns on and the input RF signal is divided between the main amplifier and the peaking amplifier.

[0122] 9C , the Doherty RF transistor amplifier 1000C includes an RF input 1001, an input divider 1003, a main amplifier 1040, a peaking amplifier 1050, an output combiner 1004, and an RF output 1002. The Doherty RF transistor amplifier 1000C includes a 90° transformer 1007 at the input of the peaking amplifier 1050, a 90° transformer 1005 at the input of the main amplifier 1040, and may optionally include an input matching network and / or an output matching network (not shown). The main amplifier 1040 and / or the peaking amplifier 1050 may be implemented using any of the RF transistor amplifier embodiments described above.

[0123] RF transistor amplifiers according to embodiments may be formed as discrete devices or as part of a monolithic microwave integrated circuit (MMIC). MMIC refers to an integrated circuit operating with radio and / or microwave frequency signals, in which all circuitry for a specific function is integrated onto a single semiconductor chip. An exemplary MMIC device is a transistor amplifier with associated matching circuits, feed networks, etc., all realized on a common substrate. MMIC transistor amplifiers typically include multiple unit cell HEMT transistors connected in parallel.

[0124] 10 is a plan view of an MMIC RF transistor amplifier 400 in accordance with an embodiment of the inventive concept. MMIC RF transistor amplifier 400, as shown in FIG. 10, comprises an integrated circuit chip 430 housed within a package 410. Package 410 may comprise a protective enclosure that surrounds and protects integrated circuit chip 430. Package 410 may be formed of, for example, a ceramic material.

[0125] Package 410 includes input leads 412 and output leads 418. Input leads 412 may be attached, for example, by soldering, to input lead pads 414. One or more input bond wires 420 may electrically connect input lead pads 414 to input bond pads on integrated circuit chip 430. Integrated circuit chip 430 includes an input feed network 438, an input impedance matching network 450, a first RF transistor amplifier stage 460, a mid-impedance matching network 440, a second RF transistor amplifier stage 462, an output impedance matching stage 470, and an output feed network 482.

[0126] Package 410 further includes output leads 418 connected, for example by soldering, to output lead pads 416. One or more output bond wires 490 may electrically connect output lead pads 416 to output bond pads on integrated circuit chip 430. First RF transistor amplifier stage 460 and / or second RF transistor amplifier stage 462 may be implemented using any of the RF transistor amplifiers according to embodiments of the inventive concept.

[0127] RF transistor amplifiers according to embodiments of the inventive concepts can be designed to operate in a variety of different frequency bands. In some embodiments, such RF transistor amplifier dies may be configured to operate in at least one of the following frequency bands: 0.6-2.7 GHz, 3.4-4.2 GHz, 5.1-5.8 GHz, 12-18 GHz, 18-27 GHz, 27-40 GHz, or 40-75 GHz, or portions of these frequency bands. Techniques according to embodiments of the inventive concepts may be particularly advantageous for RF transistor amplifiers operating at frequencies above 10 GHz.

[0128] 11A and 11B are schematic cross-sectional views illustrating some exemplary ways in which an RF transistor amplifier die according to embodiments of the inventive concept may be packaged to provide packaged RF transistor amplifiers 600A and 600B, respectively.

[0129] 11A is a schematic side view of a packaged III-nitride-based RF transistor amplifier 600A. The packaged RF transistor amplifier 600A includes an RF transistor amplifier die 100 packaged in an open cavity package 610A, as shown in FIG. 11A. The package 610A includes a metal gate lead 622A, a metal drain lead 624A, a metal submount 630, sidewalls 640, and a lid 642.

[0130] Submount 630 can include a material configured to aid in thermal management of package 600A. Submount 630 can include, for example, copper and / or molybdenum. Submount 630, in some embodiments, can be constructed of multiple layers and / or contain vias / interconnects. In an exemplary embodiment, submount 630 can be a multi-layer copper / molybdenum / copper metal flange comprising a core molybdenum layer with a copper clad layer on either major surface. Submount 630 can include a metal heat sink, which in some embodiments is part of a lead frame or metal slug. Sidewall 640 and / or lid 642 can be formed of or include an insulating material in some embodiments. Sidewall 640 and / or lid 642 can be formed of or include a ceramic material, for example.

[0131] Sidewall 640 and / or lid 642 may be formed of, for example, Al2O3 in some embodiments. Lid 642 may be adhered to sidewall 640 using an epoxy adhesive. Sidewall 640 may be attached to submount 630 by, for example, brazing. Gate lead 622A and drain lead 624A are configured to extend through sidewall 640, although embodiments of the inventive concept are not limited in this regard.

[0132] The RF transistor amplifier die 100 is mounted on top of the metal submount 630 within an air-filled cavity 612 defined by the metal submount 630, ceramic sidewalls 640, and ceramic lid 642. The gate and drain terminals of the RF transistor amplifier die 100 may be on the top side of the structure, while the source terminal is on the bottom side of the structure.

[0133] The gate lead 622A may be connected to the gate terminal of the RF transistor amplifier die 100 by one or more bond wires 654. The drain lead 624A may similarly be connected to the drain terminal of the RF transistor amplifier die 100 by one or more bond wires 654. The source terminal may be attached to a metal submount 630, for example, using a conductive die attach material (not shown). The metal submount 630 may provide an electrical connection to the source terminal 126 and may also function as a heat dissipation structure to dissipate heat generated within the RF transistor amplifier die 100.

[0134] Heat is primarily generated at the top of the RF transistor amplifier die 100 where relatively high current densities are generated, for example, in the channel regions of the unit cell transistors. This heat can be transferred through the source vias 146 and semiconductor layer structure of the device to the source terminal and then to the metal submount 630.

[0135] 11B is a schematic side view of another packaged III-nitride-based RF transistor amplifier 600B. RF transistor amplifier 600B differs from RF transistor amplifier 600A in that it includes a different package 610B. Package 610B includes a metal submount 630, as well as a metal gate 622B and a drain lead 624B. RF transistor amplifier 600B also includes a plastic overmold 660 that at least partially surrounds RF transistor amplifier die 100, leads 622B, 624B, and metal submount 630.

[0136] Many variations of the features of the above embodiments are possible. Transistor structures having features that may be used in embodiments of the present invention are disclosed in the following commonly-assigned publications, the contents of each of which are fully incorporated herein by reference in their entirety: U.S. Patent No. 6,849,882 to Chavarkar et al., entitled "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer"; U.S. Patent No. 7,230,284 to Parikh et al., entitled "Insulating Gate AlGaN / GaN HEMT"; U.S. Patent No. 7,501,669 to Parikh et al., entitled "Wide Bandgap Transistor Devices With Field Plates"; U.S. Patent No. 7,126,426 to Mishra et al., entitled "Cascode Amplifier Structures Including Wide Bandgap Field Effect Transistor With Field Plates"; U.S. Patent No. 7,550,783 to Wu et al., entitled "Wide Bandgap HEMTs With Source Connected Field Plates"; U.S. Patent No. 7,573 to Wu et al.No. 2007 / 078 to Wu et al., entitled "Wide Bandgap Transistors With Multiple Field Plates," U.S. Patent Application Publication No. 2005 / 0253167 to Wu et al., entitled "Wide Bandgap Field Effect Transistors With Source Connected Field Plates," U.S. Patent Application Publication No. 2006 / 0202272 to Wu et al., entitled "Wide Bandgap Transistors With Gate-Source Field Plates," U.S. Patent Application Publication No. 2008 / 0128752 to Wu, entitled "GaN Based HEMTs With Buried Field Plates," U.S. Patent Application Publication No. 2010 / 0276698 to Moore et al., entitled "Gate Electrodes For Millimeter-Wave Operation and Methods of Fabrication," U.S. Patent Application Publication No. 2012 / 0049973 to Smith, Jr. et al., entitled "High Power Gallium Nitride Field Effect Transistors With Source Connected Field Plates," No. 2012 / 0194276 to Fisher entitled "Low Noise Amplifiers Including Group III Nitride Based High Electron Mobility Transistors" and U.S. Patent No. 9,847,411 to Sriram et al. entitled "Recessed field plate transistor structures."

[0137] Although embodiments of the inventive concepts have been described in considerable detail with reference to specific configurations of the embodiments, other variations are possible. The field plates and gates can also have many different shapes and can be connected to the source contact in many different ways. Thus, the spirit and scope of the present invention should not be limited to the specific embodiments described above.

Claims

1. a semiconductor epitaxial layer structure comprising a channel layer and a barrier layer on the channel layer, the barrier layer having a larger bandgap than the channel layer; source and drain contacts on the barrier layer, the source and drain contacts being spaced apart in a first direction; a gate contact on the barrier layer between the source contact and the drain contact; a plurality of selective repair access regions on an upper surface of the barrier layer opposite the channel layer, the selective repair access regions comprising a material having a surface barrier height lower than that of the barrier layer, the plurality of selective repair access regions being spaced apart on the barrier layer along a width of the gate contact in a second direction perpendicular to the first direction, the plurality of selective repair access regions being provided with a charge ejection path capable of conducting charge carriers present on the upper surface of the barrier layer opposite the channel layer toward the drain contact; A transistor device comprising:

2. a doped drain region in the barrier layer, the drain contact contacting the drain region; 2. The transistor device of claim 1, wherein the selective repair access region is on the barrier layer between the gate contact and the drain region.

3. 2. The transistor device of claim 1, wherein the selective repair access region comprises an enhanced conductivity region on a top surface of the barrier layer opposite the channel layer.

4. 4. The transistor device of claim 3, wherein the selective repair access region comprises an implanted region containing implanted dopants in the top surface of the barrier layer opposite the channel layer.

5. The selective repair access region has a thickness of about 0.1 nm to about 40 nm and a thickness of about 1E14 cm －３ Approximately 1E17cm －３ 4. The transistor device of claim 3, having a doping concentration of:

6. 2. The transistor device of claim 1, wherein the selective repair access region comprises an epitaxial semiconductor layer of a material having a smaller bandgap than the barrier layer.

7. 7. The transistor device of claim 6, wherein the barrier layer comprises AlGaN and the selective repair access region comprises AlGaN having a lower Al concentration than the barrier layer.

8. The transistor device of claim 6 , wherein the barrier layer comprises AlGaN and the selective repair access region comprises GaN.

9. 7. The transistor device of claim 6, wherein the selective repair access region is doped with an n-type dopant.

10. The selective repair access region has a thickness of about 0.1 nm to about 40 nm and a thickness of about 1E14 cm －３ Approximately 1E17cm －３ 7. The transistor device of claim 6, having a doping concentration of:

11. 2. The transistor device of claim 1, wherein the gate contact does not contact the selective repair access region.

12. 2. The transistor device of claim 1, wherein the selective repair access region has a first width d1 and is spaced apart on the barrier layer along the width of the gate contact by a second width d2.

13. 13. The transistor device of claim 12, wherein the first width d1 is between about 1 micron and 100 microns, and the second width d2 is between about 1 micron and 100 microns.

14. the selective repair access region is on the barrier layer between the gate contact and the source contact; The transistor device of claim 1 .

15. the selective repair access regions are on the barrier layer between the gate contact and the source contact and between the gate contact and the drain contact; The transistor device of claim 1 .

16. 1. A method of forming a transistor device, comprising: providing a semiconductor epitaxial layer structure comprising a channel layer and a barrier layer on the channel layer, the barrier layer having a larger bandgap than the channel layer; forming source and drain contacts on the barrier layer, the source and drain contacts being spaced apart in a first direction; forming a gate contact on the barrier layer between the source contact and the drain contact; forming a plurality of selective access regions on an upper surface of the barrier layer opposite the channel layer, the selective access regions comprising a material having a surface barrier height lower than that of the barrier layer, the selective access regions being spaced apart along a width of the gate contact in a second direction perpendicular to the first direction, the selective access regions being provided with a charge ejection path capable of conducting charge carriers present on the upper surface of the barrier layer opposite the channel layer towards the drain contact; A method comprising:

17. forming the selective modification access region; forming a mask on the barrier layer, the mask having a plurality of openings exposing respective portions of an upper surface of the barrier layer; forming the selective repair access region in the portion of the top surface of the barrier layer exposed by the opening; 17. The method of claim 16, comprising:

18. forming the plurality of selectively modified access regions; forming a sacrificial dielectric layer on the mask and the barrier layer, the sacrificial dielectric layer extending into the opening and contacting the barrier layer at the portion of the top surface of the barrier layer exposed by the opening; annealing the sacrificial dielectric layer and the barrier layer; removing the sacrificial dielectric layer; 18. The method of claim 17, comprising:

19. 20. The method of claim 18, wherein the sacrificial dielectric layer comprises SiN, SiOx, AlN, AlO, and / or HfO.

20. forming the selective modification access region; Selectively forming an epitaxial layer on the portion of the top surface of the barrier layer exposed by the opening, the epitaxial layer comprising a material having a smaller bandgap than the barrier layer.

18. The method of claim 17, comprising:

21. 21. The method of claim 20, wherein the epitaxial layer is doped with an n-type dopant.

22. forming the selective modification access region; implanting an n-type dopant into the portion of the top surface of the barrier layer exposed by the opening; 18. The method of claim 17, comprising:

23. 17. The method of claim 16, wherein the gate contact does not contact the selective repair access region.

24. 17. The method of claim 16, further comprising forming a doped drain region in the barrier layer, wherein the drain contact contacts the drain region and the selective repair access region contacts the drain region.

25. 17. The method of claim 16, wherein the selective repair access region has a first width d1 and is spaced a second width d2 above the barrier layer along the width of the gate contact.

26. 26. The method of claim 25, wherein the first width d1 is between about 1 micron and 100 microns, and the second width d2 is between about 1 micron and 100 microns.

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