Semiconductor Devices

Abstract

To provide a semiconductor device with high storage capacity.SOLUTION: A semiconductor device includes first to fifth insulators, first to third conductors, a first semiconductor, and a second semiconductor. A structure in which the first insulator, the first conductor, the second insulator, the second conductor, and the third insulator are stacked in this order is provided with an opening at one time. Moreover, the second conductor is removed selectively by an etching process in the opening. After that, the fourth insulator and the first semiconductor are formed in this order on a side surface of the opening, and the third conductor is formed in a region where the second conductor is removed. In the rest part of the opening, the fifth insulator and the second semiconductor are formed in this order and thus, the semiconductor device with a three-dimensional structure is manufactured. Note that the first semiconductor may be formed of a material containing metal oxide, and the second semiconductor may be formed of a material containing metal oxide or silicon.SELECTED DRAWING: Figure 16

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an article, a method, or a manufacturing method. Process, machine, manufacture, or composition of matter Therefore, the technology of one embodiment of the present invention disclosed in this specification more specifically relates to the above. Fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, Storage device, processor, electronic device, driving method thereof, manufacturing method thereof, and inspection method thereof One example is a method or a system including at least one of them. [Background technology]

[0003] In recent years, various electronic devices such as personal computers, smartphones, and digital cameras have become The device has a central processing unit (CPU), a graphics processing unit, Electronic components such as LEDs, memory devices, and sensors are used in these devices. Improvements are being made in various aspects, including low power consumption.

[0004] In particular, the amount of data handled by the electronic devices mentioned above has been increasing in recent years. There is a demand for storage devices with large storage capacities. This paper discloses a semiconductor device that allows writing and reading of large amounts of data. To realize a memory device with a large memory capacity, technology to miniaturize the circuits of the memory device is required. It is being done. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-256400 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-199707 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one embodiment of the present invention is to provide a novel semiconductor device. An object of one embodiment of the present invention is to provide a memory device including a novel semiconductor device. One embodiment of the present invention provides an electronic device using a memory device having the novel semiconductor device. Another object of the present invention is to provide a storage device with a large data capacity. Another object of one embodiment of the present invention is to provide a highly reliable storage device. This is one of the challenges.

[0007] Note that the problems of one embodiment of the present invention are not limited to the above-listed problems. This does not preclude the existence of other problems. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by understanding the specification or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the above-listed objects and other objects. One aspect of the present invention is to solve the above-listed and other problems. You don't need to solve all of them. [Means for solving the problem]

[0008] (1) One embodiment of the present invention is a semiconductor device including first to fifth insulators, first to third conductors, a first semiconductor, and a second semiconductor. a first conductor on an upper surface of a first insulator, and a second The insulator is on the top surface of the first conductor, the second conductor is on the first top surface of the second insulator, and the second The conductor is disposed on a first lower surface of the third insulator, and the fourth insulator is disposed on a side surface of the first insulator and on the first conductor. a side surface of the second insulator, a second top surface of the second insulator, a side surface of the second conductor, and a third a first semiconductor The third conductor is connected to the surface on which the fourth insulator is formed, and the third conductor is connected to the surface on which the first semiconductor is formed. The fifth insulator is provided in a region overlapping with a side surface of the second conductor, and the fifth insulator is provided in a region overlapping with a side surface of the third conductor. a formation surface, and a region where the first semiconductor is formed that overlaps with a side surface of the first insulator; , a region overlapping with a side surface of the second conductor, a region overlapping with a side surface of the second insulator, and a third insulator and a region overlapping with the side surface of the fifth insulator, and the second semiconductor is located on the surface where the fifth insulator is formed. This is a semiconductor device characterized by the above.

[0009] (2) Alternatively, one embodiment of the present invention is a semiconductor device including first to fifth insulators, first to third conductors, and first to third a first conductor on a first top surface of a first insulator; The first conductor is disposed on a first lower surface of the second insulator, and the second conductor is disposed on a first upper surface of the second insulator. a second conductor on a first lower surface of the third insulator; and a third semiconductor on a second upper surface of the first insulator. the fourth insulator is disposed in an area including the surface, the side surface of the first conductor, and the second lower surface of the second insulator. , a side surface of the first insulator, a surface on which the first semiconductor is formed, a side surface of the second insulator, and a second surface of the second insulator. a region including the upper surface, the side surface of the second conductor, the second lower surface of the third insulator, and the side surface of the third insulator; The first semiconductor is connected to the fourth insulator forming surface, and the third The conductor is formed in a region where the first semiconductor is formed and overlaps with a side surface of the second conductor. The fifth insulator is formed between the formation surface of the third conductor and the region where the first semiconductor is formed. A region overlapping with the side surface of the first insulator, a region overlapping with the formation surface of the third semiconductor, and a second insulator and a region overlapping with a side surface of the second semiconductor and a region overlapping with the third insulator. The semiconductor device is characterized by having an edge formed on the surface.

[0010] (3) Alternatively, one embodiment of the present invention is a semiconductor device including first to fourth insulators, first to fourth conductors, and a first semiconductor. and a second semiconductor, wherein the first insulator is disposed on a first upper surface of the first conductor. the second conductor is on a first upper surface of the first insulator, and the second insulator is on a first lower surface of the third conductor. a second conductor on a first lower surface of the second insulator; and a third insulator on a side of the first conductor. a side surface of the first insulator, a second upper surface of the first conductor, a side surface of the first insulator, a second upper surface of the first insulator, and a second conductor a side surface of the first conductor, a second lower surface of the second insulator, a side surface of the second insulator, and a second lower surface of the third conductor , and a side surface of the third conductor, and the first semiconductor is connected to the region including the fourth insulator. The fourth conductor is provided so as to be continuous with the first semiconductor formed surface, and the fourth conductor is provided so as to be continuous with the first semiconductor formed surface. A region overlapping with a side surface of the first insulator, a region overlapping with a side surface of the second conductor, and a region overlapping with a side surface of the second insulator. The fourth insulator has a region overlapping the surface on which the fourth conductor is formed and the region overlapping the surface on which the first semiconductor is formed. In the region where the first conductor overlaps with the second conductor, and in the region where the third conductor overlaps with the first conductor, The semiconductor device is characterized in that the second semiconductor is formed on the surface on which the fourth insulator is formed.

[0011] (4) Alternatively, in one aspect of the present invention, in the above (1) to (3), a sixth insulator and a fifth conductor and the sixth insulator is formed on the second semiconductor formation surface, and the fourth conductor is formed in the shape of the sixth insulator. The semiconductor device is characterized by having a surface.

[0012] (5) Alternatively, in one aspect of the present invention, in any one of (1) to (4), the first semiconductor is a metal oxide The semiconductor device is characterized by having:

[0013] (6) Alternatively, in one aspect of the present invention, in any one of (1) to (5), the second semiconductor is a metal oxide The semiconductor device is characterized by having:

[0014] (7) Alternatively, in one aspect of the present invention, in any one of (1) to (5), the second semiconductor is silicon. The semiconductor device is characterized by having a

[0015] (8) Another aspect of the present invention is a semiconductor device according to any one of (1) to (7) above, and a peripheral circuit. and a storage device having:

[0016] (9) Another aspect of the present invention is an electronic device having the storage device according to (8) above and a housing. is. [Effects of the Invention]

[0017] According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment, a memory device including the novel semiconductor device can be provided. According to one aspect of the present invention, an electronic device using a memory device having a novel semiconductor device is provided. Alternatively, one embodiment of the present invention provides a storage device with a large data capacity. According to one embodiment of the present invention, a highly reliable storage device can be provided. can be done.

[0018] The effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are obvious to a person skilled in the art from the description or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may have the above-listed effects. In some cases, the [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor device. [Figure 2] FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor device. [Figure 3] FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor device. [Figure 4] 10 is a flowchart showing an example of the operation of the semiconductor device. [Figure 5] 1A and 1B are a top view and a cross-sectional view illustrating a structural example of a semiconductor device. [Figure 6] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 7]1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 8] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 9] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 10] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 11] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 12] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 13] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 14] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 15] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 16] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 17] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 18] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 19] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 20] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 21] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 22] FIG. 1 is a block diagram illustrating an example of a storage device. [Figure 23] FIG. 2 is a diagram for explaining the range of atomic ratios of metal oxides. [Figure 24] Block diagram explaining a CPU. [Figure 25] FIG. 1 is a perspective view showing an example of an electronic device. [Figure 26] FIG. 1 is a perspective view showing an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0020] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used in the active layer of a transistor, the metal Oxides are sometimes called oxide semiconductors. In other words, metal oxides have amplifying and rectifying properties. and a channel forming region of a transistor having at least one of a switching function and a gate electrode. When the metal oxide can be formed, the metal oxide is called a metal oxide semiconductor. It can be abbreviated as OS. It is also written as OS FET. In this case, the transistor may be referred to as a transistor having a metal oxide or an oxide semiconductor. can be done.

[0021] In this specification and the like, a transistor having silicon in a channel formation region is referred to as a Si It may also be referred to as a transistor.

[0022] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides (metal ox). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0023] (Embodiment 1) In this embodiment, a circuit configuration, an operation method, and a semiconductor device according to one embodiment of the disclosed invention will be described. In the following description, for example, "[x, y]" is means the element in the xth column or yth column, and "[z]" means the element in the zth row or zth column. When there is no need to specify rows or columns, these notations are omitted.

[0024] <Circuit configuration example> First, the circuit configuration of the semiconductor device will be described with reference to FIG. ) shows a circuit diagram of n memory cells (n is an integer equal to or greater than 1). That is, memory cells MC[1] to MC[n] and a memory cell that controls them. Wiring WWL[1] to wiring WWL[n], wiring RWL[1] to wiring RWL[n] ], wiring WBL, and wiring RBL. The wiring WWL functions as a write word line. The wiring RWL functions as a read word line, and the wiring WBL functions as a write bit line. The line RBL functions as a read bit line.

[0025] Each memory cell MC includes a transistor WTr, a transistor RTr, and a capacitance element C The transistor RTr shown in FIG. 1A has a back gate. By applying a potential to the back gate, the transistor RTr The threshold voltage can be changed. The buffers of the transistors RTr of the memory cells MC[1] to MC[n] are In the semiconductor device shown in FIG. The back gates of the transistors RTr of the memory cells MC[1] to MC[n] are The back gate is not electrically connected to each of the back gates. They may be electrically connected independently and supplied with different potentials.

[0026] The channel formation region of the transistor WTr is made of a metal oxide material as described in the third embodiment. In particular, indium, element M (as element M, for example, aluminum) In the case of metal oxides selected from one or more of the following: zinc, gallium, yttrium, tin, etc. Since the metal oxide functions as a wide-gap semiconductor, The transistor included in the channel formation region has the characteristic of having a very low off-state current. By applying a transistor with this characteristic to the transistor WTr that holds the data, This allows the memory cell MC to retain data for a long time. This reduces the number of times data is refreshed, thereby reducing the power consumption of the semiconductor device. It is possible.

[0027] The channel formation region of the transistor RTr is formed by the field effect mobility of the transistor. It is preferable to use a material that has a high conductivity. The semiconductor device can be operated faster. For example, the channel shape of the transistor RTr The materials contained in the composition region include metal oxides and semiconductors such as silicon, which will be described in the third embodiment. It may comprise a conductive material.

[0028] The transistor WTr functions as a write transistor, and the transistor RTr functions as a read transistor. It functions as a readout transistor. It switches the transistor WTr between on and off. The potential of one electrode of the capacitor CS is applied to the wiring WWL. The other electrode of the capacitance element CS is connected to the gate of the transistor RTr. The other electrode of the capacitance element CS can be called a memory node. The memory node of each memory cell MC is connected to the transistor of the memory cell MC. The first terminal of the power supply WTr is electrically connected to the first terminal of the power supply WTr.

[0029] In addition, the second terminal of the transistor WTr is connected to the second terminal of the adjacent memory cell MC. The first terminal of the transistor WTr is electrically connected in series with the first terminal of the transistor WTr. The first terminal of the transistor RTr of the adjacent memory cell is connected in series with the second terminal of the transistor RTr of the adjacent memory cell. The second transistor WTr of the memory cell MC[n] is electrically connected to the The terminal is electrically connected to the wiring WBL, and the transistor R The second terminal of the transistor is electrically connected to the wiring RBL. The connection point between the second terminal of the transistor RTr in the memory cell MC[n] and the wiring RBL is The first terminal of the transistor RTr in the memory cell MC[1] is referred to as node N1. In order to control the conduction state between the node N1 and the wiring RBL, A selection transistor may be connected in series with the transistor RTr. 2 and the node N2. A selection transistor may be connected in series with Tr.

[0030] Note that one embodiment of the present invention is not limited to the semiconductor device illustrated in FIG. In some cases, depending on the circumstances, or as needed, the semiconductor device shown in FIG. For example, one embodiment of the present invention is a circuit configuration in which the As shown in the figure, if necessary, the transistor WTr can also be provided with a back gate. The semiconductor device shown in FIG. 1B may be the same as the semiconductor device shown in FIG. In addition to the configuration of the semiconductor device, the transistors of the memory cells MC[1] to MC[n] A back gate is provided to the transistor WTr, and the wiring BGL and the power supply are connected to each of the back gates. In addition, for example, one embodiment of the present invention is a structure in which the electrodes are electrically connected to each other as shown in FIG. As shown in the figure, the transistors RTr and WTr are semiconductors that do not have back gates. It may also be a device.

[0031] By the way, if you want to further increase the storage capacity of the semiconductor device shown in FIGS. When the semiconductor devices shown in FIGS. 1(A), 1(B), and 1(C) are arranged in a matrix, For example, the semiconductor devices shown in FIG. 1B may be arranged in a matrix. In this case, the circuit configuration is as shown in FIG.

[0032] The semiconductor device shown in FIG. 2 is arranged in m columns (m is 1 or greater), with the semiconductor device shown in FIG. 2(B) being one column. The wiring RWL and wiring WWL are arranged in the same row. The semiconductor device shown in Figure 2 is electrically connected to the rechargeable battery MC. The semiconductor device is a matrix-shaped semiconductor device with n rows and m columns, and memory cells MC[1,1] The semiconductor device shown in FIG. [1] to wiring RWL[n], wiring WWL[1] to wiring WWL[n], and wiring RBL [1] to wiring RBL[m], wiring WBL[1] to WBL[m], and wiring BGL[1 ] to wiring BGL[m]. Rule MC[j,i] (j is an integer between 1 and n, and i is an integer between 1 and m). One electrode of the capacitance element CS is electrically connected to the wiring RWL[j], and the memory cell MC The gate of the transistor WTr at [j,i] is electrically connected to the wiring WWL[j]. The wiring WBL[i] is connected to the second terminal of the transistor WTr of the memory cell MC[n,i]. The wiring RBL[i] is electrically connected to the transistor RT It is electrically connected to the second terminal of r.

[0033] 2 shows memory cells MC[1,1], MC[1,i], and M C[1,m], memory cell MC[j,1], memory cell MC[j,i], memory cell MC [j,m], memory cell MC[n,1], memory cell MC[n,i], memory cell MC[ n,m], wiring RWL[1], wiring RWL[j], wiring RWL[n], wiring WWL[1] , Wiring WWL[j], Wiring WWL[n], Wiring RBL[1], Wiring RBL[i], Wiring R BL[m], wiring WBL[1], wiring WBL[i], wiring WBL[m], wiring BGL[1] ], wiring BGL[i], wiring BGL[m], capacitance element CS, transistor WTr, Only the resistor RTr, node N1, and node N2 are shown, and other wiring, elements, and symbols are , and symbols are omitted.

[0034] In addition, the semiconductor device shown in FIG. 2(C) is counted as one row, and m rows (m is an integer of 1 or more) are arranged. The arrangement is shown in FIG. 3. In the semiconductor device shown in FIG. 3, all the memory cells The MC has a structure in which each transistor does not have a back gate. Therefore, the semiconductor device shown in FIG. 3 does not have the wiring BGL. For the arrangement, please refer to the description of the semiconductor device shown in FIG.

[0035] <Example of operation> Next, an example of a method for operating the semiconductor device shown in FIGS. 1A to 1C will be described. In the following description, the low-level potential and the high-level potential refer to specific potentials. The actual potential may differ depending on the wiring. For example, The low level potential and high level potential applied to the wiring RWL are The potential may be different from the bell potential and the high level potential.

[0036] In addition, in this example of the operation method, the wiring BGL shown in FIGS. 1(A) and 1(B) and the wiring BGL shown in FIG. The BGW[1] to BGW[n] shown include transistors RTr and WTr. It is assumed that a voltage within the range in which the device operates normally is applied in advance. The operations of the semiconductor devices shown in A) to C can be considered to be the same as each other.

[0037] FIG. 4A is a timing chart showing an example of an operation of writing data to a semiconductor device. FIG. 4B is a timing chart showing an example of an operation of reading data from a semiconductor device. The timing charts in Figure 4(A) and (B) are for the wiring WWL[1], Line WWL[2], Wire WWL[n], Wire RWL[1], Wire RWL[2], Wire RWL [n], the potential of the node N1, and the potential of the node N2 are changed. BL indicates data supplied to the wiring WBL.

[0038] FIG. 4A shows data D[1] to data D[n] stored in memory cells MC[1] 1 to MC[n]. D[n] can be binary or multi-valued. [n] is supplied from the wiring WBL. In the circuit configuration of the semiconductor device, data is written from memory cell MC[1] to memory This is performed sequentially on cells MC[n].

[0039] Conversely, after writing data to memory cell MC[2], data is written to memory cell MC[1]. When you try to write data, the data written in memory cell MC[2] is first read. If the data stored in memory cell MC[2] is not retrieved and saved elsewhere, The data is lost when it is written to the reseller MC[1].

[0040] In the circuit configuration of the semiconductor device shown in FIGS. 1A to 1C, the memory cell MC[i]( When writing data to memory cells MC[1] to MC[2], i is an integer between 2 and n. In order to prevent the data stored in the memory cell MC[i-1] from being rewritten, the wiring WWL A low-level potential is supplied to the wirings WWL[i-1] to WWL[i-1]. Each transistor WTr in the memory cell MC[i-1] is turned off. As a result, the data stored in the memory cells MC[1] to MC[i-1] are All data can be protected.

[0041] When writing data to the memory cell MC[i], the data is supplied from the wiring WBL. Therefore, a high-level potential is supplied to the wirings WWL[i] to WWL[n] to The transistors WTr of the memory cells MC[i] to MC[n] are sufficiently This causes the data to be stored in the memory node of the memory cell MC[i]. It is possible.

[0042] When data is written to the circuit configuration of the semiconductor device shown in FIGS. The line RBL can be controlled independently and does not need to be at a specific potential. The potential of the wiring RWL, that is, the node N1, can be set to a low level potential. In addition, the potential of the node N2 can also be set to a low level potential. .

[0043] Based on the above, an example of operation shown in the timing chart of FIG. 4(A) will be described. At time T10, the wiring WWL[1] to WWL[n], the wiring RWL[1] to RWL[n], The potentials of the wiring RWL[n], the wiring WBL, the node N1, and the node N2 are low level. It is a Bell potential.

[0044] At time T11, a high-level potential is supplied to the wirings WWL[1] to WWL[n]. As a result, the respective values ​​of the memory cells MC[1] to MC[n] are The transistor WTr is fully turned on. Each of the memory cells MC[1] to MC[n] has Since the transistor WTr is fully on, the data D[1] is transferred to the memory cell It reaches the memory node of MC[1] and is written.

[0045] At time T12, a low level potential is supplied to the wire WWL[1], and the wire WWL[ A high-level potential is continuously supplied to the wirings WWL[2] to WWL[n]. The transistor WTr in the memory cell MC[1] is turned off, and the memory cell MC[2 ] to memory cell MC[n], the transistors WTr of the memory cells MC[n] are in a fully on state. Then, data D[2] is supplied to the wiring WBL. Each transistor WTr of the memory cell MC[n] is in a fully on state. Therefore, the data D[2] reaches the memory node of the memory cell MC[2] and is written. Also, the transistor WTr of the memory cell MC[1] is in the off state. Therefore, the data D[1] stored in the memory cell MC[1] is written from time T12 onwards. It is not lost by the write operations up to time T13.

[0046] Between time T13 and time T14, the memory between time T11 and time T12 The write operation of data D[1] to cell MC[1] and the write operation from time T12 to time T13 Similarly to the write operation of data D[2] to memory cell MC[2] between Data D[3] to D[n-1] are sequentially stored in the memory cells MC[3] to MC[n-1]. Specifically, the data D[n-1] is written to the memory cell where the data has already been written. memory cells MC[1] to MC[j-1] (j is an integer between 3 and n-1) The transistor WTr is turned off, and the memory cell MC in which data is not written is The transistors WTr included in the memory cells MC[j] to MC[n] are fully turned on. Data D[j] is supplied from the wiring WBL and written to the memory node of memory cell MC[j]. Then, when writing of data D[j] to memory cell MC[j] is completed, , the transistor WTr included in the memory cell MC[j] is turned off, and the wiring WBL Data D[j+1] is supplied and written to the memory node of memory cell MC[j+1]. The write operation when j is n-1 is performed at time T14, which will be described next. This refers to the operation from time T10 to time T15.

[0047] At time T14, the wirings WWL[1] to WWL[n-1] are supplied with a low-level potential. is supplied, and a high-level potential is continuously supplied to the wiring WWL[n]. The transistors WTr included in the memory cells MC[1] to MC[n-1] are turned on. The memory cell MC[n] is in an off state, and each transistor WTr of the memory cell MC[n] is in a fully off state. Then, data D[n] is supplied to the wiring WBL. Since each transistor WTr in [n] is fully on, The data D[n] reaches the memory node of the memory cell MC[n] and is written therein. The transistors WTr of the memory cells MC[1] to MC[n-1] are in the off state. Therefore, the data stored in each of the memory cells MC[1] to MC[n-1] is The data D[1] to D[n-1] held in the buffer are read from time T14 to time T15. will not be lost by any write operations up to

[0048] By the above-described operation, in any one of the semiconductor devices shown in FIGS. Data can be written to the memory cells MC of the semiconductor device.

[0049] FIG. 4B shows data D[1] to data D[n] stored in memory cells MC[1] 1 to MC[n]. At this time, each memory cell To maintain the data stored in MC, the transistor WTr must be in the off state. Therefore, data is stored in the memory cells MC[1] to MC[n]. During a read operation, the potentials of the lines WWL[1] to WWL[n] are low level potentials. Let's say.

[0050] In the circuit configuration of the semiconductor device shown in FIG. In this case, the transistor RTr of the other memory cell MC is turned on sufficiently, and then the The transistor RTr of the specific memory cell MC is operated in the saturation region. A current flows between the source and drain of the transistor RTr of the specific memory cell MC. The current flowing through the memory cell MC is determined by the source-drain voltage and the data stored in the memory cell MC. The data is determined based on the

[0051] For example, the data stored in the memory cell MC[k] (k is an integer between 1 and n) Consider the case where data is read. At this time, the memory cells M excluding the memory cell MC[k] Each of the transistors RTr of the memory cells MC[1] to MC[n] is turned on sufficiently. In order to achieve this state, high voltage is applied to the wiring RWL[1] to wiring RWL[n] except for the wiring RWL[k]. A level potential is supplied.

[0052] On the other hand, the transistor RTr of the memory cell MC[k] is In order to turn on the memory cell MC[k] in response to the data It is necessary to set the potential to the same as that of the wiring RWL[k] when writing. The potential of the wiring RWL[k] during the write and read operations is set to a low level potential. think.

[0053] For example, a potential of +3V is applied to the node N1 and a potential of 0V is applied to the node N2. The potential of the node N2 is measured after floating. When the potentials of the wirings RWL[1] to RWL[n] are set to a high level, The transistors of the memory cells MC[1] to MC[n] except for the memory cell MC[k] are On the other hand, the transistor RTr of the memory cell MC[k] The voltage between the first and second terminals of the RTr is the voltage between the gate potential of the transistor RTr and the node The potential of the node N2 is determined by the potential of the memory node N1 of the memory cell MC[k]. It depends on the data held in the card.

[0054] In this way, the data stored in the memory cell MC[k] can be read. do.

[0055] Based on the above, an example of operation shown in the timing chart of FIG. 4(B) will be described. At time T20, the wiring WWL[1] to WWL[n], the wiring RWL[1] to RWL[n], The potentials of the wiring RWL[n], the wiring WBL, the node N1, and the node N2 are low level. In particular, node N2 is in a floating state. The memory nodes of the memory cells MC[1] to MC[n] are respectively It is assumed that data D[1] to D[n] are held.

[0056] At time T21, a low level potential is supplied to the wiring RWL[1], and the wiring RWL[ A high-level potential is supplied to the wirings WWL[n] to WWL[n]. The transistors RTr of the memory cells MC[2] to MC[n] are sufficiently turned on. Then, the transistor RTr of the memory cell MC[1] is in the state of the memory cell MC[ The data D[1] stored in the memory node of the transistor D[1] is turned on. The potential V is applied to the line RBL. R As a result, the potential of node N1 becomes V R Then, node N The potential of node N2 is V R The potential of the node N2 is the memory The potential of the node N2 is determined according to the data held in the node. D[1 ] Then, the potential V of the node N2 D[1] By measuring The data D[1] stored in the memory node of C[1] can be read.

[0057] At time T22, a low-level potential is supplied to the wirings RWL[1] to WWL[n]. A low level potential is supplied to the node N2, and then the node N2 is That is, between time T22 and time T23, the wiring RW The potentials of the wirings WWL[1] to WWL[n] and the node N2 are changed from time T20 to time T The situation is the same as that up to 21. The wiring RBL continues to be connected to the potential V R supply In this operation example, the wiring RBL is supplied with a low level potential at time T After 21, the potential V R will continue to be supplied.

[0058] At time T23, a low level potential is supplied to the wiring RWL[2], and the wiring RWL[ A high-level potential is supplied to the wirings RWL[1] to WWL[n]. As a result, the memory cells MC[1], MC[3] to MC[n] have Each transistor RTr is fully turned on. Then, memory cell MC[2] The transistor RTr is connected to the data stored in the memory node of the memory cell MC[2]. D[2] is turned on. Also, the wiring RBL is at a potential V R continues to be supplied As a result, the potential of the node N2 becomes equal to the potential V of the node N1. R The potential of node N2 is The data stored in the memory node of the memory cell MC[2] is used as the The potential of node N2 is V D[2] Then, the potential V of the node N2 D[2] Measure By this, the data D[2] stored in the memory node of the memory cell MC[2] is read. You can put it out.

[0059] Between time T24 and time T25, the memory between time T20 and time T22 Read operation of data D[1] from cell MC[1] and from time T22 to time T24 The read operation of data D[2] from memory cell MC[2] during The data D[ Specifically, data D[n-1] to D[n-3] are read from memory cells MC[j] (j is When data D[j] is read from node N1, the voltage of node N2 is After the potential is set to a low level and the node N2 is set to a floating state, the wiring RWL A high-level potential is supplied to the wirings RWL[1] to RWL[n] except for [j]. The transistors of the memory cells MC[1] to MC[n] excluding the memory cell MC[j] The transistor RTr is fully turned on, and the transistor RT r is turned on according to the data D[j]. Next, the potential of the node N1 is V R To make Then, the potential of the node N2 becomes a potential according to the data D[j], and by measuring this potential, The data D[j] can be read out by the above. After the data D[j] has been read, the wiring RWL is A low-level potential is supplied to the wirings WWL[1] to WWL[n], and a low-level potential is supplied to the node N2. Then, node N2 is left floating. Preparation refers to the operations between time T25 and time T26.

[0060] At time T25, a low-level potential is supplied to the wirings RWL[1] to WWL[n]. A low level potential is supplied to the node N2, and then the node N2 is That is, between time T25 and time T26, the wiring RW The potentials of the wirings WWL[1] to WWL[n] and the node N2 are changed from time T20 to time T The situation is the same as that up to 21. The wiring RBL continues to be connected to the potential V R supply In this operation example, the wiring RBL is supplied with a low level potential at time T After 21, the potential V R will continue to be supplied.

[0061] At time T26, a low-level potential is supplied to the wiring RWL[n], and the wiring RWL[ A high-level potential is supplied to the wirings WWL[1] to WWL[n-1]. The transistors RTr of the memory cells MC[1] to MC[n-1] are sufficiently Then, the transistor RTr of the memory cell MC[n] is turned on. The transistor MC[n] is turned on in accordance with the data D[n] stored in the memory node of the transistor MC[n]. In addition, the wiring RBL has a potential V R This causes the voltage at node N2 to The potential V of the node N1 R The potential of node N2 is the memory node of memory cell MC[n]. Here, the potential of node N2 is determined according to the data held in V D[n] Tosu Then, the potential V of the node N2 D[n] By measuring ], the data D[n] stored in the memory node can be read.

[0062] By the above-described operation, each memory cell of the semiconductor device shown in FIGS. Data can be read from the MC.

[0063] <Structure examples and manufacturing methods> In order to facilitate understanding of the structure of the semiconductor device of this embodiment, a manufacturing method thereof will be described below. Reveal.

[0064] 5A and 5B are schematic diagrams showing the semiconductor device shown in FIGS. 1A to 1C. FIG. 5A shows a top view of the semiconductor device, and FIG. 5B shows a cross section of FIG. 5A. A cross-sectional view corresponding to the chain line A1-A2 is shown.

[0065] The semiconductor device includes a wiring RWL, a wiring WWL, and an insulator (shown by hatching in FIG. 5). and a laminated structure in which an opening is provided in the structure, and The conductor PG is formed so that the gap is filled. The wiring ER is formed on the conductor PG. As a result, the wiring ER and the wiring RWL or the wiring WWL are electrically connected. There are.

[0066] In addition, the structure is provided with a wiring RWL and a wiring WWL that penetrate the structure at once. An opening is formed. Then, a metal is formed in the region AR through which the wiring RWL and the wiring WWL penetrate. In order to provide a memory cell MC, an insulator, a conductor, and a semiconductor are formed in the opening. The conductor functions as the wiring WBL and the wiring RBL, and the semiconductor functions as the It functions as the channel forming region of the transistors WTr and RTr. The region in which the insulator, the conductor, and the semiconductor are formed in the opening is shown as region HL. It should be noted that a back gate is provided in the transistor of the memory cell MC. In this case, the conductor in the region HL is a wiring for electrically connecting to the back gate. It may also function as a line BGL.

[0067] That is, in FIG. 5, the semiconductor device shown in any one of FIGS. 1(A), 1(B), and 1(C) is D1, and the semiconductor device shown in FIG. 2 or 3 is configured in the area SD2. This shows:

[0068] In the following manufacturing method example 1 and manufacturing method example 2, in order to form memory cells MC in the region AR, This article explains how to do this.

[0069] <<Production method example 1>> 6 to 10 are cross-sectional views illustrating a manufacturing example of the semiconductor device shown in FIG. In particular, cross-sectional views of the transistors WTr and RTr in the channel length direction are shown. In addition, in the cross-sectional views of FIGS. 6 to 10, some elements are omitted for clarity. is doing.

[0070] As shown in FIG. 6A, the semiconductor device of FIG. 1A has a substrate (not shown) above it. an insulator 101A disposed on the insulator 101A, a conductor 131A disposed on the insulator 101A, and a conductor Insulator 101B is disposed on conductor 131A, and conductor 132 is disposed on insulator 101B. A, an insulator 101C disposed on the conductor 132A, and a A conductor 131B, an insulator 101D disposed on the conductor 131B, and a and an insulator 101E disposed on the conductor 132B. Hereinafter, a laminate having a plurality of conductors and a plurality of insulators will be referred to as laminate 1. Write it as 00.

[0071] The substrate may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, and stabilized Zirconia substrates (such as yttria-stabilized zirconia substrates) and resin substrates are also available. The semiconductor substrate may be, for example, a single semiconductor substrate such as silicon or germanium, or a carbon substrate. Silicon arsenide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, oxide There are also compound semiconductor substrates made of gallium. A semiconductor substrate having a body region, such as SOI (Silicon On Insulator) ) substrates. Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. There are also substrates with metal nitrides and substrates with metal oxides. Furthermore, a substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a conductor or a semiconductor is provided on a semiconductor substrate, Or a substrate provided with an insulator, a substrate provided with a semiconductor or an insulator on a conductive substrate, etc. Alternatively, a substrate having an element mounted on it may be used. The elements include a capacitance element, a resistance element, a switch element, a light-emitting element, a memory element, and the like.

[0072] A flexible substrate may also be used as the substrate. As a method of providing a transistor, a transistor is fabricated on a non-flexible substrate, and then the transistor is Another method is to peel off the substrate and transfer it to a flexible substrate. It is preferable to provide a peeling layer between the substrate and the transistor. Alternatively, a sheet, film, foil, or the like may be used. The substrate may also be stretchable. The substrate may also have the property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate may have a property of not returning to its original shape. m or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less The thickness of the substrate is less than 1 μm. In addition, by making the substrate thinner, it is possible to reduce the weight of the device when using glass, etc. Some materials have elasticity and return to their original shape when bending or pulling is stopped. Therefore, it is necessary to reduce the shock that may be applied to the semiconductor device on the board when it is dropped. That is, a robust semiconductor device can be provided.

[0073] The flexible substrate may be, for example, a metal, an alloy, a resin, or a glass, or The substrate, which is a flexible substrate, has a low linear expansion coefficient. The flexible substrate is preferably a wire substrate, for example, since it is less likely to deform due to the environment. Expansion rate is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less The resin may be, for example, polyester, polyolefin, or poly. Amides (nylon, aramid, etc.), polyimides, polycarbonates, acrylics, etc. In particular, aramid has a low linear expansion coefficient and is therefore suitable as a flexible substrate. .

[0074] In the manufacturing example described in this embodiment, a heat treatment is included in the manufacturing process. It is preferable to use a material that has high heat resistance and a low coefficient of thermal expansion.

[0075] The conductor 131A (conductor 131B) functions as the wiring WWL shown in FIG. The conductor 132A (the conductor 132B) functions as the wiring RWL shown in FIG.

[0076] The conductors 131A, 131B, 132A, and 132B may be, for example, , aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum , tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconia Materials containing one or more metal elements selected from the group consisting of sulphur, beryllium, indium, ruthenium, etc. In addition, polycrystalline silicon containing impurity elements such as phosphorus can be used. Alternatively, a semiconductor having high electrical conductivity, such as nickel silicide, may be used. .

[0077] The conductors, particularly the conductors 131A and 131B, are made of semiconductor 1 51, semiconductor 152, semiconductor 153a, and semiconductor 153b are included in the applicable metal oxides A conductive material containing the metal element and oxygen may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Conductive materials may also be used. Indium tin oxide, indium containing tungsten oxide, etc. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon-added Indium tin oxide containing nitrogen may also be used. By using such a material, water can be prevented from entering from surrounding insulators. It may be possible to capture the element.

[0078] In addition, the conductors, particularly the conductors 132A and 132B, may be water or hydrogen. It is preferable to use a conductive material that has the function of suppressing the permeation of impurities. tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. It is preferable that the layer is a single layer or a multilayer.

[0079] Furthermore, a plurality of conductors made of the above materials may be stacked. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated layer that combines the material containing the metal element and the conductive material containing nitrogen is also available. In addition, a material containing the above-mentioned metal element, a conductive material containing oxygen, and a material containing nitrogen may be used. A laminated structure may be formed by combining a conductive material containing a silicon dioxide atom with a conductive material containing silicon dioxide. By applying an insulator having an excess oxygen region as an insulator for the conductor, the Oxygen may diffuse into the metal-containing material and the oxygen-containing material. A laminated structure can be formed by combining a conductive material containing By applying an insulator having an excess nitrogen region as an insulator in contact with the periphery of a conductor, the Nitrogen may diffuse into the area where the body is in contact with the insulator, which can cause the metal element to A laminated structure can be formed by combining a material containing nitrogen and a conductive material containing nitrogen. .

[0080] The conductors 131A, 131B, 132A, and 132B are The materials may be the same or different from each other. Conductor 131A, conductor 131B, and conductor 132A that constitute a semiconductor device according to one embodiment of the present invention The materials for the conductor 132B can be appropriately selected and used.

[0081] The insulators 101A to 101E are made of a material having a reduced concentration of impurities such as water or hydrogen. For example, the hydrogen of the insulators 101A to 101E is preferably The amount of desorption was measured by thermal desorption spectroscopy (TDS). In spectroscopy, the temperature ranges from 50 to 500°C and the hydrogen molecules are converted to hydrogen molecules. The calculated amount of desorption is converted into the amount per area of ​​any one of the insulators 101A to 101E. 2 x 10 15 molecules / cm2 Less than 1 × 10 15 molec ules / cm 2 Less than or equal to 5 × 10 14 molecules / cm 2 Below In addition, the insulators 101A to 101E may be formed of a material that releases oxygen when heated. As described above, the conductor 131A and the conductor 131B may be formed using an insulating material. 31B, the conductor 132A, and the conductor 132B are made of a material containing a metal element and a conductive material containing oxygen. It is possible to form a laminated structure in which the above materials are combined.

[0082] The insulators 101A to 101E may include, for example, boron, carbon, nitrogen, oxygen, and fluorine. Fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, gel Magnesium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum Insulators containing silicon dioxide can be used in a single layer or a multilayer structure. Materials including silicon nitride or silicon oxynitride can be used.

[0083] In this specification, silicon oxynitride refers to a material having a higher content of oxygen than nitrogen in its composition. Silicon nitride oxide refers to a material that contains more nitrogen than oxygen. In this specification, aluminum oxynitride refers to a material with a high content. Aluminum oxide nitride is a material that has a higher oxygen content than nitrogen. It refers to a material that contains more nitrogen than oxygen as a constituent.

[0084] In the next step, as shown in Figure 6(B), resist mask formation and etching are performed. Therefore, an opening 191 can be formed in the laminate 100 shown in FIG. 6(A). .

[0085] The resist mask is formed by using a lithography method, a printing method, an inkjet method, or the like. If the resist mask is formed by the inkjet method, a photomask can be used. As no etching is required, the manufacturing cost can be reduced. Either a rubbing method or a wet etching method may be used, or both may be used.

[0086] Then, as shown in FIG. 7(A), the side surface of the opening 191 is removed by etching or the like. The conductors 132A and 132B on the side are removed, and a recess 192A (recess Here, the conductor 132A (conductor 132B) is formed as a multilayer structure. A material from which the conductor 132A (conductor 132B) of the layer 100 can be selectively removed (The insulators 101A to 101E and the conductor 131A (conductor 131B) are more elastic than the insulators 101A to 101E and the conductor 131A (conductor 131B). It is assumed that materials with high etching rates are used.

[0087] The recess 192A (recess 192B) is formed in the step of manufacturing the semiconductor device shown in FIG. In this step, a sacrificial layer is provided in the area where the opening 191 and the recess 192A (recess 192B) are to be formed. Therefore, the opening 191 may be formed at the same time as the opening 192 in the manufacturing process of the semiconductor device shown in FIG. 6B. Furthermore, when the opening 191 is formed without providing a sacrificial layer, the recess 192A (recess 19 2B) can also be formed.

[0088] In the next step, as shown in FIG. 7(B), the side surface of the opening 191 shown in FIG. 7(A) and An insulator 102 is deposited in the recessed portion.

[0089] The insulator 102 may be made of an insulating material that has a function of suppressing oxygen permeation. For example, the insulator 102 may be silicon nitride, silicon nitride oxide, or silicon oxide nitride. It is preferable to use silicon, aluminum nitride, aluminum oxide nitride, etc. By forming such an insulator 102, oxygen can penetrate through the insulator 102 and enter the It is possible to prevent the conductivity of the conductor 133 from decreasing due to oxidation of the conductor 133. .

[0090] In the next step, as shown in FIG. 8(A), the side surface of the opening 191 shown in FIG. 7(B) and In other words, the conductive material 133 is formed on the surface on which the insulator 102 is formed. A current collector 133 is formed.

[0091] The conductor 133 may be the conductor 131A, the conductor 131B, the conductor 132A, and the conductor 131B. Materials applicable to the conductive body 132B can be used. In particular, conductive materials can be used. Preferably, a high-quality material is applied to the conductor 133 .

[0092] In the next step, as shown in FIG. 8(B), resist mask formation and etching are performed. Therefore, the conductor 133 included in the opening 191 is removed so that the conductor 133 remains only in the recessed portion. 33 is removed. This forms the conductors 133a and 133b. At this time, the insulators 101A to 101E, the conductor 131A, and the conductor 131B A part of the insulator 102 may be removed so long as it is not exposed in the opening 191. .

[0093] For details about the formation of the resist mask and the etching process, please refer to the explanation of FIG. 6(B). To pour drinks.

[0094] Incidentally, the conductor 133a (conductor 133b) is not only a capacitor element CS shown in FIG. That is, in the region 181A (region 181B) shown in FIG. A capacitance element CS is formed therein.

[0095] In the next step, as shown in FIG. 9(A), the insulator 10 located on the side surface of the opening 191 is 2. A semiconductor 151 is formed on the surface on which the conductor 133a and the conductor 133b are formed.

[0096] The semiconductor 151 is made of a material containing a metal oxide described in the third embodiment. It is preferable to do so.

[0097] When the semiconductor 151 contains a metal oxide, the insulating layer in contact with the semiconductor 151 The body 102 is an insulator that has the function of suppressing the permeation of not only oxygen but also impurities such as water or hydrogen. It is preferable to use a conductive material. Impurities such as water or hydrogen penetrate through O2 and react with oxygen contained in the semiconductor 151. When water is generated in the semiconductor 151, the semiconductor 151 Oxygen vacancies may be formed within the crystal. Impurities such as hydrogen may enter these oxygen vacancies. Therefore, electrons that become carriers may be generated in the semiconductor 151. If a region containing a large amount of hydrogen exists, the region is included in the channel formation region. The transistor tends to have a normally-on characteristic. and an insulating material that has the function of suppressing the permeation of not only oxygen but also impurities such as water and hydrogen. It is desirable to use

[0098] Furthermore, when the semiconductor 151 contains a metal oxide, the semiconductor 151 has a region where the metal oxide is formed. The conductivity may differ depending on the region. Among the regions, the regions on the surface where the insulator 102 is formed are illustrated as region 151a and region 151b. The region on the surface where the conductor 133a (conductor 133b) is formed is illustrated as region 151c. In particular, the region 151a is a region overlapping the side surface of the conductor 131A (conductor 131B). The region 151b overlaps with the side surfaces of the insulator 101A (insulators 101B to 101E). The region 151c is in contact with the conductor 133a (conductor 133b). Therefore, impurities such as hydrogen or water contained in the conductor 133a may diffuse into the region 151c. As described above, when impurities such as water or hydrogen are diffused into the semiconductor 151, Since carrier electrons may be generated, the resistance of the region 151c may be reduced. Therefore, the region 151c has higher conductivity than the regions 151a and 151b. become.

[0099] The region 151a is a region that will become a channel formation region of a transistor. When the transistor is in an on state, the region 151a has a lower resistance than the region 151b. The conductivity increases.

[0100] In the next step, as shown in FIG. 9B, the semiconductor 15 located on the side of the opening 191 is On the surface of the substrate 1, an insulator 103 and a semiconductor 152 are formed in this order.

[0101] The insulator 103 may be made of any of the materials applicable to the insulator 102 described above. In particular, when the semiconductor 151 contains a metal oxide, the insulator 102 is oxygen. In addition, it must be an insulating material that has the function of suppressing the permeation of impurities such as water or hydrogen. is preferred.

[0102] In the area 182A (area 182B) shown in FIG. 9B, Specifically, the region 182A (region 182B) has a transistor WTr. In this case, the region 151a of the semiconductor 151 functions as a channel forming region of the transistor WTr. The two regions 151b of the semiconductor 151 function as source electrodes of the transistors WTr. , which functions as a drain electrode, and the conductor 132A functions as a gate electrode of the transistor WTr. In particular, when a material containing a metal oxide is used as the semiconductor 151, The transistor WTr constitutes an OS transistor.

[0103] The semiconductor 152 includes the metal oxide described in Embodiment 3, similarly to the semiconductor 151. In addition, as a substitute for the semiconductor 152, a semiconductor such as silicon can be used. A conductive material can be used.

[0104] In the next step, as shown in FIG. 10(A), an insulator 104 is formed on the surface on which the semiconductor 152 is formed. A conductor 134 is then deposited so as to fill the remaining opening 191 .

[0105] The insulator 104 is made of a material that can be used for the insulators 102 and 103 described above. It is possible.

[0106] The conductor 134 may be the above-mentioned conductor 131A, conductor 131B, conductor 132A, Materials applicable to the conductor 132B, the conductor 133a, and the conductor 133b can be used. do.

[0107] In the area 183A (area 183B) shown in FIG. 10(A), Specifically, the transistor RTr shown in FIG. 18 is configured in the region 183A (region 183B). In the figure, the region 151c of the semiconductor 151, the two regions 151b, and the conductor 133a (conductor The semiconductor 133b functions as the gate electrode of the transistor RTr, and the semiconductor 152 functions as the gate electrode of the transistor RTr. The conductor 134 functions as a channel forming region of the transistor RTr. In particular, a material containing a metal oxide is used as the semiconductor 152. In this case, the transistor RTr constitutes an OS transistor.

[0108] By carrying out the steps from FIG. 6(A) to FIG. 10(A), the semiconductor shown in FIG. A device can be fabricated.

[0109] One embodiment of the present invention is not limited to the structural example of the semiconductor device illustrated in FIG. One embodiment of the present invention is to use the semiconductor device shown in FIG. 10(A) as needed, depending on the situation, or as required. The conductor device may be modified as appropriate.

[0110] For example, as described above, one embodiment of the present invention is a transistor W It is also possible to provide a semiconductor device in which the back gate is not provided for the transistors Tr and RTr. When manufacturing the semiconductor device shown in FIG. 1C, in the process of manufacturing FIG. 10(B) can be carried out instead of the process shown in FIG. 10(A). ) is an insulating material that fills the opening 191 instead of the conductor 134 in FIG. The insulator 105 is formed on the insulating film 104. Any material that can be applied as such can be used.

[0111] Furthermore, for example, one embodiment of the present invention improves the switching characteristics of the transistor WTr. For this purpose, the configuration of the gate electrode of the transistor WTr is changed from that shown in FIG. 11(A), (B), and 12(A) and (B) show a method for manufacturing the semiconductor device. 11(A) shows an example of the opening 191 shown in FIG. The conductor 131A (conductor 131B) is removed, and the recess 193A (recess 193B) is formed. Here, the conductor 131A (conductor 131B) is formed as follows: A material that allows the conductor 131A (conductor 131B) of the laminate 100 to be selectively removed The material (conductor 132A (conductor 132B) is thicker than the insulators 101A to 101E) High tin rate materials) are applied.

[0112] The recess 193A (recess 193B) is formed in the step of manufacturing the semiconductor device shown in FIG. In the next step, a sacrificial layer is provided in the area where the opening 191 and the recess 193A (recess 193B) are to be formed. In addition, the opening 191 may be formed at the same time as the opening 191 in the manufacturing process of the semiconductor device shown in FIG. 6B. Furthermore, when the opening 191 is formed without providing a sacrificial layer, the recess 193A (recess 193B) is automatically formed. 93B) can also be formed.

[0113] In the next step, as shown in FIG. 11(B), the side surface of the opening 191 shown in FIG. 11(A), The semiconductor 153 is deposited in the recess 193A (recess 193B).

[0114] The semiconductor 153 is a material containing a metal oxide described in Embodiment 3. This shall be done.

[0115] In the next step, as shown in FIG. 12(A), a resist mask is formed and an etching process is performed. By this, the opening is formed so that the semiconductor 153 remains only in the recess 193A (recess 193B). The semiconductor 153 included in the portion 191 is removed. After the treatment, etching is performed to remove the conductor 132A (conductor 132B), forming a recess. 192A (recess 192B) is formed.

[0116] Next, similarly to the step of FIG. 8(B), a semiconductor 153a (semiconductor The insulator 102 is formed to cover the semiconductor 153 (semiconductor 153b). When a material containing a metal oxide is used as the semiconductor 153a (semiconductor 153b ) comes into contact with the insulator 102, and impurities such as hydrogen and water contained in the insulator 102 are converted into semiconductors. The semiconductor 153a (semiconductor 153b) is diffused. By contacting the conductor 133a (conductor 133b), the conductor 133a (conductor 133b) Impurities such as hydrogen and water contained in the semiconductor 153a (semiconductor 153b) diffuse into the semiconductor 153a (semiconductor 153b). The semiconductor 153a (semiconductor 153b) has a role of collecting impurities such as hydrogen and water. As a result, the resistance of the semiconductor 153a (semiconductor 153b) decreases, and the transistor WT After this, the gate electrode of ... By carrying out the same steps as in the above, the semiconductor device shown in FIG. 12(B) can be fabricated. Cut.

[0117] For example, one embodiment of the present invention is a transistor having a first terminal, Or to reduce the electrical resistance between the second terminal and the gate of the transistor RTr. As a result, the configuration of the gate electrode of the transistor RTr is changed from that shown in FIG. 13A and 13B show an example of a method for manufacturing the semiconductor device. 3(A), the conductor 132A (conductor 132B) are removed, but insulators 101A to 101E are also removed. This shows the step of forming the recess 194B (recess 194A, recess 194C). Now, let us consider the conductor 132A (conductor 132B) and the insulators 101A to 101E. In the laminate 100, the conductor 132A (conductor 132B) and the insulators 101A to 101B are The conductive material 101E is selectively removed (the conductive material 131A (the conductive material 131B) is removed). It is assumed that a material with a high etching rate is used.

[0118] The recess 194B (recess 194A, recess 194C) is formed in the semiconductor device shown in FIG. At this stage of the manufacturing process, the opening 191 and the recess 194B (recess 194A, recess 194C) A sacrificial layer is provided in the region where the opening 1 is to be formed in the manufacturing process of the semiconductor device shown in FIG. Alternatively, when the opening 191 is formed without providing a sacrificial layer, the opening 191 may be formed by itself. In some cases, the recess 194B (recess 194A, recess 194C) can be formed dynamically.

[0119] In addition, in FIG. 13(A), the recess 194B (recess 194A, recess 194C) has an insulating Insulator 101B, insulator 101C (insulator 101A, insulator 101D, insulator 101E) The conductor 132A (conductor 132B) is more largely removed than the conductor 132B. 2A (conductor 132B), the insulator 101B, the insulator 101C (insulator 101A, The insulating layer 101B may be removed to a greater extent than the insulating layer 101D. , insulator 101C (insulator 101A, insulator 101D, insulator 101E), and conductor 13 2A (conductor 132B) may be formed to the same depth.

[0120] FIG. 13B shows an example of the structure of a semiconductor device after going through the process of FIG. 13A. After the step of FIG. 13(A), the recess 194B (recess 194A, recess 194C) is filled. A conductor 133 is formed as a film so as to form the gate electrode of the transistor RTr. 3(A), a conductor 133a serving as the gate electrode of the transistor RTr, a conductor 133b and conductor 133c are shown. From this point on, from FIG. 9(A) to FIG. 10(A), By carrying out similar steps, the semiconductor device shown in FIG. 13(B) can be fabricated. This semiconductor device has a structure in which the semiconductor 151 and the conductor 13 are arranged in a more uniform manner than the semiconductor device shown in FIG. 3a (conductor 133b) has a large contact area. When a material having a metal oxide is used, the semiconductor device shown in FIG. 13B has the same structure as that shown in FIG. Since the region 151b shown in FIG. 1 does not exist, the first terminal or the second terminal of the transistor WTr , the electrical resistance between the gate of the transistor RTr and can be reduced.

[0121] <<Production method example 2>> Here, as a semiconductor device of this embodiment, an example of a structure different from that of Manufacturing Method Example 1 will be described. This will be explained with reference to FIGS. 14 to 16.

[0122] 14 to 16 are, similarly to FIGS. 6 to 10, examples of manufacturing the semiconductor device shown in FIG. 1A. 1 is a cross-sectional view for explaining the transistor WTr and the transistor RTr. 14 to 16 are cross-sectional views in the longitudinal direction of the panel. As with 0, some elements have been omitted for clarity.

[0123] The first step is the same as that described in the first example of the manufacturing method from FIG. 6(A) to FIG. 7(B). Please refer to the description.

[0124] The process shown in FIG. 14(A) is a continuation of the process shown in FIG. 7(B). In (A), a semiconductor is formed on the side surface of the opening 191 shown in FIG. 7(B) and in the recess formed therein. That is, the semiconductor 151 is formed on the surface on which the insulator 102 is formed.

[0125] As the semiconductor 151, it is preferable to use the semiconductor described in the third embodiment.

[0126] In the next step, as shown in FIG. 14(B), the side surface of the opening 191 shown in FIG. 14(A), A conductor 133 is deposited in the recess formed.

[0127] For the conductor 133, the description of the conductor 133 in Manufacturing Method Example 1 can be referred to.

[0128] In the next step, as shown in FIG. 15(A), a resist mask is formed and an etching process is performed. Therefore, the conductor 133 included in the opening 191 is removed so that the conductor 133 remains only in the recess. 133 is removed. This forms the conductors 133a and 133b. At this time, if the insulator 102 is not exposed in the opening 191, the semiconductor 151 A portion may be removed.

[0129] For details about the formation of the resist mask and the etching process, please refer to the explanation of FIG. 6(B). To pour drinks.

[0130] Incidentally, the conductor 133a (conductor 133b) is not only a capacitor element CS shown in FIG. In other words, the area 181A (area 181B) shown in FIG. In this region, a capacitance element CS is formed.

[0131] For the semiconductor 151, the description of the semiconductor 151 in Fabrication Method Example 1 can be referred to. In addition, when the semiconductor 151 contains a metal oxide, the semiconductor 151 has a region 151a, a region The area can be divided into areas 151a, 151b, and 151c. Regarding 51c, the regions 151a, 151b, and 151c described in Example 1 of the manufacturing method are Please refer to the description below.

[0132] In the next step, as shown in FIG. 15(B), the conductor 1 located on the side surface of the opening 191 is The insulator 103 is formed on the surface on which the conductor 133a, the conductor 133b, and the semiconductor 151 are formed. Then, a semiconductor 152 is formed on the surface on which the insulator 103 is formed.

[0133] For the insulator 103, the description of the insulator 103 in Manufacturing Method Example 1 can be referred to.

[0134] For the semiconductor 152, the description of the semiconductor 152 in Manufacturing Method Example 1 can be referred to.

[0135] In the area 182A (area 182B) shown in FIG. 15(B), Specifically, the transistor WTr shown in FIG. 18 is configured in the region 182A (region 182B). In this case, the region 151a of the semiconductor 151 is used as a channel forming region of the transistor WTr. Each of the two regions 151b of the semiconductor 151 functions as a source voltage source for the transistor WTr. The conductor 132A functions as the gate electrode of the transistor WTr. In particular, when a material containing a metal oxide is used as the semiconductor 151, The transistor WTr constitutes an OS transistor.

[0136] In the next step, as shown in FIG. 16(A), an insulator 104 is formed on the surface on which the semiconductor 152 is formed. A conductor 134 is then deposited so as to fill the remaining opening 191 .

[0137] For the insulator 104, the description of the insulator 104 in Manufacturing Method Example 1 can be referred to.

[0138] For the conductor 134, the description of the conductor 134 in the manufacturing method example 1 can be referred to.

[0139] In the area 183A (area 183B) shown in FIG. 16(A), Specifically, the transistor RTr shown in FIG. 18 is configured in the region 183A (region 183B). In the figure, the region 151c of the semiconductor 151, the two regions 151b, and the conductor 133a (conductor The semiconductor 133b functions as the gate electrode of the transistor RTr, and the semiconductor 152 functions as the gate electrode of the transistor RTr. The conductor 134 functions as a channel forming region of the transistor RTr. In particular, a material containing a metal oxide is used as the semiconductor 152. In this case, the transistor RTr constitutes an OS transistor.

[0140] By carrying out the steps from FIG. 6(A) to FIG. 7(B) and FIG. 14(A) to FIG. 16(A), In this way, the semiconductor device shown in FIG. 1A can be manufactured.

[0141] One embodiment of the present invention is not limited to the structural example of the semiconductor device illustrated in FIG. One embodiment of the present invention is to use the semiconductor device shown in FIG. 16(A) as needed, depending on the situation, or as required. The conductor device may be modified as appropriate.

[0142] For example, as described above, one embodiment of the present invention is a transistor W It is also possible to provide a semiconductor device in which the back gate is not provided for the transistors Tr and RTr. When manufacturing the semiconductor device shown in FIG. 1C, in the process of manufacturing FIG. 16(B) may be carried out instead of the process shown in FIG. 16(A). 16(A) so that the opening 191 is filled with an insulator. The insulator 105 is formed, for example, as the insulator 104. Any material that can be applied can be used.

[0143] Furthermore, for example, one embodiment of the present invention improves the switching characteristics of the transistor WTr. For this purpose, the configuration of the gate electrode of the transistor WTr is changed from that shown in FIG. FIG. 17 shows an example of the configuration of the semiconductor device. The semiconductor device shown in FIG. When manufacturing the recess 19, as in the configuration example shown in FIG. 12(B) described in the manufacturing method example 1, The semiconductor 153a (semiconductor 153b) is formed so as to fill the recess 193B. Then, an insulating layer is formed on the side surface of the opening 191 so as to cover the semiconductor 153a (semiconductor 153b). The body 102 is formed. After that, the same steps as those shown in FIG. 14(A) to FIG. 16(A) are performed. By doing so, the semiconductor device shown in Fig. 17 can be constructed. The effect of this is shown in FIGS. 11(A), (B), 12(A), and 12(B) described in Example 1 of the manufacturing method. Please refer to the explanation in B).

[0144] For example, one embodiment of the present invention is a transistor having a first terminal, Or to reduce the electrical resistance between the second terminal and the gate of the transistor RTr. The configuration of the gate electrode of the transistor RTr is changed from that shown in FIG. FIG. 18 shows an example of the configuration of the semiconductor device. When manufacturing the device, the configuration example shown in FIG. 13(A) explained in Manufacturing Method Example 1 is manufactured. By carrying out the same steps as those shown in FIG. 14(A) to FIG. 16(A), the semiconductor device shown in FIG. The effect of constructing the device shown in FIG. Please refer to the description of FIG. 13(B) explained in 1.

[0145] A semiconductor capable of storing a large amount of data by the above-described Manufacturing Method Example 1 or Manufacturing Method Example 2 A device can be fabricated.

[0146] Here, the semiconductor device shown in FIG. 10(A) is placed in the region SD2 of the semiconductor device shown in FIG. 5(B). The cross-sectional view of the circuit configuration of FIG. 1(A) is shown in FIG. 19. , which correspond to the memory cell MC. As shown in FIG. 19, the conductors RWL and WWL The insulating layer and the laminated structure are provided with openings all at once, and the above-described manufacturing method example 1 is performed. Alternatively, the circuit configuration of FIG. 1A can be realized by fabricating the device as described in Fabrication Method Example 2. It is possible.

[0147] <Example of connection to peripheral circuits> The semiconductor device shown in Manufacturing Method Example 1 or Manufacturing Method Example 2 has a readout circuit and a processor in a lower layer. A peripheral circuit of the memory cell array, such as a recharge circuit, may be formed. The peripheral circuit is formed by forming a Si transistor on a silicon substrate or the like, and then In Example 1 or Manufacturing Method Example 2, a semiconductor device according to one embodiment of the present invention is formed on the peripheral circuit. In Figure 20(A), the peripheral circuit is made up of planar type Si transistors, and the upper layer 21A is a cross-sectional view of a semiconductor device according to one embodiment of the present invention formed in a peripheral circuit. The circuit is configured with a FIN type Si transistor, and the semiconductor device according to one embodiment of the present invention is mounted on the upper layer. 20(A) and 20(B) are merely examples. Therefore, the configuration of FIG. 10(A) is applied.

[0148] In FIG. 20(A) and FIG. 21(A), the Si transistors constituting the peripheral circuits are The element isolation layer 1701 is formed between a plurality of Si transistors. Conductors 1712 are formed as the source and drain of the Si transistor. The conductor 1730 is formed to extend in the channel width direction, and is connected to other Si transistors or It is connected to a conductor 1712 (not shown).

[0149] The substrate 1700 may be a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor Conductor substrates, compound semiconductor substrates made of silicon germanium, SOI substrates, etc. are used. It is possible.

[0150] The substrate 1700 may be, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, or the like. Substrates, flexible substrates, laminated films, paper containing fibrous materials, or base films, etc. Alternatively, a semiconductor element may be formed on a certain substrate, and then the semiconductor element may be transferred to another substrate. The conductive elements may be transposed. In FIG. 20(A) and FIG. 21(A), as an example, the substrate 170 Figure 0 shows an example using a single crystal silicon wafer.

[0151] Here, the details of the Si transistor will be explained. The Si transistor is a planar type shown in FIG. 20(B) which is a cross section in the channel length direction. The Si transistor is shown in a cross section in the channel width direction. A channel forming region 1793, a low concentration impurity region 1794, and High concentration impurity region 1795 (collectively referred to as impurity region) and the impurity region A conductive region 1796 is provided in contact with the channel forming region 1793. a gate insulating film 1797, a gate electrode 1790 provided on the gate insulating film 1797, The gate electrode 1790 has a sidewall insulating layer 1798 and a sidewall insulating layer 1799 formed on its side. The conductive region 1796 may be made of metal silicide or the like.

[0152] The FIN type Si transistor shown in FIG. 21(A) has a cross section in the channel length direction. The FIN type Si transistor shown in FIG. 21(B) is a cross-sectional view in the channel width direction. The Si transistor shown in FIGS. 21(A) and 21(B) has a channel forming region 1793 has a convex shape, and the gate insulating film 1797 and the gate electrode 179 are formed along the side and upper surfaces thereof. In this embodiment, when a part of a semiconductor substrate is processed to form a convex portion, However, the SOI substrate may be processed to form a semiconductor layer having a convex shape. The reference numerals shown in FIGS. 21(A) and (B) are the same as those shown in FIGS. 20(A) and (B).

[0153] It should be noted that the insulators, conductors, semiconductors, etc. disclosed in this specification and the like may be deposited by PVD (Physical Vapor Deposition). cal vapor deposition) method, CVD (Chemical Vapor Deposition) method, CVD (Chemical Vapor Deposition) method, The PVD method can be, for example, , sputtering method, resistance heating evaporation method, electron beam evaporation method, PLD (Pulsed Laser Deposition) In addition, the CVD method is a plasma In particular, the thermal CVD method can be used to form the film. For example, MOCVD (Metal Organic Chemical Vapor Dep. osition method and ALD (Atomic Layer Deposition) method. Examples include:

[0154] The thermal CVD method is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no further processing is required.

[0155] In the thermal CVD method, the source gas and oxidant are simultaneously fed into a chamber, and the chamber is heated to atmospheric pressure. Alternatively, a film is formed by reacting the material near or on the substrate under reduced pressure and depositing the material on the substrate. You may go.

[0156] In addition, in the ALD method, the pressure inside the chamber is atmospheric or reduced, and the source gas for the reaction is The gases may be introduced into the chamber in sequence, and the film may be formed by repeating this gas introduction sequence. For example, by switching each switching valve (also called high-speed valve), two or more types of The above source gases are supplied to the chamber in order, and the first An inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the raw material gas. The second source gas is introduced. When an inert gas is introduced at the same time, the inert gas is It acts as a carrier gas, and even if an inert gas is introduced at the same time as the second source gas is introduced, Alternatively, instead of introducing an inert gas, the first source gas may be discharged by vacuum evacuation. After that, a second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first thin film. The first thin layer is formed, and then reacts with the second source gas introduced later, and the second thin layer is formed on the first thin layer. The order of gas introduction is controlled until the desired thickness is reached. By repeating the above steps several times, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the gas introduction sequence is repeated. This is possible and is suitable for fabricating miniaturized FETs.

[0157] Thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described above. It is possible to form various films such as metal films, semiconductor films, and inorganic insulating films. When forming a-Zn-O film, trimethylindium (In(CH3)3), ... Using methylgallium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) Furthermore, the present invention is not limited to these combinations, and trimethylgallium may be replaced with triethylgallium. Zinc (Ga(C2H5)3) can also be used, and diethylzinc ( Zn(C2H5)2) can also be used.

[0158] For example, when forming a hafnium oxide film using a film forming apparatus that uses ALD, the solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl Hafnium amides (hafnium amides such as TDMAH and Hf[N(CH3)2]4) Two types of gases are used: the vaporized source gas and ozone (O3) as an oxidizing agent. Other materials include tetrakis(ethylmethylamido)hafnium.

[0159] For example, when forming an aluminum oxide film using an ALD film forming device, A liquid containing a catalyst and an aluminum precursor compound (trimethylaluminum (TMA), Al(C) Two types of gases are used: vaporized H3)3) and H2O as an oxidizing agent. Other materials include tris(dimethylamido)aluminum and triisobutylaluminum. Aluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanediol), Onato), etc.

[0160] For example, when forming a silicon oxide film using a film forming device that uses ALD, Chlorodisilane is adsorbed onto the surface to be coated, and the radicals of oxidizing gases (O2, nitrous oxide) are removed. The adsorbate is reacted with the adsorbate.

[0161] For example, when forming a tungsten film using an ALD deposition system, WF6 The initial tungsten film was formed by sequentially introducing BH gas and BH gas. The tungsten film is formed by repeatedly introducing B2H6 gas and H2 gas in sequence. SiH4 gas may be used instead of gas.

[0162] For example, an oxide semiconductor film, such as In-Ga-Zn- When forming an O film, In(CH3)3 gas and O3 gas are introduced in sequence. Then, Ga(CH3)3 gas and O3 gas are introduced repeatedly to form a Ga After that, Zn(CH3)2 gas and O3 gas were introduced repeatedly to form an O layer. The order of these layers is not limited to this example. Mixed oxide layers such as In-Ga-O, In-Zn-O, and Ga-Zn-O are formed using It is also possible to use the HClO3 gas. Although H2O gas may be used, it is preferable to use O3 gas that does not contain H. Instead of (CH3)3 gas, In(C2H5)3 gas may be used. 3) Ga(C2H5)3 gas may be used instead of Zn(CH3)2 Gas may also be used.

[0163] Note that the respective configuration examples of the semiconductor device described in this embodiment mode may be combined with each other as appropriate. It can be done.

[0164] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0165] (Embodiment 2) In this embodiment mode, a memory device including the semiconductor device described in the above embodiment mode will be described. Reveal.

[0166] 22 shows an example of the configuration of a memory device. The memory device 2600 includes a peripheral circuit 2601 and The peripheral circuit 2601 includes a memory cell array 2610. The peripheral circuit 2601 includes a row decoder 2621, a word a bit line driver circuit 2622, a bit line driver circuit 2630, an output circuit 2640, and It has a role logic circuit 2660.

[0167] The semiconductor device illustrated in FIG. 1(A), (B), or (C) described in the first embodiment is a metal The present invention can be applied to the memory cell array 2610.

[0168] The bit line driver circuit 2630 includes a column decoder 2631 and a precharge circuit 263 2, a sense amplifier 2633, and a write circuit 2634. 32 is a node N1 (not shown in FIG. 22) of the wiring RBL described in the first embodiment. The sense amplifier 2633 has the function of precharging the readout signal to a predetermined potential. The potential of the node N2 is acquired as a data signal, and the data signal is amplified. The amplified data signal is output via output circuit 2640 as a digital data signal RDATA is output to the outside of the storage device 2600.

[0169] The storage device 2600 is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, and A high power supply voltage (VDD) for the circuit 2601, a high power supply voltage (VI L) is supplied.

[0170] The memory device 2600 also receives control signals (CE, WE, RE) and an address signal ADDR. The data signal WDATA is input from the outside. The address signal ADDR is input from the row decoder. 2621 and the column decoder 2631, and the data signal WDATA is input to the write circuit It is entered into 2634.

[0171] The control logic circuit 2660 processes external input signals (CE, WE, RE). It processes the signals to generate control signals for the row decoder 2621 and the column decoder 2631. , is the chip enable signal, WE is the write enable signal, and RE is the read enable signal. The control logic circuit 2660 processes this signal. The present invention is not limited to this, and other control signals may be input as required.

[0172] It should be noted that the above-mentioned circuits and signals can be appropriately selected or omitted as required.

[0173] In addition, a p-channel Si transistor and an oxide semiconductor (preferably A transistor containing an oxide containing In, Ga, and Zn in the channel formation region is used. By applying this to the storage device 2600, a small-sized storage device 2600 can be provided. It is possible to provide a storage device 2600 that can reduce power consumption. In particular, the Si transistor is a p-channel type By doing so, the manufacturing cost can be kept low.

[0174] The configuration example of this embodiment is not limited to the configuration shown in FIG. 22. For example, the peripheral circuit 26 01, for example, the precharge circuit 2632 or / and the sense amplifier 2633. The configuration may be changed as appropriate, for example, by providing it below the cell array 2610.

[0175] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0176] (Embodiment 3) In this embodiment, the channel formation region of the OS transistor used in the above embodiment is This section explains the metal oxides contained in these materials.

[0177] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium or tin is contained. Also, boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , neodymium, hafnium, tantalum, tungsten, magnesium, etc. One or more of these may be included.

[0178] Here, the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or Other elements that can be used for element M include boron, silicon, and titanium. Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, Odium, hafnium, tantalum, tungsten, magnesium, etc. However, elements In some cases, M may be a combination of two or more of the above elements.

[0179] Next, with reference to Figs. 23(A), 23(B), and 23(C), the metal according to the present invention will be described. A preferred range of the atomic ratio of indium, element M, and zinc contained in the oxide will be explained. In addition, in Fig. 23(A), Fig. 23(B), and Fig. 23(C), the atomic ratio of oxygen is In addition, the number of atoms of indium, element M, and zinc contained in the metal oxide is not described. The respective terms in the ratio are [In], [M], and [Zn].

[0180] In Figures 23(A), 23(B), and 23(C), the dashed lines indicate the ratio of [In]:[M ]:[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):2, [ The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):3 is n]:[M]:[Zn]=(1+α):(1-α):4, and The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):5 is shown. vinegar.

[0181] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=5:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=2:1:β is ]:[M]:[Zn]=1:1:β, the atomic ratio line, [In]:[M]:[Zn ]=1:2:β, and the atomic ratio of [In]:[M]:[Zn]=1:3:β. The atomic ratio of [In]:[M]:[Zn]=1:4:β Represents a line.

[0182] In addition, the [In]:[M]: Metal oxides with an atomic ratio of [Zn]=0:2:1 and values ​​close to that ratio form spinel-type crystals. Easy to structure.

[0183] In addition, multiple phases may coexist in metal oxides (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic ratio is close to [In]:[M]:[Zn]=0:2:1, the spinel The two phases of the hexagonal crystal structure and the layered crystal structure tend to coexist. When [M]:[Zn] is close to 1:0:0, the bixbyite-type crystal structure and the layered structure When multiple phases coexist in a metal oxide, different crystal structures are formed. Grain boundaries may be formed between the crystal structures.

[0184] The region A shown in FIG. 23(A) is a region where indium, element M, and zinc are contained in the metal oxide. 1 shows an example of a preferable range of the atomic ratio.

[0185] By increasing the indium content of metal oxides, the carrier mobility of the metal oxides ( Therefore, metal oxides with a high indium content The carrier mobility is higher compared to metal oxides with a lower indium content.

[0186] On the other hand, when the content of indium and zinc in the metal oxide is low, the carrier mobility Therefore, the atomic ratio [In]:[M]:[Zn]=0:1:0 and its vicinity In the case of a near value (for example, region C shown in FIG. 23(C)), the insulating property is high.

[0187] Therefore, the metal oxide of one embodiment of the present invention has high carrier mobility and few crystal grain boundaries. It is preferable that the atomic ratio be that shown in region A in FIG. 23(A), which tends to form a layered structure with no atomic number difference. I wish.

[0188] In particular, in the area B shown in FIG. 23(B), the CAAC (c-axis a It is easy to become an optically active (ligned crystalline)-OS, and has excellent carrier mobility. The resulting metal oxide is

[0189] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure is distorted and has a distortion. In this case, the direction of the lattice arrangement is changed between an area with a uniform lattice arrangement and another area with a uniform lattice arrangement. indicates the point where a change occurs.

[0190] Nanocrystals are basically hexagonal, but are not limited to regular hexagonal shapes. They may also have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in CAAC-OS, clear grain boundaries (grain bows) are not observed even near the strain. It is not possible to confirm the presence of grain boundaries (also called grain boundaries). This is because the CAAC-OS has a crystalline structure in the ab-plane direction. The oxygen atoms are not densely packed, and the bond distance between atoms is shortened by the substitution of metal elements. This is thought to be because distortion can be tolerated by changing the thickness of the film.

[0191] CAAC-OS is a highly crystalline metal oxide. Since it is not possible to confirm the grain boundaries, the decrease in electron mobility due to the grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides is reduced by the incorporation of impurities and the generation of defects. Therefore, CAAC-OS is a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of metal oxides having CAAC-OS are stable. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0192] Region B is [In]:[M]:[Zn]=4:2:3 to 4.1 and its vicinity. Near values ​​include, for example, [In]:[M]:[Zn]=5:3:4 In addition, region B is [In]:[M]:[Zn]=5:1:6 and its neighboring values, and and [In]:[M]:[Zn]=5:1:7, and their neighboring values.

[0193] The properties of metal oxides are not uniquely determined by the atomic ratio. Even if the ratio is the same, the properties of the metal oxide may differ depending on the formation conditions. When depositing a film of an oxide using a sputtering device, the atomic ratio may be different from the atomic ratio of the target. Also, depending on the substrate temperature during film formation, the film may be formed with [Zn] rather than the target [Zn]. The [Zn] of the film may be small. Therefore, the region shown is a region where the metal oxide has a specific characteristic. The boundary between region A and region C is not strict. stomach.

[0194] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0195] (Fourth embodiment) In this embodiment, a CPU that can include the semiconductor device of the above embodiment will be described. explain.

[0196] FIG. 24 shows an example of the configuration of a CPU that partially uses the semiconductor device described in the first embodiment. FIG.

[0197] The CPU shown in FIG. 24 includes an ALU 1191 (Arithmetic and logic unit) on a board 1190. tic logic unit, arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI substrate, The ROM 1199 and the ROM interface 1189 are It may be provided on a separate chip. Of course, the CPU shown in FIG. 24 is a simplified version of the configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their uses. For example, 24 is a core, and a configuration including a CPU or an arithmetic circuit shown in FIG. 24 is a core. , each core can be configured to operate in parallel, i.e., like a GPU. In addition, the number of bits that a CPU can handle in its internal arithmetic circuit and data bus is, for example, 8 bits, 16 bits, It can be 32-bit, 64-bit, etc.

[0198] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, Interrupt controller 1194, register controller 1197, timing controller It is entered into La1195.

[0199] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to trigger the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it accordingly. Generates an address and reads or writes register 1196 depending on the CPU state. .

[0200] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generator supplies an internal clock signal to the various circuits.

[0201] In the CPU shown in FIG. 24, a memory cell is provided in the register 1196. The transistor described in the above embodiment can be used as the memory cell of the memory cell 1196. Cut.

[0202] In the CPU shown in FIG. 24, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. If data retention in the capacitor is selected, rewriting data to the capacitor The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0203] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0204] (Embodiment 5) A memory card (e.g., an SD card) that can be equipped with the storage device of the above embodiment , USB (Universal Serial Bus) memory, SSD (Solid This can be applied to various removable storage devices such as a removable storage device (e.g., a removable storage device for a hard disk drive ... hard disk drive for a hard disk drive, a hard disk drive for a hard disk drive, a hard disk drive for a hard disk drive, a hard disk drive for a hard disk drive, a hard disk drive for a In the embodiment, some configuration examples of removable storage devices will be explained with reference to FIG. Reveal.

[0205] 25A is a schematic diagram of a USB memory. The USB memory 5100 is , a cap 5102, a USB connector 5103, and a substrate 5104. are housed in a housing 5101. A substrate 5104 includes a memory device and a drive circuit for the memory device. For example, the substrate 5104 is provided with a memory chip 5105, a controller The memory chip 5105 is the same as that in the third embodiment. The memory cell array 2610, the word line driver circuit 2622, and the row decoder 26 21, sense amplifier 2633, precharge circuit 2632, column decoder 2631, etc. The controller chip 5106 specifically includes a processor, a work memory, and The memory chip 5105 and the controller chip are The circuit configuration of each of the chips 5106 is not limited to the above description, but may be changed depending on the situation or occasion. For example, the word line driver circuit 2622, Row decoder 2621, sense amplifier 2633, precharge circuit 2632, column decoder The memory chip 5105 is not equipped with the controller 2631, but with the controller chip 5106. The USB connector 5103 may be an interface for connecting to an external device. It functions as a

[0206] Figure 25(B) is a schematic diagram of the external appearance of an SD card, and Figure 25(C) is a schematic diagram of the internal structure of an SD card. The SD card 5110 is a schematic diagram of the structure. The SD card 5110 includes a housing 5111, a connector 5112, and a board. A connector 5112 serves as an interface for connecting to an external device. The board 5113 is housed in a housing 5111. The board 5113 has a memory device. For example, the substrate 5113 is provided with a memory chip. The chip 5114 and controller chip 5115 are installed. 4 includes the memory cell array 2610 and the word line driver circuit 26 described in the third embodiment. 22, row decoder 2621, sense amplifier 2633, precharge circuit 2632, color The controller chip 5115 includes a processor It incorporates a processor, work memory, ECC circuit, etc. The circuit configuration of the controller chip 5115 is not limited to the above description, and may vary depending on the situation. The circuit configuration may be changed accordingly or in some cases. For example, the word line driver circuit 2622, row decoder 2621, sense amplifier 2633, precharge circuit 263 2. The column decoder 2631 is not located on the memory chip 5114 but on the controller chip 511. 5 may be incorporated therein.

[0207] By providing a memory chip 5114 on the back side of the substrate 5113, the SD card 5110 In addition, a wireless chip having a wireless communication function can be mounted on the substrate 5113. This allows wireless communication between an external device and the SD card 5110. This allows data to be read from and written to the memory chip 5114.

[0208] FIG. 25(D) is a schematic diagram of the external appearance of the SSD, and FIG. 25(E) is a schematic diagram of the internal structure of the SSD. The SSD 5150 includes a housing 5151, a connector 5152, and a board 5153. A connector 5152 functions as an interface for connecting to an external device. The board 5153 is housed in the housing 5151. The board 5153 includes a memory device and a For example, the substrate 5153 includes a memory chip 5154. , memory chip 5155, and controller chip 5156 are installed. The chip 5154 includes the memory cell array 2610 and the word line driver 2610 described in the third embodiment. a buffer circuit 2622, a row decoder 2621, a sense amplifier 2633, a precharge circuit 26 32, column decoder 2631, etc. are built in. There is also a memory card on the back side of the board 5153. By adding a chip 5154, the capacity of the SSD 5150 can be increased. The chip 5155 has a built-in working memory. For example, the memory chip 5155 has The controller chip 5156 includes a processor, an E CC circuits and other circuits are built in. The circuit configurations of the controller chip 5115 and the controller chip 5116 are not limited to those described above. Depending on the situation or circumstances, the circuit configuration may be changed as appropriate. The controller chip 5156 may also be provided with a memory that functions as a work memory.

[0209] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0210] (Sixth embodiment) In this embodiment, an example of an electronic device to which the storage device of the above embodiment can be applied is described. This article explains:

[0211] <Notebook personal computer> FIG. 26A shows a notebook personal computer, which includes a housing 5401 and a display unit 540. 2, a keyboard 5403, a pointing device 5404, etc. The storage device can be provided in a notebook personal computer.

[0212] <Smartwatch> FIG. 26(B) shows a smart watch, which is a type of wearable terminal, and includes a housing 5901 , a display unit 5902, operation buttons 5903, an operator 5904, a band 5905, etc. The storage device of one embodiment of the present invention can be included in a smartwatch. A display device with a function as a position input device may be used as 5902. In addition, the function as a position input device can be added by providing a touch panel to the display device. Alternatively, the function as a position input device can be realized by using a photoelectric sensor, also known as a photosensor. It can also be added by providing a conversion element in the pixel section of the display device. The 5903 includes a power switch to start the smartwatch, and a smartwatch application. Buttons for operating the functions, volume adjustment buttons, or turning on or off the display 5902 In addition, the smart switch shown in FIG. The smartwatch has two operation buttons 5903. The number of operation buttons is not limited to this. The operator 5904 also functions as a crown for adjusting the time. It is used as an input interface to operate smartwatch applications. In the smart watch shown in FIG. 26(B), the operation element 590 4, but is not limited to this, and may be configured without the operator 5904. That's fine.

[0213] <Video camera> FIG. 26C shows a video camera, which includes a first housing 5801, a second housing 5802, and a display unit 5 803, operation keys 5804, a lens 5805, a connection part 5806, etc. Such a storage device can be provided in the video camera. 5805 is provided in a first housing 5801, and a display unit 5803 is provided in a second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connection part 5806. The angle between the first housing 5801 and the second housing 5802 is determined by the connection part 5806. The image on the display unit 5803 can be displayed on the first housing at the connection unit 5806. It may be configured to switch according to the angle between 5801 and the second housing 5802.

[0214] <Mobile phone> FIG. 26(D) shows a mobile phone having an information terminal function, which includes a housing 5501, a display unit 55 02, a microphone 5503, a speaker 5504, and an operation button 5505. The display portion 5502 may include a position input device. A display device with the function of a position input device may be used. This function can be added by providing a touch panel to the display device. The function of the position input device is to connect a photoelectric conversion element, also called a photosensor, to the image of the display device. It can also be added by providing it in the base part. Power switch, buttons to operate mobile phone applications, volume control buttons or a switch for turning on or off the display unit 5502. can be done.

[0215] In addition, the mobile phone shown in FIG. 26(D) has two operation buttons 5505. However, the number of operation buttons on a mobile phone is not limited to this. The mobile phone shown in FIG. 26(D) is equipped with a light-emitting device for use as a flashlight or illumination. The configuration may include a device.

[0216] <Television equipment> 26(E) is a perspective view showing a television device. The television device has a housing 9 000, display unit 9001, speaker 9003, operation keys 9005 (power switch or including operation switches), connection terminal 9006, sensor 9007 (force, displacement, position, speed, acceleration Speed, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field , current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared measurement The storage device according to one embodiment of the present invention is provided in a television device. The television device may have a large screen, for example, 50 inches or more, or 100 It is possible to incorporate a display unit 9001 of 1 inch or more.

[0217] <Mobile object> The above-described display device can also be applied to the vicinity of the driver's seat of an automobile, which is a moving body.

[0218] For example, FIG. 26(F) is a diagram showing the area around the windshield inside the interior of an automobile. In FIG. 26(F), a display panel 5701 attached to the dashboard and a display panel 5 702, a display panel 5703, and a display panel 5704 attached to the pillar are also shown. are.

[0219] The display panels 5701 to 5703 display navigation information, a speedometer, and tachometer, mileage, fuel level, gear status, air conditioning settings, and various other information. In addition, the display items and layout displayed on the display panel can be It can be changed as needed to suit the user's preferences, improving the design. The display panels 5701 to 5703 can also be used as lighting devices. be.

[0220] The display panel 5704 displays an image captured by an imaging means provided on the vehicle body. This allows the driver to compensate for the blind spot (blind spot) that is blocked by the pillar. By displaying images from the provided imaging means, blind spots can be compensated for and safety can be improved. In addition, by projecting images that complement the invisible parts, it is possible to make the sense of incongruity appear more natural. The display panel 5704 can also be used as a lighting device. can.

[0221] The storage device according to one embodiment of the present invention can be provided in a mobile object. The device is used to display images on the display panels 5701 to 5704, for example. The frame memory that temporarily stores image data and the system that drives the moving object are also used. It can be used as a storage device for storing programs.

[0222] Although not shown, the electronic devices shown in FIGS. 26(A) to 26(C), (E), and (F) The device may have a microphone and a speaker. The electronic device can be equipped with a voice input function.

[0223] Although not shown, the electronic devices shown in FIGS. 26(A), (B), (D) to (F) may be configured to include a camera.

[0224] Although not shown, the electronic devices shown in FIGS. 26(A) to 26(F) have a housing Sensors (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetic, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration The sensor may have a function to measure movement, smell, infrared rays, etc. In addition, the mobile phone shown in FIG. 26(D) is equipped with a sensor for detecting tilt such as a gyro or an acceleration sensor. By providing a detection device having a sensor, the orientation of the mobile phone (the mobile phone in the vertical direction) can be detected. The screen display of the display unit 5502 is adjusted to match the orientation of the mobile phone. It is possible to automatically switch depending on the

[0225] Although not shown, the electronic devices shown in FIGS. 26(A) to 26(F) can be used to identify fingerprints, veins, The configuration may include a device for acquiring biometric information such as an iris or a voiceprint. By using this, an electronic device with a biometric authentication function can be realized.

[0226] In addition, flexible substrates are used as the display units of the electronic devices shown in FIGS. Specifically, the display unit may be formed by mounting transistors, capacitors, etc., on a flexible substrate. By applying this configuration, Not only flat housings like the electronic devices shown in Figs. 26(A) to 26(F), but also curved housings are available. It is possible to realize an electronic device having a housing with a surface.

[0227] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0228] (Notes regarding the present specification) The following additional notes will be given regarding the description of each component in the above embodiment.

[0229] <Additional Notes Regarding One Aspect of the Present Invention Described in the Embodiments> The configurations shown in each embodiment may be appropriately combined with the configurations shown in other embodiments to realize the present invention. In addition, in one embodiment, multiple configuration examples may be shown. In this case, the configuration examples can be appropriately combined with each other.

[0230] It should be noted that the contents (or even a part of the contents) described in one embodiment may be used in the implementation of the embodiment. Another content (or part of the content) described in the embodiment and one or more other embodiments The content described (or a part of the content) is applied to, combined with, or at least one of the contents. or replacement, etc.

[0231] The contents described in the embodiments are explained using various drawings in each embodiment. This refers to the content stated in the specification or the content stated using the text in the specification.

[0232] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. In the embodiment, another figure (or a part thereof) and one or more other embodiments may be used. At least one of the drawings (or a part thereof) described in the embodiment is combined with By adding more, more figures can be constructed.

[0233] <Note on ordinal numbers> In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of constituent elements. Therefore, the number of components is not limited. The order of the components is not limited to the above. A component referred to as "first" in the specification may be used in other embodiments or in the claims. In addition, for example, in the implementation of this specification, etc. A component referred to as "first" in one embodiment may be used in other embodiments or in a patent. It may be omitted in the claims.

[0234] <Notes regarding the description of the drawings> The embodiments are described with reference to the drawings. However, the embodiments may be implemented in many different ways. It is possible to carry out the invention in various ways without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details of the present invention. However, the present invention should not be construed as being limited to the description of the embodiments. In the configuration, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. It will be used throughout and repeated explanations will be omitted.

[0235] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship is used for convenience in explaining the relationship with reference to the drawings. The terms and expressions indicating the arrangement may be changed as appropriate depending on the direction in which each configuration is depicted. The present invention is not limited to the above description and can be rephrased appropriately depending on the situation.

[0236] In addition, the terms "above" and "below" refer to the positional relationship of the components directly above or below and directly connected to each other. For example, if the expression is "electrode B on insulating layer A," The electrode B does not need to be formed directly on the insulating layer A, and the insulating layer A and the electrode B This does not exclude the inclusion of other components in between.

[0237] In addition, in the drawings, the size, layer thickness, and area are shown at arbitrary scales for the convenience of explanation. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely schematic illustrations for the purpose of clarity, and are not limited to the shapes or values ​​shown in the drawings. fluctuations in signal, voltage, or current due to noise, or signal due to timing deviations These may include variations in signal, voltage, or current.

[0238] In addition, in the drawings, some components are shown in perspective views and the like in order to clarify the drawings. The description of the element may be omitted.

[0239] In addition, in the drawings, the same elements or elements having similar functions, elements made of the same material, or In some cases, the same reference numerals may be used to designate elements that are formed at the same time, and repeated explanations thereof will be omitted. It may be omitted.

[0240] <Notes regarding possible paraphrases> In this specification and the like, when describing the connection relationship of a transistor, The first electrode or the first terminal is referred to as the "source or drain" (or the first electrode or the first terminal). The other of the source and drain is referred to as the "other of the source or drain" (or second electrode, or second terminal). This means that the source and drain of a transistor are This is because the names of the source and drain of a transistor change depending on the operating conditions. In this case, the term source (drain) terminal, source (drain) electrode, etc. may be used appropriately depending on the situation. In this specification, the two terminals other than the gate are referred to as the first terminal and the second terminal. In this specification, etc., The channel formation region is the region where a channel is formed by applying a potential to the gate. The formation of this region allows current to flow between the source and drain.

[0241] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. do.

[0242] Furthermore, when the transistor described in this specification has two or more gates (this configuration These gates are called the first gate and the second gate. It is sometimes called a front gate or a back gate. " can be simply interchanged with the word "gate." The phrase "backgate" is interchangeable with the phrase "gate." The bottom gate is a gate electrode formed on a lower side than the channel formation region during the manufacture of a transistor. The term "top gate" refers to a terminal that is formed first during the manufacturing of a transistor. The terminal is formed after the channel forming region.

[0243] In addition, the terms "electrode" and "wiring" used in this specification and the like refer to these components functionally. This is not a limitation. For example, an "electrode" may be used as part of a "wiring." , and vice versa. Furthermore, the terms "electrode" and "wiring" may be used interchangeably with "electrodes" and "wiring." This also includes cases where the wiring is formed integrally.

[0244] In this specification and the like, the terms voltage and potential can be interchanged as appropriate. It is the potential difference from the reference potential. For example, the reference potential is the ground potential (earth potential). If we use the term "potential"), we can translate voltage into potential. Ground potential is not necessarily 0V. It does not necessarily mean that the potential is relative, and depending on the reference potential, The potential applied to wiring etc. may be changed.

[0245] In this specification, the terms "film" and "layer" may be used in some cases or depending on the situation. For example, the term "conductive layer" can be used interchangeably with "conductive layer" It may be possible to change the term to "insulating film" or, for example, The term may be changed to "insulating layer" in some cases. Alternatively, depending on the situation, words such as "film" and "layer" may be replaced with other terms. For example, the term "conductive layer" or "conductive film" can be changed to "conductor." In some cases, it may be possible to change the term to, for example, "insulating layer" or "insulating film." It may be possible to change the term to "insulator."

[0246] In this specification, terms such as "wiring," "signal line," and "power line" may be used in some cases. For example, "wiring" and "wiring" can be interchangeable. In some cases, it may be possible to change the term "signal line" to "signal line." It may be possible to change the term "wiring" to a term such as "power line." , and vice versa, terms such as "signal line" and "power line" will be changed to the term "wiring." It may be possible to change terms such as "power line" to terms such as "signal line". The reverse is also true, and terms such as "signal line" may be used interchangeably with "power line" In some cases, it may be possible to change the term to "potential" applied to the wiring. Changing the term to "signal" or similar, as the case may be, or depending on the situation. And vice versa, terms such as "signal" may be used in conjunction with "potential." It may be possible to change it to a different word.

[0247] <Notes on definitions of terms> The following provides definitions of terms used in the above embodiments.

[0248] <<About impurities in semiconductors>> The impurities in a semiconductor are, for example, substances other than the main components that make up the semiconductor layer. Elements with less than 0.1 atomic % are impurities. The formation of DOS (Density of States) and the carrier mobility The semiconductor may become an oxide semiconductor, and the crystallinity may decrease. In the case of a semiconductor, impurities that change the properties of the semiconductor include, for example, elements of Group 1 and Group 2. There are elements, group 13 elements, group 14 elements, group 15 elements, and transition metals other than the main component. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, In the case of oxide semiconductors, for example, impurities such as hydrogen can be mixed in. In addition, if the semiconductor is a silicon layer, the characteristics of the semiconductor may be affected. The impurities that change the value of the valence band include, for example, oxygen, group 1 elements excluding hydrogen, group 2 elements, and group 1 elements. These include Group 3 elements and Group 15 elements.

[0249] <<About the switch>> In this specification, a switch is a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It is a device that has the function of controlling whether or not current flows by entering a state where it is in a switched state. A switch is a device that has the function of selecting and switching the path through which current flows.

[0250] For example, an electrical switch or a mechanical switch can be used. The switch is not limited to a specific one as long as it can control the current.

[0251] An example of an electrical switch is a transistor (e.g., a bipolar transistor, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die MIS (Metal Insulator Semiconductor) die diode-connected transistors, etc.), or logic circuits that combine these There is.

[0252] When a transistor is used as a switch, the "conduction state" of the transistor is The state in which the source and drain electrodes of a transistor can be considered to be electrically shorted is called Also, the "non-conducting state" of a transistor means that the source electrode and drain electrode of the transistor are This refers to a state in which the electrodes can be considered to be electrically disconnected. When the transistor is operated as a transistor having a polarity (conductivity type), there is no particular limitation.

[0253] An example of a mechanical switch is a digital micromirror device (DMD). In 2013, a switch using MEMS (microelectromechanical systems) technology was developed. The switch has a mechanically movable electrode, and when the electrode moves, Therefore, the device operates by controlling conduction and non-conduction.

[0254] <<About connection>> In this specification, when it is stated that X and Y are connected, it means that X and Y are electrically connected. There are cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Therefore, a predetermined connection relationship, for example, a diagram or It is not limited to the connection relationships shown in the text, but also includes connection relationships other than those shown in the drawings or text. It shall be.

[0255] X, Y, etc. used here refer to objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, etc.). , conductive film, layer, etc.).

[0256] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. It has a function to control whether or not water is flushed.

[0257] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boost circuits, step-down circuits, etc.), level shifter circuits that change the signal potential level, etc. ), voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if X is transmitted to Y.

[0258] When it is explicitly stated that X and Y are electrically connected, it means that X and Y are electrically connected. When X and Y are electrically connected (i.e., when another element or circuit is inserted between X and Y) X and Y are functionally connected (i.e., there is no connection between X and Y) When X and Y are connected directly, the two are functionally connected via another circuit. (That is, when X and Y are connected without any other element or circuit between them) In other words, when it is explicitly stated that something is electrically connected, it is not simply The same applies if the document is explicitly stated as being connected to the

[0259] For example, if the source (or first terminal, etc.) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. It may be electrically connected to Y through Z2 (or not), or the source of the transistor may be The first terminal (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. When a part of Z2 is directly connected to Y, and another part of Z2 is directly connected to Y, it can be expressed as follows: It can be manifested.

[0260] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" 2 terminals) are electrically connected to each other, and X, the source (or The first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and the Y are electrically connected in this order. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Or, "X is the source (or first terminal, etc.) of the transistor. ) and the drain (or second terminal, etc.) of the transistor Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor , Y are provided in this connection order." By using this expression, the order of connections in the circuit configuration can be specified. A distinction is made between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above expressions. Here, X, Y, Z1, and Z2 are the coordinates of the object (for example, the device, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0261] Note that the circuit diagram shows independent components as if they are electrically connected to each other. Even if one component has the functions of multiple components, For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the present invention has the functions of both the electrode and the electrode. Electrical connection means that one conductive film has the functions of multiple components. This case will also be included in that category.

[0262] <<About parallel and perpendicular>> In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to a state in which two lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Explanation of symbols]

[0263] MC[1] Memory cell MC[2] Memory cell MC[n] memory cell MC[1,1] memory cell MC[j,1] memory cell MC[n,1] memory cell MC[1,i] memory cell MC[j,i] memory cell MC[n,i] memory cell MC[1,m] memory cell MC[j,m] memory cell MC[n,m] memory cell WWL[1] Wiring WWL[2] Wiring WWL[j] wiring WWL[n] wiring RWL[1] Wiring RWL[2] Wiring RWL[j] Wiring RWL[n] Wiring WBL wiring WBL[1] Wiring WBL[i] Wiring WBL[m] Wiring RBL Wiring RBL[1] Wiring RBL[i] Wiring RBL[m] Wiring BGL wiring BGL[1] wiring BGL[i] Wiring BGL[m] Wiring WTr transistor RTr transistor CS capacitive element N1 node N2 node PG Conductor WWL Wiring RWL wiring ER wiring HL area AR area SD1 area SD2 area 100 laminate 101A Insulator 101B Insulator 101C Insulator 101D Insulator 101E Insulator 102 Insulator 103 Insulator 104 Insulator 105 Insulator 131A Conductor 131B Conductor 132A Conductor 132B Conductors 133 Conductors 133a Conductor 133b Conductor 133c conductor 134 Conductors 151 Semiconductors 151a area 151b area 151c area 152 Semiconductors 153 Semiconductors 153a Semiconductors 153b Semiconductors 181A area 181B area 182A area 182B area 183A area 183B area 191 Opening 192A Recess 192B Recess 193A Recess 193B Recess 194A Recess 194B Recess 194C Recess 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1189 ROM interface 1190 PCB 1700 boards 1701 Element isolation layer 1712 Conductors 1730 Conductors 1790 gate electrode 1792 wells 1793 Channel formation region 1794 Low concentration impurity region 1795 High concentration impurity region 1796 Conductive region 1797 Gate insulating film 1798 Sidewall insulating layer 1799 Sidewall insulating layer 2600 storage device 2601 Peripheral circuit 2610 Memory Cell Array 2621 Low Decoder 2622 Word Line Driver Circuit 2630 Bit Line Driver Circuit 2631 Column Decoder 2632 Precharge Circuit 2633 Sense Amplifier 2634 Write Circuit 2640 output circuit 2660 Control Logic Circuit 5100 USB memory 5101 Housing 5102 Cap 5103 USB connector 5104 Circuit Board 5105 memory chip 5106 controller chip 5110 SD card 5111 Housing 5112 Connector 5113 Circuit Board 5114 memory chip 5115 controller chip 5150 SSD 5151 Case 5152 Connector 5153 Circuit Board 5154 memory chip 5155 memory chip 5156 controller chip 5401 Housing 5402 Display section 5403 Keyboard 5404 Pointing Device 5501 Housing 5502 Display section 5503 Microphone 5504 Speaker 5505 Operation button 5701 Display panel 5702 Display panel 5703 Display Panel 5704 Display panel 5801 1st cabinet 5802 Second cabinet 5803 Display section 5804 Operation key 5805 Lens 5806 Connection 5901 Housing 5902 Display section 5903 Operation button 5904 Operator 5905 Band 9000 chassis 9001 Display section 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor

Claims

1. a first transistor to a third transistor; one of the source and the drain of the first transistor is electrically connected to the gate of the third transistor; one of the source and the drain of the second transistor is electrically connected to the gate of the third transistor; a gate of the first transistor electrically connected to a first wiring; a gate of the second transistor electrically connected to a second wiring; a back gate of the third transistor is electrically connected to a third wiring; a first conductor having a function as the third wiring; a first insulator having a region disposed above the first conductor; a first semiconductor having a region disposed above the first insulator and having a channel formation region of the third transistor; a second insulator having a region disposed above the first semiconductor; a second semiconductor having a region disposed above the second insulator, the second semiconductor having a channel formation region of the first transistor and a channel formation region of the second transistor, and connected between the channel formation region of the first transistor and the channel formation region of the second transistor; a second conductor having a region disposed above the second semiconductor and electrically connected to the second semiconductor; a third conductor having a region disposed above the second semiconductor via a third insulator and functioning as the first wiring; a fourth conductor having a region disposed above the second semiconductor via the third insulator and functioning as the second wiring; a fifth conductor having a region disposed above the second conductor; the second conductor has a region in contact with the second semiconductor between a channel formation region of the first transistor and a channel formation region of the second transistor; the second conductor overlaps with the first semiconductor via the second insulator; A capacitance is formed between the second conductor and the fifth conductor. Semiconductor device.

2. a first transistor to a third transistor; one of the source and the drain of the first transistor is electrically connected to the gate of the third transistor; one of the source and the drain of the second transistor is electrically connected to the gate of the third transistor; a gate of the first transistor electrically connected to a first wiring; a gate of the second transistor electrically connected to a second wiring; a back gate of the third transistor is electrically connected to a third wiring; a first conductor having a function as the third wiring; a first insulator having a region disposed above the first conductor; a first semiconductor having a region disposed above the first insulator and having a channel formation region of the third transistor; a second insulator having a region disposed above the first semiconductor; a second semiconductor having a region disposed above the second insulator, the second semiconductor having a channel formation region of the first transistor and a channel formation region of the second transistor, and connected between the channel formation region of the first transistor and the channel formation region of the second transistor; a second conductor having a region disposed above the second semiconductor and electrically connected to the second semiconductor; a third conductor having a region disposed above the second semiconductor via a third insulator and functioning as the first wiring; a fourth conductor having a region disposed above the second semiconductor via the third insulator and functioning as the second wiring; a fifth conductor having a region disposed above the second conductor; the second conductor has a region in contact with the second semiconductor between a channel formation region of the first transistor and a channel formation region of the second transistor; the second conductor overlaps with the first semiconductor via the second insulator; a capacitance is formed between the second conductor and the fifth conductor; the second conductor has an overlap with the first conductor; Semiconductor device.

3. a first transistor to a third transistor; one of the source and the drain of the first transistor is electrically connected to the gate of the third transistor; one of the source and the drain of the second transistor is electrically connected to the gate of the third transistor; a gate of the first transistor electrically connected to a first wiring; a gate of the second transistor electrically connected to a second wiring; a back gate of the third transistor is electrically connected to a third wiring; a first conductor having a function as the third wiring; a first insulator having a region disposed above the first conductor; a first semiconductor having a region disposed above the first insulator and having a channel formation region of the third transistor; a second insulator having a region disposed above the first semiconductor; a second semiconductor having a region disposed above the second insulator, the second semiconductor having a channel formation region of the first transistor and a channel formation region of the second transistor, and connected between the channel formation region of the first transistor and the channel formation region of the second transistor; a second conductor having a region disposed above the second semiconductor and electrically connected to the second semiconductor; a third conductor having a region disposed above the second semiconductor via a third insulator and functioning as the first wiring; a fourth conductor having a region disposed above the second semiconductor via the third insulator and functioning as the second wiring; a fifth conductor having a region disposed above the second conductor; the second conductor has a region in contact with the second semiconductor between a channel formation region of the first transistor and a channel formation region of the second transistor; the second conductor overlaps with the first semiconductor via the second insulator; a capacitance is formed between the second conductor and the fifth conductor; the third conductor has an overlap with the first conductor; the fourth conductor has an overlap with the first conductor; Semiconductor device.

4. a first transistor to a third transistor; one of the source and the drain of the first transistor is electrically connected to the gate of the third transistor; one of the source and the drain of the second transistor is electrically connected to the gate of the third transistor; a gate of the first transistor electrically connected to a first wiring; a gate of the second transistor electrically connected to a second wiring; a back gate of the third transistor is electrically connected to a third wiring; a first conductor having a function as the third wiring; a first insulator having a region disposed above the first conductor; a first semiconductor having a region disposed above the first insulator and having a channel formation region of the third transistor; a second insulator having a region disposed above the first semiconductor; a second semiconductor having a region disposed above the second insulator, the second semiconductor having a channel formation region of the first transistor and a channel formation region of the second transistor, and connected between the channel formation region of the first transistor and the channel formation region of the second transistor; a second conductor having a region disposed above the second semiconductor and electrically connected to the second semiconductor; a third conductor having a region disposed above the second semiconductor via a third insulator and functioning as the first wiring; a fourth conductor having a region disposed above the second semiconductor via the third insulator and functioning as the second wiring; a fifth conductor having a region disposed above the second conductor; the second conductor has a region in contact with the second semiconductor between a channel formation region of the first transistor and a channel formation region of the second transistor; the second conductor overlaps with the first semiconductor via the second insulator; a capacitance is formed between the second conductor and the fifth conductor; the second conductor has an overlap with the first conductor; the third conductor has an overlap with the first conductor; the fourth conductor has an overlap with the first conductor; Semiconductor device.

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