Semiconductor Devices

Abstract

To provide a semiconductor device with less variation in transistor characteristic.SOLUTION: A semiconductor device includes an oxide 230b, oxides 243a, b and an oxide 230c thereon, conductors 242a, b on the oxides 243a, b, an oxide 230d on the oxide 230c, an insulator 250 thereon, conductors 260a, b that exist thereon and overlap with a part of the oxide 230c, an insulator 272 in contact with an upper surface of the conductors 242a, b, and an insulator 273. A groove part is formed over the oxide 230b. The height of an interface between the oxide 230b and the oxides 243a, b is preferably substantially the same as the height of an interface between the oxide 230c and the oxide 230d. The depth of the groove part is preferably substantially the same as the thickness of the oxide 230c. The atomic concentration of aluminum in impurities (aluminum, silicon, and the like) at or near the interface between the oxide 230b and the oxide 230c is 5.0 atom% or less.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] 1. Field of the Invention

[0003] One embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] Technology that constructs transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

[0005] In oxide semiconductors, c-axis aligned crystalline (CAAC) structures and nanocrystalline (nc) structures, which are neither single crystal nor amorphous, have been found (see Non-Patent Documents 1 and 2).

[0006] Non-Patent Documents 1 and 2 disclose techniques for manufacturing a transistor using an oxide semiconductor having a CAAC structure. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with little variation in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device including a first oxide, a second oxide and a third oxide on the first oxide, a first conductor on the second oxide, a second conductor on the third oxide, a fourth oxide on the first oxide and between the second oxide and the third oxide, a first insulator on the fourth oxide, and a third conductor on the first insulator, wherein the first oxide has a groove portion in a region not overlapping with the second oxide and the third oxide, the first oxide has a first layered crystal generally parallel to a surface on which the first oxide is to be formed, and in the groove portion, the fourth oxide has a second layered crystal generally parallel to a surface on which the first oxide is to be formed, and the concentration of aluminum atoms at the interface between the first oxide and the fourth oxide and in the vicinity thereof is 5.0 atomic % or less.

[0011] Another embodiment of the present invention is a semiconductor device including a first oxide, a second oxide and a third oxide on the first oxide, a first conductor on the second oxide, a second conductor on the third oxide, a fourth oxide on the first oxide and between the second oxide and the third oxide, a fifth oxide on the fourth oxide, a first insulator on the fifth oxide, and a third conductor on the first insulator, wherein the first oxide has a groove portion in a region not overlapping with the second oxide and the third oxide, the first oxide has first layered crystals substantially parallel to a surface on which the first oxide is to be formed, and in the groove portion, the fourth oxide has second layered crystals substantially parallel to a surface on which the first oxide is to be formed, and the concentration of aluminum atoms at the interface between the first oxide and the fourth oxide and in the vicinity thereof is 2.0 atomic % or less.

[0012] Another embodiment of the present invention has a first oxide, a second oxide and a third oxide on the first oxide, a first conductor on the second oxide, a second conductor on the third oxide, a fourth oxide on the first oxide and between the second oxide and the third oxide, a fifth oxide on the fourth oxide, a first insulator on the fifth oxide, and a third conductor on the first insulator, wherein the first oxide is in contact with the second oxide and the third oxide. The semiconductor device has a groove in a non-overlapping region, the first oxide has a first layer crystal that is approximately parallel to the surface on which the first oxide is formed, and in the groove, the fourth oxide has a second layer crystal that is approximately parallel to the surface on which the first oxide is formed, and on the side wall of the groove, the first layer crystal and the second layer crystal are continuously joined at their ab planes, and the concentration of aluminum atoms at the interface between the first oxide and the fourth oxide and in the vicinity thereof is 2.0 atomic % or less.

[0013] In the above, it is preferable that the difference in height between the interface between the first oxide and the second oxide and the interface between the fourth oxide and the fifth oxide is equal to or less than the film thickness of the fourth oxide.

[0014] In the above, the first oxide, fourth oxide, and fifth oxide preferably contain indium, an element M (M is gallium, aluminum, yttrium, or tin), and zinc, and the atomic ratio of indium to the element M in the first oxide is greater than the atomic ratio of indium to the element M in the fifth oxide, and the atomic ratio of indium to the element M in the fourth oxide is greater than the atomic ratio of indium to the element M in the fifth oxide. Also, in the above, the fourth oxide is preferably a metal oxide having a composition of In:Ga:Zn=4:2:3 [atomic ratio] or close thereto.

[0015] In the above, it is preferable that the first layered crystal and the second layered crystal have a c-axis that is approximately perpendicular to the surface on which the first oxide is formed.

[0016] In the above, it is preferable that either or both of the first oxide and the fourth oxide have a CAAC structure near the bottom end of the first conductor and near the bottom end of the second conductor. [Effects of the Invention]

[0017] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high reliability can be provided. According to another embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0018] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0019] [Figure 1] 1A and 1B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 2] 2A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 2B to 2D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 3] 3A to 3D are diagrams illustrating a method for forming a CAAC-OS film. [Figure 4] 4A to 4C are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 5]Figure 5A is a diagram explaining the classification of IGZO crystal structures. Figure 5B is a diagram explaining the XRD spectrum of silica glass. Figure 5C is a diagram explaining the XRD spectrum of crystalline IGZO. Figure 5D is a diagram explaining the micro-electron diffraction pattern of crystalline IGZO. [Figure 6] 6A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 6B to 6D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 7] 7A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 7B to 7D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 8] 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 8B to 8D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 9B to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 10B to 10D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 11B to 11D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 12A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 12B to 12D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 13B to 13D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 14A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 14B to 14D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 15B to 15D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 17A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 17B to 17D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] 18A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 18B to 18D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19] 19A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 19B to 19D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 20A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 20B to 20D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21] 21A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 21B to 21D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22] 22A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 22B to 22D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 23] 23A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 23B to 23D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 24]24A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 24B to 24D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 25] 25A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 25B to 25D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 26] 26A and 26B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 27] FIG. 27 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 28] FIG. 28 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 29] FIG. 29 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 30] 30A and 30B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 31] FIG. 31 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 32] FIG. 32 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 33] 33A and 33B are block diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 34] 34A to 34H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 35] FIG. 35 is a diagram showing various storage devices by hierarchy. [Figure 36] 36A and 36B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 37] 37A and 37B are diagrams illustrating an example of an electronic component. [Figure 38] 38A to 38E are schematic diagrams of a memory device according to one embodiment of the present invention. [Figure 39] 39A to 39H are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 40] 40A and 40B are TEM images according to this example. [Figure 41] Figure 41A is a TEM image according to this example, and Figures 41B to 41D are FFT images according to this example. [Figure 42] FIG. 42 is a graph showing the measurement results of the Id-Vg characteristics according to this example. [Figure 43] Fig. 43A is a graph showing the variation in Vsh according to this example, and Fig. 43B is a graph showing the variation in S value according to this example. [Figure 44] 44A to 44C are TEM images according to this example. [Figure 45] FIG. 45 is a graph showing the measurement results of the aluminum concentration according to this example. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0021] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers, resist masks, etc. may be unintentionally thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same symbols are used for identical parts or parts having similar functions across different drawings, and repeated explanations may be omitted. When referring to similar functions, the same hatch pattern may be used and no particular symbols may be assigned.

[0022] In order to make the invention easier to understand, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0023] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc. in the description. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification.

[0024] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0025] For example, if it is explicitly stated in this specification that X and Y are connected, it is assumed that the specification also discloses cases in which X and Y are electrically connected, cases in which X and Y are functionally connected, and cases in which X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is assumed that connections other than those shown in a figure or text are also disclosed in a figure or text. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0026] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. In this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0027] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0028] Note that the channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0029] The channel width refers to, for example, the length of a channel formation region in a region where a semiconductor (or a portion of the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or the length of the channel formation region in a direction perpendicular to the channel length direction in the channel formation region. Note that the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a single transistor may not be determined to a single value. Therefore, in this specification, the channel width refers to any one value, maximum value, minimum value, or average value in the channel formation region.

[0030] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In such a case, the effective channel width is larger than the apparent channel width.

[0031] In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0032] In this specification, when simply referred to as a channel width, it may refer to an apparent channel width. Alternatively, when simply referred to as a channel width, it may refer to an effective channel width. Note that values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0033] Note that impurities in semiconductors refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect state density of the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V) in the oxide semiconductor. O :oxygen vacancy) may be formed.

[0034] In this specification and the like, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0035] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0036] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0037] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0038] Furthermore, in this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1 x 10 at 85°C -18 A or less, or 1 x 10 at 125°C -16 This means that it is A or below.

[0039] (Embodiment 1) In this embodiment, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[0040] <Configuration example of semiconductor device> The configuration of a semiconductor device including a transistor 200 will be described with reference to FIGS. 1A and 1B are enlarged views of a portion of the transistor 200, and FIGS. 2A to 2D are top and cross-sectional views of a semiconductor device including the transistor 200. FIG. 2A is a top view of the semiconductor device. FIGS. 2B to 2D are cross-sectional views of the semiconductor device. FIG. 2B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 2A, which is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1A is an enlarged view of the vicinity of the channel formation region in FIG. 2B, and FIG. 1B is an enlarged view of the vicinity of the interface between the oxide 243a and the oxide 230c in FIG. 1A. FIG. 2C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 2A, which is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 2D is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 2A. Note that some elements are omitted from the top view in FIG. 2A for clarity.

[0041] A semiconductor device of one embodiment of the present invention includes an insulator 211 over a substrate (not shown), an insulator 212 over the insulator 211, an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, an insulator 280 over the transistor 200, an insulator 282 over the insulator 280, an insulator 283 over the insulator 282, and an insulator 284 over the insulator 283. The insulators 211, 212, 214, 280, 282, 283, and 284 function as interlayer films. The semiconductor device also includes a conductor 240 (conductor 240a and conductor 240b) electrically connected to the transistor 200 and functioning as a plug. Note that an insulator 241 (insulator 241a and insulator 241b) is provided in contact with a side surface of the conductor 240 functioning as a plug. In addition, conductors 246 (conductors 246a and 246b) that are electrically connected to the conductor 240 and function as wiring are provided on the insulator 284 and the conductor 240. In addition, an insulator 286 is provided on the conductor 246 and the insulator 284.

[0042] Insulator 241a is provided in contact with the inner walls of the openings of insulators 272, 273, 280, 282, 283, and 284, a first conductor of conductor 240a is provided in contact with the side surface of insulator 241a, and a second conductor of conductor 240a is provided further inward. Insulator 241b is provided in contact with the inner walls of the openings of insulators 272, 273, 280, 282, 283, and 284, a first conductor of conductor 240b is provided in contact with the side surface of insulator 241b, and a second conductor of conductor 240b is provided further inward. Here, the height of the top surface of conductor 240 and the height of the top surface of insulator 284 in the region overlapping with conductor 246 can be made approximately the same. Note that, although the transistor 200 has a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may be configured as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to indicate the order of formation.

[0043] [Transistor 200] As shown in FIGS. 2A to 2D, the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) disposed so as to be embedded in the insulator 214 or the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 243 (oxide 243a and oxide 243b) and an oxide 230c on the oxide 230b, a conductor 242a on the oxide 243a, and an oxide 243b on the oxide 243a. The oxide 230c includes a conductor 242b on the oxide 243b, an oxide 230d on the oxide 230c, an insulator 250 on the oxide 230d, a conductor 260 (conductor 260a and conductor 260b) located on the insulator 250 and overlapping with a portion of the oxide 230c, an insulator 272 in contact with a portion of the top surface of the insulator 224, a portion of the side surface of the oxide 230a, a portion of the side surface of the oxide 230b, the side surface of the oxide 243a, the side surface of the oxide 243b, the side surface of the conductor 242a, the top surface of the conductor 242a, the side surface of the conductor 242b, and the top surface of the conductor 242b, and an insulator 273 on the insulator 272. The oxide 230c also contacts the side surface of the oxide 243a, the side surface of the oxide 243b, the side surface of the conductor 242a, and the side surface of the conductor 242b. 2B and 2C, the upper surface of the conductor 260 is disposed so as to substantially coincide with the upper surfaces of the insulator 250, the oxide 230d, and the oxide 230c. The insulator 282 contacts the upper surfaces of the conductor 260, the insulator 250, the oxide 230d, the oxide 230c, and the insulator 280.

[0044] Openings reaching the oxide 230b are provided in the insulator 280, the insulator 273, and the insulator 272. The oxide 230d, the oxide 230c, the insulator 250, and the conductor 260 are disposed in the openings. In addition, the conductor 260, the insulator 250, the oxide 230d, and the oxide 230c are disposed between the conductor 242a and the oxide 243a and between the conductor 242b and the oxide 243b in the channel length direction of the transistor 200. The insulator 250 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260. In addition, in the region overlapping with the oxide 230b, the oxide 230c has a region in contact with the oxide 230b, a region overlapping with the side surface of the conductor 260 with the insulator 250 interposed therebetween, and a region overlapping with the bottom surface of the conductor 260 with the insulator 250 interposed therebetween.

[0045] The oxide 230 preferably includes an oxide 230a disposed on the insulator 224, an oxide 230b disposed on the oxide 230a, an oxide 230c disposed on the oxide 230b and at least partially in contact with the oxide 230b, and an oxide 230d disposed on the oxide 230c. By providing the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b. Furthermore, by providing the oxide 230d on the oxide 230c, it is possible to suppress the diffusion of impurities from structures formed above the oxide 230d to the oxide 230c.

[0046] Note that, in the transistor 200, the oxide 230 has a four-layer structure of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d, but the present invention is not limited to this. For example, the oxide 230 may have a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230c, a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c, or a stacked structure of five or more layers. Alternatively, each of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d may have a stacked structure.

[0047] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulator 250 functions as a first gate insulator, and the insulator 224 functions as a second gate insulator. The conductor 242a functions as one of a source and a drain, and the conductor 242b functions as the other of the source and the drain. The oxide 230 functions as a channel formation region.

[0048] In the transistor 200, it is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 230 (the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d) including the channel formation region.

[0049] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with such a wide band gap, the off-state current of the transistor can be reduced.

[0050] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 230. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230.

[0051] Here, the atomic ratio of In to the element M in the metal oxide used for the oxide 230b or the oxide 230c is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a or the oxide 230d. By disposing the oxide 230d on the oxide 230b or the oxide 230c in this manner, it is possible to suppress the diffusion of impurities from structures formed above the oxide 230d to the oxide 230b or the oxide 230c. Furthermore, by having a common element other than oxygen (as a main component) among the oxides 230a to 230d, it is possible to reduce the density of defect states at the interfaces between the oxides 230a, 230b, 230c, and 230d. In this case, the main carrier path is the oxide 230b, the oxide 230c, or the vicinity thereof, for example, the interface between the oxide 230b and the oxide 230c. Since the defect state density at the interface between the oxide 230b and the oxide 230c can be reduced, the effect of interface scattering on carrier conduction is small, and a high on-current can be obtained.

[0052] The oxide 230b and the oxide 230c preferably have crystallinity. In particular, it is preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b and the oxide 230c. Alternatively, the oxide 230d may have crystallinity.

[0053] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distorted crystal structure refers to the change in the lattice orientation between regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement in the regions where multiple nanocrystals are connected.

[0054] Nanocrystals are basically hexagonal, but not necessarily regular hexagons; they can also have non-regular hexagonal shapes. Furthermore, the lattice arrangement of CAAC-OS can be pentagonal, heptagonal, or other shapes due to distortion. It is difficult to identify clear grain boundaries in CAAC-OS, even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the ab-plane direction and the change in interatomic bond distance caused by substitution of metal elements.

[0055] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially reducing the on-state current or field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in a transistor semiconductor layer. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0056] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as an (M,Zn) layer) are stacked. Note that indium and the element M are mutually substituted, and when the element M in an (M,Zn) layer is substituted with indium, it can also be expressed as an (In,M,Zn) layer. When the indium in an In layer is substituted with the element M, it can also be expressed as an (In,M) layer.

[0057] Here, an example of the CAAC-OS growth model will be described with reference to FIG.

[0058] First, multiple nanoclusters 20, whose a-axis and b-axis directions are random, are formed on the surface (formation surface) of the substrate 32. Here, the nanoclusters 20 have a flat structure with an (M, Zn) layer located on the surface, and are composed of two (M, Zn) layers and an In layer located between them.

[0059] Next, particles 23 reach the surface of substrate 32. Particles 23 bond more easily to the side surfaces of nanoclusters 20 than to the top surfaces. Therefore, particles 23 preferentially attach to the side surfaces of nanoclusters 20, filling in the areas where no nanoclusters 20 have formed. When the bonds of particles 23 become active, they chemically bond with nanoclusters 20 to form lateral growth portions 22 (see FIG. 3A). It can also be said that particles 23 penetrate into the areas between nanoclusters 20. Note that FIG. 3A also shows an enlarged view of nanocluster 20, and a schematic diagram of the crystal structure within nanocluster 20.

[0060] The lateral growth portions 22 grow laterally (also called lateral growth) so as to fill the regions 26 between the nanoclusters 20 (regions 26 can also be called Lateral Growth Buffer Regions (LGBRs)). Here, the lateral direction refers to, for example, the direction perpendicular to the c-axis in the nanoclusters 20. Here, by heating the substrate to 450°C or less, preferably 400°C or less, a reaction occurs in which particles 23 adhere to the lateral growth portions 22 of the nanoclusters 20, oxygen diffused through the LGBR adheres to the particles 23, and then particles 23 adhere again in the same way. It is presumed that this repetition causes lateral solid-phase growth.

[0061] Furthermore, as the lateral growth portions 22 grow laterally, they collide with each other. The portions where the lateral growth portions 22 collide form connection portions 27, which connect adjacent nanoclusters 20 (see FIG. 3B). In other words, connection portions 27 are formed in region 26. This can also be said to mean that particles 23 form lateral growth portions 22 on the side surfaces of nanoclusters 20 and grow laterally, thereby filling region 26 between nanoclusters 20. In this way, lateral growth portions 22 are formed until they fill the regions where no nanoclusters 20 are formed.

[0062] Therefore, even if the nanoclusters 20 are formed facing in different directions, the particles 23 grow laterally to fill the gaps between the nanoclusters 20, and no clear crystal grain boundaries are formed.

[0063] Here, the InMZnO4 crystalline structure is a layered crystalline structure that exists stably over a wide composition range, and the bond strength and equilibrium distance between metal atoms and oxygen atoms differ for each metal atom. Therefore, it is presumed that the InMZnO4 crystalline structure is tolerant to distortion. Therefore, particles 23 smoothly connect (anchor) between nanoclusters 20, resulting in the formation of a crystalline structure at the connecting portions 27 that is neither single crystal nor polycrystalline. In other words, a crystalline structure with distortion is formed at the connecting portions 27 between nanoclusters 20. As a result, for example, at the connecting portions 27, a crystalline structure with a hexagonal top surface shape may deform, becoming pentagonal or heptagonal. Because the regions filling the gaps between the nanoclusters 20 are distorted crystalline regions, it is inappropriate to refer to these regions as amorphous structures.

[0064] Next, new nanoclusters 20 are formed with their flat surfaces facing the surface of the substrate 32. Then, particles 23 are deposited so as to fill in the areas where no nanoclusters 20 have been formed, thereby forming lateral growth portions 22 (see FIG. 3C). In this way, particles 23 adhere to the side surfaces of the nanoclusters 20, and the lateral growth portions 22 grow laterally, connecting the nanoclusters 20 in the second layer (see FIG. 3D).

[0065] According to the above-described film formation model, nanoclusters are thought to deposit on the surface of the substrate (the surface on which the film is to be formed). Since CAAC-OS films can be formed even on surfaces that do not have a crystalline structure, the above-described film formation model, which uses a growth mechanism different from epitaxial growth, is highly valid.

[0066] As described above, CAAC-OS is a metal oxide with a highly crystalline, dense structure and few impurities and defects (such as oxygen vacancies, Vo). On the other hand, it is difficult to identify clear grain boundaries in CAAC-OS, so it is unlikely that a decrease in electron mobility due to grain boundaries will occur. Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0067] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen near the oxygen vacancies may be introduced into the oxygen vacancies (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in a region in an oxide semiconductor where a channel is formed, the transistor is likely to have normally-on characteristics (a channel exists even when no voltage is applied to the gate electrode, and a current flows through the transistor). Therefore, it is preferable that impurities and oxygen vacancies are reduced as much as possible in the region in an oxide semiconductor where a channel is formed. In other words, it is preferable that the carrier concentration in the region in an oxide semiconductor where a channel is formed is reduced and the region is made i-type (intrinsic) or substantially i-type.

[0068] In contrast, by using the above-described CAAC-OS for the oxide 230b and the oxide 230c, impurities and oxygen vacancies can be reduced in a region where a channel is formed in the oxide semiconductor, thereby suppressing fluctuations in the electrical characteristics and providing a transistor with stable electrical characteristics and improved reliability.

[0069] However, when forming an opening for embedding the conductor 260 or the like, the surface of the oxide 230b at the bottom of the opening may be damaged. In the damaged region of the oxide 230b, crystal defects such as oxygen vacancies are formed, and impurities (metal elements such as hydrogen, nitrogen, silicon, and aluminum) may be present. Since oxygen vacancies and impurities such as hydrogen are likely to exist in the damaged region, V O +H→V O In this way, the reaction V O A large amount of H is formed. Therefore, even if oxide 230c is formed on oxide 230b while leaving the damaged region, the transistor tends to have normally-on characteristics. Furthermore, the state of the damaged region varies across the substrate surface, which causes variations in the characteristics of semiconductor devices having transistors.

[0070] For example, in a cross-sectional view of the transistor in the channel length direction, the damaged region can be removed by forming a groove above the oxide 230b. The oxide 230c having the CAAC-OS can be formed in the groove of the oxide 230b after the damaged region is removed. Note that cleaning treatment is preferably performed to remove the damaged region. Details of the cleaning treatment will be described later.

[0071] Therefore, in the transistor according to one embodiment of the present invention, a groove is preferably formed in the oxide 230b in a cross-sectional view of the transistor in the channel length direction, and the oxide 230c having the CAAC-OS is preferably filled in the groove. In this case, the oxide 230c is disposed to cover the inner wall (side wall and bottom surface) of the groove. In addition, the thickness of the oxide 230c is preferably approximately the same as the depth of the groove.

[0072] By using the above configuration, V O The influence of impurities such as H can be reduced, and a channel can be formed in the oxide 230c. This allows the transistor to have good electrical characteristics. Furthermore, a semiconductor device with little variation in transistor characteristics and good reliability can be provided.

[0073] 1A and 1B, which are enlarged cross-sectional views of the transistor 200 and its vicinity, the structure in the vicinity of the channel of the transistor 200 will be described in detail below. Note that the dashed lines in FIGS. 1A and 1B indicate the crystalline layers in the oxide 230b and the oxide 230c.

[0074] As shown in FIGS. 1A and 1B, the oxide 230b includes layered crystals having a crystal layer extending in the ab-plane direction and a c-axis perpendicular to the ab-plane direction. The arrow in FIG. 1B indicates the crystal c-axis. Preferably, the c-axis of the oxide 230b is oriented in a direction substantially perpendicular to the surface on which the oxide 230b is formed or the top surface of the oxide 230b. Therefore, as shown in FIG. 1, the oxide 230b has a region in which the crystal layer extends substantially parallel to the top surface of the oxide 230b.

[0075] Furthermore, a groove is formed in the upper portion of the oxide 230b. This groove corresponds to the bottom of an opening formed in the insulator 280 and the like to embed the conductor 260 and the like. In other words, this groove overlaps the conductor 260, the insulator 250, the oxide 230d, and the oxide 230c. As shown in FIGS. 1A and 1B, the sidewall of this groove is preferably approximately perpendicular to the surface on which the oxide 230b is to be formed. Similarly, the sidewall of the opening is preferably approximately perpendicular to the surface on which the oxide 230b is to be formed.

[0076] Furthermore, it is preferable that the depth of the grooves in oxide 230b roughly coincide with the film thickness of oxide 230c. In other words, it is preferable that the height of the interface between oxide 230b and oxide 243 roughly coincide with the height of the interface between oxide 230c and oxide 230d. For example, it is preferable that the difference between the height of the interface between oxide 230b and oxide 243 and the height of the interface between oxide 230c and oxide 230d be equal to or less than the film thickness of oxide 230c, and more preferably equal to or less than half the film thickness of oxide 230c.

[0077] 1A and 1B, the oxide 230c includes layered crystals having a crystal layer extending in the ab-plane direction and a c-axis perpendicular to the ab-plane direction. Preferably, the c-axis of the oxide 230c is oriented in a direction substantially perpendicular to the surface on which the oxide 230c is formed or the top surface of the oxide 230c. Therefore, as shown in FIG. 1, the oxide 230c has a region in which the crystal layer extends substantially parallel to the top surface of the oxide 230b, and a region in which the crystal layer extends substantially parallel to the side surfaces of the oxide 243, the conductor 242, the insulator 272, the insulator 273, and the insulator 280. It is more preferable that the oxide 230d also have a crystal structure similar to that of the oxide 230c, as shown in FIGS. 1A and 1B.

[0078] As described above, it is preferable to reduce or remove impurities at the interface between the oxide 230b and the oxide 230c and in the vicinity thereof. In particular, impurities such as aluminum or silicon inhibit the formation of a CAAC-OS oxide in the oxide 230c and the oxide 230b. Therefore, it is preferable to reduce or remove impurity elements such as aluminum or silicon that inhibit the formation of a CAAC-OS oxide. For example, the concentration of aluminum atoms at the interface between the oxide 230b and the oxide 230c and in the vicinity thereof may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0079] The metal oxide region where the transformation into a CAAC-OS is inhibited by impurities such as aluminum or silicon and becomes an amorphous-like oxide semiconductor (a-like OS) is sometimes called a non-CAAC region. In the CAAC-OS, a dense crystalline structure such as In-O-In is formed, whereas in the non-CAAC region, the In-O bond distance is longer, resulting in a less dense crystalline structure. In such a non-CAAC region, the reaction shown in (1) proceeds between the In-O bonds, and then the structure shown in (2) is formed. V O +H→V O H(1) In-V O H…O-In(2) This results in V in the non-CAAC region. O A large amount of H is formed, which makes the transistor more likely to be normally on. For these reasons, it is preferable that the non-CAAC region is reduced or eliminated.

[0080] In contrast, in the oxide 230b and the oxide 230c which have been converted into CAAC-OS, a dense crystal structure is formed, and therefore the In-O bond distance is shortened, and V O Furthermore, in the oxygen addition process described later, excess oxygen is supplied to the oxide 230b and the oxide 230c, and V O H→V O +H, V O +O→null reaction can proceed. This allows V in oxide 230b and oxide 230c to O Reduce H and V O In this manner, by making the oxide 230b and the oxide 230c into CAAC-OS, it is possible to prevent the transistor from becoming normally on.

[0081] 1A and 1B, in the groove portion of oxide 230b, the side surface of oxide 230c contacts the sidewall of the groove portion of oxide 230b. Hereinafter, the interface between oxide 230b and oxide 230c on the sidewall of the groove portion may be referred to as interface 232. Here, oxide 230c is formed by lateral growth starting from nanoclusters, as described above with reference to FIG. 3. Also, as described above, at interface 232, the side surface of oxide 230b is approximately perpendicular to the surface on which oxide 230b is formed.

[0082] 3A, the side surface of the oxide 230b functions similarly to the lateral growth portion 22 of the nanocluster 20 shown in FIG. 3A, and the oxide 230c is formed by lateral growth starting from the side surface of the oxide 230b. As a result, the ab planes of the CAAC-OS of the oxide 230b and the CAAC-OS of the oxide 230c are continuously bonded at the interface 232. When the ab planes of the oxide 230b and the oxide 230c are continuously bonded, for example, a clear grain boundary may not be visible in a cross-sectional TEM image of the interface between the oxide 230b and the oxide 230c.

[0083] 1A shows current paths A and B of the transistor 200. Current path A is a path that runs from the conductor 242a through the oxide 230c to the conductor 242b, and current path B is a path that runs from the conductor 242a through the oxide 243a, the oxide 230c, and the oxide 243b in this order to the conductor 242b. In most of the current paths A and B, a CAAC-OS is formed, and damaged regions of the oxide 230b are removed, preventing the formation of non-CAAC regions. This can suppress fluctuations in the electrical characteristics of the transistor 200.

[0084] In particular, a layered CAAC-OS is formed near the interface 232, that is, up to the drain edge. In other words, the semiconductor device of one embodiment of the present invention also has a CAAC structure at the drain edge or the bottom of the drain. Here, in the transistor 200, the conductor 242a or the conductor 242b and its vicinity function as the drain. That is, in the semiconductor device of one embodiment of the present invention, one or both of the oxide 230b and the oxide 230c near the bottom of the conductor 242a (conductor 242b) have the CAAC structure. Thus, even at the drain edge, which significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed. Having the CAAC structure further suppresses fluctuations in the electrical characteristics of the transistor 200. Furthermore, the reliability of the transistor 200 can be improved.

[0085] By adopting the above-described configuration, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device with good electrical characteristics.

[0086] 1 illustrates a configuration in which the side of the opening in which the conductor 260 and the like are embedded, including the groove portion of the oxide 230b, is approximately perpendicular to the surface on which the oxide 230b is formed. However, this embodiment is not limited to this. For example, as shown in FIGS. 4A and 4B, the bottom of the opening may have a gently curved U-shape. FIG. 4A is an enlarged view of the vicinity of the channel formation region of the transistor 200 corresponding to FIG. 1A, and FIG. 4B is an enlarged view of the vicinity of the interface between the oxide 243a and the oxide 230c in FIG. 4A.

[0087] As shown in FIGS. 4A and 4B, the oxide 230c includes layered crystals having a crystal layer extending in the ab-plane direction and a c-axis perpendicular to the ab-plane direction. The arrow in FIG. 4B indicates the crystal c-axis. Preferably, the c-axis of the oxide 230c is oriented in a direction substantially perpendicular to the surface on which the oxide 230c is formed or the top surface. Therefore, as shown in FIG. 4, the oxide 230d has a region in which the crystal layer extends substantially parallel to the bottom and side surfaces of the opening. As shown in FIGS. 4A and 4B, it is more preferable that the oxide 230d also have a similar crystal structure to the oxide 230c.

[0088] Furthermore, it is preferable that the depth of the grooves in oxide 230b roughly coincide with the film thickness of oxide 230c. In other words, it is preferable that the height of the interface between oxide 230b and oxide 243 roughly coincide with the height of the lowest point of the interface between oxide 230c and oxide 230d. For example, it is preferable that the difference between the height of the interface between oxide 230b and oxide 243 and the height of the lowest point of the interface between oxide 230c and oxide 230d be equal to or less than the film thickness of oxide 230c, and more preferably equal to or less than half the film thickness of oxide 230c.

[0089] Furthermore, the angle between the ab plane of the oxide 230c in the groove and the ab plane of the oxide 230b is preferably 60° or less, more preferably 45° or less, and even more preferably 30° or less. By reducing the angle between the ab plane of the oxide 230c in the groove and the ab plane of the oxide 230b in this way, the crystallinity of the oxide 230c in the groove can be increased.

[0090] Furthermore, as shown in FIG. 4C , an oxide 230e consisting of a non-CAAC region may be formed adjacent to the interface between the oxide 230b and the oxide 230c. It is preferable that impurities in the oxide 230e be reduced. In particular, it is preferable that impurity elements such as aluminum and silicon that inhibit the formation of a CAAC-OS structure be reduced. For example, the concentration of aluminum atoms in the oxide 230e may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %. As described above, it is preferable that the oxide 230e having such a non-CAAC region be reduced.

[0091] 4C, the oxide 230e is formed so as to be surrounded by the oxide 230b, the oxide 243a, the oxide 230c, and the oxide 230d, but this embodiment is not limited to this. For example, the oxide 230e may be formed so as to be sandwiched between the oxide 230b and the oxide 230c.

[0092] 2C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0093] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape improves the coverage of the groove with the insulator 250 and conductor 260 formed in a later process. Furthermore, it is possible to prevent a decrease in the length of the region without the curved surface and suppress a decrease in the on-current and mobility of the transistor 200. Therefore, a semiconductor device with excellent electrical characteristics can be provided.

[0094] The oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the metal element that is the main component is preferably larger than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.

[0095] To make the oxide 230c the main carrier path, the atomic ratio of indium to the main metal element in the oxide 230c is preferably larger than the atomic ratio of indium to the main metal element in the oxide 230b. Using a metal oxide with a high indium content for the channel formation region can increase the on-state current of the transistor. Therefore, by making the atomic ratio of indium to the main metal element in the oxide 230c larger than the atomic ratio of indium to the main metal element in the oxide 230b, the oxide 230c can be made the main carrier path.

[0096] Furthermore, the conduction band minimum of the oxide 230c is preferably farther from the vacuum level than the conduction band minimums of the oxides 230a and 230b. In other words, the electron affinity of the oxide 230c is preferably greater than the electron affinity of the oxides 230a and 230b. In this case, the oxide 230c serves as the main carrier path.

[0097] Specifically, the oxide 230c may be a metal oxide or indium oxide having a composition of In:M:Zn=4:2:3 (atomic ratio) or a composition close thereto, In:M:Zn=5:1:3 (atomic ratio) or a composition close thereto, or In:M:Zn=10:1:3 (atomic ratio) or a composition close thereto.

[0098] One parameter used to evaluate transistor reliability is the shift voltage (Vsh), measured in a +GBT (Gate Bias Temperature) stress test. The shift voltage (Vsh) is defined as the Vg at which the tangent to the maximum slope of the transistor's drain current (Id)-gate voltage (Vg) curve intersects with the line at Id = 1 pA. The amount of change in Vsh is expressed as ΔVsh.

[0099] In a +GBT stress test of a transistor, ΔVsh may shift in the negative direction over time. Also, ΔVsh may exhibit behavior in which it fluctuates in both the negative and positive directions rather than fluctuating in a negative direction (e.g., the negative direction). Note that in this specification and elsewhere, this behavior may be referred to as the jagged behavior of ΔVsh in a +GBT stress test.

[0100] By using a metal oxide that does not contain element M as a main component or a metal oxide with a low ratio of element M as oxide 230c, for example, it is possible to reduce ΔVsh, suppress the jagged behavior of ΔVsh, and improve the reliability of the transistor.

[0101] Furthermore, the oxide 230b and the oxide 230c are preferably crystalline oxides such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), and have a highly crystalline and dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 230b. This reduces the extraction of oxygen from the oxide 230b even during heat treatment, making the transistor 200 stable against high temperatures (so-called thermal budget) during the manufacturing process.

[0102] The oxide 230c is preferably a CAAC-OS, and the c-axis of the crystal of the oxide 230c is preferably oriented in a direction substantially perpendicular to the surface on which the oxide 230c is formed or the top surface of the oxide 230c. The CAAC-OS has the property of easily transferring oxygen in a direction perpendicular to the c-axis. Therefore, oxygen contained in the oxide 230c can be efficiently supplied to the oxide 230b.

[0103] Furthermore, the oxide 230d preferably contains at least one of the metal elements constituting the metal oxide used in the oxide 230c, and more preferably contains all of the metal elements. For example, the oxide 230c may be an In-M-Zn oxide, an In-Zn oxide, or an indium oxide, and the oxide 230d may be an In-M-Zn oxide, an M-Zn oxide, or an oxide of element M. This can reduce the defect state density at the interface between the oxide 230c and the oxide 230d.

[0104] Furthermore, the conduction band minimum of the oxide 230d is preferably closer to the vacuum level than the conduction band minimum of the oxide 230c. In other words, the electron affinity of the oxide 230d is preferably smaller than that of the oxide 230c. In this case, the oxide 230d is preferably made of a metal oxide that can be used for the oxide 230a or the oxide 230b. In this case, the main carrier path is the oxide 230c.

[0105] Specifically, the oxide 230c may be a metal oxide or indium oxide having a composition of In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=5:1:3 [atomic ratio] or a composition close thereto, or In:M:Zn=10:1:3 [atomic ratio] or a composition close thereto, and the oxide 230d may be a metal oxide or oxide of element M having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, M:Zn=2:1 [atomic ratio] or a composition close thereto, or M:Zn=2:5 [atomic ratio] or a composition close thereto.

[0106] Furthermore, the oxide 230d is preferably a metal oxide that suppresses the diffusion or permeation of oxygen more than the oxide 230c. By providing the oxide 230d between the insulator 250 and the oxide 230c, it is possible to suppress the diffusion of oxygen contained in the insulator 280 into the insulator 250. Therefore, the oxygen can be efficiently supplied to the oxide 230b via the oxide 230c.

[0107] Furthermore, by making the atomic ratio of In to the main component metal element in the metal oxide used for the oxide 230d smaller than the atomic ratio of In to the main component metal element in the metal oxide used for the oxide 230c, it is possible to suppress diffusion of In toward the insulator 250. Because the insulator 250 functions as a gate insulator, if In gets mixed into the insulator 250, etc., the transistor characteristics will be poor. Therefore, by providing the oxide 230d between the oxide 230c and the insulator 250, it is possible to provide a highly reliable semiconductor device.

[0108] Here, the conduction band minimum changes smoothly at the junctions between the oxides 230a, 230b, 230c, and 230d. In other words, the conduction band minimum at the junctions between the oxides 230a, 230b, 230c, and 230d changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layers formed at the interfaces between the oxides 230a and 230b, between the oxides 230b and 230c, and between the oxides 230c and 230d.

[0109] Specifically, when the oxide 230a and the oxide 230b, the oxide 230b and the oxide 230c, and the oxide 230c and the oxide 230d have a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 230b is an In-M-Zn oxide, the oxide 230a, the oxide 230c, and the oxide 230d may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0110] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. The oxide 230b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition. The oxide 230c may be a metal oxide having an atomic ratio of In:M:Zn=4:2:3 or a similar composition, an atomic ratio of In:M:Zn=5:1:3 or a similar composition, or an atomic ratio of In:M:Zn=10:1:3 or a similar composition, or an indium oxide. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M. Furthermore, as the oxide 230d, a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, a composition of M:Zn=2:1 [atomic ratio] or a composition close thereto, or a composition of M:Zn=2:5 [atomic ratio] or a composition close thereto, or an oxide of the element M may be used.

[0111] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0112] By configuring the oxides 230a, 230b, 230c, and 230d as described above, the defect state density can be reduced at the interface between the oxides 230a and 230b, the interface between the oxides 230b and 230c, and the interface between the oxides 230c and 230d, which reduces the effect of interface scattering on carrier conduction, allowing the transistor 200 to achieve a large on-state current and high frequency characteristics.

[0113] Note that the oxide 230c may be provided for each transistor 200. That is, the oxide 230c of one transistor 200 and the oxide 230c of another transistor 200 adjacent to the transistor 200 may not be in contact with each other. Alternatively, the oxide 230c of one transistor 200 and the oxide 230c of another transistor 200 adjacent to the transistor 200 may be separated from each other. In other words, the oxide 230c may not be disposed between the transistor 200 and the transistor 200 adjacent to the transistor 200.

[0114] In a semiconductor device in which multiple transistors 200 are arranged in the channel width direction, the above structure allows the oxide 230c to be independently provided in each transistor 200. This prevents a parasitic transistor from being formed between a transistor 200 and a transistor 200 adjacent to the transistor 200, thereby preventing the leakage path from being formed. This makes it possible to provide a semiconductor device that has favorable electrical characteristics and can be miniaturized or highly integrated.

[0115] For example, if the distance between the side edge of the oxide 230c of one transistor 200 and the side edge of the oxide 230c of another transistor 200 adjacent to the transistor 200, which face each other in the channel width direction of the transistor 200, is represented as L1, L1 is set to be greater than 0 nm. Furthermore, if the distance between the side edge of the oxide 230a of one transistor 200 and the side edge of the oxide 230a of another transistor 200 adjacent to the transistor 200, which face each other in the channel width direction of the transistor 200, is represented as L2, the ratio of L1 to L2 (L1 / L2) is preferably greater than 0 and less than 1, more preferably 0.1 to 0.9, and even more preferably 0.2 to 0.8. Note that L2 may also be the distance between the side edge of the oxide 230b of one transistor 200 and the side edge of the oxide 230b of another transistor 200 adjacent to the transistor 200, which face each other.

[0116] By reducing the ratio of L1 to L2 (L1 / L2), even if a misalignment occurs in the region where oxide 230c is not located between transistor 200 and the transistor 200 adjacent to said transistor 200, oxide 230c of transistor 200 can be separated from oxide 230c of the transistor 200 adjacent to said transistor 200.

[0117] Furthermore, by increasing the ratio of L1 to L2 (L1 / L2), even if the distance between a transistor 200 and an adjacent transistor 200 is narrowed, the width of the minimum processing dimension can be ensured, thereby enabling further miniaturization or high integration of semiconductor devices.

[0118] Note that the conductor 260 and the insulator 250 may be shared between adjacent transistors 200. That is, the conductor 260 of one transistor 200 has a region provided continuously with the conductor 260 of another transistor 200 adjacent to the transistor 200. Furthermore, the insulator 250 of one transistor 200 has a region provided continuously with the insulator 250 of another transistor 200 adjacent to the transistor 200.

[0119] With the above structure, the oxide 230d has a region in contact with the insulator 224 between the transistor 200 and another transistor 200 adjacent to the transistor 200. Note that the oxide 230c and the oxide 230d of one transistor 200 may be separated from the oxide 230c and the oxide 230d of another transistor 200 adjacent to the transistor 200.

[0120] The insulators 211, 212, 214, 272, 273, 282, 283, 284, and 286 preferably function as barrier insulating films that suppress the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, the insulators 211, 212, 214, 272, 273, 282, 283, 284, and 286 are preferably made of an insulating material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as NO, NO, and NO), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively ... oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like).

[0121] For example, it is preferable to use silicon nitride or the like for the insulators 211, 212, 283, and 284, and aluminum oxide or the like for the insulators 214, 272, 273, and 282. This can prevent impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200 side through the insulators 211, 212, and 214. Alternatively, it can prevent oxygen contained in the insulator 224 or the like from diffusing to the substrate side through the insulators 211, 212, and 214. It can also prevent impurities such as water and hydrogen from diffusing from the insulator 280, the conductor 246, and the like, which are arranged above the insulator 273, to the transistor 200 side through the insulators 272 and 273. In this way, it is preferable to have a structure in which transistor 200 is surrounded by insulators 211, 212, 214, 272, 273, 282, 283, and 284, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0122] It may also be preferable to reduce the resistivity of the insulators 211, 284, and 286. For example, it may be preferable to reduce the resistivity of the insulators 211, 284, and 286 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulator 211, the insulator 284, and the insulator 286 may be able to reduce charge-up of the conductor 205, the conductor 242, the conductor 260, or the conductor 246 during treatment using plasma or the like in the semiconductor device manufacturing process. The resistivity of the insulator 211, the insulator 284, and the insulator 286 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0123] Note that the insulator 211 or the insulator 212 is not necessarily provided, and the insulator 283 or the insulator 284 is not necessarily provided. For example, this may be the case when the insulator 212 and the insulator 284 are formed by a CVD method using a compound gas that does not contain hydrogen atoms or has a low hydrogen atom content.

[0124] Furthermore, the insulators 216 and 280 preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, the insulators 216 and 280 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0125] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V compared to not applying a negative potential to the conductor 205.

[0126] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulator 214 or the insulator 216.

[0127] As shown in FIG. 2A, the conductor 205 is preferably larger than the area of ​​the oxide 230 that does not overlap with the conductors 242a and 242b. In particular, as shown in FIG. 2C, the conductor 205 preferably extends to an area outside the end of the oxide 230 that intersects with the channel width direction. In other words, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator outside the side surface of the oxide 230 in the channel width direction. This structure allows the channel formation region of the oxide 230 to be electrically surrounded by the electric field of the conductor 260, which functions as the first gate electrode, and the electric field of the conductor 205, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0128] In this specification, an S-channel transistor refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. In this specification, the S-channel structure is characterized in that the side and periphery of the oxide 230 in contact with the conductors 242a and 242b, which function as source and drain electrodes, are I-type, just like the channel formation region. Furthermore, the side and periphery of the oxide 230 in contact with the conductors 242a and 242b can be I-type, just like the channel formation region, because they are in contact with the insulator 280. In this specification, I-type can be treated as the same as the high-purity intrinsic oxide described later. The S-channel structure disclosed in this specification differs from the fin structure and planar structure. The S-channel structure enhances resistance to the short-channel effect, in other words, makes the transistor less susceptible to the short-channel effect.

[0129] 2C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Furthermore, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0130] Note that, in the transistor 200, the conductor 205 has a stacked structure of the conductor 205a and the conductor 205b, but the present invention is not limited to this. For example, the conductor 205 may have a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, it may be distinguished by assigning an ordinal number to the order of formation.

[0131] Here, the conductor 205a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0132] By using a conductive material capable of suppressing oxygen diffusion for the conductor 205a, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials capable of suppressing oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 205a may be a multilayer of tantalum, tantalum nitride, ruthenium, or ruthenium oxide with titanium or titanium nitride.

[0133] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Although the conductor 205b is illustrated as a single layer, it may have a multilayer structure, for example, a multilayer structure of titanium or titanium nitride and the conductive material.

[0134] Insulator 222 and insulator 224 function as gate insulators.

[0135] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0136] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 can be prevented from reacting with the insulator 224 or the oxygen contained in the oxide 230.

[0137] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0138] The insulator 222 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0139] The insulator 224 in contact with the oxide 230 preferably releases oxygen by heating. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

[0140] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating, in other words, an insulator material having an excess oxygen region, as the insulator 224. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0 × 10 19 molecules / cm 3 More preferably, 2.0 × 10 19 molecules / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0141] Furthermore, the oxide 230 may be brought into contact with an insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 230 can be removed. For example, in the oxide 230, defects (V) in which hydrogen has entered an oxygen vacancy can be removed. O A reaction occurs in which the bond of V O H→V O +H" reaction occurs, resulting in dehydrogenation. Some of the hydrogen generated at this time may combine with oxygen to form HO, which may be removed from the oxide 230 or an insulator near the oxide 230. Some of the hydrogen may also diffuse or be captured (also called gettering) by the conductor 242.

[0142] The microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using an oxygen-containing gas and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 230 or an insulator near the oxide 230 by applying RF to the substrate side. The microwave treatment may be performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. The gases introduced into the microwave treatment apparatus may be, for example, oxygen and argon, with an oxygen flow ratio (O2 / (O2+Ar)) of 50% or less, preferably 10% to 30%.

[0143] In addition, during the manufacturing process of the transistor 200, it is preferable to perform heat treatment while the surface of the oxide 230 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0144] By subjecting the oxide 230 to oxygen addition treatment, oxygen vacancies in the oxide 230 are repaired by the supplied oxygen. In other words, OFurthermore, the reaction of the hydrogen remaining in the oxide 230 with the supplied oxygen can be removed as H2O (dehydration). As a result, the hydrogen remaining in the oxide 230 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0145] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structures are not limited to those made of the same material, and may be those made of different materials.

[0146] Oxide 243 (oxide 243a and oxide 243b) may be provided on oxide 230b.

[0147] The oxide 243 (oxide 243a and oxide 243b) preferably has a function of suppressing oxygen permeation. By disposing the oxide 243, which has a function of suppressing oxygen permeation, between the conductor 242, which functions as a source electrode or a drain electrode, and the oxide 230b, the electrical resistance between the conductor 242 and the oxide 230b is reduced, which is preferable. This structure can improve the electrical characteristics and reliability of the transistor 200. Note that if the electrical resistance between the conductor 242 and the oxide 230b can be sufficiently reduced, the oxide 243 may not be provided.

[0148] A metal oxide containing element M may be used as oxide 243. In particular, element M may be aluminum, gallium, yttrium, or tin. Preferably, oxide 243 has a higher concentration of element M than oxide 230b. Alternatively, oxide 243 may be gallium oxide. Alternatively, oxide 243 may be a metal oxide such as In-M-Zn oxide. Specifically, the atomic ratio of element M to In in the metal oxide used for oxide 243 is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. Furthermore, the film thickness of oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. Furthermore, oxide 243 preferably has crystallinity. When oxide 243 has crystallinity, oxygen release from oxide 230 can be effectively suppressed. For example, oxide 243 with a hexagonal or other crystal structure may be able to suppress oxygen release from oxide 230.

[0149] The conductor 242a is provided over the oxide 243a, and the conductor 242b is provided over the oxide 243b. The conductor 242a and the conductor 242b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0150] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when they absorb oxygen.

[0151] If the oxide 243 is not provided, contact between the conductor 242 and the oxide 230b or the oxide 230c may cause oxygen in the oxide 230b or the oxide 230c to diffuse into the conductor 242, resulting in oxidation of the conductor 242. The oxidation of the conductor 242 is likely to result in a decrease in the conductivity of the conductor 242. The diffusion of oxygen in the oxide 230b or the oxide 230c into the conductor 242 can be rephrased as the conductor 242 absorbing the oxygen in the oxide 230b or the oxide 230c.

[0152] Furthermore, oxygen in the oxide 230b or the oxide 230c diffuses into the conductor 242a and the conductor 242b, which may form layers between the conductor 242a and the oxide 230b, between the conductor 242b and the oxide 230b, or between the conductor 242a and the oxide 230c, and between the conductor 242b and the oxide 230c. Because these layers contain more oxygen than the conductor 242a or the conductor 242b, they are presumed to have insulating properties. In this case, the three-layer structure of the conductor 242a or the conductor 242b, the layer, and the oxide 230b or the oxide 230c can be regarded as a three-layer structure consisting of a metal, an insulator, and a semiconductor, and can be regarded as a metal-insulator-semiconductor (MIS) structure or a diode junction structure primarily based on the MIS structure.

[0153] Note that hydrogen contained in the oxide 230b, the oxide 230c, and the like may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b, the oxide 230c, and the like is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b, the oxide 230c, and the like may be absorbed by the conductor 240a or the conductor 242b.

[0154] Furthermore, there may be a curved surface between the side surface of the conductor 242 and the top surface of the conductor 242. In other words, the end of the side surface and the end of the top surface may be curved. The curved surface has a radius of curvature of, for example, 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less, at the end of the conductor 242. The lack of corners at the end improves film coverage in the subsequent film formation process.

[0155] The insulator 272 preferably covers the top and side surfaces of the conductor 242 and functions as a barrier layer. This structure can prevent the conductor 242 from absorbing excess oxygen contained in the insulator 280. Furthermore, by preventing oxidation of the conductor 242, an increase in contact resistance between the transistor 200 and wiring can be suppressed. Therefore, the transistor 200 can have good electrical characteristics and reliability.

[0156] Therefore, the insulator 272 preferably has a function of suppressing oxygen diffusion. For example, the insulator 272 preferably has a function of suppressing oxygen diffusion more than the insulator 280. As the insulator 272, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. Alternatively, as the insulator 272, for example, an insulator containing aluminum nitride may be used.

[0157] In addition, oxygen may be supplied to the insulator 224 during the formation of the insulator 272. The oxygen supplied to the insulator 224 is prevented from diffusing outward because the insulator 224 is sealed by the insulators 272 and 273, and can be efficiently supplied to the oxide 230. In addition, hydrogen in the insulator 224 may be absorbed by the insulator 273, which is preferable.

[0158] Note that instead of providing the insulators 272 and 273, an insulator functioning as a barrier layer may be provided between the top surface of the conductor 242 and the insulator 280. This structure can prevent the conductor 242 from absorbing excess oxygen contained in the insulator 280. Furthermore, by suppressing oxidation of the conductor 242, an increase in contact resistance between the transistor 200 and wiring can be suppressed. Therefore, the transistor 200 can have good electrical characteristics and reliability.

[0159] Therefore, it is preferable that the insulator has a function of suppressing the diffusion of oxygen. For example, it is preferable that the insulator has a function of suppressing the diffusion of oxygen more than the insulator 280.

[0160] As the insulator, for example, an insulator containing oxide of one or both of aluminum and hafnium may be formed. In particular, an aluminum oxide film may be formed by atomic layer deposition (ALD). By forming the film using the ALD method, a dense film with reduced defects such as cracks and pinholes and a uniform thickness may be formed. Furthermore, as the insulator, for example, an insulator containing aluminum nitride may be used.

[0161] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with at least a portion of the oxide 230c. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0162] The insulator 250 is preferably formed using an insulator that releases oxygen upon heating, similar to the insulator 224. By providing the insulator that releases oxygen upon heating as the insulator 250 in contact with the top surface of the oxide 230c, oxygen can be effectively supplied to the channel formation region of the oxide 230b, thereby reducing oxygen vacancies in the channel formation region of the oxide 230b. Therefore, a transistor with suppressed fluctuations in electrical characteristics, stable electrical characteristics, and improved reliability can be provided. Furthermore, similar to the insulator 224, the concentrations of impurities such as water and hydrogen in the insulator 250 are preferably reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0163] Although the insulator 250 is illustrated as a single layer in FIGS. 2B and 2C , it may have a laminated structure of two or more layers. When the insulator 250 has a laminated structure of two layers, it is preferable that the lower layer of the insulator 250 is formed using an insulator that releases oxygen when heated, and the upper layer of the insulator 250 is formed using an insulator that has the function of suppressing oxygen diffusion. This configuration can suppress the diffusion of oxygen contained in the lower layer of the insulator 250 into the conductor 260. In other words, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to oxygen contained in the lower layer of the insulator 250. For example, the lower layer of the insulator 250 can be formed using a material that can be used for the insulator 250 described above, and the upper layer of the insulator 250 can be formed using a material similar to that of the insulator 222.

[0164] When silicon oxide or silicon oxynitride is used for the lower layer of the insulator 250, the upper layer of the insulator 250 may be made of an insulating material, which is a high-k material with a high dielectric constant. By forming the gate insulator into a laminated structure consisting of the lower layer of the insulator 250 and the upper layer of the insulator 250, a laminated structure that is stable against heat and has a high dielectric constant can be achieved. This makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0165] Specifically, the upper layer of the insulator 250 can be made of a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.

[0166] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0167] It is preferable that the metal oxide functions as a part of the first gate electrode. For example, the metal oxide that can be used as the oxide 230 can be used as the metal oxide. In this case, by forming the conductor 260a by a sputtering method, the electrical resistance value of the metal oxide can be reduced to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0168] The inclusion of the metal oxide can improve the on-state current of the transistor 200 without weakening the influence of the electric field from the conductor 260. Furthermore, the physical thickness of the insulator 250 and the metal oxide can maintain a distance between the conductor 260 and the oxide 230, thereby suppressing leakage current between the conductor 260 and the oxide 230. Furthermore, the provision of a stacked structure of the insulator 250 and the metal oxide can easily and appropriately adjust the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230.

[0169] The conductor 260 functions as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in FIGS. 2B and 2C, the top surface of the conductor 260 is substantially flush with the top surfaces of the insulator 250 and the oxide 230c. While the conductor 260 is shown in FIGS. 2B and 2C as having a two-layer structure of the conductor 260a and the conductor 260b, it may have a single-layer structure or a stacked structure of three or more layers.

[0170] The conductor 260a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0171] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0172] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0173] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably placed in the region between the conductor 242a and the conductor 242b without alignment.

[0174] 2C , in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b, relative to the bottom surface of the insulator 222. The conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, making it easier for the electric field of the conductor 260 to act on the entire channel formation region of the oxide 230b. This increases the on-state current of the transistor 200 and improves its frequency characteristics. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxides 230a and 230b do not overlap with the conductor 260, relative to the bottom surface of the insulator 222, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0175] The insulator 280 is provided on the insulator 224, the oxide 230, the conductor 242, and the insulator 273. The top surface of the insulator 280 may be planarized.

[0176] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce the parasitic capacitance that occurs between wirings. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is released by heating.

[0177] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. The insulator 280 preferably has a low hydrogen concentration and an excess oxygen region or excess oxygen, and may be formed using, for example, the same material as the insulator 216. The insulator 280 may also have a stacked structure of the above materials, such as a stacked structure of silicon oxide formed by sputtering and silicon oxynitride formed thereon by chemical vapor deposition (CVD). Silicon nitride may also be stacked on top of this.

[0178] The insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 280. The insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 282 and the insulator 283 may be made of, for example, aluminum oxide, silicon nitride, or silicon nitride oxide. For example, the insulator 282 may be made of aluminum oxide, which has a high blocking property against oxygen, and the insulator 283 may be made of silicon nitride, which has a high blocking property against hydrogen.

[0179] The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 240a and 240b may have a layered structure.

[0180] Furthermore, when the conductor 240 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the conductors in contact with the insulators 284, 283, 282, 280, 273, and 272. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Using such a conductive material can prevent oxygen added to the insulator 280 from being absorbed by the conductors 240a and 240b. Furthermore, it is possible to prevent impurities such as water and hydrogen contained in layers above the insulator 284 from being mixed into the oxide 230 through the conductors 240a and 240b.

[0181] The insulators 241a and 241b may be made of, for example, silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 241a and 241b are provided in contact with the insulators 273 and 272, respectively, and thus can prevent impurities such as water and hydrogen contained in the insulator 280 from entering the oxide 230 through the conductors 240a and 240b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a and 240b.

[0182] Conductors 246 (conductors 246a and 246b) may be disposed in contact with the upper surfaces of the conductors 240a and 240b, functioning as wiring. Conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as its main component. The conductor may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0183] Insulator 286 is provided on conductor 246 and on insulator 284. As a result, the upper surface and side surfaces of conductor 246 contact insulator 286, and the lower surface of conductor 246 contacts insulator 284. In other words, conductor 246 can be configured to be surrounded by insulators 284 and 286. This configuration can suppress the permeation of oxygen from the outside and prevent oxidation of conductor 246. This is also preferable because it can prevent impurities such as water and hydrogen from conductor 246 from diffusing to the outside.

[0184] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0185] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride and a metal oxide. Examples of other substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0186] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0187] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0188] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0189] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0190] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0191] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0192] <<Conductors>> The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0193] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0194] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0195] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0196] <<Metal oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as the oxide 230. Metal oxides that can be used as the oxide 230 according to the present invention will be described below.

[0197] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0198] Here, we consider a case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, there are cases where a combination of the aforementioned elements can be used as element M.

[0199] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0200] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors, such as CAAC-OS, polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0201] The nc-OS has periodic atomic arrangement in a small region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0202] In-Ga-Zn oxide (hereinafter referred to as IGZO), a type of metal oxide containing indium, gallium, and zinc, can sometimes have a stable structure when made into the above-mentioned nanocrystals. In particular, since IGZO tends to have difficulty growing crystals in the atmosphere, it may be structurally more stable to make it into smaller crystals (for example, the above-mentioned nanocrystals) than larger crystals (here, crystals of a few millimeters or a few centimeters).

[0203] The a-like OS is a metal oxide having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0204] Oxide semiconductors (metal oxides) have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0205] In addition to the oxide semiconductor, a cloud-aligned composite (CAC)-OS may be used.

[0206] CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and the material as a whole functions as a semiconductor. When CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is a function of allowing electrons (or holes) to flow as carriers, and the insulating function is a function of preventing the flow of electrons as carriers. By making the conductive function and the insulating function act complementarily, a switching function (on / off function) can be imparted to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0207] Furthermore, CAC-OS or CAC-metal oxide has conductive regions and insulating regions. The conductive regions have the above-mentioned conductive function, and the insulating regions have the above-mentioned insulating function. In addition, the conductive regions and the insulating regions may be separated at the nanoparticle level in the material. In addition, the conductive regions and the insulating regions may be unevenly distributed in the material. In addition, the conductive regions may be observed as connected in a cloud-like shape with the periphery blurred.

[0208] In addition, in CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may be dispersed in the material with sizes of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0209] Furthermore, a CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, a CAC-OS or CAC-metal oxide is composed of a component with a wide gap due to an insulating region and a component with a narrow gap due to a conductive region. In this configuration, when carriers flow, the carriers mainly flow in the component with the narrow gap. Furthermore, the component with the narrow gap acts complementarily with the component with the wide gap, and carriers also flow in the component with the wide gap in conjunction with the component with the narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in a channel formation region of a transistor, the transistor can achieve high current driving power in the on state, i.e., a large on-state current, and high field-effect mobility.

[0210] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0211] Furthermore, when focusing on the crystal structure, oxide semiconductors may be classified differently from the above. Here, the classification of the crystal structure of oxide semiconductors will be explained using FIG. 5A. FIG. 5A is a diagram explaining the classification of the crystal structure of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0212] As shown in Figure 5A, IGZO is broadly classified into Amorphous, Crystalline, and Crystal. Amorphous includes completely amorphous. Crystalline includes c-axis aligned crystalline (CAAC), nanocrystalline (nc), and Cloud-Aligned Composite (CAC). Crystalline excludes single crystal, polycrystal, and completely amorphous. Crystal includes single crystal and polycrystal.

[0213] The structure within the bold frame in Figure 5A is an intermediate state between amorphous and crystal, and is a structure belonging to a new boundary region (new crystalline phase). This structure is in the boundary region between amorphous and crystal. In other words, this structure can be described as a structure that is completely different from the energetically unstable amorphous and crystal.

[0214] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) images. Figures 5B and 5C show the XRD spectra of silica glass and IGZO (also called crystalline IGZO), which has a crystal structure classified as Crystalline. Figure 5B shows the XRD spectrum of silica glass, and Figure 5C shows the XRD spectrum of crystalline IGZO. The composition of the crystalline IGZO shown in Figure 5C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the crystalline IGZO shown in Figure 5C is 500 nm.

[0215] As shown by the arrows in Figure 5B, the peak shape of the XRD spectrum of silica glass is nearly symmetrical. On the other hand, as shown by the arrows in Figure 5C, the peak shape of the XRD spectrum of crystalline IGZO is asymmetrical. The asymmetrical peak shape of the XRD spectrum clearly indicates the presence of crystals. In other words, if the peak shape of the XRD spectrum is not symmetrical, it cannot be said to be amorphous. Note that Figure 5C clearly shows the crystalline phase (IGZO crystal phase) at or near 2θ = 31°. The asymmetrical peak shape of the XRD spectrum is presumed to be due to the crystalline phase (microcrystals).

[0216] Specifically, the XRD spectrum of crystalline IGZO shown in Figure 5C has a peak at or near 2θ = 34°. Microcrystals have a peak at or near 2θ = 31°. When an oxide semiconductor film is evaluated using an X-ray diffraction image, as shown in Figure 5C, the spectrum width on the lower angle side is wider than the peak at or near 2θ = 34°. This suggests that the oxide semiconductor film contains microcrystals with a peak at or near 2θ = 31°.

[0217] The crystalline structure of the film can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). Figure 5D shows the diffraction pattern of an IGZO film deposited at room temperature. The IGZO film shown in Figure 5D was deposited by sputtering using an oxide target with an In:Ga:Zn=1:1:1 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction was performed with a probe diameter of 1 nm.

[0218] As shown in Figure 5D, a spot-like pattern, rather than a halo, is observed in the diffraction pattern of the IGZO film deposited at room temperature. Therefore, it is presumed that the IGZO film deposited at room temperature is in an intermediate state, neither crystalline nor amorphous, and it cannot be concluded that it is in an amorphous state.

[0219] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0220] When impurities are mixed into an oxide semiconductor, defect states or oxygen vacancies may be formed. Therefore, when impurities are mixed into the channel formation region of the oxide semiconductor, the electrical characteristics of a transistor using the oxide semiconductor are likely to fluctuate, and the reliability may be reduced. Furthermore, when oxygen vacancies are present in the channel formation region, the transistor is likely to have normally-on characteristics (a channel exists even when no voltage is applied to the gate electrode, and current flows through the transistor).

[0221] A transistor using a metal oxide tends to have a normally-on characteristic due to fluctuations in its electrical characteristics caused by impurities and oxygen vacancies in the metal oxide. Furthermore, when the transistor is operated in a state where the metal oxide contains excess oxygen exceeding the appropriate amount, the valence of the excess oxygen atoms changes, which causes fluctuations in the electrical characteristics of the transistor, and this can lead to reduced reliability.

[0222] Therefore, it is preferable to use a metal oxide with a low carrier concentration in the channel formation region of a transistor. When the carrier concentration of a metal oxide is to be low, the impurity concentration in the metal oxide is reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that in this specification and the like, a metal oxide with a carrier concentration of 1×10 16 cm -3 The following cases are defined as substantially high purity and authentic:

[0223] The carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is 1×10 or less. 16 cm -3 More preferably, it is 1×10 or less. 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0224] Impurities in metal oxides include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. In particular, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water, which can cause oxygen vacancies in the metal oxide. If oxygen vacancies are present in the channel formation region of the metal oxide, the transistor may exhibit normally-on characteristics. Furthermore, if hydrogen enters an oxygen vacancy in the metal oxide, the oxygen vacancy and hydrogen bond to form a V O H may be formed. A defect where hydrogen enters an oxygen vacancy (V OHydrogen atoms (H) function as donors, generating electrons as carriers. Some hydrogen atoms may also bond with oxygen atoms that bond with metal atoms, generating electrons as carriers. Therefore, transistors using metal oxides containing a large amount of hydrogen tend to exhibit normally-on characteristics. Furthermore, since hydrogen atoms in metal oxides are easily moved by stresses such as heat and electric fields, the presence of a large amount of hydrogen in metal oxides can reduce the reliability of transistors.

[0225] In one embodiment of the present invention, V in the oxide 230 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain metal oxides with sufficiently reduced H, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment), and to supply oxygen to the metal oxide to compensate for oxygen deficiencies (sometimes referred to as oxygen addition treatment). O By using a metal oxide in which impurities such as H are sufficiently reduced for the channel formation region of a transistor, stable electrical characteristics can be achieved.

[0226] A defect where hydrogen has entered an oxygen vacancy (V O H) can function as a donor in metal oxides. However, it is difficult to quantitatively evaluate such defects. Therefore, metal oxides are sometimes evaluated by carrier concentration rather than donor concentration. Therefore, in this specification and the like, as a parameter of metal oxides, carrier concentration assuming a state in which no electric field is applied may be used rather than donor concentration. In other words, the "carrier concentration" described in this specification and the like can sometimes be rephrased as "donor concentration." Furthermore, the "carrier concentration" described in this specification and the like can sometimes be rephrased as "carrier density."

[0227] Therefore, it is preferable that the hydrogen content in the metal oxide is reduced as much as possible. Specifically, the hydrogen concentration in the metal oxide obtained by secondary ion mass spectrometry (SIMS) is set to 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0228] The defect levels may include trap levels. Charges trapped in the trap levels of metal oxides take a long time to disappear and may behave like fixed charges. Therefore, a transistor having a channel formation region made of a metal oxide with a high density of trap levels may have unstable electrical characteristics.

[0229] Furthermore, the presence of impurities in the channel formation region of the oxide semiconductor may reduce the crystallinity of the channel formation region or the crystallinity of an oxide provided in contact with the channel formation region. The low crystallinity of the channel formation region tends to reduce the stability or reliability of the transistor. Furthermore, the low crystallinity of the oxide provided in contact with the channel formation region may form an interface state, which may reduce the stability or reliability of the transistor.

[0230] Therefore, in order to improve the stability or reliability of a transistor, it is effective to reduce the concentration of impurities in and around a channel formation region of an oxide semiconductor, such as hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0231] Specifically, the concentration of the impurities measured by SIMS in the channel formation region of the oxide semiconductor and its vicinity is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 or less. Alternatively, the concentration of the impurity in the channel formation region of the oxide semiconductor and its vicinity, as determined by elemental analysis using EDX, is set to 1.0 atomic % or less. Note that when an oxide containing element M is used as the oxide semiconductor, the concentration ratio of the impurity to element M in the channel formation region of the oxide semiconductor and its vicinity is set to less than 0.10, preferably less than 0.05. Here, the concentration of element M used in calculating the concentration ratio may be the concentration in the same region as the region where the concentration of the impurity is calculated, or may be the concentration in the oxide semiconductor.

[0232] Furthermore, metal oxides with reduced impurity concentrations have a low defect state density, and therefore may also have a low trap state density.

[0233] Furthermore, when impurities and oxygen vacancies exist in a channel formation region of a transistor including an oxide semiconductor, the resistance of the oxide semiconductor may be reduced, and the electrical characteristics may be easily changed, resulting in reduced reliability.

[0234] For example, silicon has a higher bond energy with oxygen than indium and zinc. For example, when an In-M-Zn oxide is used as an oxide semiconductor, if silicon is mixed into the oxide semiconductor, oxygen contained in the oxide semiconductor may be taken by the silicon, resulting in oxygen vacancies being formed near the indium or zinc.

[0235] In a transistor using an oxide semiconductor for its channel formation region, if a low-resistance region is formed in the channel formation region, a leakage current (parasitic channel) between the source and drain electrodes of the transistor is likely to occur in the low-resistance region. The parasitic channel is likely to cause defects in transistor characteristics, such as normally-on transistors, increased leakage current, and threshold voltage shift due to stress application. Furthermore, if the processing precision of transistors is low, the state of the parasitic channel varies from transistor to transistor, resulting in variations in transistor characteristics.

[0236] Therefore, it is preferable to reduce the impurities and oxygen vacancies as much as possible in the channel formation region of the oxide semiconductor and its vicinity.

[0237] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 230 is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the oxide 230. For example, it is preferable to use a semiconductor of a simple element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also called an atomic layer material or a two-dimensional material). In particular, it is preferable to use a layered material that functions as a semiconductor.

[0238] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0239] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0240] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0241] <Modification of Semiconductor Device> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS. 6A to 6D and 7A to 7D.

[0242] 6A and 7A show top views of the semiconductor device. Also, FIGS. 6B and 7B are cross-sectional views corresponding to the portion indicated by the dashed line A1-A2 in FIGS. 6A and 7A. Also, FIGS. 6C and 7C are cross-sectional views corresponding to the portion indicated by the dashed line A3-A4 in FIGS. 6A and 7A. Also, FIGS. 6D and 7D are cross-sectional views corresponding to the portion indicated by the dashed line A5-A6 in FIGS. 6A and 7A. Some elements are omitted from the top views of FIGS. 6A and 7A for clarity.

[0243] 6A to 6D and 7A to 7D, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Configuration Example of Semiconductor Device>. Note that, in this section as well, the materials described in detail in <Configuration Example of Semiconductor Device> can be used as the constituent materials of the semiconductor device.

[0244] <<Semiconductor Device Variation 1>> The semiconductor device shown in Figures 6A to 6D is a modified example of the semiconductor device shown in Figures 2A to 2D. The semiconductor device shown in Figures 6A to 6D differs from the semiconductor device shown in Figures 2A to 2D in the shapes of the insulators 283 and 284. The semiconductor device also differs in that it has insulators 274 and 287.

[0245] 6A to 6D , the insulators 212, 214, 216, 222, 224, 272, 273, 280, and 282 are patterned, and the insulator 287 is provided in contact with the side surfaces of the insulators 212, 214, 216, 222, 224, 272, 273, 280, and 282. The insulators 283 and 284 are structured to cover the insulators 212, 214, 216, 222, 224, 272, 273, 280, 282, and 287. That is, insulator 283 contacts the top surface of insulator 282, the top surface and side surfaces of insulator 287, and the top surface of insulator 211, and insulator 284 contacts the top surface and side surfaces of insulator 283. As a result, insulators 214, 216, 222, 224, 272, 273, 280, 282, and 287, including oxide 230 and the like, are isolated from the outside by insulators 283 and 284 and insulator 211. In other words, transistor 200 is disposed within a region sealed by insulators 283, 284, and insulator 211.

[0246] For example, it is preferable to form the insulators 212, 214, 287, and 282 using a material that can capture and fix hydrogen, and to form the insulators 211, 283, and 284 using a material that can suppress the diffusion of hydrogen and oxygen. Typically, aluminum oxide can be used for the insulators 212, 214, 287, and 282. Typically, silicon nitride can be used for the insulators 211, 283, and 284.

[0247] With this configuration, it is possible to prevent hydrogen contained outside the sealed region from being mixed into the sealed region.

[0248] 6A to 6D, the transistor 200 has a structure in which the insulator 211, the insulator 283, and the insulator 284 are provided as a single layer, but the present invention is not limited to this. For example, each of the insulator 211, the insulator 283, and the insulator 284 may have a stacked structure of two or more layers.

[0249] The insulator 274 functions as an interlayer film. The insulator 274 preferably has a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. The insulator 274 can be formed using, for example, a material similar to that of the insulator 280.

[0250] <<Semiconductor Device Modification Example 2>> The semiconductor device shown in Figures 7A to 7D is a modified example of the semiconductor device shown in Figures 6A to 6D. The semiconductor device shown in Figures 7A to 7D differs from the semiconductor device shown in Figures 6A to 6D in that, instead of the oxide 230b, an oxide 230b1 is provided under the oxide 243a and an oxide 230b2 is provided under the oxide 243b. As a result, in the transistor 200 shown in Figure 7, the bottom surface of the oxide 230c is in contact with the top surface of the oxide 230a. Furthermore, the side surfaces of the oxide 230c are in contact with the oxide 230b1, the oxide 230b2, the oxide 243a, the oxide 243b, the conductor 242a, and the conductor 242b.

[0251] In a manufacturing method of the transistor 200 described later, when an opening is formed in the insulator 280 or the like to fill with the conductor 260 or the like, an opening is also formed in the oxide 230b, so that the oxide 230b1 and the oxide 230b2 can be formed. Therefore, the oxide 230b1 and the oxide 230b2 can be formed using the same material as the oxide 230b.

[0252] This structure can remove the damaged regions of the oxide 230b formed in the opening process. This allows the transistor 200 to be manufactured without being affected by impurities such as aluminum or a low-crystallinity structure that occurs in the damaged regions of the oxide 230b. This allows the provision of a semiconductor device with reduced variation in transistor characteristics.

[0253] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device shown in FIGS. 6A to 6D, which is one embodiment of the present invention, will be described with reference to FIGS. 8A to 25A, 8B to 25B, 8C to 25C, and 8D to 25D.

[0254] 8A to 25A are top views. FIGS. 8B to 25B are cross-sectional views corresponding to the portion indicated by the dashed dotted line A1-A2 in FIGS. 8A to 25A, and are also cross-sectional views of the transistor 200 in the channel length direction. FIGS. 8C to 25C are cross-sectional views corresponding to the portion indicated by the dashed dotted line A3-A4 in FIGS. 8A to 25A, and are also cross-sectional views of the transistor 200 in the channel width direction. FIGS. 8D to 25D are cross-sectional views of the portion indicated by the dashed dotted line A5-A6 in FIGS. 8A to 25A. Note that some elements are omitted from the top views in FIGS. 8A to 25A for clarity.

[0255] First, a substrate (not shown) is prepared, and then a film of the insulator 211 is formed on the substrate. The insulator 211 can be formed by a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0256] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0257] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0258] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a plasma enhanced ALD method in which a plasma excited reactant is used, or the like can be used.

[0259] Furthermore, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, enabling the formation of ultrathin films, films with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. The PEALD (Plasma Enhanced ALD) method utilizes plasma, which can be preferable because it enables film formation at lower temperatures. Note that some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by the ALD method may contain higher amounts of impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0260] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0261] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0262] In this embodiment, the insulator 211 is formed by depositing silicon nitride by the CVD method.

[0263] Next, the insulator 212 is deposited on the insulator 211. The insulator 212 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon nitride film is deposited as the insulator 212 by a sputtering method.

[0264] In this way, by using an insulator that is impermeable to copper, such as silicon nitride, as insulators 211 and 212, even if a metal that easily diffuses, such as copper, is used in a conductor below insulator 211 (not shown), it is possible to prevent the metal from diffusing upward through insulators 211 and 212. Furthermore, by using an insulator that is impermeable to impurities, such as water and hydrogen, such as silicon nitride, it is possible to prevent the diffusion of impurities, such as water and hydrogen, contained in the layer below insulator 211.

[0265] Next, the insulator 214 is deposited over the insulator 212. The insulator 214 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is used as the insulator 214.

[0266] It is preferable that the hydrogen concentration of the insulator 212 is lower than that of the insulator 211, and that the hydrogen concentration of the insulator 214 is lower than that of the insulator 212. By forming a silicon nitride film as the insulator 212 by a sputtering method, it is possible to form silicon nitride having a lower hydrogen concentration than the insulator 211 formed by forming a silicon nitride film by a CVD method. Furthermore, by using aluminum oxide as the insulator 214, it is possible to make the hydrogen concentration lower than that of the insulator 212.

[0267] In a subsequent process, the transistor 200 is formed on the insulator 214, and it is preferable that the film close to the transistor 200 has a relatively low hydrogen concentration, and it is preferable that the film with a relatively high hydrogen concentration be placed farther from the transistor 200.

[0268] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide or silicon oxynitride is used as the insulator 216. The insulator 216 is preferably deposited by a deposition method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration in the insulator 216 to be reduced.

[0269] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The region where the opening is formed may also be referred to as an opening. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form the groove. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, it is preferable to use silicon nitride, aluminum oxide, or hafnium oxide for the insulator 214.

[0270] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source may be used. For example, an inductively coupled plasma (ICP) etching apparatus may be used as the dry etching apparatus having a high-density plasma source.

[0271] After the opening is formed, a conductive film that will become the conductor 205a is formed. The conductive film preferably contains a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film can be a stacked film of a conductor that has a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0272] In this embodiment, the conductive film that becomes the conductor 205a has a multilayer structure. First, a tantalum nitride film is formed by sputtering, and then titanium nitride is laminated on the tantalum nitride. By using such a metal nitride as the lower layer of the conductor 205b, even if a metal that easily diffuses, such as copper, is used in the conductive film that becomes the conductor 205b (described later), the metal can be prevented from diffusing out of the conductor 205a.

[0273] Next, a conductive film that will become the conductor 205b is formed. The conductive film can be formed by plating, sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, a low-resistance conductive material such as copper is deposited as the conductive film that will become the conductor 205b.

[0274] Next, a CMP process is performed to remove the conductive film that will become the conductor 205a and a portion of the conductive film that will become the conductor 205b, thereby exposing the insulator 216. As a result, the conductor 205a and the conductor 205b remain only in the openings. This allows the formation of a conductor 205 with a flat upper surface (see FIGS. 8A to 8D). Note that the CMP process may remove a portion of the insulator 216.

[0275] In the above description, the conductor 205 is formed so as to be embedded in the opening of the insulator 216, but this embodiment is not limited to this. For example, the conductor 205 may be formed on the insulator 214, the insulator 216 may be formed on the conductor 205, and a part of the insulator 216 may be removed by performing CMP treatment on the insulator 216, thereby exposing the surface of the conductor 205.

[0276] Next, the insulator 222 is formed over the insulator 216 and the conductor 205. The insulator 222 may be an insulator containing one or both of aluminum and hafnium oxides. Note that aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing one or both of aluminum and hafnium oxides. An insulator containing one or both of aluminum and hafnium oxides has barrier properties against oxygen, hydrogen, and water. The insulator 222 having barrier properties against hydrogen and water prevents hydrogen and water contained in structures provided around the transistor 200 from diffusing into the inside of the transistor 200 through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0277] The insulator 222 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0278] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment may be performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by another heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0279] In this embodiment, heat treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour after the formation of the insulator 222, followed by heat treatment in an oxygen atmosphere at 400° C. for 1 hour. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. The heat treatment can also be performed at the timing after the formation of the insulator 224.

[0280] Next, the insulator 224 is deposited on the insulator 222. The insulator 224 can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon oxide or silicon oxynitride is deposited by CVD as the insulator 224. The insulator 224 is preferably deposited by a deposition method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration of the insulator 224 to be reduced. Since the insulator 224 will be the insulator 224 that comes into contact with the oxide 230a in a later process, it is preferable that the hydrogen concentration be reduced in this manner.

[0281] Here, to form an excess oxygen region in the insulator 224, a plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use an apparatus having a power source that generates high-density plasma using, for example, microwaves. Alternatively, a power source that applies RF (radio frequency) to the substrate side may be provided. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment containing an inert gas using this apparatus, a plasma treatment containing oxygen may be performed to replenish the desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In this case, heat treatment is not required.

[0282] Here, after forming an aluminum oxide film on the insulator 224 by, for example, a sputtering method, CMP processing may be performed until the aluminum oxide reaches the insulator 224. This CMP processing can planarize and smooth the surface of the insulator 224. By placing the aluminum oxide on the insulator 224 and performing the CMP processing, it becomes easier to detect the end point of the CMP processing. Furthermore, the CMP processing may polish a portion of the insulator 224, resulting in a thinner film of the insulator 224. However, the film thickness can be adjusted during the formation of the insulator 224. Planarizing and smoothing the surface of the insulator 224 may prevent a deterioration in the coverage of the oxide film to be formed later and may prevent a decrease in the yield of the semiconductor device. Furthermore, forming an aluminum oxide film on the insulator 224 by a sputtering method is preferable because it allows oxygen to be added to the insulator 224.

[0283] Next, oxide films 230A and 230B are sequentially formed on insulator 224 (see FIGS. 8A to 8D). Preferably, oxide films 230A and 230B are formed consecutively without being exposed to the atmosphere. By forming the films without being exposed to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to oxide films 230A and 230B, and to keep the vicinity of the interface between oxide films 230A and 230B clean.

[0284] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0285] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0286] In particular, during the deposition of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0287] When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by forming the oxide film while heating the substrate.

[0288] In this embodiment, oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. Oxide film 230B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. Each oxide film can be formed according to the desired characteristics of oxide 230a and oxide 230b by appropriately selecting the film formation conditions and atomic ratio.

[0289] Next, an oxide film 243A is formed on the oxide film 230B (see FIGS. 8A to 8D). The oxide film 243A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The atomic ratio of Ga to In in the oxide film 243A is preferably greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 243A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0290] It is preferable to form the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A without exposing them to the atmosphere, for example, by using a multi-chamber film forming apparatus.

[0291] Next, a heat treatment may be performed. The heat treatment can be performed under the heat treatment conditions described above. The heat treatment can remove impurities such as water and hydrogen from the oxide film 230A, the oxide film 230B, and the oxide film 243A. In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 400°C for one hour, followed by another heat treatment in an oxygen atmosphere at 400°C for one hour.

[0292] Next, a conductive film 242A is formed on the oxide film 243A (see FIGS. 8A to 8D). The conductive film 242A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. Note that heat treatment may be performed before the formation of the conductive film 242A. The heat treatment may be performed under reduced pressure, and the conductive film 242A may be formed successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide film 243A can be removed, and the moisture and hydrogen concentrations in the oxide films 230A, 230B, and 243A can be further reduced. The heat treatment temperature is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the heat treatment temperature is set to 200° C.

[0293] Next, the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A are processed into island shapes using lithography to form the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B (see FIGS. 9A to 9D). This processing can be performed using dry etching or wet etching. Dry etching is suitable for fine processing. The oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A may be processed under different conditions. In this process, the thickness of the insulator 224 in the region not overlapping with the oxide 230a may be reduced.

[0294] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. Then, etching is performed through the resist mask to process conductors, semiconductors, insulators, and the like into desired shapes. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or an ion beam may also be used instead of the light described above. When an electron beam or an ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0295] Alternatively, a hard mask made of an insulator or a conductor may be used instead of a resist mask. When using a hard mask, an insulating film or a conductive film that serves as a hard mask material is formed on the conductive film 242A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. The conductive film 242A may be etched after removing the resist mask or with the resist mask left in place. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film 242A. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0296] Here, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are formed so that at least a portion thereof overlaps with the conductor 205. Preferably, the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are approximately perpendicular to the top surface of the insulator 222. When the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are approximately perpendicular to the top surface of the insulator 222, a smaller area and higher density can be achieved when providing multiple transistors 200. Alternatively, the angles formed by the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B and the top surface of the insulator 222 may be small. In this case, it is preferable that the angle formed between the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B and the upper surface of the insulator 222 is 60 degrees or more and less than 70 degrees. By using such a shape, the coverage of the insulator 272 and the like can be improved in subsequent steps, and defects such as voids can be reduced.

[0297] Furthermore, a curved surface is present between the side surface of the conductive layer 242B and the top surface of the conductive layer 242B. In other words, it is preferable that the end of the side surface and the end of the top surface are curved. For example, the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm, at the end of the conductive layer 242B. The lack of corners at the end improves film coverage in the subsequent film formation process.

[0298] Next, the insulator 272 is deposited over the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B (see FIGS. 10B to 10D). The insulator 272 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is deposited by a sputtering method as the insulator 272. By depositing aluminum oxide by a sputtering method, oxygen can be injected into the insulator 224.

[0299] Next, the insulator 273 is deposited on the insulator 272 (see FIGS. 10B to 10D). The insulator 273 can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon nitride is deposited by sputtering as the insulator 273. Alternatively, aluminum oxide may be deposited by ALD as the insulator 273.

[0300] Next, an insulating film to be the insulator 280 is formed on the insulator 273. The insulating film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film can be formed by a sputtering method, and a silicon oxide film can be formed thereon by a PEALD method or a thermal ALD method. The insulating film is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This reduces the hydrogen concentration in the insulator 280. Heat treatment may be performed before the insulating film is formed. The heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 273 can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, the oxide layer 243B, and the insulator 224 can be further reduced. The heat treatment conditions described above can be used.

[0301] Next, the insulating film is subjected to CMP processing to form an insulator 280 with a flat upper surface (see FIGS. 10B to 10D). Note that, similar to the insulator 224, an aluminum oxide film may be formed on the insulator 280 by, for example, a sputtering method, and the CMP processing may be performed until the aluminum oxide reaches the insulator 280.

[0302] Here, microwave treatment may be performed. The microwave treatment is preferably performed in an oxygen-containing atmosphere under reduced pressure. By performing the microwave treatment, an electric field due to microwaves is applied to the insulator 280, the oxide 230b, the oxide 230a, etc., and V in the oxide 230b and the oxide 230a is increased. O H is converted to oxygen vacancy (V O ) and hydrogen (H). At this time, some of the hydrogen that is split may combine with oxygen contained in the insulator 280 and be removed as water molecules. Also, some of the hydrogen may be gettered to the conductor 242 via the insulators 272 and 273.

[0303] Alternatively, a heat treatment may be performed while maintaining the reduced pressure after the microwave treatment. By performing such a treatment, hydrogen in the insulator 280, the oxide 230b, and the oxide 230a can be efficiently removed. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower.

[0304] Furthermore, microwave treatment can modify the film quality of the insulator 280, thereby suppressing the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230 via the insulator 280 in post-processing steps after the formation of the insulator 280 or by heat treatment, etc.

[0305] Next, a portion of the insulator 280, a portion of the insulator 273, a portion of the insulator 272, a portion of the conductive layer 242B, a portion of the oxide layer 243B, and a portion of the oxide 230b are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the conductor 242a, the conductor 242b, the oxide 243a, and the oxide 243b are formed (see FIGS. 11A to 11D).

[0306] When forming the opening, the upper portion of the oxide 230b is removed. By removing a portion of the oxide 230b, a groove is formed in the oxide 230b. Depending on the depth of the groove, the groove may be formed in the process of forming the opening, or may be formed in a process different from the process of forming the opening.

[0307] Furthermore, a portion of the insulator 280, a portion of the insulator 273, a portion of the insulator 272, a portion of the conductive layer 242B, a portion of the oxide layer 243B, and a portion of the oxide 230b can be processed by dry etching or wet etching. Dry etching is suitable for fine processing. The processing may be performed under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 273 and a portion of the insulator 272 may be processed by wet etching, and a portion of the oxide layer 243B, a portion of the conductive layer 242B, and a portion of the oxide 230b may be processed by dry etching. The processing of a portion of the oxide layer 243B and a portion of the conductive layer 242B may be performed under different conditions from the processing of a portion of the oxide 230b.

[0308] Here, when a part of the oxide 230b is removed by dry etching to form the groove, it is preferable to perform the process by increasing the bias power. For example, the power density of the bias power is set to 0.02 W / cm. 2 It should be more than 0.03W / cm 2 It is preferable to set it to 0.06W / cm or more. 2 The dry etching time may be appropriately set in accordance with the depth of the groove.

[0309] Here, it is preferable to remove impurities attached to the surfaces of or diffused into the oxides 230a and 230b. It is also preferable to remove damaged areas formed on the surface of the oxide 230b by the dry etching. Examples of such impurities include those derived from components contained in the insulators 280, 273, and 272, and the conductive layer 242B, components contained in the materials used in the device used to form the openings, and components contained in the gas or liquid used in etching. Examples of such impurities include aluminum, silicon, tantalum, fluorine, and chlorine.

[0310] In order to remove the above-mentioned impurities, a cleaning process is performed. The cleaning method includes wet cleaning using a cleaning solution, plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.

[0311] For wet cleaning, cleaning treatment may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be used in combination as appropriate.

[0312] In this specification, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be referred to as "diluted hydrofluoric acid," and an aqueous solution obtained by diluting commercially available ammonia water with pure water may be referred to as "diluted ammonia water." The concentration, temperature, and other parameters of the aqueous solution may be adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be set to 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be set to 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0313] It is preferable to use a frequency of 200 kHz or more, and more preferably 900 kHz or more, for ultrasonic cleaning, as this frequency can reduce damage to the oxide 230b and the like.

[0314] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0315] In this embodiment, the cleaning process involves wet cleaning using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. This cleaning process can remove impurities that have adhered to the surfaces of or diffused into the oxides 230a and 230b. Furthermore, it can improve the crystallinity of the oxide 230c formed on the oxide 230b.

[0316] In the past, processes such as dry etching or the above-mentioned cleaning process may result in the thickness of the insulator 224 in the area that overlaps the opening but does not overlap with the oxide 230b being thinner than the thickness of the insulator 224 in the area that overlaps with the oxide 230b.

[0317] After the etching or cleaning, a heat treatment may be performed. The heat treatment may be performed at a temperature of 100°C or higher and 450°C or lower, preferably 350°C or higher and 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230a and the oxide 230b, thereby reducing the oxygen vacancy V. O This heat treatment can reduce the crystallinity of the oxide 230b and also improve the crystallinity of the oxide 230c formed in the grooves of the oxide 230b. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0318] Next, the oxide film 230C is formed (see FIGS. 12A to 12D). Heat treatment may be performed before the formation of the oxide film 230C. The heat treatment is preferably performed under reduced pressure, and the oxide film 230C is formed immediately after the formation of the oxide film 230C without exposure to the atmosphere. The heat treatment is preferably performed in an oxygen-containing atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is 200°C.

[0319] Here, it is preferable that oxide film 230C is provided so as to be in contact with at least the inner wall of the groove formed in oxide 230b, part of the side surface of oxide 243, part of the side surface of conductor 242, part of the side surface of insulator 272, part of the side surface of insulator 273, and part of the side surface of insulator 280. By being surrounded by oxide 243, insulator 272, insulator 273, and oxide film 230C, conductor 242 can be prevented from decreasing in conductivity due to oxidation of conductor 242 in subsequent steps.

[0320] The oxide film 230C can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film 230C may be formed by the same method as that used for the oxide film 230A or 230B, depending on the desired characteristics of the oxide film 230C. In this embodiment, the oxide film 230C is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:3, an oxide target with an atomic ratio of In:Ga:Zn=5:1:3, an oxide target with an atomic ratio of In:Ga:Zn=10:1:3, or an indium oxide target.

[0321] During the formation of the oxide film 230C, some of the oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Alternatively, during the formation of the oxide film 230C, some of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230C should be 70% or more, preferably 80% or more, and more preferably 100%. Furthermore, by forming the oxide film 230C in such an oxygen-rich atmosphere, the oxide film 230C is more likely to become a CAAC-OS.

[0322] The oxide film 230C is preferably formed while heating the substrate. By setting the substrate temperature at 200°C or higher, oxygen vacancies in the oxide film 230C and the oxide 230b can be reduced. By forming the oxide film 230C while heating the substrate, the crystallinity of the oxide film 230C and the oxide 230b can be improved. By forming the oxide film 230C in this manner, the oxide film 230C can grow laterally, starting from the sidewalls of the grooves in the oxide 230b, as shown in FIG. 3.

[0323] Next, a mask is formed on the oxide film 230C by lithography. Note that a hard mask or a resist mask may be used as the mask.

[0324] Next, using the mask, a portion of the oxide film 230C is selectively removed. Note that the portion of the oxide film 230C may be removed by wet etching or the like. This step allows the removal of a portion of the oxide film 230C located between the transistors 200 adjacent to each other in the channel width direction.

[0325] In the above process, the surfaces of insulators 224 and 280 are exposed in the region where part of oxide film 230C has been removed. At this time, the film thickness of insulators 224 and 280 in the region may become thinner. Furthermore, insulator 224 may be removed in the region, exposing the surface of insulator 222. Furthermore, the process of forming the mask may also serve as a process of removing part of oxide film 230C.

[0326] Next, the mask is removed (see FIGS. 13A, 13C, and 13D). The mask may be removed by etching or the like.

[0327] Next, an oxide film 230D is formed (see FIGS. 14A to 14D). It is preferable that the oxide film 230D is formed continuously from the oxide film 230C without exposure to the atmosphere.

[0328] The oxide film 230D can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film 230D may be formed by the same film formation method as that for the oxide film 230A or 230B, depending on the desired characteristics of the oxide film 230D. In this embodiment, the oxide film 230D is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=In:Ga:Zn=1:3:4.

[0329] When forming the oxide film 230D, some of the oxygen contained in the sputtering gas may be supplied to the oxide film 230C. Alternatively, when forming the oxide film 230D, some of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230D may be 70% or more, preferably 80% or more, and more preferably 100%.

[0330] Next, the insulating film 250A is formed (see FIGS. 14A to 14D). A heat treatment may be performed before the formation of the insulating film 250A. The heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed immediately without exposure to the atmosphere. The heat treatment is preferably performed in an oxygen-containing atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230C can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, and the oxide film 230C can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0331] The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This reduces the hydrogen concentration in the insulating film 250A. The insulating film 250A will become the insulator 250 that contacts the oxide 230d in a later process, so it is preferable that the hydrogen concentration be reduced in this way.

[0332] When the insulator 250 has a two-layer laminated structure, it is preferable to successively deposit the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250 without exposing them to the atmospheric environment. Depositing the films without exposing them to the atmospheric environment can prevent impurities or moisture from the atmospheric environment from adhering to the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250, and can keep the vicinity of the interface between the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250 clean.

[0333] Here, after the insulating film 250A is formed, a microwave treatment may be performed in an oxygen-containing atmosphere under reduced pressure. By performing the microwave treatment, an electric field due to microwaves is applied to the insulating film 250A, the oxide film 230C, the oxide 230b, the oxide 230a, etc., and V in the oxide film 230C, the oxide 230b, and the oxide 230a is increased. O H to V Oand hydrogen. At this time, some of the hydrogen separated may combine with oxygen to form H2O, which may be removed from the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a. Also, some of the hydrogen may be gettered to the conductor 242 (the conductor 242a and the conductor 242b). In this way, by performing microwave treatment, the hydrogen concentrations in the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a can be reduced. Also, V in the oxide 230a, the oxide 230b, and the oxide film 230C can be reduced. O H to V O V that can exist after splitting into and hydrogen O Oxygen is supplied to V O can be repaired.

[0334] Alternatively, a heat treatment may be performed while maintaining the reduced pressure after the microwave treatment. By performing such a treatment, hydrogen can be efficiently removed from the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a. Some of the hydrogen may be gettered to the conductor 242 (the conductor 242a and the conductor 242b). Alternatively, a heat treatment step may be repeated multiple times while maintaining the reduced pressure after the microwave treatment. Repeated heat treatments can more efficiently remove hydrogen from the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a. The heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0335] Furthermore, microwave treatment can modify the film quality of the insulating film 250A, thereby suppressing the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. via the insulator 250 in a post-process such as film formation of a conductive film that becomes the conductor 260, or in a post-treatment such as heat treatment.

[0336] Next, a conductive film 260A and a conductive film 260B are formed in this order (see FIGS. 15A to 15D). The conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film 260A is formed by an ALD method, and the conductive film 260B is formed by a CVD method.

[0337] Next, the oxide film 230C, the oxide film 230D, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c, the oxide 230d, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) (see FIGS. 16A to 16D). As a result, the oxide 230c is arranged to cover the inner walls (side walls and bottom surface) of the opening that reaches the oxide 230b and the groove of the oxide 230b. The oxide 230d is arranged to cover the inner walls of the opening and the groove via the oxide 230c. The insulator 250 is arranged to cover the inner walls of the opening and the groove via the oxide 230d. The conductor 260 is arranged to fill the opening and the groove via the oxide 230c, the oxide 230d, and the insulator 250.

[0338] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0339] Next, the insulator 282 is formed over the oxide 230c, the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 17B to 17D). The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 282 is preferably formed, for example, by a sputtering method using aluminum oxide. By forming the insulator 282 in an oxygen-containing atmosphere using a sputtering method, oxygen can be added to the insulator 280 during the film formation. At this time, the insulator 282 is preferably formed while heating the substrate. Furthermore, forming the insulator 282 in contact with the top surface of the conductor 260 is preferable because it can prevent oxygen contained in the insulator 280 from being absorbed by the conductor 260 during subsequent heat treatment.

[0340] Next, portions of the insulators 282, 280, 273, 272, 224, 222, 216, 214, and 212 are processed to form openings that reach the insulator 211 (see FIGS. 18A to 18D ). The openings may be formed to surround the transistor 200. Alternatively, the openings may be formed to surround multiple transistors 200. Thus, portions of the side surfaces of the insulators 282, 280, 273, 272, 224, 222, 216, 214, and 212 are exposed in the openings.

[0341] A dry etching method or a wet etching method can be used to process a portion of the insulator 282, a portion of the insulator 280, a portion of the insulator 273, a portion of the insulator 272, a portion of the insulator 224, a portion of the insulator 222, a portion of the insulator 216, a portion of the insulator 214, and a portion of the insulator 212. Processing by the dry etching method is suitable for fine processing. Furthermore, the processing may be performed under different conditions.

[0342] Next, an insulator 287A is formed to cover the insulators 282, 280, 273, 272, 224, 222, 216, 214, and 212 (see FIGS. 19A to 19D). The insulator 287A is preferably formed under the same conditions as those for the insulator 282. For example, the insulator 287A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0343] Specifically, it is preferable to form the insulator 287A by, for example, sputtering, using aluminum oxide. By forming the insulator 287A in an oxygen-containing atmosphere using sputtering, oxygen can be added to the insulator 280 while the film is being formed. At this time, it is preferable to form the insulator 287A while heating the substrate. Furthermore, since the insulator 282 is formed in contact with the upper surface of the conductor 260, it is possible to prevent the oxygen contained in the insulator 280 from being absorbed by the conductor 260 during the film formation process of the insulator 287A.

[0344] Next, an anisotropic etching process is performed on insulator 287A to form insulator 287 on the side surfaces of insulators 282, 280, 273, 272, 224, 222, 216, 214, and 212 (see Figures 20A to 20D).

[0345] Here, the side edge of insulator 282 contacts the upper end of insulator 287, and the side edge of insulator 214 contacts the lower end of insulator 287, thereby forming a structure that seals transistor 200 and insulator 280.

[0346] The anisotropic etching is preferably performed by dry etching, which removes the insulating film formed on a surface approximately parallel to the substrate surface, thereby forming the insulator 287 in a self-aligned manner.

[0347] Next, the insulator 283 is formed to cover the insulators 282, 287, and 211 (see FIGS. 21A to 21D). The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 283 may also be a multilayer structure. For example, a silicon nitride film may be formed by a sputtering method, and another silicon nitride film may be formed on the silicon nitride film by a CVD method. As shown in FIG. 21, the insulator 283 contacts the insulator 211 at the bottom of the opening. That is, the upper and side surfaces of the transistor 200 are surrounded by the insulator 283, and the lower surface is surrounded by the insulator 211. In this way, by surrounding the transistor 200 with the insulator 283 and the insulator 211, which have high barrier properties, moisture and hydrogen can be prevented from entering from the outside.

[0348] Next, the insulator 284 may be formed on the insulator 283 (see FIGS. 22A to 22D). Note that the insulator 284 is preferably formed using a film formation method with high film-forming properties. For example, the insulator 284 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the insulator 284 is preferably formed using the same material as the insulators 212 and 283.

[0349] Specifically, it is preferable to deposit silicon nitride by a CVD method, and in particular, it is preferable to deposit the insulator 284 by a CVD method using a compound gas that does not contain hydrogen atoms or that contains a small amount of hydrogen atoms.

[0350] Next, an insulating film that will become the insulator 274 is formed on the insulator 284. The insulating film that will become the insulator 274 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film can be formed using a CVD method. Furthermore, the insulating film that will become the insulator 274 is preferably formed by a film formation method using a gas in which hydrogen atoms have been reduced or removed as described above. This allows the hydrogen concentration of the insulating film that will become the insulator 274 to be reduced.

[0351] Next, the insulating film that will become the insulator 274 is subjected to CMP processing to form the insulator 274 with a flat upper surface (see FIGS. 23A to 23D).

[0352] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. This heat treatment allows oxygen added by the formation of the insulator 282 to diffuse into the insulator 280 and to be further supplied to the oxide 230a and the oxide 230b via the oxide 230c. Note that this heat treatment may be performed not only after the formation of the insulator 274 but also after the formation of the insulator 282 or the insulator 284.

[0353] Next, openings are formed in the insulators 272, 273, 280, 282, 283, and 284, reaching the conductor 242 (see FIGS. 24A to 24D). The openings may be formed using lithography. Note that although the shape of the openings is circular in top view in FIG. 24A, the shape is not limited to this. For example, the openings may have a substantially circular shape such as an oval, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners in top view.

[0354] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 (see Figures 24A to 24D). The insulating film that will become the insulator 241 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable to use an insulating film that has the function of suppressing oxygen permeation as the insulating film that will become the insulator 241. For example, it is preferable to form a film of aluminum oxide using the ALD method. Alternatively, it is preferable to form a film of silicon nitride using the PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen.

[0355] Furthermore, dry etching, for example, may be used for anisotropic etching of the insulating film that will become the insulator 241. By providing the insulator 241 on the sidewall of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent oxidation of the conductors 240a and 240b that will be formed next. It is also possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductors 240a and 240b.

[0356] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film that will become the conductor 240a and the conductor 240b is preferably a layered structure including a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a layered structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that will become the conductor 240 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0357] Next, CMP processing is performed to remove portions of the conductive film that will become conductors 240a and 240b, exposing the upper surfaces of insulators 284 and 274. As a result, the conductive film remains only in the openings, thereby forming conductors 240a and 240b with flat upper surfaces (see Figures 24A to 24D). Note that the CMP processing may remove portions of the upper surfaces of insulators 284 and 274.

[0358] Next, a conductive film is formed to become the conductor 246. The conductive film to become the conductor 246 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0359] Next, the conductive film that will become the conductor 246 is processed by lithography to form the conductor 246a that contacts the top surface of the conductor 240a and the conductor 246b that contacts the top surface of the conductor 240b. At this time, part of the insulator 284 may be removed in the region where the conductors 246a and 246b do not overlap with the insulator 284 (see FIGS. 25A to 25D).

[0360] Next, an insulator 286 is formed on the conductor 246 and the insulator 284 (see FIGS. 6A to 6D). The insulator 286 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulator 286 may also be multi-layered. For example, a silicon nitride film may be formed by sputtering, and another silicon nitride film may be formed on the silicon nitride by CVD.

[0361] Through the above steps, a semiconductor device including the transistor 200 illustrated in FIGS. 6A to 6D can be manufactured. As illustrated in FIGS. 8A to 25A, 8B to 25B, 8C to 25C, and 8D to 25D, the transistor 200 can be manufactured by using the manufacturing method of a semiconductor device described in this embodiment. Note that when a semiconductor device including the transistor 200 illustrated in FIGS. 2A to 2D is manufactured, the semiconductor device can be manufactured without performing the steps illustrated in FIGS. 18 to 23.

[0362] <Application examples of semiconductor devices> 26A and 26B , an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention, which is different from those described in the above <Structural Example of Semiconductor Device> and the above <Variations of Semiconductor Device>, will be described. In the semiconductor device shown in FIGS. 26A and 26B , structures having the same functions as those of the semiconductor device described in <<Variations of Semiconductor Device 1>> (see FIGS. 2A to 2D ) are denoted by the same reference numerals. In this section, the transistor 200 can be made of materials described in detail in the <Structural Example of Semiconductor Device> and the <Variations of Semiconductor Device>.

[0363] 26A and 26B show a configuration in which a plurality of transistors 200_1 to 200_n are encapsulated by an insulator 283 and an insulator 211. Note that although the transistors 200_1 to 200_n appear to be aligned in the channel length direction in FIGS. 26A and 26B, this is not a limitation. The transistors 200_1 to 200_n may be aligned in the channel width direction or may be arranged in a matrix. Furthermore, the transistors may be arranged without any regularity depending on the design.

[0364] 26A, a portion where the insulator 283 and the insulator 211 contact each other (hereinafter, may be referred to as a sealing portion 265) is formed outside the plurality of transistors 200_1 to 200_n. The sealing portion 265 is formed so as to surround the plurality of transistors 200_1 to 200_n. With this structure, the plurality of transistors 200_1 to 200_n can be enclosed by the insulator 283 and the insulator 211. Therefore, a plurality of transistor groups surrounded by the sealing portion 265 are provided on the substrate.

[0365] Also, dicing lines (sometimes called scribe lines, division lines, or cutting lines) may be provided overlapping the sealing portion 265. The substrate is divided along the dicing lines, so that a group of transistors surrounded by the sealing portion 265 is extracted as one chip.

[0366] 26A shows an example in which the plurality of transistors 200_1 to 200_n are surrounded by one sealing portion 265, but the present invention is not limited to this. As shown in Fig. 26B, the plurality of transistors 200_1 to 200_n may be surrounded by a plurality of sealing portions. In Fig. 26B, the plurality of transistors 200_1 to 200_n are surrounded by a sealing portion 265a and further surrounded by an outer sealing portion 265b.

[0367] In this manner, by using a structure in which the plurality of transistors 200_1 to 200_n are surrounded by a plurality of sealing portions, the area in which the insulator 283 and the insulator 212 are in contact with each other increases, thereby further improving the adhesion between the insulator 283 and the insulator 212. This makes it possible to more reliably seal the plurality of transistors 200_1 to 200_n.

[0368] In this case, a dicing line may be provided so as to overlap the sealing portion 265a or the sealing portion 265b, or a dicing line may be provided between the sealing portion 265a and the sealing portion 265b.

[0369] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high reliability can be provided. According to another embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0370] The structures, methods, and the like described in this embodiment can be used in appropriate combination with structures, methods, and the like described in other embodiment modes or examples.

[0371] (Embodiment 2) In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0372] [Storage device 1] 27 illustrates an example of a semiconductor device (memory device) according to one embodiment of the present invention. In the semiconductor device according to one embodiment of the present invention, a transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistors 300 and 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.

[0373] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. The transistor 200 has a low off-state current; therefore, when used in a memory device, the stored data can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the memory device can be sufficiently reduced.

[0374] 27, a wiring 1001 is electrically connected to the source of a transistor 300, and a wiring 1002 is electrically connected to the drain of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of a transistor 200, a wiring 1004 is electrically connected to a first gate of the transistor 200, and a wiring 1006 is electrically connected to a second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of a capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0375] Moreover, the memory device shown in FIG. 27 can be arranged in a matrix to form a memory cell array.

[0376] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel type or an n-channel type.

[0377] Here, in the transistor 300 shown in FIG. 27, a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. In addition, a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. In addition, although the case where the convex portion is formed by processing a part of the semiconductor substrate has been shown, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0378] Note that the transistor 300 shown in FIG. 27 is just an example, and the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration and driving method.

[0379] <Capacitor element 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 functioning as a first electrode, a conductor 120 functioning as a second electrode, and an insulator 130 functioning as a dielectric. Here, the insulator 130 is preferably the same as the insulator 286 described in the above embodiment.

[0380] For example, the conductor 112 over the conductor 246 and the conductor 110 can be formed simultaneously. Note that the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

[0381] 27, the conductor 112 and the conductor 110 are shown as having a single layer structure, but are not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0382] The insulator 130 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be formed as a stacked layer or a single layer.

[0383] For example, it is preferable to use a layered structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitor 100 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitor 100 can improve its dielectric strength by having an insulator with high dielectric strength, thereby preventing electrostatic breakdown of the capacitor 100.

[0384] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0385] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide or resin with pores, etc.

[0386] <Wiring layer> Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductor functioning as a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0387] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328 and 330 electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings.

[0388] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0389] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 27, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0390] Similarly, a conductor 218 and a conductor (conductor 205) constituting the transistor 200 are embedded in the insulators 210, 211, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided over the conductor 120 and the insulator 130.

[0391] Here, similar to the insulator 241 described in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 that functions as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 211, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 211, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0392] The insulator 217 may be, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 217 is provided in contact with the insulators 211, 212, 214, and 222, and therefore can prevent impurities such as water or hydrogen from the insulator 210 or the insulator 216 from mixing into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. In addition, the insulator 217 can prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0393] The insulator 217 can be formed by a method similar to that of the insulator 241. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0394] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0395] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0396] For example, insulators 150, 210, 352, and 354 preferably have an insulator with a low dielectric constant. For example, the insulator preferably includes silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, pore-containing silicon oxide, or resin. Alternatively, the insulator preferably has a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or pore-containing silicon oxide, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with resin to form a thermally stable layered structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (e.g., nylon, aramid), polyimide, polycarbonate, and acrylic.

[0397] Furthermore, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, the insulators 214, 211, 212, and 350 can be insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0398] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0399] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0400] For example, the conductors 328, 330, 356, conductor 218, and conductor 112 can be formed using a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed using low-resistance conductive materials such as aluminum and copper. Using a low-resistance conductive material can reduce wiring resistance.

[0401] <Wiring or plug in layer provided with oxide semiconductor> When an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0402] 27, for example, an insulator 241 may be provided between the insulator 224 and the insulator 280 containing excess oxygen and the conductor 240. By providing the insulator 241 in contact with the insulator 222, the insulator 272, the insulator 273, the insulator 282, the insulator 283, and the insulator 284, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties.

[0403] That is, the insulator 241 can prevent excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 240. Furthermore, the insulator 241 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 240.

[0404] The insulator 241 may be an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide. Silicon nitride is particularly preferable because it has a high blocking property against hydrogen. Other examples that can be used include metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide.

[0405] As in the above embodiment, the transistor 200 is preferably sealed with the insulators 211, 212, 214, 287, 282, 283, and 284. This structure can reduce the intrusion of hydrogen contained in the insulators 274, 150, and the like into the insulator 280 and the like.

[0406] Here, the conductor 240 penetrates the insulators 284, 283, and 282, and the conductor 218 penetrates the insulators 214, 212, and 211. However, as described above, the insulator 241 is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. This makes it possible to reduce hydrogen that is mixed into the inside of the insulators 211, 212, 214, 287, 282, 283, and 284 via the conductors 240 and 218. In this way, the transistor 200 can be more reliably sealed with the insulators 211, 212, 214, 287, 282, 283, 284, 241, and 217, and it is possible to reduce the intrusion of impurities such as hydrogen contained in the insulator 274 from the outside.

[0407] Furthermore, as described in the previous embodiment, the insulators 216, 224, 280, 250, and 274 are preferably formed by a deposition method using a gas in which hydrogen atoms are reduced or removed, thereby reducing the hydrogen concentrations in the insulators 216, 224, 280, 250, and 274.

[0408] In this way, the hydrogen concentration in the silicon-based insulating film near the transistor 200 can be reduced, and the hydrogen concentration in the oxide 230 can be reduced.

[0409] <Dicing line> The following describes dicing lines (sometimes called scribe lines, dividing lines, or cutting lines) that are provided when dividing a large-area substrate into individual semiconductor elements to extract multiple semiconductor devices in chip form. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (divide) the multiple semiconductor devices.

[0410] 27, for example, it is preferable to design the insulator 282, the insulator 280, the insulator 273, the insulator 272, the insulator 224, the insulator 222, the insulator 216, the insulator 214, and the insulator 212 so that the area where the insulator 283 and the insulator 211 contact each other overlaps with the dicing line. That is, in the vicinity of the area that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200, openings are provided in the insulators 282, 280, 273, 272, 224, 222, 216, 214, and 212.

[0411] That is, the insulator 211 and the insulator 283 contact each other through openings formed in the insulators 282, 280, 273, 272, 224, 222, 216, 214, and 212. Alternatively, openings may be formed in the insulators 282, 280, 273, 272, 224, 222, 216, and 214, so that the insulators 212 and 283 contact each other. For example, the insulators 212 and 283 may be formed using the same material and the same method. Providing the insulators 212 and 283 using the same material and the same method can improve adhesion. For example, silicon nitride is preferably used.

[0412] With this structure, the transistor 200 can be surrounded by the insulators 211, 212, 214, 287, 282, 283, and 284. At least one of the insulators 211, 212, 214, 287, 282, 283, and 284 has a function of suppressing diffusion of oxygen, hydrogen, and water. Therefore, even when the substrate is divided into a plurality of chips by dividing the substrate into each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side direction of the divided substrate and diffusing into the transistor 200.

[0413] Furthermore, this structure can prevent excess oxygen in the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which a channel is formed in the transistor 200. The oxygen can reduce oxygen vacancies in the oxide in which a channel is formed in the transistor 200. This allows the oxide in which a channel is formed in the transistor 200 to be an oxide semiconductor with a low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

[0414] 27, the shape of the capacitor 100 is a planar type, but the shape of the capacitor 100 in the memory device of this embodiment is not limited to this. For example, as shown in FIG. 28, the shape of the capacitor 100 may be a cylindrical type. Note that the memory device shown in FIG. 28 has the same configuration below the insulator 150 as the semiconductor device shown in FIG. 27.

[0415] 28 includes an insulator 150 on an insulator 130, an insulator 142 on the insulator 150, a conductor 115 disposed in an opening formed in the insulator 150 and the insulator 142, an insulator 145 on the conductor 115 and the insulator 142, a conductor 125 on the insulator 145, and an insulator 152 on the conductor 125 and the insulator 145. Here, at least a portion of the conductor 115, the insulator 145, and the conductor 125 are disposed in the openings formed in the insulator 150 and the insulator 142.

[0416] The conductor 115 functions as the lower electrode of the capacitor 100, the conductor 125 functions as the upper electrode of the capacitor 100, and the insulator 145 functions as the dielectric of the capacitor 100. The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surfaces of the openings in the insulators 150 and 142, allowing for a larger capacitance per unit area. Therefore, the deeper the openings, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0417] The insulator 152 may be an insulator that can be used for the insulator 280. The insulator 142 preferably functions as an etching stopper when forming an opening in the insulator 150, and may be an insulator that can be used for the insulator 214.

[0418] The shape of the openings formed in the insulator 150 and the insulator 142 when viewed from above may be rectangular, a polygonal shape other than a rectangular, a polygonal shape with curved corners, or a circular shape including an ellipse. Here, it is preferable that the area over which the openings and the transistor 200 overlap in the top view is large. With such a configuration, the area occupied by a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0419] The conductor 115 is disposed in contact with the insulator 142 and an opening formed in the insulator 150. The upper surface of the conductor 115 preferably substantially coincides with the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening in the insulator 130. The conductor 115 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using, for example, a conductor that can be used for the conductor 205.

[0420] The insulator 145 is disposed to cover the conductor 115 and the insulator 142. For example, the insulator 145 is preferably formed by an ALD method, a CVD method, or the like. The insulator 145 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer. For example, the insulator 145 can be an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order.

[0421] Furthermore, it is preferable to use a material with high dielectric strength, such as silicon oxynitride, or a high dielectric constant (high-k) material for the insulator 145. Alternatively, a laminated structure of a material with high dielectric strength and a high dielectric constant (high-k) material may be used.

[0422] Examples of high-dielectric-constant (high-k) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. Using such high-k materials ensures sufficient capacitance of the capacitor 100 even when the insulator 145 is thick. By thickening the insulator 145, leakage current between the conductor 115 and the conductor 125 can be suppressed.

[0423] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with vacancies, and resin. For example, silicon nitride (SiN) formed using the ALD method is x ), silicon oxide (SiO x), silicon nitride (SiN x ) can be used. By using such an insulator with high dielectric strength, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0424] The conductor 125 is arranged to fill the openings formed in the insulator 142 and the insulator 150. The conductor 125 is electrically connected to the wiring 1005 via the conductor 140 and the conductor 153. The conductor 125 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using, for example, a conductor that can be used for the conductor 205.

[0425] The conductor 153 is provided over the insulator 154 and is covered with the insulator 156. The conductor 153 may be any conductor that can be used for the conductor 112, and the insulator 156 may be any insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the top surface of the conductor 140 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[0426] [Storage device 2] An example of a semiconductor device (memory device) according to one embodiment of the present invention is illustrated in FIG.

[0427] <Memory device configuration example> 2A to 2D. Fig. 29 is a cross-sectional view of a semiconductor device including a memory device 290. The memory device 290 shown in Fig. 29 includes a capacitor device 292 in addition to the transistor 200 shown in Fig. 2A to 2D. Fig. 29 corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

[0428] The capacitor 292 includes a conductor 242b, an insulator 272 and an insulator 273 provided on the conductor 242b, and a conductor 294 provided on the insulator 273. That is, the capacitor 292 constitutes a metal-insulator-metal (MIM) capacitor. One of a pair of electrodes of the capacitor 292, i.e., the conductor 242b, can also serve as a source electrode of a transistor. Furthermore, a dielectric layer of the capacitor 292 can also serve as a protective layer provided in the transistor, i.e., the insulators 272 and 273. Therefore, part of the manufacturing process of the transistor can be used in the manufacturing process of the capacitor 292, resulting in a highly productive semiconductor device. Furthermore, because one of the pair of electrodes of the capacitor 292, i.e., the conductor 242b, also serves as a source electrode of the transistor, the area in which the transistor and the capacitor are arranged can be reduced.

[0429] The conductor 294 may be made of, for example, a material that can be used for the conductor 242.

[0430] <Modifications of memory devices> 30A , 30B , 31 , and 32 will be used to describe an example of a semiconductor device including a transistor 200 and a capacitor device 292 according to one embodiment of the present invention, which is different from those described above in <Configuration Example of Memory Device>. In the semiconductor devices illustrated in FIGS. 30A , 30B , 31 , and 32 , the same reference numerals are used to designate structures having the same functions as those in the semiconductor device (see FIG. 29 ) described in the above embodiment and <Configuration Example of Memory Device>. In this section, the transistor 200 and the capacitor device 292 can be made of materials described in detail in the above embodiment and <Configuration Example of Memory Device>.

[0431] <<Memory Device Variation 1>> An example of a semiconductor device 600 including a transistor 200a, a transistor 200b, a capacitor 292a, and a capacitor 292b according to one embodiment of the present invention will be described below with reference to FIG. 30A.

[0432] 30A is a cross-sectional view in the channel length direction of a semiconductor device 600 including a transistor 200a, a transistor 200b, a capacitor 292a, and a capacitor 292b. The capacitor 292a includes a conductor 242a, an insulator 272 covering the conductor 242a, an insulator 273 covering the insulator 272, and a conductor 294a that partially overlaps with the conductor 242a over the insulator 273. The capacitor 292b includes a conductor 242b, an insulator 272 covering the conductor 242b, an insulator 273 covering the insulator 272, and a conductor 294b that partially overlaps with the conductor 242b over the insulator 273.

[0433] As shown in FIG. 30A , the semiconductor device 600 has a symmetrical configuration with the dashed line A3-A4 as the axis of symmetry. Conductor 242c serves as both the source electrode or drain electrode of transistor 200a and the source electrode or drain electrode of transistor 200b. Conductor 246, which functions as wiring, and transistors 200a and 200b are also connected by conductor 240, which functions as a plug. By configuring the two transistors, two capacitance devices, and the connections between the wiring and plugs as described above, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0434] The configuration examples of the semiconductor device illustrated in FIGS. 2A to 2D and 29 can be referred to for the configurations and effects of the transistor 200a, the transistor 200b, the capacitor 292a, and the capacitor 292b.

[0435] <<Memory Device Variation 2>> In the above, the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b are given as examples of the configuration of the semiconductor device, but the semiconductor device described in this embodiment is not limited to this. For example, as shown in FIG. 30B , a configuration may be adopted in which a semiconductor device 600 and a semiconductor device having a configuration similar to that of the semiconductor device 600 are connected via a capacitance unit. In this specification, a semiconductor device including the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b is referred to as a cell. For the configurations of the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b, the above descriptions of the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b can be referred to.

[0436] FIG. 30B is a cross-sectional view of a semiconductor device 600 having a transistor 200a, a transistor 200b, a capacitance device 292a, and a capacitance device 292b, and a cell having a similar configuration to the semiconductor device 600, connected via a capacitance section.

[0437] As shown in FIG. 30B, the conductor 294b, which functions as one electrode of the capacitance device 292b of the semiconductor device 600, also serves as one electrode of the capacitance device of a semiconductor device 601 having a similar configuration to the semiconductor device 600. Although not shown, the conductor 294a, which functions as one electrode of the capacitance device 292a of the semiconductor device 600, also serves as one electrode of the capacitance device of the semiconductor device adjacent to the left side of the semiconductor device 600, i.e., in the A1 direction in FIG. 30B. The same configuration is also true for the cells on the right side of the semiconductor device 601, i.e., in the A2 direction in FIG. 30B. In other words, a cell array (also referred to as a memory device layer) can be configured. This cell array configuration reduces the spacing between adjacent cells, thereby reducing the projected area of ​​the cell array and enabling higher integration. Furthermore, by arranging the cell array configuration shown in FIG. 30B in a matrix, a matrix cell array can be configured.

[0438] As described above, by forming the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b in the configuration shown in this embodiment, the cell area can be reduced, and miniaturization or high integration of a semiconductor device having a cell array can be achieved.

[0439] Furthermore, the cell array may be configured not only in a plane but also in a stacked configuration. Fig. 31 shows a cross-sectional view of a configuration in which cell arrays 610 are stacked in n layers. As shown in Fig. 31, by stacking multiple cell arrays (cell arrays 610_1 to 610_n), cells can be integrated and arranged without increasing the area occupied by the cell arrays. In other words, a 3D cell array can be configured.

[0440] <Memory Device Modification Example 3> FIG. 32 shows an example in which a memory unit 470 includes a transistor layer 413 including a transistor 200T and four memory device layers 415 (memory device layers 415_1 to 415_4).

[0441] Each of the memory device layers 415_1 to 415_4 includes a plurality of memory devices 420.

[0442] The memory device 420 is electrically connected to the memory device 420 in a different memory device layer 415 and the transistor 200T in the transistor layer 413 via the conductor 424 and the conductor 205.

[0443] The memory unit 470 is sealed by the insulators 211, 212, 214, 287, 282, 283, and 284 (hereinafter referred to as a sealing structure for convenience). The insulator 274 is provided around the insulator 284. Furthermore, the insulators 274, 284, 283, and 211 are provided with conductors 440, which are electrically connected to the element layer 411.

[0444] Furthermore, an insulator 280 is provided inside the sealing structure. The insulator 280 has a function of releasing oxygen when heated. Alternatively, the insulator 280 has an excess oxygen region.

[0445] Note that the insulators 211, 283, and 284 are preferably made of a material having a high blocking property against hydrogen, and the insulators 214, 282, and 287 are preferably made of a material having a function of capturing or fixing hydrogen.

[0446] For example, examples of the material having a high blocking property against hydrogen include silicon nitride and silicon nitride oxide, while examples of the material having a function of capturing or fixing hydrogen include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0447] In this specification, the term "barrier property" refers to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability), or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0448] Note that the crystal structure of the materials used for the insulators 211, 212, 214, 287, 282, 283, and 284 is not particularly limited, and may be amorphous or crystalline. For example, an amorphous aluminum oxide film is preferably used as a material capable of capturing or fixing hydrogen. Amorphous aluminum oxide may be able to capture and fix a larger amount of hydrogen than aluminum oxide with high crystallinity.

[0449] Insulators 282 and 214 are preferably provided between the transistor layer 413 and the memory device layer 415 or between the memory device layers 415. Insulators 296 are preferably provided between the insulators 282 and 214. The insulator 296 can be made of a material similar to that of the insulators 283 and 284. Alternatively, silicon oxide or silicon oxynitride can be used. Alternatively, a known insulating material can be used.

[0450] Here, the excess oxygen in the insulator 280 can be considered as follows for the diffusion of hydrogen in the oxide semiconductor in contact with the insulator 280.

[0451] Hydrogen present in the oxide semiconductor diffuses to other structures via the insulator 280 in contact with the oxide semiconductor. The hydrogen diffuses as follows: excess oxygen in the insulator 280 reacts with hydrogen in the oxide semiconductor to form an OH bond, and the hydrogen diffuses through the insulator 280. When the hydrogen atom having the OH bond reaches a material (typically, the insulator 282) that has the function of capturing or fixing hydrogen, the hydrogen atom reacts with an oxygen atom that is bonded to an atom (e.g., a metal atom) in the insulator 282, and is captured or fixed in the insulator 282. Meanwhile, the oxygen atom of the excess oxygen that had the OH bond is presumably left as excess oxygen in the insulator 280. In other words, the excess oxygen in the insulator 280 is highly likely to play a bridging role in the diffusion of the hydrogen.

[0452] In order to satisfy the above model, the manufacturing process of the semiconductor device is one of the important factors.

[0453] For example, the insulator 280 containing excess oxygen is formed over an oxide semiconductor, and then the insulator 282 is formed. After that, heat treatment is preferably performed. Specifically, the heat treatment is performed in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixed atmosphere of oxygen and nitrogen at a temperature of 350° C. or higher, preferably 400° C. or higher. The heat treatment time is 1 hour or longer, preferably 4 hours or longer, and further preferably 8 hours or longer.

[0454] By the above heat treatment, hydrogen in the oxide semiconductor can diffuse outward through the insulators 280, 282, and 287. That is, the absolute amount of hydrogen present in and around the oxide semiconductor can be reduced.

[0455] After the heat treatment, the insulators 283 and 284 are formed. The insulators 283 and 284 are made of materials that have a high blocking property against hydrogen, and therefore can prevent hydrogen that has diffused outward or hydrogen present outside from entering the interior, specifically, the oxide semiconductor or the insulator 280.

[0456] Note that the heat treatment described above is performed after the insulator 282 is formed, but is not limited thereto. For example, the heat treatment may be performed after the transistor layer 413 is formed or after the memory device layers 415_1 to 415_3 are formed. When hydrogen is diffused outward by the heat treatment, the hydrogen diffuses upward or laterally in the transistor layer 413. Similarly, when the heat treatment is performed after the memory device layers 415_1 to 415_3 are formed, the hydrogen diffuses upward or laterally.

[0457] By using the above manufacturing process, the insulator 211 and the insulator 283 are bonded together, thereby forming the above-described sealing structure.

[0458] As described above, by using the above structure and manufacturing process, a semiconductor device including an oxide semiconductor with a reduced hydrogen concentration can be provided. Therefore, a semiconductor device with high reliability can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided.

[0459] The structures, methods, and the like described in this embodiment can be used in appropriate combination with structures, methods, and the like described in other embodiment modes or examples.

[0460] (Embodiment 3) In this embodiment, a transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a memory device including a capacitor (hereinafter also referred to as an OS memory device) according to one embodiment of the present invention will be described with reference to FIGS. 33A, 33B, and 34A to 34H. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. The off-state current of the OS transistor is extremely small, so the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

[0461] <Storage device configuration example> 33A shows an example of the configuration of an OS memory device. The memory device 1400 has a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 has a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0462] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is connected to a memory cell in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 also includes, for example, a row decoder, a word line driver circuit, etc., and can select a row to access.

[0463] The memory device 1400 is supplied with a low power supply voltage (VSS) from the outside as power supply voltages, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470. Control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are also input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0464] The control logic circuit 1460 processes control signals (CE, WE, RE) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0465] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0466] 33A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited to this. For example, as shown in FIG. 33B, the memory cell array 1470 may be provided so as to overlap a portion of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0467] 34A to 34H illustrate examples of the configuration of a memory cell that can be applied to the above-described memory cell MC.

[0468] [DOSRAM] 34A to 34C show circuit configuration examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 34A includes a transistor M1 and a capacitor CA. The transistor M1 includes a gate (sometimes referred to as a top gate) and a back gate.

[0469] The first terminal of the transistor M1 is connected to the first terminal of the capacitance element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, the back gate of the transistor M1 is connected to the wiring BGL, and the second terminal of the capacitance element CA is connected to the wiring CAL.

[0470] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0471] 34A corresponds to the memory device shown in FIG 29. That is, the transistor M1 corresponds to the transistor 200, and the capacitance element CA corresponds to the capacitance device 292.

[0472] The memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 34B. Furthermore, for example, the memory cell MC may be configured as a memory cell having a single-gate structure, that is, a memory cell including a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 34C.

[0473] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Furthermore, the refresh operation of the memory cell can be made unnecessary. Furthermore, because the leakage current is very small, multilevel data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0474] Furthermore, in the DOSRAM, if the sense amplifier is configured to overlap under the memory cell array 1470 as described above, the bit line can be shortened, which reduces the bit line capacitance and the storage capacitance of the memory cell.

[0475] [NOSRAM] 34D to 34G show circuit configuration examples of a gain cell type memory cell with two transistors and one capacitor. The memory cell 1474 shown in FIG. 34D includes a transistor M2, a transistor M3, and a capacitor CB. The transistor M2 has a top gate (sometimes simply referred to as a gate) and a back gate. In this specification and the like, a memory device having a gain cell type memory cell using an OS transistor as the transistor M2 may be referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0476] The first terminal of transistor M2 is connected to the first terminal of capacitor CB, the second terminal of transistor M2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitor CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitor CB.

[0477] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0478] Here, the memory cell 1474 shown in Fig. 34D corresponds to the memory device shown in Fig. 27. That is, the transistor M2 corresponds to the transistor 200, the capacitor CB corresponds to the capacitor 100, the transistor M3 corresponds to the transistor 300, the wiring WBL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, the wiring CAL corresponds to the wiring 1005, the wiring RBL corresponds to the wiring 1002, and the wiring SL corresponds to the wiring 1001.

[0479] Furthermore, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 34E. Furthermore, for example, the memory cell MC may be configured as a memory cell having a single gate structure, that is, a memory cell including a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 34F. Furthermore, for example, the memory cell MC may be configured such that the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 34G.

[0480] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor CB can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be significantly reduced. This allows written data to be held by the transistor M2 for a long time, thereby reducing the frequency of refreshing the memory cell. Furthermore, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0481] Note that the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, may be referred to as a Si transistor). The conductivity type of the Si transistor may be either an n-channel type or a p-channel type. The Si transistor may have higher field-effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read transistor. Furthermore, by using a Si transistor as the transistor M3, the transistor M2 can be stacked on top of the transistor M3, thereby reducing the area occupied by the memory cell and achieving higher integration of the memory device.

[0482] Furthermore, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured as a circuit using only n-type transistors.

[0483] FIG. 34H shows an example of a gain cell type memory cell with three transistors and one capacitor. The memory cell 1478 shown in FIG. 34H includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL. The GNDL wiring is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to wirings RBL and WBL instead of wiring BIL.

[0484] The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not necessarily have a back gate.

[0485] Note that the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured using only n-channel transistors.

[0486] When the semiconductor device described in the above embodiment is used in the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistors M5 and M6 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made extremely small.

[0487] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.

[0488] Generally, various storage devices (memories) are used in semiconductor devices such as computers depending on the application. Figure 35 shows various storage devices by layer. The higher the layer, the faster the access speed required, while the lower the layer, the larger the storage capacity and recording density required. Figure 35 shows, from the top layer, memories embedded as registers in arithmetic processing units such as CPUs, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0489] The memory embedded as a register in a CPU or other processing unit is frequently accessed by the processing unit because it is used to temporarily store the results of calculations. Therefore, a faster operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0490] SRAM is used, for example, in caches. Caches have the function of storing a copy of the information stored in main memory. By storing copies of frequently used data in the cache, access speed to the data can be increased.

[0491] DRAM is used, for example, as main memory. Main memory has the function of storing programs and data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 is.

[0492] 3D NAND memory is used, for example, in storage. Storage has the function of storing data that requires long-term storage and various programs used by processing units. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. The recording density of memory devices used in storage is approximately 0.6 to 6.0 Gbit / mm 2 is.

[0493] A storage device according to one embodiment of the present invention has a high operating speed and can retain data for a long period of time. The storage device according to one embodiment of the present invention can be suitably used as a storage device located in a boundary area 901 that includes both a tier where a cache is located and a tier where a main memory is located. The storage device according to one embodiment of the present invention can also be suitably used as a storage device located in a boundary area 902 that includes both a tier where a main memory is located and a tier where a storage is located.

[0494] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or examples.

[0495] (Fourth embodiment) In this embodiment, an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown using Figures 36A and 36B. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this way is sometimes called a system on chip (SoC).

[0496] As shown in FIG. 36A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0497] Chip 1200 is provided with bumps (not shown), which are connected to a first surface of a printed circuit board (PCB) 1201, as shown in Fig. 36B. In addition, a plurality of bumps 1202 are provided on the backside of the first surface of PCB 1201, which is connected to a motherboard 1203.

[0498] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM described in the previous embodiment may be used as the DRAM 1221. Also, for example, the NOSRAM described in the previous embodiment may be used as the flash memory 1222.

[0499] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the NOSRAM or DOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing and multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-and-accumulate operations with low power consumption.

[0500] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of the calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212.

[0501] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0502] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0503] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0504] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0505] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0506] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204.

[0507] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a small size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0508] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or examples.

[0509] (Embodiment 5) This embodiment mode will describe examples of electronic components and electronic devices in which the memory device or the like described in the above embodiment mode is incorporated.

[0510] <Electronic components> First, an example of an electronic component incorporating memory device 720 will be described with reference to FIGS. 37A and 37B.

[0511] FIG. 37A shows a perspective view of electronic component 700 and a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 37A has memory device 720 inside mold 711. FIG. 37A omits a portion of the interior of electronic component 700 to show it. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to memory device 720 by wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0512] The memory device 720 includes a driver circuit layer 721 and a memory circuit layer 722 .

[0513] 37B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple memory devices 720 provided on interposer 731.

[0514] In the electronic component 730, an example is shown in which the storage device 720 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0515] The package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. The interposer 731 may be a silicon interposer, a resin interposer, etc.

[0516] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrodes. In addition, with a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0517] It is preferable to use a silicon interposer as the interposer 731. Since a silicon interposer does not require the provision of active elements, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of a silicon interposer can be performed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0518] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0519] Furthermore, in SiPs and MCMs that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the surface of a silicon interposer is highly flat, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on an interposer.

[0520] A heat sink (heat dissipation plate) may be provided over the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 720 and the height of the semiconductor device 735.

[0521] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 37B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0522] The electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0523] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes or examples.

[0524] (Embodiment 6) In this embodiment, application examples of a storage device using the semiconductor device described in the previous embodiment will be described. The semiconductor device described in the previous embodiment can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), recording / playback devices, navigation systems, etc.). Note that the term "computer" here refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system. Alternatively, the semiconductor device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). FIGS. 38A to 38E schematically show several configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment can be processed into a packaged memory chip and used in various storage devices and removable memories.

[0525] 38A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1105 or the like.

[0526] FIG. 38B is a schematic diagram of the appearance of an SD card, and FIG. 38C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113. Furthermore, a wireless chip with a wireless communication function may be provided on the substrate 1113. This enables data to be read from and written to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1114 or the like.

[0527] FIG. 38D is a schematic diagram of the appearance of an SSD, and FIG. 38E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chip 1154, memory chip 1155, and controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be, for example, a DOSRAM chip. By providing memory chip 1154 on the back side of board 1153, the capacity of SSD 1150 can be increased. The semiconductor device described in the previous embodiment can be incorporated into memory chip 1154 or the like.

[0528] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes or examples.

[0529] (Embodiment 7) A semiconductor device according to one embodiment of the present invention can be used in a processor such as a CPU or a GPU, or a chip. Specific examples of electronic devices including a processor such as a CPU or a GPU, or a chip according to one embodiment of the present invention are shown in FIGS. 39A to 39H.

[0530] <Electronic devices and systems> A GPU or chip according to one embodiment of the present invention can be mounted in various electronic devices. Examples of such electronic devices include electronic devices with relatively large screens, such as televisions, monitors for desktop or notebook information terminals, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game machines, personal digital assistants, and audio playback devices. Furthermore, by providing an electronic device with a GPU or chip according to one embodiment of the present invention, it is possible to equip the electronic device with artificial intelligence.

[0531] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0532] An electronic device according to one embodiment of the present invention may have a sensor (including a function for measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0533] An electronic device of one embodiment of the present invention can have various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, etc. Examples of electronic devices are shown in FIGS. 39A to 39H.

[0534] [Information terminal] 39A shows a mobile phone (smartphone), which is one type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. As input interfaces, a touch panel is provided on the display unit 5102 and buttons are provided on the housing 5101.

[0535] By applying the chip of one embodiment of the present invention, the information terminal 5100 can execute applications using artificial intelligence. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display portion 5102, an application that recognizes characters, figures, and the like input by a user to a touch panel provided in the display portion 5102 and displays them on the display portion 5102, and an application that performs biometric authentication such as fingerprint or voiceprint authentication.

[0536] 39B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0537] The notebook information terminal 5200 can execute applications using artificial intelligence by applying a chip of one embodiment of the present invention, similar to the information terminal 5100 described above. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Furthermore, new artificial intelligence can be developed by using the notebook information terminal 5200.

[0538] In the above description, a smartphone and a notebook information terminal are illustrated as examples of electronic devices in Figures 39A and 39B, but information terminals other than smartphones and notebook information terminals can also be applied. Examples of information terminals other than smartphones and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0539] [Game consoles] FIG. 39C illustrates a portable game machine 5300, which is an example of a game machine. The portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, and the like. The housing 5302 and the housing 5303 can be detached from the housing 5301. By attaching the connection unit 5305 of the housing 5301 to another housing (not shown), the video displayed on the display unit 5304 can be output to another video device (not shown). In this case, the housing 5302 and the housing 5303 can each function as an operation unit. This allows multiple players to play a game simultaneously. The chips described in the above embodiments can be incorporated into the substrates of the housings 5301, 5302, and 5303.

[0540] 39D shows an example of a game machine, a stationary game machine 5400. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wire.

[0541] A game machine with low power consumption can be realized by applying a GPU or a chip of one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0542] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5300, the portable game console 5300 can have artificial intelligence.

[0543] Originally, the expression of the progress of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game console 5300, it becomes possible to express things that are not limited to the game program. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of people appearing in the game.

[0544] Furthermore, when playing a game requiring multiple players on the portable game console 5300, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent an artificial intelligence game player.

[0545] 39C and 39D illustrate a portable game machine and a stationary game machine as examples of game machines, but game machines to which the GPU or chip of one embodiment of the present invention is applied are not limited to these. Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0546] [Mainframe Computer] The GPU or chip according to one embodiment of the present invention can be applied to a mainframe computer.

[0547] 39E is a diagram showing a supercomputer 5500, which is an example of a mainframe computer. FIG. 39F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0548] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and the GPU or chip described in the above embodiment can be mounted on the boards.

[0549] The supercomputer 5500 is a large-scale computer primarily used for scientific and technological calculations. Scientific and technological calculations require high-speed processing of enormous amounts of calculations, resulting in high power consumption and large amounts of heat generated by the chip. By applying a GPU or chip according to one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. Furthermore, low power consumption can reduce heat generation from circuits, thereby reducing the impact of heat generation on the circuits themselves, peripheral circuits, and modules.

[0550] 39E and 39F illustrate a supercomputer as an example of a mainframe computer, but the mainframe computer to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. Examples of the mainframe computer to which the GPU or chip of one embodiment of the present invention is applied include a computer (server) that provides services, a large general-purpose computer (mainframe), etc.

[0551] [Moving object] The GPU or chip according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the area around the driver's seat of an automobile.

[0552] Fig. 39G is a diagram showing the area around the windshield inside the interior of an automobile, which is an example of a moving body, showing display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0553] The display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, air conditioning settings, etc. The display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, allowing for improved design. The display panels 5701 to 5703 can also be used as lighting devices.

[0554] The display panel 5704 can complement the view (blind spot) blocked by the pillar by displaying an image from an imaging device (not shown) installed in the vehicle. That is, by displaying an image from an imaging device installed outside the vehicle, blind spots can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0555] Since the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system for automobiles. The chip can also be used in a system that provides road guidance, hazard prediction, etc. The display panels 5701 to 5704 may be configured to display information such as road guidance and hazard prediction.

[0556] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies can include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets), and the chip of one embodiment of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

[0557] [electric appliances] 39H shows an example of the electrical appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0558] The electric refrigerator-freezer 5800 having artificial intelligence can be realized by applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800. By using artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800 and their expiration dates, a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5800, and the like.

[0559] Although electric refrigerator-freezers have been described as an example of electrical appliances, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0560] The electronic devices, functions of the electronic devices, application examples of artificial intelligence, and effects thereof described in this embodiment can be appropriately combined with descriptions of other electronic devices.

[0561] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes or examples. [Example]

[0562] In this example, the transistor described in the above embodiment was manufactured, and the electrical characteristics were measured using a transmission electron microscope (TEM). The results are described.

[0563] In this example, transistors having the same configuration as the transistor 200 shown in FIG. 6 were arranged at 2.0 pieces / μm 2 Sample 1 was prepared in which the particles were arranged at a density of 10 ...

[0564] First, a description will be given of the configuration of the transistor that constitutes Sample 1. As shown in Fig. 6, the transistor of Sample 1 has insulator 212, insulator 214, insulator 216, conductor 205, insulator 222, insulator 224, oxide 230a, oxide 230b, oxide 243 (oxide 243a, oxide 243b), conductor 242 (conductor 242a, conductor 242b), insulator 272, insulator 273, insulator 280, oxide 230c, oxide 230d, insulator 250, conductor 260 (conductor 260a, conductor 260b), insulator 282, insulator 287, insulator 283, insulator 284, insulator 274, conductor 240, and insulator 241.

[0565] The following describes details of each component of Sample 1. Note that the transistor of Sample 1 was manufactured using the manufacturing method described in the above embodiment with reference to FIGS.

[0566] Silicon nitride was used as the insulator 212. The silicon nitride was deposited to a thickness of 20 nm by RF sputtering. Aluminum oxide was used as the insulator 214. The aluminum oxide was deposited to a thickness of 40 nm by RF sputtering.

[0567] The insulator 216 was a silicon oxynitride film formed by PECVD. The conductor 205a was a tantalum nitride film formed by DC sputtering. The conductor 205b was a conductive film in which titanium nitride and tungsten were laminated in this order using a metal CVD apparatus.

[0568] Hafnium oxide with a thickness of 20 nm formed by ALD was used as the insulator 222. Silicon oxynitride with a thickness of 30 nm formed by PECVD was used as the insulator 224.

[0569] The oxide 230a was an In-Ga-Zn oxide film with a thickness of 5 nm, which was formed by DC sputtering. The oxide 230a was formed using a target with an atomic ratio of In:Ga:Zn=1:3:4, oxygen gas at 45 sccm, a deposition pressure of 0.7 Pa (measured with a Canon Anelva MG-2 miniature gauge), a deposition power of 500 W, a substrate temperature of 200°C, and a target-substrate distance of 60 mm.

[0570] The oxide 230b was a 15-nm-thick In-Ga-Zn oxide film formed by DC sputtering. The oxide 230b was formed using a target with an In:Ga:Zn atomic ratio of 4:2:4.1, oxygen gas at 45 sccm, a deposition pressure of 0.7 Pa (measured with a Canon Anelva MG-2 miniature gauge), a deposition power of 500 W, a substrate temperature of 200°C, and a target-substrate distance of 60 mm. The oxide 230b was formed immediately after the oxide 230a without exposure to the air.

[0571] The oxide 243 was a 2-nm-thick In-Ga-Zn oxide film formed by DC sputtering. The oxide 243 was formed using a target with an In:Ga:Zn atomic ratio of 1:3:4, 45 sccm of oxygen gas, a deposition pressure of 0.7 Pa (measured with a Canon Anelva MG-2 miniature gauge), a deposition power of 500 W, a substrate temperature of 200°C, and a target-substrate distance of 60 mm. The oxide 243 was formed immediately after the oxide 230b without exposure to the air. After the oxide film that would become the oxide 243 was formed, it was subjected to a heat treatment in a nitrogen atmosphere at 400°C for 1 hour, followed by a further heat treatment in an oxygen atmosphere at 400°C for 1 hour.

[0572] The conductor 242 was made of tantalum nitride with a thickness of 25 nm and deposited by DC sputtering. The insulator 272 was made of aluminum oxide with a thickness of 5 nm and deposited by RF sputtering. The insulator 273 was made of aluminum oxide with a thickness of 3 nm and deposited by ALD.

[0573] The insulator 280 was a laminated film consisting of a first layer and a second layer on the first layer. The first layer of the insulator 280 was made of silicon oxide with a film thickness of 60 nm, deposited by RF sputtering. The first layer of the insulator 280 was deposited using a SiO2 target and 50 sccm of oxygen gas as the deposition gas, with a deposition pressure of 0.7 Pa, a deposition power of 1500 W, a substrate temperature of 170°C, and a distance of 60 mm between the target and the substrate. The second layer of the insulator 280 was made of silicon oxynitride deposited by PECVD.

[0574] In the fabrication process of Sample 1, as shown in FIG. 11, an opening reaching the oxide 230b was formed in the insulator 280 and the like, and channel etching was performed to form the conductor 242a and the conductor 242b. To form the opening, the insulator 280 was removed by dry etching, and the insulators 272 and 273 were removed by wet etching. The etching of the conductor 242, the oxide 243, and the oxide 230b was performed using Cl gas at 80 sccm and Ar gas at 20 sccm, with a pressure of 1.00 Pa, an ICP power of 1000 W, a bias power of 100 W, an electrode distance of 200 mm, and a processing time of 16 seconds. The bias power density was 0.06 W / cm. 2 After etching the conductor 242 and the oxide 243, oxygen plasma treatment was performed without exposing them to the air.

[0575] After the etching, the substrate was washed for 30 seconds using diluted hydrofluoric acid with a hydrogen fluoride concentration of 2 ppm.

[0576] The oxide 230c was a 3-nm-thick In-Ga-Zn oxide film formed by DC sputtering. The first layer of the oxide 230c was formed using a target with an In:Ga:Zn atomic ratio of 4:2:4.1, oxygen gas at 45 sccm, a deposition pressure of 0.7 Pa (measured using a Canon Anelva MG-2 miniature gauge), a deposition power of 500 W, a substrate temperature of 200°C, and a target-to-substrate distance of 60 mm. Prior to deposition of the oxide 230c, a heat treatment was performed at 200°C for 5 minutes under reduced pressure. After the heat treatment, the oxide 230c was continuously deposited without exposure to the air. In this example, the oxide 230c was not patterned (see FIG. 13).

[0577] The oxide 230d was a 3-nm-thick In-Ga-Zn oxide film formed by DC sputtering. The second layer, oxide 230c, was formed using a target with an atomic ratio of In:Ga:Zn=1:3:4, oxygen gas at 45 sccm, a deposition pressure of 0.7 Pa (measured with a Canon Anelva MG-2 miniature gauge), a deposition power of 500 W, a substrate temperature of 200°C, and a target-to-substrate distance of 60 mm. The oxide 230d was formed immediately after the deposition of oxide 230c, without exposure to the air.

[0578] The insulator 250 was a silicon oxynitride film with a thickness of 6 nm, formed by PECVD. Before forming the insulator 250, a heat treatment was performed at 200°C for 5 minutes under reduced pressure. After the heat treatment, the insulator 250 was continuously formed without exposure to the outside air. Furthermore, titanium nitride with a thickness of 5 nm was used as the conductor 260a. Furthermore, tungsten was used as the conductor 260b. After forming the insulator 250, a microwave treatment was performed. The microwave treatment used 150 sccm of Ar gas and 50 sccm of O2 gas as the treatment gas, with a pressure of 400 Pa, a power of 4000 W, a treatment temperature of 400°C, and a treatment time of 600 seconds.

[0579] After the oxide 230c, the oxide 230d, the insulator 250, and ...

Claims

1. a first oxide; and a second oxide and a third oxide on the first oxide; a first conductor on the second oxide; and a second conductor on the third oxide; and a fourth oxide on the first oxide and between the second oxide and the third oxide; a first insulator on the fourth oxide; a third conductor on the first insulator; the first oxide has a groove in a region that does not overlap with the second oxide and the third oxide, the first oxide has first layer-like crystals that are substantially parallel to a surface on which the first oxide is formed, In the trench, the fourth oxide has second layer-like crystals that are approximately parallel to the surface on which the first oxide is formed.

2. a first oxide; and a second oxide and a third oxide on the first oxide; a first conductor on the second oxide; and a second conductor on the third oxide; and a fourth oxide having a region located on the first oxide and between the second oxide and the third oxide; a first insulator on the fourth oxide; a third conductor on the first insulator; the first oxide has a groove in a region that does not overlap with the second oxide and the third oxide, the first oxide has first layer-like crystals that are substantially parallel to a surface on which the first oxide is formed, In the groove portion, the fourth oxide has second layer-like crystals that are substantially parallel to a surface on which the first oxide is formed, The semiconductor device, wherein each of the first oxide and the fourth oxide contains indium, an element M (M is gallium, aluminum, yttrium, or tin), and zinc.

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