Semiconductor Devices

Abstract

To provide a semiconductor device capable of reducing the chip size when forming a plurality of structures having mutually independent high voltage behavior on the same chip.SOLUTION: A semiconductor device includes a semiconductor substrate 1, a first conductivity type first region 2 selectively provided on an upper portion of the semiconductor substrate 1, a second conductivity type second region 4 provided in contact with the first region 2 on the upper part of the semiconductor substrate 1, a second conductivity type third region 5 provided on the semiconductor substrate 1 and spaced apart from the second region 4, a second conductivity type fourth region 3 provided between the second region 4 and the third region 5 on the upper part of the semiconductor substrate 1. a first isolation region 31 provided between the second region 4 and the fourth region 3, and a second separation region 32 provided between the third region 5 and the fourth region 3.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] A switching power supply device, such as an LLC current resonant converter IC, is composed of a start-up element of a start-up circuit connected to a high-voltage input terminal (VH terminal) to which high voltage is input from the AC input line via a diode bridge, a high-side circuit (high-side gate drive circuit) connected to a high-voltage VB terminal or VS terminal for driving the gate of the power switching element on the high side of the half-bridge circuit, level shift elements, etc. (see Non-Patent Document 1).

[0003] The startup element is a switch device that charges the external VCC power supply capacitor when the power supply is started and starts up the VCC power supply circuitry, and is generally composed of a high-voltage junction field-effect transistor (JFET) or metal-oxide semiconductor field-effect transistor (MOSFET).

[0004] The high-side circuit is composed of a level shift circuit, latch circuit, UVLO circuit, gate driver circuit, etc., and is surrounded by a high-voltage junction termination region (HVJT). To convert the voltage levels of the high-side power supply potential VB, which is composed of a bootstrap circuit, and the high-side reference potential VS, the on / off operation of two level shift elements, SET and RESET, which receive input signals from the microcontroller, switches the output logic to the HO terminal and controls the turn-on / turn-off of the gate of the power switching element on the high side of the half-bridge circuit. Self-isolation and EPI junction isolation are commonly used for element isolation, but some converter ICs use dielectric isolation such as trench oxide film.

[0005] In recent years, with the increasing demand for lower prices for communication devices, home appliances, etc., there is a demand for chip shrink technology to realize smaller chip sizes for switching power supplies themselves. For this reason, in conventional LLC current resonant converter ICs, the control chip with digital control functions and trimming functions is manufactured using fine processes such as 0.13 μm rules, while high-voltage devices such as the start-up element, high-side circuit, and level shift element are manufactured on separate chips with larger process processing rules, and a multi-chip configuration in which multiple chips are placed on the same die pad has become mainstream.

[0006] Patent Document 1 discloses providing a p-isolation diffusion region between the PMOS and NMOS in the high-side region. Patent Document 2 discloses providing a p-isolation diffusion region between the high-voltage MOSFET and the VS reference potential region. - It is disclosed that a region is provided. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 6008054 specification [Patent Document 2] Patent No. 5293831 Specification [Non-patent literature]

[0008] [Non-Patent Document 1] PCIM Asia2012. A New 600V-Class Power Management IC Realizing a System Downsizing for Current Resonant Type Converters Summary of the Invention [Problem to be solved by the invention]

[0009] However, when forming the startup element and high-side circuit on the same high-voltage chip, they cannot be formed within the same voltage-resistant structure because they are connected to the VH and VB terminals, which have different high-voltage behaviors during charging, switching, etc., and are instead placed in separate areas separated by a ground potential area, which becomes an obstacle to shrinking the chip size.

[0010] In view of the above problems, the present invention aims to provide a semiconductor device that can reduce the chip size when multiple structures that exhibit independent high-voltage behavior are formed on the same chip. [Means for solving the problem]

[0011] One aspect of the present invention is summarized as a semiconductor device comprising: (a) a semiconductor substrate; (b) a first region of a first conductivity type selectively provided on an upper portion of the semiconductor substrate; (c) a second region of a second conductivity type provided on an upper portion of the semiconductor substrate in contact with the first region; (d) a third region of the second conductivity type provided on an upper portion of the semiconductor substrate spaced apart from the second region; (e) a fourth region of the second conductivity type provided between the second region and the third region on the upper portion of the semiconductor substrate; (f) a first isolation region provided between the second region and the fourth region; and (g) a second isolation region provided between the third region and the fourth region. [Effects of the Invention]

[0012] According to the present invention, it is possible to provide a semiconductor device that can reduce the chip size when a plurality of structures that exhibit independent high-voltage behaviors are formed on the same chip. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along line AA′ in FIG. 2. [Figure 4] FIG. 10 is a plan view of a semiconductor device according to a comparative example. [Figure 5] FIG. 10 is a plan view of a semiconductor device according to a second embodiment. [Figure 6] FIG. 6 is a cross-sectional view taken along line AA′ in FIG. 5. [Figure 7] FIG. 10 is a plan view of a semiconductor device according to a third embodiment. [Figure 8] FIG. 8 is a cross-sectional view taken along line AA′ in FIG. 7. [Figure 9] FIG. 10 is a plan view of a semiconductor device according to a fourth embodiment. [Figure 10] FIG. 10 is a cross-sectional view taken along line AA′ in FIG. 9. [Figure 11] FIG. 10 is a plan view of a semiconductor device according to a fifth embodiment. [Figure 12] FIG. 10 is a plan view of a semiconductor device according to a sixth embodiment. [Figure 13] FIG. 13 is a cross-sectional view taken along line AA′ in FIG. [Figure 14] FIG. 10 is a cross-sectional view of a semiconductor device according to another embodiment. [Figure 15] FIG. 10 is another cross-sectional view of the semiconductor device according to the other embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, first to sixth embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the first to sixth embodiments shown below are examples of devices and methods for embodying the technical concept of the present invention, and the technical concept of the present invention does not limit the materials, shapes, structures, arrangements, etc. of component parts to those described below.

[0015] In this specification, the term "carrier supply region" refers to a semiconductor region that supplies majority carriers constituting the main current, such as the source region of a field-effect transistor (FET) or static induction transistor (SIT), or the emitter region of an insulated gate bipolar transistor (IGBT). In static induction (SI) thyristors and gate turn-off (GTO) thyristors, the anode region serves as the carrier supply region. In SI thyristors and GTO thyristors, the cathode region functions as the carrier receiving region. In FETs, SITs, IGBTs, SI thyristors, and GTO thyristors, the "control electrode" refers to the gate electrode of an FET, SIT, IGBT, SI thyristor, or GTO thyristor, and has the function of controlling the flow of the main current between the carrier supply region and the carrier receiving region.

[0016] Furthermore, the definitions of directions such as up and down in this specification are merely for the convenience of explanation and do not limit the technical concept of the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are inverted and read as such.

[0017] In this specification, the first conductivity type is p-type and the second conductivity type is n-type. However, the conductivity types may be reversed, with the first conductivity type being n-type and the second conductivity type being p-type. The "+" and "-" affixed to "n" and "p" indicate a semiconductor region with a relatively higher or lower impurity concentration, respectively, compared to a semiconductor region without the "+" and "-" affixed. However, semiconductor regions with the same "n" and "n" affixed do not necessarily have the same impurity concentration. Furthermore, in the following description, components and regions with the "first conductivity type" and "second conductivity type" affixed refer to components and regions made of semiconductor materials, even if not otherwise explicitly stated.

[0018] (First embodiment) 1, a high-voltage integrated circuit (HVIC) including a startup element 100, a high-side circuit 101, and level shift elements T1 and T2 is exemplified as a semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment includes a VH terminal 102, an SMD terminal 103, an LS_S terminal 104, an LS_R terminal 105, a GND terminal 106, a VB terminal 107, an HO terminal 108, and a VS terminal 109.

[0019] The startup element 100 is an element that constitutes part of a startup circuit used in a switching power supply. The startup element 100 is connected to a VH terminal 102 and an SMD terminal 103. A high VH potential (first potential) is applied to the VH terminal 102 from the AC input line via a diode bridge. An external startup circuit is connected to the SMD terminal 103. The startup element 100 charges an external VCC power supply capacitor via the SMD terminal 103 in accordance with the VH potential applied from the VH terminal 102 when the power supply is started, and starts up the VCC power supply circuitry.

[0020] The startup element 100 is configured, for example, by a junction field effect transistor (JFET). The drain of the JFET, which is the startup element 100, is connected to a VH terminal 102, and the source of the JFET is connected to an SMD terminal 103. Note that the startup element 100 may also be configured by a MOSFET or the like in addition to a JFET.

[0021] The connection between the startup element 100 and the VH terminal 102 is made via a resistor R1 to a GND terminal 106. The cathode of a protection diode D3 is connected to the startup element 100 and the SMD terminal 103. The anode of the protection diode D3 is connected to the GND terminal 106.

[0022] The level shift elements T1 and T2 are configured, for example, by high-voltage n-channel MOSFETs. The drains of the level shift elements T1 and T2 are each connected to the high-side circuit 101. The sources of the level shift elements T1 and T2 are each connected to the GND terminal 106. The gate of the level shift element T1 is connected to the LS_S terminal 104 via a resistor R3. The gate of the level shift element T2 is connected to the LS_R terminal 105 via a resistor R4.

[0023] The level shift elements T1 and T2 are elements for transmitting signals between an external low-potential side circuit (low-side circuit) and the high-side circuit 101. The level shift element T1 converts an on / off signal for setting the GND potential reference, which is input from the external low-side circuit via the LS_S terminal 104, into an on / off signal for setting the VS potential reference, and transmits it to the high-side circuit 101. The level shift element T2 converts an on / off signal for resetting the GND potential reference, which is input from the external low-side circuit via the LS_R terminal 105, into an on / off signal for resetting the VS potential reference, and transmits it to the high-side circuit 101.

[0024] One end of resistor R2 and the cathode of protection diode D2 are connected between resistor R3, which is connected to the gate of level shift element T1, and the LS_S terminal 104. The other end of resistor R2 and the anode of protection diode D2 are connected to the GND terminal 106. The cathode of protection diode D1 is connected between resistor R4, which is connected to the gate of level shift element T2, and the LS_R terminal 105. The anode of protection diode D1 is connected to the GND terminal 106.

[0025] The high-side circuit 101 is connected to a VB terminal 107, an HO terminal 108, and a VS terminal 109. A VB potential (second potential) which is a power supply potential that is the highest potential of the high-side circuit 101 is applied to the VB terminal 107. A VS potential which is the lowest potential of the high-side circuit 101 and is about 15 V lower than the VB potential is applied to the VS terminal 109. The HO terminal 108 is connected to the gate of the high-potential side power switching element of a power conversion unit formed by connecting a high-potential side power switching element and a low-potential side power switching element. The VS terminal 109 is connected to the connection point between the high-potential side power switching element and the low-potential side power switching element. The VS potential is the high potential of the high-potential side power switching element. from Low potential of the power switching element on the low potential side of Therefore, the VB potential also fluctuates with the VS potential. The power switching element is composed of, for example, an IGBT or a MOSFET.

[0026] Although not shown, the high-side circuit 101 includes, for example, a level shift resistor, a level shift circuit, a latch circuit, a UVLO circuit, and a gate drive circuit. The gate drive circuit includes, for example, a CMOS circuit configured with nMOS transistors and pMOS transistors in its output stage. The high-side circuit 101 uses the VS potential applied to a VS terminal 109 as its reference potential and the VB potential applied to a VB terminal 107 as its power supply potential. The high-side circuit 101 outputs an output signal HO to an HO terminal 108 in response to on / off signals from the level shift elements T1 and T2, thereby driving the gate of a power switching element connected to the HO terminal 108.

[0027] One end of a resistor R5 and the cathode of a protection diode D4 are connected to the high-side circuit 101. The other end of the resistor R5 and the anode of the protection diode D4 are connected to a GND terminal 106.

[0028] Fig. 2 is a plan view showing the configuration of the semiconductor device according to the first embodiment shown in Fig. 1. As shown in Fig. 2, the semiconductor device according to the first embodiment includes an activation element 10, a high-potential side circuit region (high-side circuit region) 5, and a protection element region 8, all of which are provided on the same high-voltage semiconductor chip (p-type semiconductor substrate) 1. The activation element 10 and the high-side circuit region 5 correspond to the activation element 100 and the high-side circuit 101 shown in Fig. 1, respectively. The protection element region 8 shown in Fig. 2 is a region in which the protection diodes D1 to D5 and resistors R1 to R5, etc. shown in Fig. 1 are formed.

[0029] The p-type semiconductor substrate 1 has, for example, a rectangular planar shape. The high-side circuit region 5 is provided on the right side of the center of the rectangle formed by the p-type semiconductor substrate 1. The high-side circuit region 5 has a substantially rectangular planar shape. The startup element 10 is provided on the left side of the rectangle formed by the p-type semiconductor substrate 1. The startup element 10 is provided to extend parallel to the left side of the rectangle formed by the high-side circuit region 5. The protection element region 8 is provided on the left side of the startup element 10 of the rectangle formed by the p-type semiconductor substrate 1. The protection element region 8 is provided to extend parallel to the longitudinal direction of the startup element 10 and in a straight line along the left side of the rectangle formed by the p-type semiconductor substrate 1.

[0030] Although not shown, various elements such as nMOS transistors and pMOS transistors that constitute the CMOS circuit of the output stage are provided in the high-side circuit region 5. A ring-shaped nMOS transistor is arranged around the high-side circuit region 5. - A type-type breakdown voltage region 6 is provided. The breakdown voltage region 6 is configured, for example, by a high-voltage junction termination region (HVJT). Level shift elements 7a and 7b are provided in the breakdown voltage region 6. The level shift elements 7a and 7b are configured, for example, by high-voltage n-channel MOSFETs. The breakdown voltage regions of the level shift elements 7a and 7b are common to the breakdown voltage region 6.

[0031] The semiconductor device according to the first embodiment includes a VH pad 12, an SMD pad 13, an LS_S pad 14, an LS_R pad 15, a GND pad 16, a VB pad 17, an HO pad 18, and a VS pad 19, which respectively configure electrode pads. The VH pad 12, the SMD pad 13, the LS_S pad 14, the LS_R pad 15, the GND pad 16, the VB pad 17, the HO pad 18, and the VS pad 19 correspond to the VH terminal 102, the SMD terminal 103, the LS_S terminal 104, the LS_R terminal 105, the GND terminal 106, the VB terminal 107, the HO terminal 108, and the VS terminal 109, respectively, shown in FIG.

[0032] The VH pad 12 is provided above the activation device 10, near the right side of the center in the longitudinal direction of the activation device 10. A metal wiring 22 is connected to the VH pad 12. The metal wiring 22 extends along the longitudinal direction of the activation device 10 and is electrically connected to the drain region of the activation device 10 through a via in the layer below the metal wiring 22.

[0033] The SMD pad 13 is provided above the ground potential region 2 in the lower left region of the rectangle formed by the p-type semiconductor substrate 1. A metal wiring 23 is connected to the SMD pad 13. The metal wiring 23 extends along the longitudinal direction of the startup element 10 and is electrically connected to the source region of the startup element 10 through a via in the layer below the metal wiring 23.

[0034] The LS_S pad 14 is provided above the ground potential region 2, between the protection element region 8 and the startup element 10, near the lower left of the rectangle formed by the p-type semiconductor substrate 1. A metal wiring 24 is connected to the LS_S pad 14. The metal wiring 24 extends between the protection element region 8 and the startup element 10 and is connected to the level shift element 7a.

[0035] The LS_R pad 15 is provided above the ground potential region 2, adjacent to the right side of the SMD pad 13 near the lower left of the rectangle formed by the p-type semiconductor substrate 1. A metal wiring 25 is connected to the LS_R pad 15. The metal wiring 25 is connected to the level shift element 7b.

[0036] The GND pad 16 is provided above the ground potential region 2 in the lower right region of the rectangle formed by the p-type semiconductor substrate 1. A metal wiring 26 is connected to the GND pad 16. The metal wiring 26 extends along the lower side of the rectangle formed by the p-type semiconductor substrate 1, passes between the SMD pad 13 and the LS_R pad 15, and extends along the longitudinal direction of the startup element 10. Furthermore, the metal wiring 26 is U-shaped at the end of the metal wiring 23. character The metal wiring is folded back in a shape and extends along the longitudinal direction of the starting element 10. 26 is metal wiring 26 This is electrically connected to the ground potential region 2 and the gate electrode of the starter element 10 through vias in the lower layer.

[0037] The VB pad 17 is provided above the high-side circuit region 5. A metal wiring 20 and a metal wiring 27 are connected to the VB pad 17. The metal wiring 20 is electrically connected to a ring-shaped metal wiring 21 located below the metal wiring 20 via a via located below the metal wiring 20. The metal wiring 21 is connected to the high-side circuit region 5 located below the metal wiring 21 via a via located below the metal wiring 21. The metal wiring 27 is electrically connected to necessary portions of various elements included in the high-side circuit region 5 via a via located below the metal wiring 27.

[0038] The HO pad 18 is provided above the high-side circuit region 5. A metal wiring 28 is connected to the HO pad 18. The metal wiring 28 is electrically connected to necessary portions of various elements included in the high-side circuit region 5 through vias in a layer below the metal wiring 28.

[0039] The VS pad 19 is provided above the high-side circuit region 5. A metal wiring 29 is connected to the VS pad 19. The metal wiring 29 is electrically connected to necessary portions of various elements included in the high-side circuit region 5 through vias in a layer below the metal wiring 29.

[0040] The starting element 10 is n - The high-side circuit 101-side withstand voltage region 6 and the startup device 10-side withstand voltage region 4 are provided in a p-type ground potential region 2. The high-side circuit 101-side withstand voltage region 6 and the startup device 10-side withstand voltage region 4 are surrounded by a p-type ground potential region 2. A double isolation region (first isolation region) 31 and an isolation region (second isolation region) 32 are provided between the high-side circuit 101-side withstand voltage region 6 and the startup device 10-side withstand voltage region 4. The isolation regions 31 and 32 are formed of, for example, p-type diffusion layers. FIG. 2 illustrates an example in which the isolation regions 31 and 32 have a linear planar shape extending in the vertical direction of FIG. 2. The longitudinal ends of the isolation regions 31 and 32 coincide with the outer peripheral ends of the withstand voltage regions 4 and 6 and are in contact with the ground potential region 2.

[0041] Between the isolation regions 31 and 32, n - A floating potential region 3 of a rectangular shape is provided. The floating potential region 3 has a linear planar shape extending parallel to the isolation regions 31 and 32. The longitudinal ends of the floating potential region 3 are in contact with the ground potential region 2. The floating potential region 3 is not fixed at a specific potential, but is at a floating potential. Not being fixed at a specific potential means that, for example, a specific potential such as a VS potential is not applied during normal operation.

[0042] 3 is a cross-sectional view taken along line AA' passing through the starting element 10 in FIG. 2. As shown in FIG. 3, an insulating film 40 is provided on the upper surface of a p-type semiconductor substrate 1. The insulating film 40 is not shown in FIG. 2. The p-type semiconductor substrate 1 is made of, for example, a silicon (Si) substrate, but is not limited thereto and may be made of, for example, a semiconductor substrate made of silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or the like. The p-type semiconductor substrate 1 may also be made of a p-type epitaxial layer provided on a semiconductor substrate.

[0043] A p-type ground potential region (first region) 2 is provided above the p-type semiconductor substrate 1. Above the ground potential region 2, a p +A contact region 34 is provided on the insulating film 40. The contact region 34 is connected to the metal wiring 26 on the insulating film 40 through a via 61 that penetrates the insulating film 40. A GND potential (for example, 0 V) ​​is applied to the contact region 34 through the via 61, the metal wiring 26, and the GND pad 16, and the contact region 34 is fixed to the GND potential.

[0044] The upper portion of the p-type semiconductor substrate 1 is in contact with the ground potential region 2, and - A type-type voltage-resistant region (second region) 4 is provided. An n-type region of the starter element 10 having a higher impurity concentration than the voltage-resistant region 4 is provided above the ground potential region 2 side of the voltage-resistant region 4. + A source region (seventh region) 35, which is a carrier supply region for the mold, is provided. The source region 35 is connected to a metal wiring 23 on the insulating film 40 through a via 62 that penetrates the insulating film 40, and is electrically connected to the SMD pad 13.

[0045] A p-type gate region 30 of the startup device 10 is provided above the breakdown voltage region 4, spaced apart from the source region 35. Note that, depending on the type of startup device 10, the gate region 30 need not be provided at this position. For example, the gate region 30 is provided in a vertically pinched-off structure as shown in FIG. 3 . However, it need not be provided at this position in a structure in which the planar shapes of the source region and gate region of the startup device 10 are gear-shaped. A gate electrode 50 of the startup device 10 is provided on the gate region 30 via a gate insulating film, which is part of the insulating film 40, and is embedded in the insulating film 40. The gate electrode 50 is connected to the metal wiring 26 on the insulating film 40 via a via 63 that penetrates the insulating film 40 above the gate electrode 50. A GND potential is applied to the gate electrode 50 via the via 63, the metal wiring 26, and the GND pad 16.

[0046] Above the voltage-resistant region 4, the n-type semiconductor layer of the starter element 10 is provided, which is spaced apart from the source region 35 and the gate region 30 and has a higher impurity concentration than the voltage-resistant region 4. + A drain region (eighth region) 36, which is a carrier-receiving region of the silicon dioxide film, is provided. teeth, and is connected to the metal wiring 22 on the insulating film 40 through a via 64 that penetrates the insulating film 40. A VH potential higher than the GND potential, for example, several hundred volts, is applied to the drain region 36 through the via 64, the metal wiring 22, and the VH pad 12.

[0047] In the start-up device 10, a VH potential is applied to the drain region 36, and a current flows from the drain region 36 to the source region 35 via the breakdown voltage region 4, which functions as a drift region. fart The flowing current charges the external VCC power supply capacitor via the SMD pad 13, starting up the VCC power supply circuit. When the potential of the voltage-resistant region 4 rises, a depletion layer expands from the pn junction between the voltage-resistant region 4 and the gate region 30, pinching off the voltage-resistant region 4 below the gate region 30. This turns off the startup device 10.

[0048] An isolation region (first isolation region) 31 is provided in the upper part of the p-type semiconductor substrate 1, in contact with the voltage-resistant region 4. The isolation region 31 is made of a p-type diffusion region. The depth of the isolation region 31 is deeper than the depths of the voltage-resistant region 4 and the floating potential region 3. The bottom of the isolation region 31 reaches the p-type semiconductor substrate 1. The isolation region 31 is electrically connected to the GND potential via the p-type semiconductor substrate 1.

[0049] The upper portion of the isolation region 31 is provided with a p + An anti-inversion region 37 is provided. Although not shown in FIG. 2, the anti-inversion region 37 may extend linearly along the linear planar shape of the isolation region 31. The impurity concentration of the anti-inversion region 37 is adjusted to a concentration that prevents complete depletion when a high VH voltage is applied to the adjacent voltage-resistant region 4. The anti-inversion region 37 has the function of preventing the formation of an inversion layer in the isolation region 31 due to surface charges of the isolation region 31, etc.

[0050] The upper portion of the p-type semiconductor substrate 1 is in contact with the isolation region 31 and has a floating potential n -A floating potential region (fourth region) 3 is provided. The width W1 of the floating potential region 3 is preferably, for example, about 50 μm to 100 μm. The depth of the floating potential region 3 may be the same as the depth of the voltage-resistant region 6. The impurity concentration of the floating potential region 3 may be the same as the impurity concentration of the voltage-resistant region 6.

[0051] An isolation region (second isolation region) 32 is provided on the upper part of the p-type semiconductor substrate 1, in contact with the floating potential region 3. Like the isolation region 31, the isolation region 32 is formed of a p-type diffusion region. The impurity concentration of the isolation region 32 may be the same as or different from the impurity concentration of the isolation region 31. The depth of the isolation region 32 is deeper than the depths of the floating potential region 3 and the voltage-withstanding region 6. The depth of the isolation region 32 may be the same as or different from the depth of the isolation region 31. The bottom of the isolation region 32 reaches the p-type semiconductor substrate 1. The isolation region 32 is electrically connected to the GND potential via the p-type semiconductor substrate 1.

[0052] The upper portion of the isolation region 32 is formed with a p + The mold inversion prevention region 38 is provided. The inversion prevention region 38 is not shown in FIG. 2, but it is the same as the isolation region. 32 The impurity concentration of the inversion prevention region 38 is adjusted to a level that prevents complete depletion when a high VB voltage is applied to the adjacent voltage-resistant region 6. The inversion prevention region 38 has the function of preventing the formation of an inversion layer in the isolation region 32 due to surface charges of the isolation region 32, etc.

[0053] An n-type high-side circuit region (third region) 5 is provided on the upper portion of the p-type semiconductor substrate 1, on the opposite side of the floating potential region 3 of the isolation region 32. An n-type voltage-resistant region (third region) having a lower impurity concentration than the high-side circuit region 5 is provided on the upper portion of the p-type semiconductor substrate 1 between the isolation region 32 and the high-side circuit region 5. 6The voltage-withstanding region 6 is provided so as to surround the high-side circuit region 5 at least in the region other than between the isolation region 32 and the high-side circuit region 5. The voltage-withstanding region 6 between the isolation region 32 and the high-side circuit region 5 does not have to be provided. When the voltage-withstanding region 6 is not provided between the isolation region 32 and the high-side circuit region 5, the isolation region 32 and the high-side circuit region 5 may be in contact with each other. Above the high-side circuit region 5, an n-type impurity layer having a higher impurity concentration than the high-side circuit region 5 is provided. + The contact region 39 is connected to a metal wiring on the insulating film 40 via a via 65 that penetrates the insulating film 40. 21 The contact region 39 is connected to a via 65, a metal wiring 21 A VB potential higher than the GND potential is applied via the VB pad 17. The VB potential is applied separately and independently from the VH potential. The VB potential may be equal to the VH potential, lower than the VH potential, or higher than the VH potential.

[0054] That is, in the semiconductor device according to the first embodiment, n - The structure is such that an activation element 10 is provided in a part of the voltage-resistant regions 4 and 6 of the mold, the high-side circuit region 5 and the activation element 10 are separated by two or more isolation regions 31 and 32, and a floating potential region 3 of a floating potential is provided between the isolation regions 31 and 32.

[0055] In the startup element 10 of the semiconductor device according to the first embodiment, when a high voltage VH potential of several hundred volts is applied to the drain region 36 of the startup element 10 via the VH pad 12, metal wiring 22, and via 64, a depletion layer spreads from the pn junction between the isolation region 31 and the withstand voltage region 4, depleting the lower part of the isolation region 31 and applying an electric field to the floating potential region 3. The floating potential region 3 is at an intermediate potential between the potential of the withstand voltage region 4 on the startup element 10 side and the potential of the withstand voltage region 6 on the high-side circuit region 5 side, and the withstand voltage can be maintained at a lower voltage than the withstand voltage region 4 on the startup element 10 side without causing localized electric field concentration from the outer ground potential region 2 to the high potential region.

[0056] Furthermore, in the high-side circuit region 5 of the semiconductor device according to the first embodiment, when a high voltage VB potential is applied to the contact region 39 above the high-side circuit region 5 via the VB pad 17, the metal wiring 21, and the via 65, a depletion layer spreads from the pn junction between the isolation region 32 and the voltage-resistant region 6, depleting the lower part of the isolation region 32 and applying an electric field to the floating potential region 3. The floating potential region 3 is at an intermediate potential between the potential of the voltage-resistant region 4 on the startup device 10 side and the potential of the voltage-resistant region 6 on the high-side circuit region 5 side, and can maintain a voltage resistance at a lower voltage than the voltage-resistant region 6 on the high-side circuit region 5 side.

[0057] Furthermore, when a high voltage VH potential is applied to the drain region 36 of the startup device 10 of the semiconductor device according to the first embodiment and at the same time a high voltage VB potential is applied to the contact region 39 above the high-side circuit region 5, the lower portions of the isolation regions 31 and 32 are depleted, and an electric field is also applied to the floating potential region 3. The floating potential region 3 is also depleted from the voltage-resistant region 4 on the startup device 10 side. and The withstand voltage can be maintained in a state where the voltage is lower than that of the withstand voltage region 6 on the high side circuit region 5 side.

[0058] Furthermore, in the semiconductor device according to the first embodiment, the voltage-resistant region 4 on the startup element 10 side and the voltage-resistant region 6 on the high-side circuit region 5 side are separated by two or more separation regions 31, 32, and the width W1 of the floating potential region 3 is set to 50 μm or more. This allows the n-type well region, p-type semiconductor substrate 1, and n-type well region, which are the high-side circuit region 5, to remain stable even when voltage noise due to overshoot or undershoot caused by switching or an external surge is instantaneously applied to the VH pad 12 or VB pad 17. - Since the parasitic npn bipolar transistor formed by the type voltage-resistant region 4 becomes a wide-base transistor and the gain is kept small, the operation of the parasitic npn bipolar transistor in response to voltage fluctuations in VH pad 12 and VB pad 17 can be suppressed, and thermal runaway breakdown can be suppressed. Therefore, a high-voltage chip with high noise resistance can be realized at low cost.

[0059] <Comparative Example> Here, a semiconductor device according to a comparative example will be described. As shown in Fig. 4, the semiconductor device according to the comparative example is similar to the semiconductor device according to the first embodiment shown in Fig. 2 in that the startup element 210 and the high-side circuit region 205 are provided on the same high-voltage semiconductor chip 201. However, the semiconductor device according to the comparative example differs from the semiconductor device according to the first embodiment in that the startup element 210 and the high-side circuit region 205 are separated by a p-type ground potential region 202 and are arranged in separate regions as individual elements. A protection element region 208 is provided adjacent to the startup element 210 and the high-side circuit region 205.

[0060] The VH pad 212 is connected to the drain region of the activation element 210 via metal wiring 222 and metal wiring 203. The SMD pad 213 is connected to the source region of the activation element 210 via metal wiring 223. The LS_S pad 214 is connected to the level shift element 207a via metal wiring 224. The LS_R pad 215 is connected to the level shift element 207b via metal wiring 225. The GND pad 216 is connected to the ground potential region 202 and the gate electrode of the activation element 210 via metal wiring 226.

[0061] The VB pad 217 is connected to the outer periphery of the high-side circuit region 205 via metal wiring 220 and metal wiring 221. The VB pad 217 is electrically connected to the high-side circuit region 205 via metal wiring 227. The HO pad 218 is electrically connected to the high-side circuit region 205 via metal wiring 228. The VS pad 219 is electrically connected to the high-side circuit region 205 via metal wiring 229.

[0062] In the semiconductor device according to the comparative example, startup device 210 and high-side circuit region 205 are separated by ground potential region 202 and arranged in separate regions as individual devices, making chip shrink difficult. In contrast, in the semiconductor device according to the first embodiment, as shown in Figures 2 and 3, startup device 10 is provided in part of withstand voltage regions 4 and 6 surrounding high-side circuit region 5, and withstand voltage region 4 on the startup device 10 side is separated from withstand voltage region 6 on the high-side circuit region 5 side by isolation regions 31 and 32 and floating potential region 3. This makes it possible to integrate high-withstand voltage devices to which two different high potentials, VB potential and VH potential, are applied, thereby significantly reducing the chip size.

[0063] (Second embodiment) Fig. 5 is a plan view of a semiconductor device according to a second embodiment, and Fig. 6 is a cross-sectional view taken along the line AA' in Fig. 5. As shown in Figs. 5 and 6, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment shown in Figs. 2 and 3 in that the metal wiring 22 connected to the VH pad 12 and the metal wiring 21 connected to the VB pad 17 extend horizontally toward the floating potential region 3 and have protruding portions 22a, 21a that protrude above the floating potential region 3 via the insulating film 40. The other configuration of the semiconductor device according to the second embodiment is substantially the same as that of the semiconductor device according to the first embodiment, and therefore a redundant description will be omitted.

[0064] The semiconductor device according to the second embodiment can reduce the chip size while maintaining the breakdown voltage, similar to the semiconductor device according to the first embodiment. Furthermore, since the metal wiring 22 connected to the VH pad 12 and the metal wiring 21 connected to the VB pad 17 extend over the floating potential region 3 via the insulating film 40, when the VH potential is applied to the VH pad 12 or the VB potential is applied to the VB pad 17, the potential of the floating potential region 3 is easily raised, and the lower portions of the isolation regions 31 and 32 are easily depleted.

[0065] (Third embodiment) FIG. 7 is a plan view of a semiconductor device according to a third embodiment, and FIG. 8 is a cross-sectional view taken along the line AA′ in FIG. 7. As shown in FIGS. 7 and 8, the semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment shown in FIGS. 2 and 3 in that isolation regions 51 and 52 are formed by trenches using DTI (Deep Trench Isolation). The insides of the trenches of the isolation regions 51 and 52 are filled with an insulating film such as an LP-TEOS film or a polysilicon film. The bottoms of the isolation regions 51 and 52 reach the p-type semiconductor substrate 1. The other configurations of the semiconductor device according to the third embodiment are substantially the same as those of the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0066] According to the semiconductor device of the third embodiment, even when the isolation regions 51 and 52 are formed by trench grooves using DTI, when the VH potential or VB potential becomes a high voltage state, the floating potential region 3 and the diode formed by the p-type semiconductor substrate 1 and the n - Type withstand voltage region 4 or n - The depletion layers extending from the die breakdown voltage regions 6 overlap in the regions below the isolation regions 51 and 52 formed therebetween, and by depleting the entire region, it is possible to reduce the chip size while maintaining the breakdown voltage. In the semiconductor device according to the third embodiment, similarly to the semiconductor device according to the second embodiment shown in FIGS. 5 and 6, the metal wiring 22 connected to the VH pad 12 and the metal wiring 21 connected to the VB pad 17 may extend to the floating potential region 3 side and protrude above the floating potential region 3 via the insulating film 40. In addition, the two isolation regions 51,52 One of them may be formed by a p-type diffusion region, and the other may be formed by a trench groove formed by DTI.

[0067] (Fourth embodiment) Fig. 9 is a plan view of the semiconductor device according to the fourth embodiment, and Fig. 10 is a cross-sectional view taken along the line AA' in Fig. 9. As shown in Figs. 9 and 10, the semiconductor device according to the fourth embodiment differs from the semiconductor device according to the first embodiment shown in Figs. 2 and 3 in that triple isolation regions 31 to 33 are provided.

[0068] For example, the isolation regions 31 to 33 are made of p-type diffusion layers. The isolation regions 31 to 33 may be made of DTI. The n-type diffusion layer is sandwiched between the isolation regions 31 and 33 and is not fixed to a specific potential but is at a floating potential. - A floating potential region (fifth region) 3a is provided between the isolation region 32 and the isolation region 33. The floating potential region 3a is not fixed to a specific potential and is in a floating potential n. - Similar to the isolation regions 31 and 32, the isolation region 33 also has a p-type floating potential region (fourth region) 3b. + A mold inversion prevention region may be provided. The other configuration of the semiconductor device according to the fourth embodiment is substantially the same as that of the semiconductor device according to the first embodiment, and therefore a duplicated description will be omitted.

[0069] According to the semiconductor device of the fourth embodiment, even when triple isolation regions 31 to 33 are provided, it is possible to reduce the chip size while maintaining the breakdown voltage, as in the semiconductor device of the first embodiment. Also in the semiconductor device of the fourth embodiment, as in the semiconductor device of the second embodiment shown in FIGS. 5 and 6, the metal wiring 22 connected to the VH pad 12 and the metal wiring 21 connected to the VB pad 17 may extend toward the floating potential regions 3a and 3b and overhang above the floating potential regions 3a and 3b via the insulating film 40. Although the semiconductor device of the fourth embodiment has been exemplified as having triple isolation regions 31 to 33, four or more isolation regions may also be provided.

[0070] (Fifth embodiment) As shown in FIG. 11, the semiconductor device according to the fifth embodiment has double isolation regions (31a, 31b, 51 a ) and separation regions (32a, 32b, 52 a ) are configured by a combination of different structures, which is different from the semiconductor device according to the first embodiment shown in FIG.

[0071] Separation area (31a, 31b, 51 aThe separation region (32a, 32b, 52) includes a central separation region 51a provided adjacent to the starting element 10, an end separation region 31a connected to one end of the central separation region 51a, and an end separation region 31b connected to the other end of the central separation region 51a. a ) includes a central separation portion 52a that is arranged opposite to and parallel to the central separation portion 51a, an end side separation portion 32a that is connected to one end side of the central separation portion 52a, and an end side separation portion 32b that is connected to the other end side of the central separation portion 52a.

[0072] For example, the central isolation portions 51a and 52a are formed by trenches using DTI, and the end isolation portions 31a, 31b, 32a, and 32b are formed by p-type diffusion layers. The other configurations of the semiconductor device according to the fifth embodiment are substantially the same as those of the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0073] According to the semiconductor device of the fifth embodiment, the double isolation regions (31a, 31b, 51 a ) and separation regions (32a, 32b, 52 a ) are configured with a combination of different structures, the chip size can be reduced while maintaining the breakdown voltage, as in the semiconductor device according to the first embodiment. Note that in the semiconductor device according to the fifth embodiment, the metal wiring 22 connected to the VH pad 12 and the metal wiring 21 connected to the VB pad 17 may also extend toward the floating potential region 3 and protrude above the floating potential region 3 via the insulating film 40, as in the semiconductor device according to the second embodiment shown in FIGS.

[0074] (Sixth embodiment) Fig. 12 is a plan view of the semiconductor device according to the sixth embodiment, and Fig. 13 is a cross-sectional view taken along the line AA' in Fig. 12. As shown in Fig. 12 and Fig. 13, the semiconductor device according to the sixth embodiment is different from the semiconductor device according to the first embodiment shown in Fig. 2 in that triple isolation regions 31, 32, and 51 are provided, and one isolation region 51 of the triple isolation regions 31, 32, and 51 has a structure different from the other isolation regions 31 and 32.

[0075] For example, of the triple isolation regions 31, 32, and 51, the central isolation region 51 is formed by a trench groove using DTI, and the isolation regions 31 and 32 adjacent to the isolation region 51 are each formed by a p-type diffusion layer. The other configurations of the semiconductor device according to the sixth embodiment are substantially the same as those of the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0076] According to the semiconductor device of the sixth embodiment, triple isolation regions 31, 32, and 51 are provided, and even if one isolation region 51 of the triple isolation regions 31, 32, and 51 has a structure different from the other isolation regions 31 and 32, it is possible to reduce the chip size while maintaining the breakdown voltage, as in the semiconductor device of the first embodiment. Note that, in the semiconductor device of the sixth embodiment, as in the semiconductor device of the second embodiment shown in Figures 5 and 6, the metal wiring 22 connected to the VH pad 12 and the metal wiring 21 connected to the VB pad 17 may extend toward the floating potential regions 3a and 3b and protrude above the floating potential regions 3a and 3b via the insulating film 40.

[0077] (Other embodiments) As described above, the present invention has been described with reference to the first to sixth embodiments, but the descriptions and drawings that form part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0078] For example, as the semiconductor device according to the first to sixth embodiments, a structure in which an n-type diffusion layer such as a floating potential region 3, a voltage-resistant region 4, 6, and an n-type well region which is a high-side circuit region 5 is formed on the upper part of a p-type semiconductor substrate 1 has been exemplified, but the present invention is not limited to this. For example, as shown in FIG. 14, - The p-type epitaxial growth layers (3, 4, 6) are grown on the p-type semiconductor substrate 1a and n-type epitaxial growth layers (3, 4, 6). - The semiconductor substrate 1 may be made up of epitaxially grown layers (3, 4, 6). -The p-type epitaxial growth layer (3, 4, 6) is partitioned by a p-type ground potential region 2, p-type isolation regions 31, 32, and an n-type high-side circuit region 5, which are diffusion layers, to form a floating potential region 3 and voltage-resistant regions 4, 6. In addition, at the bottom of the high-side circuit region 5, i.e., between the p-type semiconductor substrate 1 and the high-side circuit region 5, there is an n-type semiconductor substrate 4 with a higher impurity concentration than the high-side circuit region 5. + The n-type buried layer 9 may be formed of a diffusion layer doped with an n-type impurity such as antimony (Sb), phosphorus (P), or arsenic (As).

[0079] As shown in FIG. 15, a p-type semiconductor substrate 1a is - The p-type epitaxial growth layer 1b is grown on the p-type semiconductor substrate 1a and the p-type epitaxial growth layer 1b. - The semiconductor substrate 1 may be formed of a p-type epitaxial growth layer 1b. - Type epitaxial growth layer 1 b An n-type diffusion layer may be formed in the p-type region to form the floating potential region 3, the voltage-resistant regions 4 and 6, and the high-side circuit region 5. - Type epitaxial growth layer 1 b A p-type diffusion layer may be formed in the p-type semiconductor substrate 1 to form the ground potential region 2 and the isolation regions 31 and 32. a Between the high-side circuit region 5 and the high-side circuit region 5, there is provided an n + A mold burying layer 9 may be provided.

[0080] Furthermore, in the semiconductor devices according to the first to sixth embodiments, the startup element 10 and the high-side circuit region 5 are formed on the same high-voltage semiconductor chip 1, but the present invention is not limited to the startup element 10 and the high-side circuit region 5. In other words, the present invention is applicable to the case where a plurality of structures that exhibit high-voltage behavior independent from each other are formed on the same high-voltage semiconductor chip.

[0081] Furthermore, the configurations disclosed in the first to sixth embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description. [Explanation of symbols]

[0082] 1...Semiconductor substrate (semiconductor chip) 1a...Semiconductor substrate 1b...Epitaxial growth layer 2...Ground potential area 3, 3a, 3b...Floating potential region (floating potential region) 4,6...Voltage range 5...High-side circuit area (well area) 7a, 7b...Level shift elements 8...Protection element area 9...Buried layer 10...Starting element 12...VH pad 13...SMD pad 14...LS_S pad 15...LS_R pad 16...GND pad 17...VB Pad 18...HO pad 19...VS Pad 20~29...Metal wiring 21a, 22a...protruding parts 30...Gate area 31~33…Separation area 31a, 31b, 32a, 32b...End side separation part 34...Contact area 35...Carrier supply region (source region) 36...Carrier receiving region (drain region) 37, 38...Anti-reversal area 39…Contact area 40...Insulating film 50...Gate electrode 51,52…separation area 51a, 52a…Central side separation part 61~65...Beer 100...Starting element 101...High-side circuit 102...VH terminal 103...SMD terminal 104…LS_S terminal 105…LS_R terminal 106...GND terminal 107...VB terminal 108…HO terminal 109…VS terminal 201...Semiconductor chip 202...Ground potential area 203...Metal wiring 205...High-side circuit area 207a, 207b...Level shift elements 210...Starting element 212...VH pad 213...SMD pad 214...LS_S pad 215...LS_R pad 216...GND pad 217...VB Pad 218...HO pad 219…VS Pad 220~229...Metal wiring D1 to D5: Protection diodes R1~R5...Resistors T1, T2...Level shift elements

Claims

1. a semiconductor substrate; a first region of a first conductivity type selectively provided on an upper portion of the semiconductor substrate; a second region of a second conductivity type provided in contact with the first region on an upper portion of the semiconductor substrate; a third region of the second conductivity type provided on the semiconductor substrate and spaced apart from the second region; a fourth region of the second conductivity type provided between the second region and the third region on the upper portion of the semiconductor substrate; a first isolation region provided between the second region and the fourth region; a second isolation region provided between the third region and the fourth region; a sixth region of the second conductivity type having a lower impurity concentration than the third region, the sixth region being provided in an upper portion of the semiconductor substrate so as to be in contact with the third region and surround at least a portion of the periphery of the third region; Equipped with A semiconductor device characterized in that, in a planar view, the upper and lower ends of the second region and the sixth region are aligned in a direction perpendicular to the direction in which the first isolation region and the second isolation region sandwich the fourth region.

2. 2. The semiconductor device according to claim 1, wherein each of the first and second isolation regions is a diffusion layer of a first conductivity type.

3. 3. The semiconductor device according to claim 2, further comprising an inversion prevention layer of the first conductivity type provided above each of the first and second isolation regions and having a higher impurity concentration than the first and second isolation regions.

4. A semiconductor substrate; a first region of a first conductivity type selectively provided on an upper portion of the semiconductor substrate; a second region of a second conductivity type provided in contact with the first region on an upper portion of the semiconductor substrate; a third region of the second conductivity type provided on the semiconductor substrate and spaced apart from the second region; a fourth region of the second conductivity type provided between the second region and the third region on the upper portion of the semiconductor substrate; a first isolation region provided between the second region and the fourth region; a second isolation region provided between the third region and the fourth region; Equipped with 10. A semiconductor device, wherein each of the first and second isolation regions is a trench.

5. A semiconductor substrate; a first region of a first conductivity type selectively provided on an upper portion of the semiconductor substrate; a second region of a second conductivity type provided in contact with the first region on an upper portion of the semiconductor substrate; a third region of the second conductivity type provided on the semiconductor substrate and spaced apart from the second region; a fourth region of the second conductivity type provided between the second region and the third region on the upper portion of the semiconductor substrate; a first isolation region provided between the second region and the fourth region; a second isolation region provided between the third region and the fourth region; Equipped with a portion of each of the first and second isolation regions is formed by a portion of a diffusion layer of a first conductivity type; Another portion of each of the first and second isolation regions is formed as a trench. The semiconductor device according to claim 1,

6. 6. The semiconductor device according to claim 1, wherein the width of the fourth region is 50 μm or more.

7. a first wiring electrically connected to the second region and to which a first potential is applied; a second wiring electrically connected to the third region and to which a second potential different from the first potential is applied; Further provided with The fourth region is a region having a floating potential.

7. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer.

8. A semiconductor substrate; a first region of a first conductivity type selectively provided on an upper portion of the semiconductor substrate; a second region of a second conductivity type provided in contact with the first region on an upper portion of the semiconductor substrate; a third region of the second conductivity type provided on the semiconductor substrate and spaced apart from the second region; a fourth region of the second conductivity type provided between the second region and the third region on the upper portion of the semiconductor substrate; a first isolation region provided between the second region and the fourth region; a second isolation region provided between the third region and the fourth region; a first wiring electrically connected to the second region and to which a first potential is applied; a second wiring electrically connected to the third region and to which a second potential different from the first potential is applied; Equipped with the fourth region is a region having a floating potential, the first wiring has a first protruding portion that protrudes from the first isolation region side to above the fourth region, The second wiring has a second extension portion that extends from the second isolation region side to above the fourth region. A semiconductor device characterized by:

9. a fifth region of the second conductivity type provided between the fourth region and the first isolation region on the upper portion of the semiconductor substrate; a third isolation region provided between the fourth region and the fifth region; 9. The semiconductor device according to claim 1, further comprising:

10. 10. The semiconductor device according to claim 9, wherein the third isolation region has a structure different from that of the first isolation region and the second isolation region.

11. A semiconductor substrate; a first region of a first conductivity type selectively provided on an upper portion of the semiconductor substrate; a second region of a second conductivity type provided in contact with the first region on an upper portion of the semiconductor substrate; a third region of the second conductivity type provided on the semiconductor substrate and spaced apart from the second region; a fourth region of the second conductivity type provided between the second region and the third region on the upper portion of the semiconductor substrate; a first isolation region provided between the second region and the fourth region; a second isolation region provided between the third region and the fourth region; Equipped with A semiconductor device according to claim 1, characterized in that the first and second isolation regions each have a linear planar shape extending parallel to each other, and both longitudinal ends of the planar shapes of the first and second isolation regions are in contact with the first region.

12. A semiconductor device described in any one of claims 1 to 3, characterized in that the sixth region is arranged in contact with the third region and surrounding the third region, at least except between the second isolation region and the third region.

13. a seventh region of the second conductivity type provided above the second region and having a higher impurity concentration than the second region; an eighth region of the second conductivity type provided above the second region and spaced apart from the seventh region, the eighth region having a higher impurity concentration than the second region; 13. The semiconductor device according to claim 12, further comprising:

14. the third region is a region including an electrode pad connected to a low potential side terminal of a high potential side power switching element of two power switching elements connected in series, and in which a gate drive circuit is formed; the seventh region is a carrier supply region of the starting element; The eighth region is a carrier receiving region for the activation element and is provided between the seventh region and the first isolation region.

14. The semiconductor device according to claim 13.

15. A seventh region of a second conductivity type provided above the second region and having a higher impurity concentration than the second region; an eighth region of the second conductivity type provided above the second region and spaced apart from the seventh region, the eighth region having a higher impurity concentration than the second region; Further provided with the third region is a region including an electrode pad connected to a low potential side terminal of a high potential side power switching element of two power switching elements connected in series, and in which a gate drive circuit is formed; the seventh region is a carrier supply region of the starting element; the eighth region is a carrier receiving region for the activation element and is provided between the seventh region and the first isolation region; 8. The semiconductor device of claim 7, wherein the first potential is applied to the carrier-receiving region.

16. A seventh region of a second conductivity type provided above the second region and having a higher impurity concentration than the second region; an eighth region of the second conductivity type provided above the second region and spaced apart from the seventh region, the eighth region having a higher impurity concentration than the second region; Further provided with the third region is a region including an electrode pad connected to a low potential side terminal of a high potential side power switching element of two power switching elements connected in series, and in which a gate drive circuit is formed; the seventh region is a carrier supply region of the starting element; the eighth region is a carrier receiving region for the activation element and is provided between the seventh region and the first isolation region; The second potential is a potential of a power supply with the potential applied to the electrode pad as a reference potential.

8. The semiconductor device according to claim 7, wherein the semiconductor device is a semiconductor device having a first insulating layer.

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