AD conversion circuit

Abstract

To provide an AD converter circuit capable of keeping time differences in ADC conversion completion within a desired range.SOLUTION: An AD converter circuit includes: a first and a second AD converters(ADC)200-1, 200-2; a CPU 206 for outputting conversion start request signals START_CH1, START_CPU to the ADC200-1, 200-2, respectively; and a control part 209 for transmitting the conversion start request signal START_CPU to the ADC200-2 in a normal mode, and for halting the transmission of the conversion start request signal START_CPU to the ADC200-2 and outputting a conversion start request signal START_ST to the ADC200-2 at the timing the ADC200-1 and 200-2 synchronizes in a synchronization mode in which the ADC200-1 and 200-2 are synchronized.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an AD conversion circuit. [Background technology]

[0002] Pressure transmitters are equipped with various sensors, such as a differential pressure (DP) sensor, a high-pressure static pressure (STH) sensor, a low-pressure static pressure (STL) sensor, and a temperature (TEMP) sensor, and calculate the measured value (PV) of gauge pressure / absolute pressure by calculating the AD converted values ​​of these sensor outputs. For the DP signal required for this calculation, a dedicated AD converter (ADC: Analog-to-Digital Converter) must be provided for DP, and AD conversion must be performed continuously to avoid the effects of aliasing during sampling. On the other hand, as continuous sampling is not required for the remaining STH, STL, and TEMP signals, a separate ADC is provided, and AD conversion is performed while switching between the three inputs of STH, STL, and TEMP, resulting in a system configuration using a total of two ADC channels.

[0003] For products that require reliability, such as pressure transmitters, in addition to measuring DP to calculate the PV value, it is also necessary to measure STH, STL, and TEMP for correction, and to measure to detect sensor and ADC failures during operation.As such, as shown above, a two-channel ADC is prepared, with DP measured using the ADC on channel 1, and the ADC on channel 2 used to measure STH, STL, and TEMP for correction, as well as DP for sensor failure diagnosis (inter-channel synchronization not required), and DP for ADC failure diagnosis (inter-channel synchronization required).

[0004] To correctly diagnose an ADC failure, it is necessary to measure DP using channel 2 with the same ADC settings as channel 1 and at approximately the same timing as channel 1. If the DP acquisition cycle of the ADC on channel 1 is, for example, 50 ms, then the ADC on channel 2 is required to acquire DP values ​​at a timing within a ±2% range of that (±1 ms). If this time constraint is not observed, fluctuations in the DP value may result in a false determination that the ADC is faulty, even though it is not.

[0005] As mentioned above, constant sampling is essential for the ADC on channel 1 to avoid the effects of aliasing. Therefore, in order to synchronously acquire the ADC values ​​on channels 1 and 2, two commercially available ADC chips (such as TI's ADS1248 or Analog Devices' AD7176-2) with input terminals that can externally specify an ADC conversion start request are used.

[0006] Each chip is designated as channel 1 and channel 2, and when obtaining the DP value (DP SYNC) for ADC diagnosis on channel 2, the CPU (Central Processing Unit) checks the conversion completion interrupt signal on channel 1 and generates a conversion start request signal on channel 2.

[0007] Fig. 8 is a block diagram showing the configuration of a conventional AD conversion circuit, and Fig. 9 and Fig. 10 are timing charts explaining the operation of the AD conversion circuit. Fig. 10 shows the timing after time ts in Fig. 9. In the examples of Fig. 8 to Fig. 10, the measurement value acquisition period of ADC 100-1 on channel 1 is set to 50 ms, and the measurement value acquisition period of ADC 100-2 on channel 2 is set to 180 ms.

[0008] The CPU 102 receives a timer interrupt signal INT_TIM_CH1 with a 50 ms cycle for channel 1 and a timer interrupt signal INT_TIM_CH2 with a 180 ms cycle for channel 2 from the timers 103 and 104. In response to the timer interrupt signal INT_TIM_CH1, the CPU 102 outputs a conversion start request signal START_CH1 to the ADC 100-1 of channel 1.

[0009] The ADC 100-1 of channel 1 receives the DP signal from the DP sensor in synchronization with the conversion start request signal START_CH1, performs AD conversion, and outputs a conversion completion interrupt signal INT_CH1 when the conversion is complete. ADC_CH1 in Figures 9 and 10 shows the output of the ADC 100-1 of channel 1.

[0010] Furthermore, the CPU 102 outputs a conversion start request signal START_CH2 to the ADC 100-2 of channel 2 in response to the timer interrupt signal INT_TIM_CH2. The ADC100-2 of channel 2 synchronizes with the conversion start request signal START_CH2, sequentially takes in the STH, STL, TEMP, DP, and DP SYNC signals from the STH sensor, STL sensor, TEMP sensor, and DP sensor, performs AD conversion, and outputs a conversion completion interrupt signal INT_CH2 when the conversion is complete.

[0011] In order to switch between the STH, STL, TEMP, DP, and DP SYNC signals, the output of the multiplexer 101 is switched every 180 ms. ADC_CH2 in FIGS. 9 and 10 indicates the output of the ADC 100-2 on channel 2.

[0012] As mentioned above, the DP signal is measured twice: once for the sensor fault diagnosis (no inter-channel synchronization required) and once for the ADC fault diagnosis (inter-channel synchronization required). In Figures 8 to 10, the DP value acquired for the ADC fault diagnosis is referred to as DP SYNC.

[0013] When acquiring DP SYNC, the CPU 102 must check the conversion completion interrupt signal INT_CH1 of channel 1 and output a conversion start request signal START_CH2 of channel 2, thereby aligning the timing of acquiring DP SYNC with the timing of acquiring DP of channel 1.

[0014] However, pressure transmitters have strict requirements for current consumption, and considering that the CPU needs to operate at a frequency of 1 MHz or less, it was difficult to keep the time difference between the conversion completion timing of channels 1 and 2 within ±2% (±1 ms) using low-speed CPU processing.

[0015] The inventor also proposed a multi-channel ADC capable of AD conversion of multiple channels at different cycles (see Patent Document 1). The multi-channel ADC disclosed in Patent Document 1 also allows synchronization between channels, but is restricted in that the output cycle of each channel must be an integer multiple of the shortest cycle. [Prior art documents] [Patent documents]

[0016] [Patent Document 1] Japanese Patent Application Publication No. 2018-156220 Summary of the Invention [Problem to be solved by the invention]

[0017] The present invention has been made to solve the above-mentioned problems, and aims to provide an AD conversion circuit that can keep the time difference between the conversion completion timings of a first AD converter and a second AD converter within a desired range. [Means for solving the problem]

[0018] The AD conversion circuit of the present invention includes a first AD converter configured to convert a first analog input signal into a digital signal, a second AD converter configured to convert a second analog input signal, which may be the same as or different from the first analog input signal, into a digital signal, a CPU configured to output first and second conversion start request signals to the first and second AD converters, respectively, a control unit configured to transmit the second conversion start request signal to the second AD converter in a normal mode in which synchronization of the first and second AD converters is not necessary, and to stop transmission of the second conversion start request signal to the second AD converter and output a third conversion start request signal to the second AD converter at a timing when the first and second AD converters are synchronized, in a synchronous mode in which the first and second AD converters are synchronized, and a control unit configured to selectively output one of a plurality of second analog input signals to the second AD converter. 1 and a multiplexer of the second analog input signal, wherein the CPU outputs a first control signal for specifying either the normal mode or the synchronous mode in synchronization with the second conversion start request signal, and selects one of the plurality of second analog input signals in synchronization with the second conversion start request signal. 1 and outputs a second control signal to the multiplexer, and the control unit operates in a mode designated by the first control signal. In addition, in one configuration example of the AD conversion circuit of the present invention, the control unit is characterized in that, in the synchronous mode, after the second conversion start request signal is output from the CPU and the conversion by the first AD converter is completed, the control unit outputs the third conversion start request signal to the second AD converter so that the next conversion by the first AD converter and the conversion by the second AD converter are synchronized. In one configuration example of the AD conversion circuit of the present invention, the control unit includes a signal generation unit configured to generate the third conversion start request signal, and a second AD converter configured to output the second conversion start request signal to the second AD converter in the normal mode and to output the third conversion start request signal to the second AD converter in the synchronous mode.2 and a multiplexer.

[0019] Also In one configuration example of the AD conversion circuit of the present invention, the CPU outputs the second control signal that sequentially specifies the plurality of second analog input signals, and switches to synchronous mode when it is the turn for the first and second AD converters to synchronously capture the same analog input signal.

[0021] In one configuration example of the AD conversion circuit of the present invention, the CPU periodically outputs the first conversion start request signal to the first AD converter. In addition, in one configuration example of the AD conversion circuit of the present invention, the CPU is characterized in that it periodically outputs the second conversion start request signal at a second period longer than a first period for outputting the first conversion start request signal. In addition, in one configuration example of the AD conversion circuit of the present invention, the CPU always sets the first conversion start request signal to a significant value and periodically outputs the second conversion start request signal, and the first AD converter outputs the conversion result at a pre-specified output data rate. [Effects of the Invention]

[0022] According to the present invention, by providing a control unit that transmits a second conversion start request signal to the second AD converter in the normal mode, and stops transmission of the second conversion start request signal to the second AD converter in the synchronous mode in which the first and second AD converters are synchronized, and outputs a third conversion start request signal to the second AD converter at the timing when the first and second AD converters are synchronized, it is possible to keep the time difference between the conversion completion timings of the first AD converter and the second AD converter within a desired range even when a low-speed CPU is used.Furthermore, the present invention can eliminate restrictions on the output period between channels.

[0023] Furthermore, in the present invention, the control unit operates autonomously in either the normal mode or the synchronous mode in synchronization with the second conversion start request signal, thereby reducing the load on the CPU.

[0024] Furthermore, in the present invention, the CPU always sets the first conversion start request signal to a significant value, thereby reducing the load on the CPU. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a block diagram showing the configuration of an AD conversion circuit according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a timing chart illustrating the operation of the AD conversion circuit according to the first embodiment of the present invention. [Figure 3] FIG. 3 is a timing chart illustrating the operation of the AD conversion circuit according to the first embodiment of the present invention. [Figure 4] FIG. 4 is a block diagram showing the configuration of an AD conversion circuit according to a second embodiment of the present invention. [Figure 5] FIG. 5 is a timing chart illustrating the operation of the AD conversion circuit according to the second embodiment of the present invention. [Figure 6] FIG. 6 is a timing chart illustrating the operation of the AD conversion circuit according to the second embodiment of the present invention. [Figure 7] FIG. 7 is a block diagram showing the configuration of an AD conversion circuit according to a reference example of the present invention. [Figure 8] FIG. 8 is a block diagram showing the configuration of a conventional AD conversion circuit. [Figure 9] FIG. 9 is a timing chart illustrating the operation of a conventional AD conversion circuit. [Figure 10] FIG. 10 is a timing chart illustrating the operation of a conventional AD conversion circuit. DETAILED DESCRIPTION OF THE INVENTION

[0026] [First Example] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1 is a block diagram showing the configuration of an AD conversion circuit according to a first embodiment of the present invention. The AD conversion circuit of this embodiment includes an ADC 200-1 of channel 1 that converts a DP signal (first analog input signal) output from a DP sensor (not shown) into a digital signal, an ADC 200-2 of channel 2 that converts into a digital signal any one of the STH signal, STL signal, TEMP signal, and DP signal output from an STH sensor, STL sensor, TEMP sensor, and DP sensor (not shown), ... and a multiplexer 201 that selectively outputs any one of the STH signal, STL signal, TEMP signal, and DP signal to the ADC 200-2.

[0027] Furthermore, the AD conversion circuit is composed of an interface unit (SPI_IF) 202 for connection with the CPU, a signal generation unit (STATE_CTRL) 203 that generates a conversion start request signal that synchronizes ADC200-1 and ADC200-2, a multiplexer 204 that selectively outputs either the conversion start request signal output from the CPU or the conversion start request signal output from STATE_CTRL 203 to ADC200-2, and an MCU (Micro Control Unit) 205.

[0028] The STATE_CTRL 203 and the multiplexer 204 constitute a control unit 209 . The MCU 205 includes a CPU 206 and timers 207 and 208. The CPU 206 executes the processing of this embodiment in accordance with a program stored in an internal memory.

[0029] 2 and 3 are timing charts illustrating the operation of the AD conversion circuit of this embodiment. Note that Fig. 3 shows the timing after time ts in Fig. 2. In this embodiment, SPI (Serial Peripheral Interface) is used as the serial bus connecting the ADCs 200-1 and 200-2 and the MCU 205. 2Other serial buses such as SPI or I / O may also be used. 2 Instead of C, the connection can be made using an internal bus such as the Advanced Microcontroller Bus Architecture (AMBA) defined by Arm.

[0030] In this embodiment, the measurement value acquisition period (first period) of the ADC 200-1 of channel 1 is set to 50 ms, and the measurement value acquisition period (second period) of the ADC 200-2 of channel 2 is set to 180 ms.

[0031] The timer 207 of the MCU 205 outputs a timer interrupt signal INT_TIM_CH1 for channel 1 with a period of 50 ms to the CPU 206. The timer 208 of the MCU 205 outputs a timer interrupt signal INT_TIM_CH2 for channel 2 with a period of 180 ms to the CPU 206.

[0032] The CPU 206 outputs a conversion start request signal START_CH1 (first conversion start request signal) in response to the timer interrupt signal INT_TIM_CH1. The CPU 206 also outputs a conversion start request signal START_CPU (second conversion start request signal) in response to the timer interrupt signal INT_TIM_CH2.

[0033] The ADC 200-1 of channel 1 receives a DP signal from a DP sensor (not shown) in synchronization with the conversion start request signal START_CH1, performs AD conversion of the DP signal, and outputs a conversion completion interrupt signal INT_CH1 when the conversion is complete. ADC_CH1 in Figures 2 and 3 indicates the output of the ADC 200-1. This operation of the ADC 200-1 is the same as that of the conventional ADC.

[0034] In the conventional technology, the CPU issues a conversion start request signal to each of the ADCs of channel 1 and channel 2.

[0035] In contrast to this, in this embodiment, for the ADC 200-1 of channel 1, a conversion start request is made only from the CPU 206 as described above. On the other hand, for the ADC 200-2 of channel 2, there are provided a STATE_CTRL 203 that can issue a conversion start request signal to a party other than the CPU 206, and a multiplexer 204 that selects and outputs either the conversion start request signal START_ST (third conversion start request signal) output from the STATE_CTRL 203 or the conversion start request signal START_CPU output from the CPU 206.

[0036] When STATE_CTRL203 receives a conversion start request signal START_CPU from CPU206 while the multiplexer control signal START_SEL output from CPU206 via SPI_IF202 is "High", it monitors the conversion completion interrupt signal INT_CH1 of ADC200-1 on channel 1 and generates a conversion start request signal START_ST in synchronization with this interrupt.

[0037] The CPU 206 outputs a multiplexer control signal START_SEL (first control signal) and a multiplexer control signal MUX_SEL (second control signal) via the SPI_IF 202 so that the STH, STL, and DP signals are sequentially AD converted in synchronization with the timer interrupt signal INT_TIM_CH2 from the timer 208.

[0038] Specifically, in a mode in which one of the signals STH, STL, or DP (no inter-channel synchronization required) is taken in, i.e., in a normal mode in which the ADC 200-1 of channel 1 and the ADC 200-2 of channel 2 do not need to be synchronized, the CPU 206 sets the multiplexer control signal START_SEL to "Low" in synchronization with the conversion start request signal START_CPU, and outputs a multiplexer control signal MUX_SEL that specifies which of STH, STL, or DP to select.

[0039] At this time, the CPU 206 switches the designation by the multiplexer control signal MUX_SEL in the order of STH→STL→DP (inter-channel synchronization required)→DP (inter-channel synchronization not required)→STH→ . . . in synchronization with the conversion start request signal START_CPU.

[0040] When the multiplexer control signal START_SEL output from the CPU 206 via the SPI_IF 202 is "Low", the multiplexer 204 outputs the conversion start request signal START_CPU output from the CPU 206 as the conversion start request signal START_CH2.

[0041] The multiplexer 201 selects one of the signals STH, STL, and DP in response to a multiplexer control signal MUX_SEL output from the CPU 206 via the SPI_IF 202, and outputs the selected signal to the ADC 200-2.

[0042] The ADC 200-2 receives one of the STH, STL, and DP signals via the multiplexer 201 in synchronization with the conversion start request signal START_CH2 output from the multiplexer 204, performs AD conversion on the signal, and outputs a conversion completion interrupt signal INT_CH2 when the conversion is complete. ADC_CH2 in Figures 2 and 3 indicates the output of the ADC 200-2. Note that, for simplicity, Figure 2 only shows an example of receiving an STL signal.

[0043] For the ADC 200-2 of channel 2, the input is switched by the multiplexer 201, so it is necessary to reset the internal digital filter and register of the ADC 200-2 before capturing the signal. Therefore, the STATE_CTRL 203 sets the reset signal RST_CH2 to "High" in response to the conversion start request signal START_CPU output from the CPU 206. When the reset signal RST_CH2 becomes "High," the digital filter and registers inside the ADC 200-2 are reset. When the reset signal RST_CH2 becomes "Low," the ADC 200-2 is released from the reset mode and becomes able to convert data.

[0044] The ADC 200-1 of channel 1 does not have a multiplexer in the previous stage and always converts DP signals, so STATE_CTRL 203 only needs to set the reset signal RST_CH1 to "High" at the initial startup.

[0045] Next, as shown in Figure 3, in the mode for incorporating DP SYNC, i.e., in the sync mode in which ADC200-1 of channel 1 and ADC200-2 of channel 2 need to be synchronized, the CPU206 sets the multiplexer control signal START_SEL to "High" in synchronization with the conversion start request signal START_CPU, and outputs the multiplexer control signal MUX_SEL that specifies DP as the selection target.

[0046] As will be described later, when a conversion start request signal START_ST is output from the STATE_CTRL 203, the CPU 206 returns the multiplexer control signal START_SEL from "High" to "Low."

[0047] When the multiplexer control signal START_SEL is "High", a conversion start request signal START_CPU is output from CPU 206, and after the reset time of ADC 200-2 has elapsed (when the reset signal RST_CH2 becomes "Low") and the conversion completion interrupt signal INT_CH1 of ADC 200-1 becomes "High", STATE_CTRL 203 generates a conversion start request signal START_ST so that the next conversion by ADC 200-1 and the conversion by ADC 200-2 are synchronized.

[0048] The STATE_CTRL 203 can detect through the SPI_IF 202 that the multiplexer control signal START_SEL has become “High.” Furthermore, the time from when the conversion start request signal START_CH1 goes "High" until the conversion completion interrupt signal INT_CH1 goes "High" is known. In other words, the time required for the ADC 200-1 to perform AD conversion is known. Because the period of the conversion start request signal START_CH1 is a known value, the time from when the conversion completion interrupt signal INT_CH1 goes "High" until the next time the conversion start request signal START_CH1 goes "High" is also known. Therefore, when the multiplexer control signal START_SEL is "High," the STATE_CTRL 203 simply sets the conversion start request signal START_ST to "High" after a specified time has elapsed since the conversion completion interrupt signal INT_CH1 went "High."

[0049] When the multiplexer control signal START_SEL output from the CPU 206 via the SPI_IF 202 is "High," the multiplexer 204 outputs the conversion start request signal START_ST output from the STATE_CTRL 203 as the conversion start request signal START_CH2. This stops the transmission of the conversion start request signal START_CPU to the ADC 200-2, and the conversion start request signal START_ST is transmitted to the ADC 200-2.

[0050] The multiplexer 201 selects the DP signal in response to the multiplexer control signal MUX_SEL output from the CPU 206 via the SPI_IF 202, and outputs the selected signal to the ADC 200-2.

[0051] The ADC 200-2 receives the DP signal via the multiplexer 201 in synchronization with the conversion start request signal START_CH2 output from the multiplexer 204, performs AD conversion on the signal, and outputs a conversion completion interrupt signal INT_CH2 when the conversion is completed.

[0052] By the above operation, in this embodiment, the signals are acquired in the order of STH → STL → DP SYNC → DP → STH → . . . and are AD converted. The length of the period during which the multiplexer control signal MUX_SEL specifies STH and STL is 180 ms (the period of INT_TIM_CH2 and START_CPU). On the other hand, since the DP signal needs to be captured twice in succession, the length of the period during which the multiplexer control signal MUX_SEL specifies DP is 2 x 180 ms, as can be seen from Figure 3.

[0053] In this embodiment, as shown by the timing of dashed line 210 in Fig. 3, the conversion completion timings of ADC 200-1 and ADC 200-2 can be synchronized in synchronous mode, and the time difference between the conversion completion timings of ADC 200-1 and ADC 200-2 can be kept within a desired range (for example, ±1 ms) even when using a low-speed CPU 206. Furthermore, in this embodiment, it is possible to eliminate the constraints on the output period between channels that are imposed by the multi-channel ADC disclosed in Patent Document 1.

[0054] Furthermore, commercially available ADC chips (for example, TI's ADS1248) require a certain amount of time to reset (32 cycles of a 32 kHz clock in the case of the ADS1248). Therefore, if a conversion start request signal START_CH2 is generated after detecting the conversion completion interrupt signal INT_CH1 for channel 1 in a configuration like the conventional technology, conversion for channel 2 will start after the reset time has elapsed, resulting in a difference in the conversion completion timing between channel 1 and channel 2 by the reset time.

[0055] On the other hand, in this embodiment, after receiving the conversion start request signal START_CPU from the CPU 206, STATE_CTRL 203 detects the rising edge of the conversion completion interrupt signal INT_CH1 of channel 1 after the reset time has elapsed and generates the conversion start request signal START_ST of channel 2, so there is no delay in conversion completion between channel 1 and channel 2 due to the reset time.

[0056] [Second Example] Next, a second embodiment of the present invention will be described. Fig. 4 is a block diagram showing the configuration of an AD conversion circuit according to the second embodiment of the present invention. The AD conversion circuit of this embodiment is composed of an ADC 200-1 for channel 1, an ADC 200-2 for channel 2, a multiplexer 201, an SPI_IF 202, a STATE_CTRL 203, a multiplexer 204, and an MCU 205a.

[0057] The MCU 205a includes a CPU 206a and a timer 208. The CPU 206a executes the processing of this embodiment in accordance with a program stored in an internal memory.

[0058] 5 and 6 are timing charts illustrating the operation of the AD conversion circuit of this embodiment. Note that Fig. 6 shows the timing after time ts in Fig. 5. In the first embodiment, every time conversion is performed by the ADC 200-1 of channel 1, the CPU 206 outputs a conversion start request signal START_CH1, and the ADC 200-1 performs AD conversion of the DP signal.

[0059] On the other hand, the CPU 206a of this embodiment, as shown in FIGS. 5 and 6, always keeps the conversion start request signal START_CH1 at a significant value "High." Therefore, the ADC 200-1 continues to output the AD conversion result of the DP signal at a predetermined output data rate. In this case, the ADC 200-1 is set in advance to continuously output the AD conversion result at a desired data rate (50 ms in this embodiment), and the conversion start request signal START_CH1 is set to "High."

[0060] As explained in the first embodiment, STATE_CTRL203 sets the reset signal RST_CH1 to "High" at the initial startup, so when the reset signal RST_CH1 returns to "Low", ADC200-1 is released from reset mode and outputs the AD conversion result of the DP signal at the specified output data rate.

[0061] In this embodiment, since the conversion start request signal START_CH1 is always set to "High", it is not necessary to supply the timer interrupt signal INT_TIM_CH1 to the CPU 206a, so the timer 207 is not required and only the timer 208 is required. The operation of the CPU 206a other than the output process of the conversion start request signal START_CH1 is the same as that of the CPU 206 of the first embodiment. Furthermore, the operation of the components other than the CPU 206a and the ADC 200-1 is the same as that of the first embodiment.

[0062] In this way, this embodiment can achieve the same effects as in Embodiment 1. Furthermore, in this embodiment, the CPU 206a does not need to receive the timer interrupt signal INT_TIM_CH1, so the load on the CPU 206a can be reduced.

[0063] [ Reference example ] Next, the present invention Reference example FIG. 7 shows the structure of the present invention. Reference example FIG. 1 is a block diagram showing the configuration of an AD conversion circuit according to the present invention. Reference example The AD conversion circuit is composed of an ADC 200-1 for channel 1, an ADC 200-2 for channel 2, a multiplexer 201, an SPI_IF 202, a STATE_CTRL 203b, a multiplexer 204, and an MCU 205b.

[0064] The STATE_CTRL 203b and the multiplexer 204 constitute a control unit 209b. The MCU 205b includes a CPU 206b and a timer 208. The CPU 206b executes the main program according to a program stored in an internal memory. Reference example Execute the process.

[0065] In the first and second embodiments, the multiplexer control signals START_SEL and MUX_SEL are output from the CPU 206 and 206a via the SPI_IF 202. In response to this, Reference exampleIn this case, instead of the CPUs 206 and 206a, the STATE_CTRL 203b outputs the multiplexer control signals START_SEL and MUX_SEL.

[0066] As in the second embodiment, the CPU 206b keeps the conversion start request signal START_CH1 at "High" all the time, and outputs the conversion start request signal START_CPU in response to the timer interrupt signal INT_TIM_CH2 from the timer 208.

[0067] The STATE_CTRL 203b outputs multiplexer control signals START_SEL and MUX_SEL so that the signals STH, STL, and DP are sequentially AD converted in synchronization with a conversion start request signal START_CPU from the CPU 206b.

[0068] Specifically, in the normal mode, the STATE_CTRL 203b sets the multiplexer control signal START_SEL to "Low" in synchronization with the conversion start request signal START_CPU, and outputs a multiplexer control signal MUX_SEL that specifies the selection target from STH, STL, or DP. At this time, the STATE_CTRL 203b switches the specification by the multiplexer control signal MUX_SEL in the order of STH → STL → DP (inter-channel synchronization required) → DP (inter-channel synchronization not required) → STH → ... in synchronization with the conversion start request signal START_CPU.

[0069] Next, in the synchronous mode, the STATE_CTRL 203b sets the multiplexer control signal START_SEL to "High" in synchronization with the conversion start request signal START_CPU, and outputs the multiplexer control signal MUX_SEL that designates the DP as the selection target.

[0070] In the first and second embodiments, when it is the turn to capture the DP SYNC, the CPU 206, 206a sets the multiplexer control signal START_SEL to "High" as it is in the synchronous mode. Reference exampleThen, when it is the turn to capture DP SYNC, the STATE_CTRL 203b sets the multiplexer control signal START_SEL to "High" as it is in synchronous mode.

[0071] The operation of the STATE_CTRL 203b other than the output process of the multiplexer control signals START_SEL and MUX_SEL is the same as that of the STATE_CTRL 203 in the first and second embodiments. As described above, the CPU 206b does not output the multiplexer control signals START_SEL and MUX_SEL, but other operations are the same as those of the CPU 206a in the second embodiment. Furthermore, the operations of the components other than the STATE_CTRL 203b and the CPU 206b are the same as those in the second embodiment.

[0072] Thus, the book Reference example In this case, the same operation as that shown in the timing charts of Figures 5 and 6 can be realized. Reference example In this case, the load on the CPU 206b can be further reduced by performing hardware processing by the STATE_CTRL 203b to output the multiplexer control signals START_SEL and MUX_SEL, rather than software processing by the CPU.

[0073] Book Reference example In this embodiment, as in the second embodiment, the CPU 206b constantly keeps the conversion start request signal START_CH1 at "High," but as in the first embodiment, the conversion start request signal START_CH1 may be output in response to the timer interrupt signal INT_TIM_CH1. That is, the CPU 206b does not output the multiplexer control signals START_SEL and MUX_SEL, but other operations may be the same as those of the CPU 206 in the first embodiment. In this case, it goes without saying that the timer 207 is required.

[0074] No. 1 , Second Example and Reference ExampleIn the example above, the signals are acquired in the order STH → STL → DP SYNC → DP → STH → ... and then AD converted. However, as with the conventional technology, TEMP may be added as a selection target for channel 2 in normal mode. Also, if there are other signals other than STH, STL, TEMP, DP, and DP SYNC that you want to acquire on channel 2, you can add them as appropriate. Conversely, it is also possible to reduce the number of signals that do not need to be acquired. For example, in this Reference example Here, we are acquiring two static pressure sensor signals, STH and STL, but it is fine to use just one.

[0075] Also, the first , Second Example and Reference Example Although the description does not cover the processing of the AD conversion results output from the ADCs 200-1 and 200-2, in the present invention, a means for processing the AD conversion results is not an essential component, and the AD conversion results may be transferred to the CPUs 206, 206a, and 206b via the SPI_IF 202, for example. At this time, an individual ID may be added to the AD conversion results before transfer. This processing is disclosed in Patent Document 1. It goes without saying that the means for processing the AD conversion results is not limited to the configuration disclosed in Patent Document 1.

[0076] Furthermore, the application of the present invention is not limited to pressure transmitters, but can also be applied to devices other than pressure transmitters. [Industrial Applicability]

[0077] The present invention can be applied to a technique for AD conversion of analog input signals of multiple channels. [Explanation of symbols]

[0078] 200-1, 200-2...ADC, 201, 204...multiplexer, 202...interface unit, 203, 203b...signal generation unit, 205, 205a, 205b...MCU, 206, 206a, 206b...CPU, 207, 208...timer, 209, 209b...control unit.

Claims

1. a first analog-to-digital converter configured to convert a first analog input signal into a digital signal; a second analog-to-digital converter configured to convert a second analog input signal, which may be the same as or different from the first analog input signal, into a digital signal; a CPU configured to output first and second conversion start request signals to the first and second AD converters, respectively; a control unit configured to transmit the second conversion start request signal to the second AD converter in a normal mode in which synchronization of the first and second AD converters is not required, and to stop transmission of the second conversion start request signal to the second AD converter in a synchronous mode in which the first and second AD converters are synchronized, and to output a third conversion start request signal to the second AD converter at a timing when the first and second AD converters are synchronized; a first multiplexer configured to selectively output any one of the plurality of second analog input signals to the second AD converter; the CPU outputs a first control signal for specifying either the normal mode or the synchronous mode in synchronization with the second conversion start request signal, and outputs a second control signal for specifying selection of one of the plurality of second analog input signals to the first multiplexer in synchronization with the second conversion start request signal; The AD conversion circuit is characterized in that the control unit operates in a mode designated by the first control signal.

2. 2. The AD conversion circuit according to claim 1, an AD conversion circuit characterized in that, in the synchronous mode, after the second conversion start request signal is output from the CPU and conversion by the first AD converter is completed, the control unit outputs the third conversion start request signal to the second AD converter so that the next conversion by the first AD converter and the conversion by the second AD converter are synchronized.

3. 3. The AD conversion circuit according to claim 1, The control unit a signal generator configured to generate the third conversion start request signal; a second multiplexer configured to output the second conversion start request signal to the second AD converter in the normal mode, and to output the third conversion start request signal to the second AD converter in the synchronous mode.

4. 2. The AD conversion circuit according to claim 1, The AD conversion circuit is characterized in that the CPU outputs the second control signal that sequentially specifies the plurality of second analog input signals, and switches to a synchronous mode when it is the turn for the first and second AD converters to synchronously capture the same analog input signal.

5. 5. The AD conversion circuit according to claim 1, The AD conversion circuit is characterized in that the CPU periodically outputs the first conversion start request signal to the first AD converter.

6. 6. The AD conversion circuit according to claim 5, The AD conversion circuit is characterized in that the CPU periodically outputs the second conversion start request signal at a second period longer than a first period for outputting the first conversion start request signal.

7. 5. The AD conversion circuit according to claim 1, the CPU always sets the first conversion start request signal to a significant value and periodically outputs the second conversion start request signal; The AD conversion circuit is characterized in that the first AD converter outputs a conversion result at a pre-specified output data rate.

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