Selective Silicide Deposition for 3D Drums

Abstract

A memory device having a metal silicide resulting in a low resistance contact is described. A method of forming the memory device is described. The method includes forming a metal silicide layer on a semiconductor material layer on a memory stack, the semiconductor material layer having a capacitor side and a bit line side. A capacitor is then formed on the capacitor side of the metal silicide layer and a bit line is formed on the bit line side of the metal silicide layer.

Description

[Technical Field]

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic devices and electronic device manufacturing. More particularly, embodiments of the present disclosure provide a three-dimensional (3D) dynamic random access memory cell. [Background technology]

[0002]

[0002] Electronic devices, such as personal computers, workstations, computer servers, mainframes, and other computer-related equipment such as printers, scanners, and hard disk drives, use memory devices that provide ample data storage capacity while consuming low power. There are two main types of random access memory cells suitable for use in electronic devices: dynamic and static. Dynamic random access memory (DRAM) can be programmed to store a voltage representing one of two binary values, but may require periodic reprogramming or "refreshing" to maintain this voltage for more than a very short period of time. Static random access memory (SRAM) is so named because it does not require periodic refreshing.

[0003] DRAM memory circuits are fabricated by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field-effect transistor (FET) and a capacitor.

[0004]

[0004] Fabricating a DRAM cell involves fabricating a transistor, a capacitor, and three contacts (one each for the bit line, word line, and reference voltage). DRAM manufacturing is a competitive business. There is a continuous push to reduce the size of individual cells and increase the density of memory cells, especially at densities above 256 megabits, so that more memory can be packed onto a single memory chip. Constraints on shrinking cell size include the path of both active and inactive word lines through the cell, the size of the cell capacitor, and the compatibility of array devices with non-array devices. Forming low-resistance contacts between the active area and the bottom electrode of a 3D DRAM is essential to device performance.

[0005]

[0005] Therefore, there is a need in the art for memory devices and methods of forming memory devices that have low resistance contacts. Summary of the Invention

[0006]

[0006] One or more embodiments of the present disclosure are directed to a method of forming a memory device. In one or more embodiments, the method of forming the memory device includes forming a metal silicide layer on a semiconductor material layer on a memory stack, the semiconductor material layer having a capacitor side and a bit line side, forming a capacitor on the capacitor side of the metal silicide layer, and forming a bit line on the bit line side of the metal silicide layer.

[0007]

[0007] Additional embodiments of the present disclosure are directed to methods of forming a memory device. In one or more embodiments, the method of forming the memory device includes forming a memory stack, the memory stack including a sacrificial layer and alternating layers of a first material layer, a second material layer, and a semiconductor material layer, forming active openings through the memory stack and recessing the first material layer through the active openings to form recessed regions, depositing a gate oxide layer on the second material layer, forming word lines in the recessed regions, the word lines including one or more of a barrier layer and a word line metal, depositing a fill material in the active openings, forming slit pattern openings through the memory stack, recessing the second material layer and the semiconductor material layer through the slit pattern openings to form capacitor openings, forming a metal silicide layer on the semiconductor material layer, forming a capacitor in the capacitor opening, forming a bit line opening in the fill material, and forming a bit line in the bit line opening.

[0008]

[0008] A further embodiment of the present disclosure, when executed by a controller of a processing chamber, includes directing the processing chamber to perform operations of forming a memory stack, the memory stack including a sacrificial layer and alternating layers of a first material layer, a second material layer, and a semiconductor material layer; forming an active opening through the memory stack and recessing the first material layer through the active opening to form a recessed region; depositing a gate oxide layer on the second material layer; and forming word lines in the recessed region, the word lines comprising a barrier layer and a word line metal pore. forming a word line, the word line including one or more of: depositing a fill material in the active opening; forming a slit pattern opening through the memory stack; forming a capacitor opening by recessing the second material layer and the semiconductor material layer through the slit pattern opening; forming a metal silicide layer on the semiconductor material layer; forming a capacitor in the capacitor opening; forming a bit line opening in the fill material; and forming a bit line in the bit line opening.

[0009]

[0009] Additional embodiments of the present disclosure are directed to a method of forming a semiconductor device. In one or more embodiments, the method includes forming a film stack on a substrate, the film stack including a plurality of alternating layers of semiconductor material and dielectric layers, patterning the film stack to form an opening, the opening extending from a top surface of the film stack to the substrate and having an aspect ratio of 10:1 or greater, recessing the semiconductor material layer through the opening to form a recessed semiconductor material layer, and selectively depositing a metal layer on the recessed semiconductor material layer.

[0010]

[0010] So that the features of the present disclosure described above can be understood in detail, a more particular description of the present disclosure briefly summarized above will be obtained by reference to embodiments, some of which are illustrated in the accompanying drawings. However, since the present disclosure may admit of other equally effective embodiments, it should be noted that the accompanying drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered as limiting the scope of the present disclosure. The embodiments described herein are illustrated by way of example and not limitation in the accompanying drawings, in which like reference numerals indicate similar elements. [Brief explanation of the drawings]

[0011] [Figure 1] 1 shows a process flow diagram of a method according to one or more embodiments. [Figure 2A]

[0012] 1 illustrates a cross-sectional view of a memory device according to one or more embodiments of the present disclosure. [Figure 2B]

[0013] 1 illustrates a cross-sectional view of a memory device according to one or more embodiments of the present disclosure. [Figure 2C]

[0014] 1 illustrates a cross-sectional view of a memory device according to one or more embodiments of the present disclosure. [Figure 2D]

[0015] 1 illustrates a cross-sectional view of a memory device according to one or more embodiments of the present disclosure. [Figure 2E]

[0016] 1 illustrates a cross-sectional view of a memory device according to one or more embodiments of the present disclosure. [Figure 2F]

[0017] 1 illustrates a cross-sectional view of a memory device according to one or more embodiments of the present disclosure. [Figure 2G]

[0018] 1 illustrates a cross-sectional view of a memory device according to one or more embodiments of the present disclosure. [Figure 2H]

[0019] 1 illustrates a cross-sectional view of a memory device according to one or more embodiments of the present disclosure. [Figure 2I]

[0020] 1 illustrates a cross-sectional view of a memory device according to one or more embodiments of the present disclosure. [Figure 2J]

[0021] 1 illustrates a cross-sectional view of a memory device according to one or more embodiments of the present disclosure. [Figure 2K]

[0022] 1 illustrates a cross-sectional view of a memory device according to one or more embodiments of the present disclosure. [Figure 2L]

[0023] 1 illustrates a cross-sectional view of a memory device according to one or more embodiments of the present disclosure. [Figure 2M]

[0024] 1 illustrates a cross-sectional view of a memory device according to one or more embodiments of the present disclosure. [Figure 2N]

[0025] 1 illustrates a cross-sectional view of a memory device according to one or more embodiments of the present disclosure. [Figure 2O]

[0026] 1 illustrates a cross-sectional view of a memory device according to one or more embodiments of the present disclosure. [Figure 2P]

[0027] 1 illustrates a cross-sectional view of a memory device according to one or more embodiments of the present disclosure. [Figure 2Q]

[0028] 1 illustrates a cross-sectional view of a memory device according to one or more embodiments of the present disclosure. [Figure 3]

[0029] 1 illustrates a cluster tool in accordance with one or more embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0030] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0013]

[0031] In the following description, numerous specific details (such as particular materials, chemical properties, and dimensions of elements) are presented to provide a thorough understanding of one or more embodiments of the present disclosure. However, it will be apparent to one skilled in the art that one or more embodiments of the present disclosure may be practiced without these specific details. In other instances, semiconductor manufacturing processes, techniques, materials, equipment, and the like have not been described in detail so as not to unnecessarily obscure the description. Using the description contained herein, one skilled in the art will be able to implement the appropriate functionality without undue experimentation.

[0014]

[0032] While certain exemplary embodiments of the present disclosure have been described and are shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and do not limit the present disclosure, and that the present disclosure is not limited to the specific constructions and arrangements shown and described, since variations may occur to those skilled in the art.

[0015]

[0033] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably and refer to any gas species capable of reacting with the substrate surface.

[0016]

[0034] According to one or more embodiments, the term "on," with respect to a film or layer of a film, includes a film or layer directly on a surface (e.g., a substrate surface) as well as one or more underlying layers between the film or layer and the surface (e.g., a substrate surface). Thus, in one or more embodiments, the phrase "on the substrate surface" is intended to include one or more underlying layers. In other embodiments, the phrase "directly" refers to a layer or film in contact with a surface (e.g., a substrate surface) without any intervening layers. Thus, "a layer directly on the substrate surface" refers to a layer in direct contact with the substrate surface with no intervening layers.

[0017]

[0035] As used herein, the term "dynamic random access memory" or "DRAM" refers to a memory cell that stores data bits by storing a packet of charge (i.e., a binary 1) or no charge (i.e., a binary 0) on a capacitor. The charge is gated onto the capacitor through an access transistor and sensed by turning on the same transistor and observing the voltage perturbation caused by dumping the charge packet onto the interconnect line at the transistor output. Thus, a single DRAM cell is made of one transistor and one capacitor. A DRAM device is formed from an array of DRAM cells.

[0018]

[0036] Traditionally, DRAM cells have recessed high work function metal structures in a buried word line structure. In DRAM devices, the word lines are formed in a polysilicon gate level at the surface of the substrate, while the bit lines are formed in a metal level located above the substrate. In buried word lines (bWL), the word lines are buried below the surface of the semiconductor substrate, using metal as the gate electrode.

[0019]

[0037] In one or more embodiments, a memory device having a metal silicide layer is provided, advantageously forming a low resistance contact for 3D DRAM. Forming high-quality silicide on the active area of ​​a 3D DRAM is challenging due to the lack of direct openings. Furthermore, deposition of the silicide is difficult. PVD is not an option due to the non-line-of-sight properties of the structure. On the other hand, CVD occupies a large amount of space, reducing the volume of the cavity and therefore the capacitance of the device. Accordingly, one or more embodiments provide a selective deposition method for forming a metal silicide.

[0020]

[0038] In one or more embodiments, metal deposition and other processes can be performed in an isolated environment (e.g., a cluster processing tool). Accordingly, some embodiments of the present disclosure provide an integrated tool system with associated process modules for performing the present methods.

[0021]

[0039] FIG. 1 illustrates a process flow diagram of method 10, which may include any or all of the illustrated processes. Furthermore, the order of the individual processes may be varied. Method 10 may begin with any of the listed processes without departing from this disclosure. Referring to FIG. 1 , in step 15, a memory stack is formed. In step 20, active openings are patterned in the memory stack. In step 25, a first material layer, such as a nitride layer, may be recessed through the active openings. In step 30, a gate oxide is deposited. In step 35, word line replacements are formed. In step 40, an oxide is deposited. In step 45, the memory stack is slit-patterned. In step 50, a capacitor opening is patterned. In step 55, a semiconductor material layer is recessed through the capacitor openings. In step 60, a metal silicide layer is deposited. In step 65, a capacitor is formed. In step 70, bit line openings are patterned. In step 75, bit lines are formed.

[0022]

[0040] 2A-2Q illustrate cross-sectional views of a memory device according to one or more embodiments.

[0023]

[0041] Referring to Figure 2A, an initial or starting mold of an electronic device 100 is formed in accordance with one or more embodiments of the present disclosure. In some embodiments, the electronic device 100 shown in Figure 2A is formed in layers on a bare substrate (not shown). In one or more embodiments, the electronic device of Figure 2A is comprised of a substrate 170, a first sacrificial layer 102, a second sacrificial layer 104, and a memory stack 106.

[0024]

[0042] The substrate 170 can be any suitable material known to those skilled in the art. As used herein and in the appended claims, the term "substrate" refers to a surface or portion of a surface upon which a process acts. Those skilled in the art will also understand that a reference to a substrate may also refer to only a portion of a substrate, unless the context clearly dictates otherwise. Furthermore, a reference to deposition on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed on its surface.

[0025]

[0043] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatments may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to performing film treatments directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film treatment steps may also be performed on underlying layers formed on the substrate, as described in more detail below. The term "substrate surface" is intended to include such underlying layers, as the context indicates. Thus, for example, if a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0026]

[0044] In one or more embodiments, a first sacrificial layer 102 is on a substrate 170, and a second sacrificial layer 104 is on the first sacrificial layer 102. The first sacrificial layer 102 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the first sacrificial layer 102 comprises an insulating layer. In one or more embodiments, the first sacrificial layer 102 comprises silicon nitride (SiN).

[0027]

[0045] The second sacrificial layer 104 may also be referred to as a semiconductor material layer or an active layer. As used herein, the terms "active layer" or "memory layer" refer to a layer of material in which a channel, bit line, word line, or capacitor can be formed. In one or more embodiments, the active layer includes one or more of silicon or doped silicon.

[0028]

[0046] The second sacrificial layer 104 can be formed by any suitable technique known to those skilled in the art and can be made from any suitable material. In some embodiments, the semiconductor material can be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the semiconductor material can be doped using any suitable process, such as an ion implantation process. As used herein, the term "n-type" refers to a semiconductor material layer formed by doping with an electron donor element during fabrication. The term n-type comes from the negative charge of electrons. In an n-type semiconductor material layer, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of wells (or holes). In contrast to n-type semiconductor materials, p-type semiconductor materials have a hole concentration that is greater than the electron concentration. In p-type semiconductor materials, holes are the majority carriers and electrons are the minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorous (P), arsenic (As), other semiconductor dopants, or combinations thereof. In some embodiments, the second sacrificial layer 104 comprises several different conductive or semiconductor materials.

[0029]

[0047] The first sacrificial layer 102 and the second sacrificial layer 104 may be formed on a substrate 170 and may be made of any suitable material. In some embodiments, one or more of the first sacrificial layer 102 and the second sacrificial layer 104 may be removed and replaced in a later process. In some embodiments, one or more of the first sacrificial layer 102 and the second sacrificial layer 104 are not removed and remain in the memory device 100. In this case, the term "sacrificial" has an expanded meaning to include permanent layers, which may be referred to as conductive layers. In one or more embodiments, one or more of the first sacrificial layer 102 and the second sacrificial layer 104 comprise a material that can be selectively removed relative to adjacent layers of the memory stack 106.

[0030]

[0048] The memory stack 106 in the illustrated embodiment includes a plurality of alternating first material layers 108, second material layers 110, first sacrificial layers 102, and second sacrificial layers 104. While the memory stack 106 shown in FIG. 2A has a single set of alternating first material layers 108, second material layers 110, first material layers 108, second material layers 110, first sacrificial layers 102, and second sacrificial layers 104, those skilled in the art will recognize that this is for illustrative purposes only. The memory stack 106 may have any number of alternating first material layers 108, second material layers 110, first sacrificial layers 102, and second sacrificial layers 104. For example, in some embodiments, the memory stack 106 includes 192 pairs of alternating first material layers 108, second material layers 110, first sacrificial layers 102, and second sacrificial layers 104. In other embodiments, the memory stack 106 includes more than 50 pairs of alternating first material layers 108, second material layers 110, first sacrificial layers 102, and second sacrificial layers 104, or more than 100 pairs of alternating first material layers 108, second material layers 110, first sacrificial layers 102, and second sacrificial layers 104, or more than 300 pairs of alternating first material layers 108, second material layers 110, first sacrificial layers 102, and second sacrificial layers 104.

[0031]

[0049] In one or more embodiments, sequential deposition is used to form multiple active area regions, and in one or more embodiments, films of alternating layers such as oxide-polysilicon, polysilicon-nitride, oxide-nitride, silicon-silicon germanium, etc. are deposited.

[0032]

[0050] In one or more embodiments, the first material layer 108 and the second material layer 110 independently comprise insulating materials. In one or more embodiments, the first material layer 108 comprises a nitride layer, and the second material layer 106 comprises an oxide layer. In some embodiments, the memory stack 106 comprises a non-displacement gate, such as alternating oxide and polysilicon (OP), oxide and metal, or oxide and sacrificial layers. The second layer 110 comprises a material that has etch selectivity with respect to the first layer 108, such that the second layer 110 can be removed without substantially affecting the first layer 108. In one or more embodiments, the first layer 108 comprises silicon nitride (SiN). In one or more embodiments, the second layer 110 comprises silicon oxide (SiOx). In one or more embodiments, the first layer 108 and the second layer 110 are deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0033]

[0051] The individual alternating layers may be formed to any suitable thickness. In some embodiments, the thickness of each second layer 110 is approximately equal. In one or more embodiments, each second layer 110 has a second layer thickness. In some embodiments, the thickness of each first layer 108 is approximately equal. When used in this sense, approximately equal thicknesses are within ±5% of each other. In some embodiments, a silicon layer (not shown) is formed between the second layer 110 and the first layer 108. The thickness of the silicon layer may be relatively thin compared to the thickness of either the second layer 110 or the first layer 108. In one or more embodiments, the first layer 108 has a thickness in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, first layer 108 has a thickness in the range of about 0.5 to about 40 nm. In one or more embodiments, second layer 110 has a thickness in the range of about 0.5 to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, second layer 110 has a thickness in the range of about 0.5 to about 40 nm.

[0034]

[0052] 2B, the device is patterned to form an active opening 210. In some embodiments, patterning the active opening 150 includes etching through the memory stack 106, the first sacrificial layer 102, the second sacrificial layer 104, and into the substrate 170. Referring to FIG. 2B, the active opening 210 has sidewalls that extend through the memory stack 106 and expose a surface of the second material layer 110 and a surface of the first material layer 108.

[0035]

[0053] The first sacrificial layer 102 and the second sacrificial layer 104 have exposed surfaces as sidewalls of an active opening 210. The active opening 210 extends a distance into the substrate 170 such that the sidewall surfaces and the bottom of the active opening 210 are formed within the substrate 170. The bottom of the active opening 210 can be formed at any point within the thickness of the substrate 170. In some embodiments, the active opening 210 extends into the substrate 170 a thickness in the range of about 10% to about 90%, or about 20% to about 80%, or about 30% to about 70%, or about 40% to about 60% of the thickness of the substrate 102. In some embodiments, the active opening 210 extends into the substrate 170 a distance of 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80% or more of the thickness of the substrate 170.

[0036]

[0054] 2C, the first sacrificial layer 102 and the first material layer 108, e.g., a nitride layer, are selectively recessed through the active openings 210 to form recessed regions 116. In one or more embodiments, the second material layer 110, e.g., a nitride layer, is recessed through the active openings 210 using reactive species formed via a remote plasma from a process gas including oxygen (O) and nitrogen trifluoride (NF). In other embodiments, the second material layer 110, e.g., a nitride layer, is recessed through the active openings 210 using hot phosphorus (HP).

[0037]

[0055] Referring to FIG. 2D , a gate oxide layer 114 is deposited on the second sacrificial layer 104 through the active opening 210. The gate oxide layer 114 may comprise any suitable material known to those skilled in the art. The gate oxide layer 114 may be deposited using one or more deposition techniques known to those skilled in the art. In one or more embodiments, the gate oxide layer 114 is deposited using one of a number of deposition techniques, including, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other deposition techniques known to those skilled in the art. In the illustrated embodiment, the gate oxide layer 114 is shown as a conformal layer having a uniform shape. However, those skilled in the art will recognize that this is for illustrative purposes only, and that the gate oxide layer 114 may be formed isotropically, such that the gate oxide layer 114 has a rounded appearance. In some embodiments, the gate oxide layer 114 is selectively deposited as a conformal layer on the surface of the second sacrificial layer 104. In some embodiments, the gate oxide layer 114 is formed by oxidation of a semiconductor surface.

[0038]

[0056] In one or more embodiments, the gate oxide layer 114 comprises silicon oxide (SiOx). While the term "silicon oxide" may be used to describe the gate oxide layer 114, those skilled in the art will recognize that the present disclosure is not limited to a particular stoichiometry. For example, the terms "silicon oxide" and "silicon dioxide" may both be used to describe a material having any suitable stoichiometric ratio of silicon atoms to oxygen atoms. The same is true for other materials listed in this disclosure, such as silicon nitride, silicon oxynitride, tungsten oxide, zirconium oxide, aluminum oxide, and hafnium oxide.

[0039]

[0057] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit layers of material on a substrate surface. A substrate, or a portion of a substrate, is separately exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay to allow each compound to deposit and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, different portions of the substrate surface, or materials on the substrate surface, are substantially simultaneously exposed to two or more reactive compounds such that any given point on the substrate is not simultaneously exposed to multiple reactive compounds. As used herein and in the appended claims, the term "substantially" used in this sense means that, as understood by those skilled in the art, small portions of a substrate may be simultaneously exposed to multiple reactive gases due to diffusion, and simultaneous exposure is not intentional.

[0040]

[0058] In one embodiment of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A, e.g., an aluminum precursor) is pulsed into the reaction zone followed by a first time delay. Then, a second precursor or compound B (e.g., an oxidizer) is pulsed into the reaction zone followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive compound or reaction by-products from the reaction zone. Alternatively, a purge gas can flow continuously throughout the deposition process, such that only the purge gas flows during the time delay between pulses of reactive compound. The reactive compounds are alternately pulsed until a desired film or film thickness is formed on the substrate surface. In either case, an ALD process pulsing compound A, purge gas, compound B, and purge gas is one cycle. A cycle can begin with either compound A or compound B and continue in each order until a film having a predetermined thickness is achieved.

[0041]

[0059] In a spatial ALD process embodiment, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are simultaneously supplied to a reaction zone but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas supply system so that any given point on the substrate is exposed to both the first reactive gas and the second reactive gas.

[0042]

[0060] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to either co-flow or overlap for the majority of the precursor exposure.

[0043]

[0061] Plasma-enhanced chemical vapor deposition (PECVD) is widely used to deposit thin films due to its cost-effectiveness and versatility in film properties. In a PECVD process, a hydrocarbon source, such as a gas-phase hydrocarbon or liquid-phase hydrocarbon vapor entrained in a carrier gas, is introduced into a PECVD chamber. A plasma-initiating gas, typically helium, is also introduced into the chamber. A plasma is then initiated in the chamber, generating excited CH radicals. The excited CH radicals chemically bond with the surface of a substrate placed in the chamber to form a desired film thereon. The embodiments described herein with respect to PECVD processes can be practiced using any suitable thin film deposition system. Any apparatus descriptions described herein are exemplary and should not be understood or interpreted as limiting the scope of the embodiments described herein.

[0044]

[0062] Referring to FIG. 2E, wordlines are formed. The wordlines include one or more of a barrier layer 116 and a wordline metal 118. The oxide layer 114 may include any suitable material known to those skilled in the art. The barrier layer 116 may include any suitable material known to those skilled in the art. In one or more embodiments, the barrier layer 116 includes one or more of titanium nitride (TiN), tantalum nitride (TaN), or the like. In one or more embodiments, the wordline metal 118 includes a bulk metal including one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). In one or more embodiments, the wordline metal 118 includes tungsten (W). In other embodiments, the wordline metal 184 includes ruthenium (Ru).

[0045]

[0063] 2F illustrates step 40 of method 10, in which active opening 210 is filled with filler material 120. Filler material 120 can be any suitable material known to those skilled in the art. In one or more embodiments, filler material 120 comprises one or more dielectric materials. As used herein, the term "dielectric material" refers to a layer of material that is an electrical insulator polarizable in an electric field. In one or more embodiments, the dielectric material comprises one or more of an oxide, a carbon-doped oxide, silicon oxide (SiO), porous silicon dioxide (SiO), silicon nitride (SiN), silicon oxide / silicon nitride, a carbide, an oxycarbide, a nitride, an oxynitride, an oxycarbonitride, a polymer, a phosphosilicate glass, a fluorosilicate glass (SiOF) glass, or an organosilicate glass (SiOCH).

[0046]

[0064] FIG. 2G illustrates step 45 of method 10 where the device is slit patterned to form slit pattern openings 122 extending from the top surface of memory stack 106 down to substrate 170 .

[0047]

[0065] 2H illustrates steps 50 and 55 of method 10, where capacitor openings 124 are formed and second sacrificial layer 104 and polysilicon layer 105 are recessed through slit pattern openings 122. This process is also referred to as a "pull back" process. In one or more embodiments, the process illustrated in FIG. 2H is a polysilicon pull back.

[0048]

[0066] 2I illustrates step 60 of method 10, in which a metal silicide layer 126 is formed in opening 124 on second sacrificial layer 104. Metal silicide layer 126 may be formed by any suitable technique known to those skilled in the art. In one or more embodiments, metal silicide layer 126 is selectively deposited onto polysilicon layer 105 through capacitor opening 124. For example, tungsten fluoride (WF) and hydrogen (H) may be used to selectively deposit tungsten (W) or tungsten silicide (WS) on silicon (Si) surfaces.

[0049]

[0067] In one or more embodiments, the metal silicide layer 126 includes a metal. The metal can be any suitable metal known to those skilled in the art. In one or more embodiments, the metal is selected from one or more of titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), iridium (Ir), and molybdenum (Mo). Thus, in one or more embodiments, the metal silicide layer 126 includes one or more of titanium silicide (TiSi), tantalum silicide (TaSi), tungsten silicide (WSi), ruthenium silicide (RuSi), iridium silicide (IrSi), and molybdenum silicide (MoSi).

[0050]

[0068] Without intending to be bound by theory, it is believed that the presence of the metal silicide layer 126 forms a low resistance contact, and in some embodiments, the metal silicide layer 126 may reduce the resistance by an amount ranging from 0.5 to 0.01 compared to a 3D DRAM device without the metal silicide layer.

[0051]

[0069] 2J-2N illustrate step 65 of method 10, in which capacitor 180 is formed. In FIG. 2J, opening 124 is widened prior to forming the capacitor, forming widened capacitor opening 128. Opening 124 can be widened by any suitable technique known to those skilled in the art. After opening 124 is widened to capacitor opening 128, capacitor 180 is formed therein, as shown in FIGS. 2K-2M. In some embodiments, capacitor opening 124 is widened by a percentage of the thickness of active region 105. In some embodiments, capacitor opening 124 is widened by an amount ranging from 10% to 80% of the thickness of active region 105. In some embodiments, capacitor opening 124 is widened by an amount ranging from 20% to 75%, or from 30% to 60%. In some embodiments, capacitor opening 124 is widened using a dilute HF (~1% HF in water) wet etch. In some embodiments, widening the capacitor opening increases the capacitor surface area by between 1% and 85%, or between 5% and 80%, or between 10% and 75%, or between 20% and 60%.

[0052]

[0070] 2K-2N show a capacitor 180 formed in a widened capacitor opening 128 adjacent to the recessed polysilicon layer 105. In some embodiments, the capacitor is formed by first depositing a bottom electrode 130 in the capacitor opening 128. The bottom electrode 130, also referred to as a bottom electrode or bottom contact, can be formed by any suitable technique known to those skilled in the art. In some embodiments, the bottom electrode 130 is a conformal film deposited by atomic layer deposition. In one or more embodiments, the bottom electrode 130 comprises a material selected from one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt), and metal nitrides of any of the foregoing metals. For example, in one or more embodiments, the bottom electrode 130 comprises a material selected from one or more of copper nitride, cobalt nitride, tungsten nitride, titanium nitride, molybdenum nitride, nickel nitride, ruthenium nitride, silver nitride, gold nitride, iridium nitride, tantalum nitride, or platinum nitride. In some embodiments, the capacitor comprises a bottom electrode, a capacitor dielectric, and a top electrode. In some embodiments, the capacitor comprises a bilayer, for example, a top electrode and a bilayer of titanium nitride plus silicon germanium.

[0053]

[0071] In some embodiments, forming the capacitor includes depositing one or more of a bottom electrode, a high-k dielectric layer, a top electrode, and a silicon germanium (SiGe) layer.

[0054]

[0072] Referring to FIG. 2L, a high-k dielectric 132 is deposited on the bottom electrode 130 in the capacitor opening 128. In some embodiments, the high-k dielectric 132 comprises hafnium oxide. In some embodiments, the high-k dielectric 132 is deposited as a conformal film by atomic layer deposition. Referring to FIG. 2M, a top electrode 134 is formed in the capacitor opening 128 in the high-k dielectric 132. The top electrode 134, also referred to as a top contact or top electrode, can be formed by any suitable technique known to those skilled in the art. In one or more embodiments, the top electrode 134 comprises a conductive material including one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt), and metal nitrides of any of the foregoing metals. For example, in one or more embodiments, bottom electrode 130 comprises a material selected from one or more of copper nitride, cobalt nitride, tungsten nitride, titanium nitride, molybdenum nitride, nickel nitride, ruthenium nitride, silver nitride, gold nitride, iridium nitride, tantalum nitride, or platinum nitride. In some embodiments, although not shown, a dielectric is deposited to fill any empty space remaining in capacitor opening 128 after formation of top electrode 130. The dielectric in some embodiments separates individual unit cells from adjacent unit cells, preventing shorting.

[0055]

[0073] In one or more embodiments, referring to FIG. 2N, the slit pattern openings 122 are filled with a silicon germanium (SiGe) layer 136 to form a capacitor 180 on the top electrode 130.

[0056]

[0074] 2O illustrates step 70 of method 10, in which bit line holes 138 (also referred to as bit line openings) are formed. In some embodiments, the electronic device is patterned to form a plurality of bit line holes 138. The bit line holes 138 may be formed by any suitable technique known to those skilled in the art. In some embodiments, the bit line holes 138 are formed by positioning a patterned hard mask and etching the dielectric 120 through the hard mask.

[0057]

[0075] 2P, in one or more embodiments, the second sacrificial layer 104 and the polysilicon layer 105 are doped, for example, by a gas-phase doping process. The gas-phase doping process forms a doped layer 140 on the outer edges of the polysilicon layer 105 and the second sacrificial layer 104. In some embodiments, the doping occurs during deposition of the polysilicon layer 105 material using a dopant source. For example, phosphorus-doped silica glass (PSG) or boron-phosphorus-doped glass (BPSG) is diffused into the material. In some embodiments, the doped layer 140 has a thickness (measured from the outer edge of the polysilicon layer 105 toward the bitline opening 138) in a range from about 1 nm to about 20 nm.

[0058]

[0076] 2Q illustrates step 75 of method 10, in which bitlines 142 are formed in bitline holes 138. In one or more embodiments, bitlines 142 may include an optional bitline liner (also referred to as a bitline barrier layer) and a bitline metal.

[0059]

[0077] The optional bitline liner can be made of any suitable material deposited by any suitable technique known to those skilled in the art. In some embodiments, the bitline liner is conformally deposited within the plurality of bitline holes 138 and over the exposed surfaces of the dielectric 120 and the doped surface 140 (or exposed surfaces) of the active material 105. In one or more embodiments, the bitline liner is deposited on the source / drain regions at the inner ends of the active material 105. The bitline liner can be any suitable material, including, but not limited to, titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the optional bitline liner comprises or consists essentially of titanium nitride (TiN). When used in this manner, the term “consisting essentially of” means that the film composition is greater than or equal to about 95%, 98%, 99%, or 99.5% of the stated species. In some embodiments, the optional bitline liner comprises or consists essentially of tantalum nitride (TaN). In some embodiments, the bit line liner is a conformal layer. In some embodiments, the bit line liner is deposited by atomic layer deposition.

[0060]

[0078] In some embodiments, the bitlines 142 comprise a bitline metal. The bitline metal may comprise any suitable metal known to those skilled in the art. In one or more embodiments, the bitline metal comprises, or consists essentially of, one or more of tungsten silicide (WSi), tungsten nitride (WN), or tungsten (W). The bitline metal may be deposited by any suitable technique known to those skilled in the art and may be any suitable material. In one or more embodiments, forming the bitlines 142 further comprises forming a bitline metal seed layer (not shown) before depositing the bitline metal.

[0061]

[0079] An additional embodiment of the present disclosure is directed to a processing tool 900 for forming the described memory devices and methods, as shown in Figure 3. The cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are disposed within the central transfer station 921, 931 and configured to move a robot blade and wafer to each of the multiple sides.

[0062]

[0080] The cluster tool 900 includes multiple processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as process stations, connected to a central transfer station. The various processing chambers provide distinct processing regions separate from adjacent processing stations. The processing chambers may be any suitable chamber, including, but not limited to, a pre-clean chamber, a buffer chamber, one or more transfer spaces, a wafer orientation / degassing chamber, a cryogenic cooling chamber, a deposition chamber, an annealing chamber, an etch chamber, a selective etch chamber, etc. The specific arrangement of processing chambers and components may vary depending on the cluster tool and should not be construed as limiting the scope of the present disclosure.

[0063]

[0081] 3, a factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front 951 of the factory interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, one skilled in the art will understand that this represents only one possible configuration.

[0064]

[0082] The size and shape of the loading chamber 954 and unloading chamber 956 can vary depending on, for example, the substrates being processed in the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and unloading chamber 956 are sized to hold a wafer cassette with multiple wafers arranged within the cassette.

[0065]

[0083] The robot 952 resides within the factory interface 950 and can move between a loading chamber 954 and an unloading chamber 956. The robot 952 can transfer wafers from a cassette in the loading chamber 954 through the factory interface 950 to a load lock chamber 960. The robot 952 can also transfer wafers from the load lock chamber 962 through the factory interface 950 to a cassette in the unloading chamber 956. As will be appreciated by those skilled in the art, the factory interface 950 can include multiple robots 952. For example, the factory interface 950 can include a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960 and a second robot that transfers wafers between the load lock chamber 962 and the unloading chamber 956.

[0066]

[0084] The illustrated cluster tool 900 has a first section 920 and a second section 930. The first section 920 is connected to a factory interface 950 through load lock chambers 960 and 962. The first section 920 includes a first transfer chamber 921 with at least one robot 925 disposed therein. The robot 925 is also referred to as a robotic wafer transport mechanism. The first transfer chamber 921 is centrally located relative to the load lock chambers 960 and 962, the processing chambers 902, 904, 916, and 918, and the buffer chambers 922 and 924. In some embodiments, the robot 925 is a multi-arm robot capable of independently moving multiple wafers at a time. In some embodiments, the first transfer chamber 921 includes multiple robotic wafer transfer mechanisms. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers surrounding the first transfer chamber 921. Individual wafers are carried on a wafer transport blade located at the distal end of the first robotic mechanism.

[0067]

[0085] After processing the wafer in the first section 920, the wafer may pass through a pass-through chamber to the second section 930. For example, chambers 922, 924 may be unidirectional or bidirectional pass-through chambers. The pass-through chambers 922, 924 may be used, for example, to cryogenically cool the wafer before processing in the second section 930, or to allow wafer cooling or post-processing before returning to the first section 920.

[0068]

[0086] A system controller 990 is in communication with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 may be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 may be a computer including a central processing unit (CPU), memory, appropriate circuitry, and storage.

[0069]

[0087] The processes may generally be stored in the memory of the system controller 990 as software routines that, when executed by a processor, cause the processing chamber to perform the processes of the present disclosure. The software routines may be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the processes may be implemented in software and executed using a computer system, for example, in hardware as an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls chamber operation to perform the processes.

[0070]

[0088] Spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein for ease of description to describe the relationship of one element or feature to another element or feature, as shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown. For example, if the device in the figures were turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an upper and lower orientation. The device may be in other orientations (such as rotated 90 degrees or other orientations), and the spatially relative descriptions used herein will be interpreted accordingly.

[0071]

[0089] In the context of describing the materials and methods discussed herein (particularly in the context of the claims that follow), the use of "a" and "an," "the," and similar referents should be construed to encompass both the singular and the plural unless otherwise indicated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better describe the materials and methods and does not limit the scope unless specifically claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0072]

[0090] Throughout this specification, references to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments," "a particular embodiment," "in one embodiment," or "an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0073]

[0091] Although the disclosure herein has been described with reference to particular embodiments, those skilled in the art will recognize that the described embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure includes modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of forming a memory device, the method comprising: forming a memory stack, the memory stack including one or more sacrificial layers, a polysilicon layer, a first material layer, a second material layer, and a semiconductor material layer; forming an active opening through the memory stack and recessing the first material layer through the active opening to form a recessed region; depositing a gate oxide layer over the polysilicon layer and over the semiconductor material layer; forming a word line in the recessed region, the word line including one or more of a barrier layer and a word line metal; depositing a filler material within the active openings; forming a slit pattern opening through the memory stack; forming a capacitor opening by recessing the polysilicon layer and the semiconductor material layer through the slit pattern opening; forming a metal silicide layer on the semiconductor material layer and on the polysilicon layer; forming a capacitor in the capacitor opening; forming a bit line opening in the fill material; forming a bit line in the bit line opening; forming the metal silicide layer between the capacitor and the bit line to form the memory device; A method comprising:

2. The method of claim 1 , wherein the first and second material layers independently comprise insulating materials.

3. The method of claim 2 , wherein the first material layer comprises a nitride layer and the second material layer comprises an oxide layer.

4. The method of claim 3 , wherein the first material layer comprises silicon nitride and the second material layer comprises silicon oxide.

5. The method of claim 1 , wherein the layer of semiconductor material comprises polysilicon.

6. 10. The method of claim 1, wherein the metal silicide layer comprises a metal selected from one or more of titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), iridium (Ir), and molybdenum (Mo).

7. 10. The method of claim 1, wherein forming the capacitor comprises depositing one or more of a bottom electrode, a high-k dielectric layer, a top electrode, and a silicon germanium (SiGe) layer.

8. 1. A method of forming a memory device, the method comprising: forming a memory stack, the memory stack including one or more sacrificial layers, a polysilicon layer, a first material layer, a second material layer, and a semiconductor material layer; forming an active opening through the memory stack and recessing the first material layer through the active opening to form a recessed region; depositing a gate oxide layer over the polysilicon layer and over the semiconductor material layer; forming a word line in the recessed region, the word line including one or more of a barrier layer and a word line metal; depositing a filler material within the active openings; forming a slit pattern opening through the memory stack; forming a capacitor opening by recessing the polysilicon layer and the semiconductor material layer through the slit pattern opening; forming a metal silicide layer on the semiconductor material layer and on the polysilicon layer; forming a capacitor in the capacitor opening; forming a bit line opening in the fill material; forming a bit line in the bit line opening; A method comprising:

9. The method of claim 8 , wherein the first layer of material and the second layer of material independently comprise insulating materials.

10. The method of claim 9 , wherein the first material layer comprises a nitride layer and the second material layer comprises an oxide layer.

11. The method of claim 10 , wherein the first material layer comprises silicon nitride and the second material layer comprises silicon oxide.

12. The method of claim 8 , wherein the layer of semiconductor material comprises polysilicon.

13. 9. The method of claim 8, wherein the metal silicide layer comprises a metal selected from one or more of titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), iridium (Ir), and molybdenum (Mo).

14. 10. The method of claim 8, wherein forming the capacitor comprises depositing one or more of a bottom electrode, a high-k dielectric layer, a top electrode, and a silicon germanium (SiGe) layer.

15. When executed by a controller of a processing chamber, the processing chamber: forming a memory stack, the memory stack including one or more of a sacrificial layer, a polysilicon layer, a first material layer, a second material layer, and a semiconductor material layer; forming an active opening through the memory stack and recessing the first material layer through the active opening to form a recessed region; depositing a gate oxide layer over the polysilicon layer and over the semiconductor material layer; forming word lines in the recessed regions, the word lines including one or more of a barrier layer and a word line metal; depositing a filler material within the active openings; forming a slit pattern opening through the memory stack; forming a capacitor opening by recessing the polysilicon layer and the semiconductor material layer through the slit pattern opening; forming a metal silicide layer over the polysilicon layer and the semiconductor material layer; forming a capacitor in the capacitor opening; forming a bit line opening in the fill material; forming a bit line in the bit line opening; A non-transitory computer-readable medium containing instructions for performing

16. 16. The non-transitory computer-readable medium of claim 15, wherein the first material layer comprises silicon nitride, the second material layer comprises silicon oxide, and the semiconductor material layer comprises polysilicon.

17. 16. The non-transitory computer-readable medium of claim 15, wherein the metal silicide layer comprises a metal selected from one or more of titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), iridium (Ir), and molybdenum (Mo).

18. 1. A method of forming a semiconductor device, the method comprising: forming a film stack on a substrate, the film stack including a plurality of alternating layers of semiconductor material and a corresponding plurality of dielectric layers; patterning the film stack to form an opening, the opening extending from a top surface of the film stack to the substrate and having an aspect ratio of 10:1 or greater; recessing each of the plurality of layers of semiconductor material through the opening to form a recessed plurality of layers of semiconductor material; selectively depositing a metal layer on each of the recessed layers of semiconductor material; depositing a filler material within the opening; forming a bit line opening in the fill material; forming a bit line in the bit line opening; connecting one side of the metal layer to a bit line through the filler material to form the semiconductor device; A method comprising:

19. 20. The method of claim 18, wherein the metal layer comprises a metal selected from one or more of titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), iridium (Ir), and molybdenum (Mo).

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