Analog-to-digital conversion circuit

Abstract

An analog-digital conversion circuit (1) that has a variable gain amplifier (10), a delta-sigma modulator (20) that modulates the output of the variable gain amplifier (10) into a pulse density modulation (PDM) signal, and a decimation filter (30) that down samples the PDM signal and outputs a multi-bit first digital signal. The decimation filter (30) has: a weight modification unit (40) that converts the PDM signal to a second digital signal that has a weight that is the product of the weight of the PDM signal and the reciprocal of the amplification factor of the variable gain amplifier (10); and a first digital filter unit (50) that receives the second digital signal as input and outputs the first digital signal.

Description

[Technical Field]

[0001] The present disclosure relates to analog-to-digital conversion circuits. [Background technology]

[0002] Conventionally, an analog-to-digital conversion circuit with an automatic gain control function has been known, which includes a variable gain amplifier, a delta-sigma modulator that modulates the output of the variable gain amplifier into a PDM (Pulse Density Modulation) signal, and a decimation filter that downsamples the PDM signal and outputs a multi-bit digital signal (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 3214981 Summary of the Invention [Problem to be solved by the invention]

[0004] In a conventional analog-to-digital conversion circuit of the type described in Patent Document 1, in which the output of a decimation filter is fed back to the amplification factor of a variable gain amplifier, when the amplification factor is changed, the output of the analog-to-digital conversion circuit becomes unstable from the time the amplification factor is changed until the response time of the decimation filter has elapsed.

[0005] Therefore, an object of the present disclosure is to provide an analog-to-digital converter circuit that can suppress unstable outputs. [Means for solving the problem]

[0006] An analog-to-digital conversion circuit according to one embodiment of the present disclosure includes a variable gain amplifier, a delta-sigma modulator that modulates the output of the variable gain amplifier into a PDM (Pulse Density Modulation) signal, and a decimation filter that downsamples the PDM signal and outputs a multi-bit first digital signal, wherein the decimation filter has a weight changing unit that converts the PDM signal into a weighted second digital signal obtained by multiplying the weight of the PDM signal by the reciprocal of the amplification factor of the variable gain amplifier, and a first digital filter unit that receives the second digital signal as an input and outputs the first digital signal. [Effects of the Invention]

[0007] According to an analog-to-digital converter circuit according to an aspect of the present disclosure, it is possible to suppress unstable output. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an analog-to-digital converter according to the first embodiment. [Figure 2] FIG. 2 is a characteristic diagram showing an example of the frequency characteristic of the variable gain amplifier according to the first embodiment. [Figure 3] FIG. 3 is a block diagram illustrating an example of the configuration of a weight modification unit according to the first embodiment. [Figure 4] FIG. 4 is a characteristic diagram illustrating an example of frequency characteristics of the digital filter unit according to the first embodiment. [Figure 5] FIG. 5 is a schematic diagram showing the operation of switching the amplification factor performed by the analog-to-digital converter according to the first embodiment. [Figure 6] FIG. 6 is a timing chart showing how the clock generator according to the first embodiment temporarily stops supplying the clock signal. [Figure 7] FIG. 7 is a waveform diagram showing an example of the relationship between an analog signal input to the analog-to-digital converter according to the first embodiment and a digital signal output from the analog-to-digital converter. [Figure 8] FIG. 8 is a block diagram illustrating an example of the configuration of the analog-to-digital converter according to the second embodiment. [Figure 9] FIG. 9 is a block diagram illustrating an example of the configuration of the analog-to-digital converter according to the third embodiment. [Figure 10] FIG. 10 is a block diagram illustrating an example of the configuration of a weight modification unit according to the third embodiment. [Figure 11] FIG. 11 is a waveform diagram showing an example of an output waveform when automatic gain control is performed in a conventional configuration. DETAILED DESCRIPTION OF THE INVENTION

[0009] (How one aspect of the present disclosure was achieved) A delta-sigma analog-to-digital converter (hereinafter also referred to as a "delta-sigma ADC") is configured to include a delta-sigma modulator and a decimation filter, and reduces noise obtained by oversampling the delta-sigma modulator. Shaping This effect makes it well known as an architecture for analog-to-digital converters (hereinafter also referred to as "ADCs") that can achieve a high dynamic range and high resolution with an effective bit range of about 12 to 16 bits.

[0010] A delta-sigma modulator calculates the difference (Δ, delta) between the signal obtained by integrating (Σ, sigma) the analog input signal and the signal obtained by digital-to-analog converting the digital output and feeding it back, and converts the analog input signal into a PDM signal quantized to one or multiple bits.

[0011] A decimation filter increases the resolution (number of bits) by integrating the single-bit or multi-bit PDM signal output from a delta-sigma modulator at the oversampling frequency (fosr) up to the analog-to-digital conversion frequency (fs). For example, in a delta-sigma ADC with a 256x oversampling rate, the PDM signal is output at a frequency of 256 × fs = fosr, and the decimation filter reduces the data output frequency to 1 / 256th of that frequency (fs). Such decimation filters are composed of digital filters such as SINC filters, FIR filters, and IIR filters. To attenuate noise shifted to high frequencies by the delta-sigma modulator's noise shaping, the filter configuration must be of a higher order than the delta-sigma modulator. For example, in a second-order delta-sigma ADC, the delta-sigma modulator has a second-order order, so the downstream decimation filter is often composed of a third-order or higher order filter.

[0012] Generally, the dynamic range of an ADC is limited by the power supply voltage of the ADC at the upper limit and the thermal noise of the ADC itself at the lower limit. Therefore, the dynamic range is expressed as SNR (Signal to Noise Ratio) or Effective Number of Bits (Enob). of It is often specified in bits. To perform analog-to-digital conversion correctly using an ADC, the amplitude of the input analog signal must be limited within the dynamic range of the ADC. Therefore, if the input signal amplitude is too large to exceed the dynamic range of the ADC, or conversely, if the input signal amplitude is too small to be buried in the thermal noise of the ADC, an amplifier or attenuator is installed before the ADC to adjust the amplification factor so that the maximum and minimum input amplitudes fall within the dynamic range of the ADC.

[0013] In particular, in the case of a system with large fluctuations in analog input amplitude, where the resolution of the minimum input amplitude cannot be obtained when the amplification factor is adjusted to the maximum input amplitude, a variable gain amplifier (hereinafter also referred to as "VGA") is installed in front of the ADC, and the dynamic range of the ADC is expanded by changing the amplification factor of the VGA according to the input amplitude. Furthermore, a system in which the amplification factor of the VGA can be automatically changed according to the input amplitude is called an automatic gain control (hereinafter referred to as "AGC: Auto matic This is called "Gain Control."

[0014] An example of an embodiment in which AGC is realized by connecting a VGA to an ADC is disclosed in, for example, Patent Document 1. In particular, as described in Patent Document 1, a method in which the variable range of the VGA amplification factor is configured to be discrete, the magnitude of the digital output amplitude is determined by a digital circuit, and the VGA is feedback-controlled is called digital AGC.

[0015] However, in the case of a digital AGC that connects a VGA and a delta-sigma ADC and uses a digital circuit to detect the digital output amplitude after a decimation filter and feedback-control the VGA gain, as in the configuration disclosed in Patent Document 1, the response time of the decimation filter that occurs when the VGA gain is switched becomes an issue.When the VGA gain is switched in this configuration, the output data fluctuates due to a step response for at least the shortest sampling period (1 / fs) equal to the order of the decimation filter.

[0016] Figure 11 shows an example of a step response waveform that appears in the decimation filter output when AGC control is performed with a conventional configuration. Here, the VGA amplification factor is changed to 4x when the input signal amplitude falls below the reference level, and changed to 1x when it exceeds the reference level. In this waveform example, the output of the decimation filter fluctuates when the VGA gain is switched, and the input signal is not correctly converted to digital.

[0017] In practice, to prevent the step response of switching the VGA gain from affecting the output signal, a typical conventional digital AGC, such as that described in Patent Document 1, narrows the variable range of the VGA gain to minimize the step response when switching the VGA gain, and includes a loop filter with a sufficiently large time constant in the AGC feedback loop to gently change the gain, thereby setting the response of the AGC feedback loop to avoid any impact on the system. Conversely, to achieve high-speed AGC response, a configuration may be adopted in which, when changing the VGA gain, data before switching the VGA is retained until the decimation filter response stabilizes, thereby ignoring the step response when changing the VGA gain. In any case, conventional AGCs using delta-sigma ADCs have the problem of being unable to perform analog-to-digital conversion while changing the VGA gain faster than the decimation filter response time.

[0018] Therefore, the inventors conducted extensive research and repeated experiments to develop an analog-to-digital converter that can perform analog-to-digital conversion even when the gain of the VGA is changed faster than the response time of the decimation filter. As a result, the inventors came up with the following analog-to-digital conversion circuit that can suppress unstable output.

[0019] An analog-to-digital conversion circuit according to one embodiment of the present disclosure includes a variable gain amplifier, a delta-sigma modulator that modulates the output of the variable gain amplifier into a PDM (Pulse Density Modulation) signal, and a decimation filter that downsamples the PDM signal and outputs a multi-bit first digital signal, wherein the decimation filter has a weight changing unit that converts the PDM signal into a weighted second digital signal obtained by multiplying the weight of the PDM signal by the reciprocal of the amplification factor of the variable gain amplifier, and a first digital filter unit that receives the second digital signal as an input and outputs the first digital signal.

[0020] In the analog-to-digital converter circuit having the above configuration, when the amplification factor of the variable gain amplifier is multiplied by k (k is any number greater than 0), the weight of the PDM signal is multiplied by k, whereas the weight of the second digital signal is further multiplied by 1 / k, so the weight of the second digital signal does not change. Therefore, in the analog-to-digital converter circuit having the above configuration, the weight of the second digital signal can be varied faster than the response time of the decimation filter. gain Even if the amplification factor of the amplifier is changed, analog-to-digital conversion can be performed.

[0021] In this way, the analog-to-digital converter circuit having the above configuration can suppress unstable outputs.

[0022] Furthermore, the amplification factor may be a power of 2, and the weight change unit may include a two's complement conversion circuit that converts the PDM signal into a third digital signal in two's complement representation with the same weight as the weight of the PDM signal, and a shift circuit that outputs the second digital signal by performing an n-bit arithmetic right shift on the third digital signal when the amplification factor is 2 to the nth power (n is an integer greater than or equal to 0).

[0023] This allows the weight change unit to have a configuration that does not include a circuit with a relatively large circuit scale, such as a divider.

[0024] Furthermore, the digital signal processing device may further include a gain control unit that changes the amplification factor based on the value of the first digital signal.

[0025] This allows the output of the decimation filter to be fed back to the amplification factor of the variable gain amplifier.

[0026] The gain control unit may also change the amplification factor so that when the absolute value of the value of the first digital signal multiplied by the amplification factor is greater than a first reference level, the gain control unit reduces the amplification factor by 1 / 2, and when the absolute value is smaller than a second reference level that is smaller than 1 / 2 of the first reference level, the gain control unit increases the amplification factor by 2.

[0027] This allows hysteresis to be imparted to the change in the gain of the variable gain amplifier, thereby making it possible to stabilize the change in the gain of the variable gain amplifier.

[0028] The decimation filter may output the first digital signal in a first period, and the gain control unit may change the amplification factor in the first period.

[0029] This allows the change in the amplification factor of the variable gain amplifier to be synchronized with the period of the output of the decimation filter.

[0030] The first digital filter unit may further include a second digital filter unit that receives the second digital signal as an input and outputs a fourth digital signal having a smaller number of bits than the first digital signal, and a third digital filter unit that receives the fourth digital signal as an input and outputs the first digital signal, and may further include a gain control unit that changes the amplification factor based on the value of the fourth digital signal.

[0031] This makes it possible to reduce the circuit scale of the gain control section.

[0032] The delta-sigma modulator may temporarily hold the value of the PDM signal in synchronization with the timing at which the gain control unit changes the amplification factor.

[0033] This makes it possible to prevent the effect of the response time when the gain of the variable gain amplifier is changed from being reflected in the input to the decimation filter, thereby further reducing unstable output from the analog-to-digital conversion circuit.

[0034] Specific examples of analog-to-digital conversion circuits according to an embodiment of the present disclosure will be described below with reference to the drawings. Each of the embodiments shown here illustrates a specific example of the present disclosure. Therefore, the numerical values, shapes, components, component arrangements, connection configurations, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is a schematic diagram and is not necessarily a precise illustration.

[0035] (Embodiment 1) FIG. 1 is a block diagram showing an example of the configuration of an analog-to-digital converter 1 according to the first embodiment.

[0036] Here, as an example, the analog-to-digital conversion circuit 1 will be described as converting the voltage across a shunt resistor 200 connected in series to a battery pack 300 and a load 400 into a digital value and outputting the digital value. The load 400 is, for example, a motor that drives an electric vehicle, and the battery pack 300 is, for example, a lithium-ion battery that drives the motor.

[0037] As shown in FIG. 1, the analog-to-digital converter circuit 1 includes a variable gain amplifier 10, a delta-sigma modulator 20, a decimation filter 30, a gain control unit 80, a control unit 90, and a clock generator 100.

[0038] The variable gain amplifier 10 amplifies the input analog signal by an amplification factor indicated by a GAIN signal, which will be described later, and outputs the amplified signal.

[0039] FIG. 2 is a characteristic diagram showing an example of the frequency characteristic of the variable gain amplifier 10. As shown in FIG.

[0040] 2, the following description will be given assuming that the gain of the variable gain amplifier 10 is a power of 2. More specifically, the following description will be given assuming that the gain of the variable gain amplifier 10 is set to one of 1, which is 2 to the power of 0, 2, which is 2 to the power of 1, 4, which is 2 to the power of 2, and 8, which is 2 to the power of 3.

[0041] Returning to FIG. 1, the analog-to-digital converter 1 will be described further.

[0042] The delta-sigma modulator 20 modulates the output of the variable gain amplifier 10 into a PDM (Pulse Density Modulation) signal and outputs it. Here, the delta-sigma modulator 20 is described as having a second order, oversampling at an oversampling frequency fosr that is 256 times the sampling frequency fs of the analog-to-digital conversion circuit 1, and outputting a 1-bit PDM signal indicating a binary value of +1 or −1 at the oversampling frequency fosr.

[0043] The decimation filter 30 downsamples the PDM signal output from the delta-sigma modulator 20 and outputs a multi-bit first digital signal. Here, the decimation filter 30 is described as downsampling at a sampling frequency fs that is 1 / 256 of the oversampling frequency fosr and outputting a 29-bit first digital signal.

[0044] As shown in FIG. 1, the decimation filter 30 includes a weight changing unit 40 and a digital filter unit 50.

[0045] The weight change unit 40 converts the PDM signal output from the delta-sigma modulator 20 into a weighted second digital signal in which the weight of the PDM signal is multiplied by the reciprocal of the amplification factor of the variable gain amplifier 10.

[0046] FIG. 3 is a block diagram showing an example of the configuration of the weight change unit 40. As shown in FIG.

[0047] As shown in FIG. 3, the weight change unit 40 includes a two's complement conversion circuit 60 and a shift circuit 70.

[0048] The two's complement conversion circuit 60 converts the PDM signal into a third digital signal in two's complement representation with the same weight as the weight of the PDM signal. Here, the third digital signal is a signed 5-bit digital signal. More specifically, as shown in FIG. 3 , the two's complement conversion circuit 60 operates at an oversampling frequency fosr (=256×fs) and converts a PDM signal indicating a value of +1 into a third digital signal indicating 01000, and converts a PDM signal indicating a value of −1 into a third digital signal indicating 11000.

[0049] When the amplification factor of the variable gain amplifier 10 is 2 to the power of n (n is an integer greater than or equal to 0), the shift circuit 70 performs an n-bit arithmetic right shift on the third digital signal to output a weighted second digital signal in which the weight of the PDM signal is multiplied by the reciprocal of the amplification factor of the variable gain amplifier 10. More specifically, as shown in FIG. 3, the shift circuit 70 operates at an oversampling frequency fosr (=256×fs), and (1) when the gain of the variable gain amplifier 10 is 1, it performs a 0-bit arithmetic right shift on the third digital signal to output a weighted second digital signal in which the weight of the PDM signal is multiplied by 1; (2) when the gain of the variable gain amplifier 10 is 2, it performs a 1-bit arithmetic right shift on the third digital signal to output a weighted second digital signal in which the weight of the PDM signal is multiplied by 1 / 2; (3) when the gain of the variable gain amplifier 10 is 4, it performs a 2-bit arithmetic right shift on the third digital signal to output a weighted second digital signal in which the weight of the PDM signal is multiplied by 1 / 4; and (4) when the gain of the variable gain amplifier 10 is 8, it performs a 3-bit arithmetic right shift on the third digital signal to output a weighted second digital signal in which the weight of the PDM signal is multiplied by 1 / 8.

[0050] 3 is realized by a configuration that does not include a circuit with a relatively large circuit scale, such as a divider, and therefore can convert the PDM signal into the third digital signal in a relatively short time.

[0051] Returning to FIG. 1, the analog-to-digital converter 1 will be described further.

[0052] The digital filter unit 50 is a digital filter that receives the second digital signal as input and outputs the first digital signal. Here, the digital filter unit 50 is described as a digital filter having a third order, which is greater than the order of the delta-sigma modulator 20, and that downsamples the second digital signal at a sampling frequency fs that is 1 / 256 of the oversampling frequency fosr, and outputs a 29-bit first digital signal. The digital filter unit 50 may be configured, for example, by a SINC filter, an FIR filter, or an IIR filter.

[0053] FIG. 4 is a characteristic diagram showing an example of the frequency characteristics of the digital filter unit 50 when the digital filter unit 50 is configured by a third-order SINC filter with a decimation rate of 1 / 256.

[0054] Returning to FIG. 1, the analog-to-digital converter 1 will be described further.

[0055] The gain control unit 80 changes the amplification factor of the variable gain amplifier 10 based on the value of the first digital signal. The gain control unit 80 then outputs a GAIN signal indicating the amplification factor. Here, the gain control unit 80 is described as changing the amplification factor at the sampling frequency fs of the first digital signal, and changing the amplification factor so that the amplification factor is reduced by 1 / 2 when the absolute value of the value of the first digital signal multiplied by the amplification factor is greater than a first reference level, and the amplification factor is increased by 2 when the absolute value is smaller than a second reference level that is smaller than 1 / 2 of the first reference level.

[0056] As shown in FIG. 1, the gain control section 80 includes a multiplier 81, an absolute value calculation section 82, an upper reference level output section 83, a lower reference level output section 84, a comparator 85, and an up / down counter 86.

[0057] The multiplier 81 multiplies the value of the first digital signal by an amplification factor indicated by the GAIN signal, and outputs an amplified signal obtained by multiplying the value of the first digital signal by the amplification factor.

[0058] The absolute value calculation unit 82 calculates the absolute value of the value indicated by the amplified signal output from the multiplier 81. Then, it outputs an absolute value signal indicating the absolute value of the value indicated by the amplified signal.

[0059] The upper reference level output section 83 outputs an upper reference level signal indicating a predetermined upper reference level.

[0060] The lower reference level output section 84 outputs a lower reference level signal that is a predetermined value smaller than the upper mold reference level.

[0061] The comparator 85 compares the absolute value indicated by the absolute value signal output from the absolute value calculation unit 82 with the upper reference level indicated by the upper reference level signal output from the upper reference level output unit 83 and the lower reference level indicated by the lower reference level signal output from the lower reference level output unit 84. More specifically, the comparator 85 (1) outputs a Down signal when the absolute value indicated by the absolute value signal is equal to or greater than the upper reference level indicated by the upper reference level signal, and (2) outputs an Up signal when the absolute value indicated by the absolute value signal is equal to or less than the lower reference level indicated by the lower reference level signal.

[0062] The up / down counter 86 is a counter that holds a GAIN signal that indicates the amplification factor of the variable gain amplifier 10, and outputs the held GAIN signal. (1) When a Down signal is output from the comparator 85, the up / down counter 86 changes the held GAIN signal so that the amplification factor indicated by the GAIN signal becomes 1 / 2, and (2) When an Up signal is output from the comparator 85, the up / down counter 86 changes the held GAIN signal so that the amplification factor indicated by the GAIN signal becomes 2 times.

[0063] With the above configuration, the gain control unit 80 changes the amplification factor indicated by the GAIN signal at the period of the first digital signal output from the decimation filter 30 (here, 1 / fs).

[0064] The analog-to-digital converter 1 includes the gain control section 80 configured as described above, and thereby feeds back the output of the decimation filter 30 to the amplification factor of the variable gain amplifier 10.

[0065] Fig. 5 is a schematic diagram showing the operation of switching the gain of the variable gain amplifier 10 performed by the analog-to-digital converter 1. In Fig. 5, the vertical axis represents the gain of the variable gain amplifier 10, and the horizontal axis represents the dynamic range of the analog-to-digital converter 1 at that gain. The width of the scale along the horizontal axis at each gain represents the resolution of the analog-to-digital converter 1 at that gain.

[0066] As shown in FIG. 5, the analog-to-digital converter 1 realizes an automatic gain control function by feeding back the output of the decimation filter 30 to the amplification factor of the variable gain amplifier 10.

[0067] Returning to FIG. 1, the analog-to-digital converter 1 will be described further.

[0068] The clock generator 100 generates a clock signal CKosr having a frequency fosr and a clock signal CKs having a frequency fs, supplies the generated clock signal CKosr to the delta-sigma modulator 20 and the decimation filter 30, and supplies the generated clock signal CKs to the decimation filter 30.

[0069] The control unit 90 controls the clock generator 100. More specifically, the control unit 90 receives the Down signal and the Up signal output from the comparator 85, and when the Down signal or the Up signal is received, the control unit 90 temporarily stops the supply of the clock signal CKosr by the clock generator 100. Here, the period during which the supply of the clock signal CKosr by the clock generator 100 is temporarily stopped will be described as the response time period when the amplification factor of the variable gain amplifier 10 is changed.

[0070] FIG. 6 is a timing chart showing how the clock generator 100 temporarily stops supplying the clock signal CKosr.

[0071] The clock generator 100 is controlled by the control unit 90 to temporarily stop supplying the clock signal CKosr at the timing when the comparator 85 outputs a Down signal or an Up signal, that is, at the timing when the gain of the variable gain amplifier 10 is switched.

[0072] As a result, the delta-sigma modulator 20 temporarily holds the value of the PDM signal in synchronization with the timing at which the gain control section 80 switches the amplification factor of the variable gain amplifier 10.

[0073] Like common variable gain amplifiers, variable gain amplifier 10 has a low-pass filter characteristic as shown in Fig. 2. When the gain of variable gain amplifier 10 is changed discretely, i.e., when the gain is changed suddenly, variable gain amplifier 10 having a low-pass filter characteristic may output an output signal that resembles the input signal multiplied by the step response of variable gain amplifier 10.

[0074] Therefore, when the amplification factor of the variable gain amplifier 10 is changed discretely, a certain amount of time according to the frequency characteristics of the variable gain amplifier 10 is required for the output signal to stabilize.

[0075] On the other hand, when the PDM signal multiplied by the step response of the variable gain amplifier 10 is input to the decimation filter 30, a certain amount of time according to the frequency characteristics of the decimation filter 30 is required until the output of the decimation filter 30 stabilizes.

[0076] Generally, the frequency characteristics of a variable gain amplifier are designed to have a cutoff frequency that is sufficiently higher than the oversampling frequency (fOSR) of the delta-sigma modulator, so the response time when changing the gain of the variable gain amplifier converges in a very short period of time.In contrast, the frequency characteristics of a decimation filter are generally designed to have a very low cutoff frequency, so the effect of the step response of the decimation filter continues for a long time.

[0077] Therefore, the analog-to-digital converter 1 temporarily stops supplying the clock signal CKosr during the response time when the gain of the variable gain amplifier 10 is changed, thereby realizing the function of temporarily holding the value of the PDM signal.

[0078] As described above, the analog-to-digital conversion circuit 1 has the function of temporarily holding the value of the PDM signal. Therefore, by designing the frequency characteristics of the variable gain amplifier 10 so that the cutoff frequency is sufficiently higher than the oversampling frequency (fosr) of the delta-sigma modulator 20, the period during which the value of the PDM signal is temporarily held can be made very short, so that the analog-to-digital conversion is not affected.

[0079] <Consideration> In the analog-to-digital converter 1 configured as described above, when the gain of the variable gain amplifier 10 is multiplied by k, the weight of the PDM signal is multiplied by k, whereas the weight of the second digital signal is further multiplied by 1 / k, so that the weight of the second digital signal remains unchanged. Therefore, the analog-to-digital converter 1 configured as described above can perform analog-to-digital conversion even if the gain of the variable gain amplifier 10 is changed faster than the response time of the decimation filter 30.

[0080] FIG. 7 is a waveform diagram showing an example of the relationship between the analog signal input to the analog-to-digital converter 1 and the first digital signal output from the analog-to-digital converter 1. As shown in FIG.

[0081] 7, when the signal amplitude of the analog signal input to the analog-to-digital converter 1 approaches the zero crossing, the gain of the variable gain amplifier 10 is changed from 1 to 4. However, in the analog-to-digital converter 1, the weight of the second digital signal is not changed even when the gain of the variable gain amplifier 10 is changed. Therefore, a step response of the decimation filter 30 caused by the change in the gain of the variable gain amplifier 10 is not generated in the first digital signal.

[0082] In this way, the analog-to-digital converter 1 configured as above can suppress unstable outputs.

[0083] Therefore, the analog-to-digital converter 1 is useful when the input analog signal fluctuates quickly and over a wide range.

[0084] For example, in an electric vehicle powered by a lithium-ion battery, the output current of the lithium-ion battery fluctuates rapidly and irregularly from a few hundred μA to a few hundred A when the battery is at full stop to maximum output. Because the range of this change is more than a million times, a dynamic range of 120 dB or more is required for measuring the output current of the lithium-ion battery. Even with a delta-sigma ADC capable of achieving a high dynamic range, it is difficult to achieve such a dynamic range without an AGC function. Meanwhile, conventional delta-sigma ADCs with an AGC function are unable to track such rapid current changes due to the response time of the AGC feedback loop.

[0085] In contrast, the analog-to-digital converter 1 configured as described above has an AGC function that realizes a wide dynamic range and can also follow steep current changes. For this reason, the analog-to-digital converter 1 configured as described above is particularly useful for measuring the output current value of a lithium-ion battery in an electric vehicle that operates on a lithium-ion battery.

[0086] Furthermore, according to the analog-to-digital converter 1 configured as described above, the weight change section 40 can be configured to not include a circuit with a relatively large circuit scale, such as a divider.

[0087] Furthermore, according to the analog-to-digital converter 1 configured as described above, the output of the decimation filter 30 can be fed back to the amplification factor of the variable gain amplifier 10.

[0088] Furthermore, according to the analog-to-digital converter 1 having the above configuration, hysteresis can be imparted to the change in the gain of the variable gain amplifier 10, so that the change in the gain of the variable gain amplifier 10 can be made stable.

[0089] Furthermore, according to the analog-to-digital converter 1 configured as described above, the change in the amplification factor of the variable gain amplifier 10 can be synchronized with the period of the output of the decimation filter 30.

[0090] Furthermore, the analog-to-digital converter 1 having the above configuration can prevent the effect of the response time when the gain of the variable gain amplifier 10 is changed from being reflected in the input to the decimation filter 30. This makes it possible to further prevent unstable output from the analog-to-digital converter 1.

[0091] (Embodiment 2) An analog-to-digital converter according to a second embodiment, which is configured by partially modifying the analog-to-digital converter 1 according to the first embodiment, will be described below.

[0092] In the following, for the analog-digital converter circuit of embodiment 2, components that are similar to the components of the analog-digital converter circuit 1 of embodiment 1 have already been explained, so they are assigned the same symbols and detailed explanations are omitted, and the explanation will focus on the differences from the analog-digital converter circuit 1.

[0093] FIG. 8 is a block diagram showing an example of the configuration of an analog-to-digital converter 1A according to the second embodiment.

[0094] As shown in FIG. 8, the analog-to-digital converter 1A is configured by replacing the gain control section 80 in the analog-to-digital converter 1 according to the first embodiment with a gain control section 80A.

[0095] Gain control section 80A is configured by deleting multiplier 81 from gain control section 80 according to the first embodiment and adding dividers 87 and 88.

[0096] The divider 87 divides the value of the upper reference level signal output from the upper reference level output section 83 by the amplification factor indicated by the GAIN signal.

[0097] The divider 88 divides the value of the lower reference level signal output from the lower reference level output section 84 by the amplification factor indicated by the GAIN signal.

[0098] In the gain control unit 80A having the above configuration, the multiplier 81 is not present, and therefore the first digital signal is directly input to the absolute value calculation unit 82. Therefore, in the gain control unit 80A, the absolute value calculation unit 82 outputs the absolute value of the value of the first digital signal.

[0099] In the gain control section 80 according to the first embodiment, the comparator 85 compares the absolute value of the value obtained by multiplying the first digital signal by the amplification factor with the upper reference level and the lower reference level.

[0100] In contrast, in the gain control unit 80A, the comparator 85 compares the absolute value of the first digital signal with the value obtained by dividing the upper reference level by the amplification factor and the value obtained by dividing the lower reference level by the amplification factor.

[0101] Therefore, the comparator 85 in the gain control section 80A outputs the same signal as the comparator 85 in the gain control section 80 according to the first embodiment.

[0102] Therefore, the gain control section 80A configured as described above operates in the same manner as the gain control section 80 according to the first embodiment.

[0103] <Consideration> As described above, the gain control section 80A operates in the same manner as the gain control section 80 according to the first embodiment. Therefore, the analog-to-digital converter 1A operates in the same manner as the analog-to-digital converter 1 according to the first embodiment.

[0104] (Embodiment 3) An analog-to-digital converter according to a third embodiment, which is configured by partially modifying the analog-to-digital converter 1 according to the first embodiment, will be described below.

[0105] In the following, for the analog-digital converter circuit of embodiment 3, components that are similar to the components of the analog-digital converter circuit 1 of embodiment 1 have already been explained, so they will be assigned the same symbols and their detailed explanation will be omitted, and the explanation will focus on the differences from the analog-digital converter circuit 1.

[0106] FIG. 9 is a block diagram showing an example of the configuration of an analog-to-digital converter 1B according to the third embodiment.

[0107] As shown in FIG. 9, the analog-to-digital converter 1B is configured by changing the delta-sigma modulator 20 of the analog-to-digital converter 1 according to the first embodiment to a MASH-type delta-sigma modulator 20B, changing the decimation filter 30 to a decimation filter 30B, and changing the gain control unit 80 to a gain control unit 80B.

[0108] MASH-type delta-sigma modulator 20B modulates the output of variable gain amplifier 10 into a PDM signal and outputs it. Here, the MASH-type delta-sigma modulator 20B is described as having a second order, oversampling at an oversampling frequency fosr that is 256 times the sampling frequency fs of analog-to-digital conversion circuit 1B, and outputting a 2-bit PDM signal indicating three values: +1, 0, and −1, at the oversampling frequency fosr.

[0109] The decimation filter 30B downsamples the PDM signal output from the MASH delta-sigma modulator 20B and outputs a multi-bit first digital signal and a fourth digital signal. Here, the decimation filter 30B downsamples at a sampling frequency fs that is 1 / 256 of the oversampling frequency fosr to output a 29-bit first digital signal, and downsamples at a sampling frequency 16fs that is 1 / 16 of the oversampling frequency fosr to output a 21-bit fourth digital signal.

[0110] As shown in FIG. 9, decimation filter 30B is configured by changing weight modification section 40 of decimation filter 30 according to the first embodiment to weight modification section 40B and changing digital filter section 50 to digital filter section 50B.

[0111] The weight change unit 40B converts the PDM signal output from the MASH type delta sigma modulator 20B into a weighted second digital signal in which the weight of the PDM signal is multiplied by the reciprocal of the amplification factor of the variable gain amplifier 10.

[0112] FIG. 10 is a block diagram showing an example of the configuration of the weight change unit 40B.

[0113] As shown in FIG. 10, weight modification section 40B is configured by changing weight modification section 40 according to the first embodiment to a two's complement conversion circuit 60B instead of two's complement conversion circuit 60.

[0114] The two's complement conversion circuit 60B converts the PDM signal into a third digital signal in two's complement representation with the same weight as the weight of the PDM signal. Here, the third digital signal is a signed 5-bit digital signal. More specifically, the two's complement conversion circuit 60 B As shown in Figure 10, operates at an oversampling frequency fosr (=256 × fs), converts a PDM signal indicating a value of +1 into a third digital signal indicating 01000, converts a PDM signal indicating a value of 0 into a third digital signal indicating 00000, and converts a PDM signal indicating a value of -1 into a third digital signal indicating 11000.

[0115] Returning to FIG. 9, the analog-to-digital converter 1B will be further described.

[0116] The digital filter unit 50B is a digital filter that receives the second digital signal as an input and outputs the first digital signal and the fourth digital signal. Here, the digital filter unit 50B transfers the second digital signal using a transfer function H1(Z -1 ) and transfer function H2(Z -1 ), and downsamples it at a sampling frequency of 16fs, which is 1 / 16 of the oversampling frequency fosr, to output a 21-bit fourth digital signal. The fourth digital signal is then subjected to a transfer function H2(Z -1 ) and transfer function H3(Z -1 ) at a sampling frequency fs that is 1 / 16 of the sampling frequency 16fs, and outputs a 29-bit first digital signal.

[0117] Gain control unit 80B changes the amplification factor of variable gain amplifier 10 based on the value of the fourth digital signal. Gain control unit 80B then outputs a GAIN signal indicating that amplification factor. More specifically, gain control unit 80B is configured such that, compared to gain control unit 80 according to the first embodiment, the input digital signal is a 29-bit first digital signal, whereas the input digital signal is a 21-bit fourth digital signal.

[0118] In accordance with this change, the gain control section 80B is configured by changing the multiplier 81 to a multiplier 81B, the absolute value calculation section 82 to an absolute value calculation section 82B, the upper reference level output section 83 to an upper reference level output section 83B, the lower reference level output section 84 to a lower reference level output section 84B, and the comparator 85 to a comparator 85B. More specifically, the multiplier 81B is configured by changing the number of bits of the multiplier 81 from 29 bits to 21 bits, the upper reference level output section 83B is configured by changing the number of bits of the upper reference level output section 83 from 29 bits to 21 bits, the lower reference level output section 84B is configured by changing the number of bits of the lower reference level output section 84 from 29 bits to 21 bits, and the comparator 85B is configured by changing the number of bits of the comparator 85 from 29 bits to 21 bits.

[0119] <Consideration> In the analog-to-digital converter 1B having the above configuration, the number of bits of the components of the gain control section 80B, namely the multiplier 81B, the absolute value calculation section 82B, the upper reference level output section 83B, the lower reference level output section 84B, and the comparator 85B, are smaller than the number of bits of the components of the gain control section 80 according to Embodiment 1, namely the multiplier 81, the absolute value calculation section 82, the upper reference level output section 83, the lower reference level output section 84, and the comparator 85. In this way, in the analog-to-digital converter 1B having the above configuration, the circuit size of the gain control section 80B can be reduced.

[0120] (supplement) While the analog-to-digital converter according to one aspect of the present disclosure has been described above based on Embodiments 1 to 3, the present disclosure is not limited to these embodiments. As long as they do not deviate from the spirit of the present disclosure, various modifications conceivable by those skilled in the art to these embodiments and configurations constructed by combining components of different embodiments may also be included within the scope of one or more aspects of the present disclosure.

[0121] (1) In the first embodiment, the shunt resistor 200 has been described as if it were not a component of the analog-digital converter 1. However, the shunt resistor 200 may be considered to be a component of the analog-digital converter 1. In other words, the analog-digital converter 1 may be provided with the shunt resistor 200.

[0122] (2) In the first embodiment, the amplification factor of the variable gain amplifier 10 has been described as being a power of 2. However, the amplification factor of the variable gain amplifier 10 does not need to be limited to a power of 2. However, if the variable gain amplifier 10 in the analog-to-digital conversion circuit 1 is configured such that its amplification factor is not a power of 2, the shift circuit 70 must be configured to divide the value of the third digital signal by its amplification factor, thereby outputting a weighted second digital signal in which the weight of the PDM signal is multiplied by the reciprocal of the amplification factor of the variable gain amplifier 10. [Industrial Applicability]

[0123] The present disclosure is widely applicable to analog-to-digital conversion circuits. [Explanation of symbols]

[0124] 1, 1A, 1B Analog-to-digital conversion circuit 10 Variable Gain Amplifier 20 Delta-Sigma Modulator 20B MASH type delta-sigma modulator 30, 30B Decimation Filter 40, 40B Weight change section 50, 50B Digital filter section 60, 60B 2's complement conversion circuit 70 Shift circuit 80, 80A, 80B Gain control section 81, 81B multiplier 82, 82B Absolute value calculation section 83, 83B Upper reference level output section 84, 84B Lower reference level output section 85, 85B comparator 86 Up / Down Counter 87, 88 Divider 90 Control Unit 100 Clock Generator 200 Shunt Resistor 300 battery packs 400 load

Claims

1. a variable gain amplifier; a delta-sigma modulator that modulates the output of the variable gain amplifier into a PDM (Pulse Density Modulation) signal; a decimation filter that downsamples the PDM signal and outputs a multi-bit first digital signal; The decimation filter a weight changing unit that converts the PDM signal into a weighted second digital signal obtained by multiplying the weight of the PDM signal by the reciprocal of the amplification factor of the variable gain amplifier; a first digital filter unit that receives the second digital signal as an input and outputs the first digital signal; further comprising a gain control unit that changes the amplification factor based on a value of the first digital signal; The gain control unit changes the amplification factor so as to decrease the amplification factor when an absolute value obtained by multiplying the value of the first digital signal by the amplification factor is greater than a first reference level, and to increase the amplification factor when the absolute value is smaller than a second reference level that is smaller than the first reference level. Analog-to-digital conversion circuit.

2. the amplification factor is a power of 2, The weight change unit a two's complement conversion circuit that converts the PDM signal into a third digital signal in two's complement representation with the same weight as the weight of the PDM signal; a shift circuit that outputs the second digital signal by performing an n-bit arithmetic shift on the third digital signal when the amplification factor is 2 n (n is an integer equal to or greater than 0).

2. The analog-to-digital conversion circuit according to claim 1.

3. The n-bit arithmetic shift is an n-bit arithmetic right shift.

3. The analog-to-digital conversion circuit according to claim 2.

4. The gain control unit changes the amplification factor so that when an absolute value of the value of the first digital signal multiplied by the amplification factor is greater than the first reference level, the amplification factor is reduced to 1 / 2, and when the absolute value is smaller than the second reference level which is smaller than 1 / 2 of the first reference level, the amplification factor is increased to 2.

4. The analog-to-digital conversion circuit according to claim 1.

5. the decimation filter outputs the first digital signal at a first period; The gain control unit changes the amplification factor in the first period.

5. The analog-to-digital conversion circuit according to claim 1.

6. a variable gain amplifier; a delta-sigma modulator that modulates the output of the variable gain amplifier into a PDM (Pulse Density Modulation) signal; a decimation filter that downsamples the PDM signal and outputs a multi-bit first digital signal; The decimation filter a weight changing unit that converts the PDM signal into a weighted second digital signal obtained by multiplying the weight of the PDM signal by the reciprocal of the amplification factor of the variable gain amplifier; a first digital filter unit that receives the second digital signal as an input and outputs the first digital signal; The first digital filter unit a second digital filter unit that receives the second digital signal as an input and outputs a fourth digital signal having a smaller number of bits than the first digital signal; a third digital filter unit that receives the fourth digital signal as an input and outputs the first digital signal; Further, a gain control unit that changes the amplification factor based on the value of the fourth digital signal is provided. Analog-to-digital conversion circuit.

7. The delta-sigma modulator temporarily holds the value of the PDM signal in synchronization with the timing at which the gain control unit changes the amplification factor.

7. The analog-to-digital conversion circuit according to claim 1.

8. The amplification factor is a power of 2, The weight change unit a two's complement conversion circuit that converts the PDM signal into a third digital signal in two's complement representation with the same weight as the weight of the PDM signal; a shift circuit that outputs the second digital signal by performing an n-bit arithmetic shift on the third digital signal when the amplification factor is 2 n (n is an integer equal to or greater than 0).

7. The analog-to-digital conversion circuit according to claim 6.

9. The n-bit arithmetic shift is an n-bit arithmetic right shift.

9. The analog-to-digital conversion circuit according to claim 8.

10. The gain control unit changes the amplification factor so that when an absolute value of the value of the first digital signal multiplied by the amplification factor is greater than a first reference level, the amplification factor is reduced to 1 / 2, and when the absolute value is smaller than a second reference level that is smaller than 1 / 2 of the first reference level, the amplification factor is increased to 2.

10. The analog-to-digital converter circuit according to claim 6, claim 8, or claim 9.

11. The decimation filter outputs the first digital signal at a first period; The gain control unit changes the amplification factor in the first period.

11. The analog-to-digital conversion circuit according to claim 6, or any one of claims 8 to 10.

Images