A / d converter

Abstract

The present invention is provided with: a ΔΣ modulator having an input terminal to which an input signal is inputted, a first amplification integration circuit, a second amplification integration circuit, an adder, and a quantizer; and a digital filter having a first digital integration circuit that outputs a third digital signal generated by integrating an output signal of the ΔΣ modulator, and a second digital integration circuit that outputs a fourth digital signal generated by integrating the third digital signal. The digital filter outputs a fifth digital signal generated by subtracting 1 / 2 of the third digital signal from the fourth digital signal.

Description

AD converter

[0001] The present invention relates to an AD converter.

[0002] Patent Document 1 listed below discloses a technique for improving resolution by operating an ADC for one cycle after N cycles to generate a remainder value, shifting the remainder by three bits using a digital adder, and then adding the remainder value to the shifted bits, resulting in +3 bits.

[0003] U.S. Patent No. 9,866,238

[0004] However, the above document does not solve the problem that the full scale varies when the oversampling (hereinafter sometimes referred to as "OSR") is changed in a second-order or higher incremental AD converter.

[0005] An AD converter according to one embodiment comprises an input terminal to which an input signal is input, a ΔΣ modulator having a first amplifying and integrating circuit, a second amplifying and integrating circuit, an adder, a quantizer, and a digital-to-analog converter, and a digital filter having a first digital integrating circuit that outputs a third digital signal generated by integrating an output signal of the ΔΣ modulator, and a second digital integrating circuit that outputs a fourth digital signal generated by integrating the third digital signal. In the ΔΣ modulator, in a first step, the digital-to-analog converter converts the first digital signal output from the quantizer into a feedback analog signal, the first amplifying and integrating circuit generates a first integrated signal by integrating a signal obtained by adding a signal obtained by amplifying the input signal with a predetermined gain and a signal obtained by amplifying the feedback analog signal with a predetermined gain, the second amplifying and integrating circuit generates a second integrated signal by integrating a signal obtained by amplifying the first integrated signal with the first gain, and the adder adds the signal obtained by amplifying the input signal with a predetermined gain and the first integrated signal with a predetermined gain. a quantizer converting the first signal output from the adder to generate a first digital signal; in a second step, the second amplifying and integrating circuit converts the first integrated signal to generate a fourth integrated signal; the first amplifying and integrating circuit converts the fourth integrated signal to generate a third integrated signal; the adder converts the fourth integrated signal to generate a second signal; the quantizer converts the second signal output from the adder to generate a second digital signal; the digital filter converts the second signal output from the adder to generate a fifth digital signal; the second amplifying and integrating circuit converts the fourth integrated signal to generate a fourth integrated signal; the first amplifying and integrating circuit converts the fourth integrated signal to generate a third integrated signal; the adder converts the third integrated signal to generate a second signal; the quantizer converts the second signal output from the adder to generate a second digital signal; and the digital filter converts the fourth digital signal to generate a fifth digital signal.

[0006] According to an AD converter according to one embodiment, the full scale of the output of the digital filter can be set to a power of 2, and the magnitude of the full scale can be kept the same even when the OSR is changed.

[0007] FIG. 1 shows an example of the configuration of an AD converter according to an embodiment; A timing chart showing an example of the operation timing of each control signal in a ΔΣ modulator according to an embodiment; A diagram for explaining an example of the effect of a digital filter according to an embodiment; A diagram for explaining an example of signal processing by a digital filter according to an embodiment; A diagram for explaining an example of a problem with an AD converter of a comparative example; A diagram showing an example of the circuit configuration of a ΔΣ modulator according to an embodiment; A diagram showing an example of the circuit state during the first operation Φ1 in the first step of a ΔΣ modulator according to an embodiment; A diagram showing an example of the circuit state during the second operation Φ2 in the first step of a ΔΣ modulator according to an embodiment; A diagram showing an example of the circuit state during the first operation Φ1 in the second step of a ΔΣ modulator according to an embodiment; A diagram showing an example of the circuit state during the second operation Φ2 in the second step of a ΔΣ modulator according to an embodiment;

[0008] Hereinafter, an embodiment will be described with reference to the drawings.

[0009] 1 is a diagram showing an example of the configuration of an AD converter 1 according to an embodiment. As shown in FIG. 1, the AD converter 1 according to an embodiment includes a ΔΣ modulator 100 and a digital filter 200.

[0010] <Configuration of ΔΣ Modulator 100> The ΔΣ modulator 100 can convert an analog signal (e.g., an output signal from a current detection resistor, a sensor, etc.) into a digital signal. The ΔΣ modulator 100 has a configuration in which integration is performed at different orders in the first step and the second step.

[0011] As shown in FIG. 1, the ΔΣ modulator 100 includes switches 101 to 104, an input terminal Vin, an output terminal Q, a first adder 105, a first integrating circuit 110, a second integrating circuit 120, a second adder 130, a quantizer 140, and a digital-to-analog converter DAC.

[0012] The switch 101 is provided between the input terminal Vin and the input of the first adder 105. The switch 101 is switched on in the first step and switched off in the second step.

[0013] The switch 102 is provided between the output of the second integrator circuit 120 and the input of the first adder 105. The switch 102 is switched off in the first step and switched on in the second step.

[0014] The switch 103 is provided between the output of the first integrator circuit 110 and the input of the second integrator circuit 120. The switch 103 is switched on in the first step and switched off in the second step.

[0015] The switch 104 is provided between the input terminal Vin and the input of the quantizer 140. The switch 104 is switched on in a first step and switched off in a second step.

[0016] An analog signal U (for example, an output signal from a current detection resistor, a sensor, etc.) is input to the input terminal Vin.

[0017] The output terminal Q is connected to the output side of the quantizer 140. In the first step, the output terminal Q outputs the first digital signal V1 output from the quantizer 140, and in the second step, the output terminal Q outputs the second digital signal V2 output from the quantizer 140.

[0018] The digital-to-analog converter DAC is connected between the output side of the quantizer 140 and the output terminal Q. In a first step, the digital-to-analog converter DAC converts the first digital signal V1 output from the quantizer 140 into a first feedback analog signal UF1 and outputs the first feedback analog signal UF1. In a second step, the digital-to-analog converter DAC converts the second digital signal V2 output from the quantizer 140 into a second feedback analog signal UF2 and outputs the second feedback analog signal UF2.

[0019] The first adder 105 is provided on the input side of the first integrating circuit 110 .

[0020] In the first step, the first adder 105 generates a first sum signal X0 by adding a signal obtained by amplifying the analog signal U input from the input terminal Vin with a gain b1 and a signal obtained by amplifying the first feedback analog signal UF1 output from the digital-to-analog converter DAC with a gain c1, and outputs the first sum signal X0 to the first integration circuit 110.

[0021] In the second step, the first adder 105 generates a second sum signal X0′ by adding a signal obtained by amplifying the second feedback analog signal UF2 output from the digital-to-analog converter DAC with a gain c1′ and a signal obtained by amplifying the fourth integration signal X2′ output from the second integration circuit 120 with a gain b1′, and outputs the second sum signal X0′ to the first integration circuit 110.

[0022] The first integrating circuit 110 is provided in the subsequent stage of the first adder 105. The first integrating circuit 110 is a so-called delay integrator.

[0023] In the first step, the first integration circuit 110 generates a first integration signal X1 by integrating the first sum signal X0 output from the first adder 105, and outputs the first integration signal X1.

[0024] In the second step, the first integration circuit 110 integrates the second sum signal X0′ output from the first adder 105 to generate a third integration signal X1′, and outputs the third integration signal X1′.

[0025] The second integrating circuit 120 is provided in the subsequent stage of the first integrating circuit 110. The second integrating circuit 120 is a so-called delay-free integrator.

[0026] In the first step, the second integration circuit 120 receives a signal obtained by amplifying the first integration signal X1 output from the first integration circuit 110 by a first gain c2, integrates the signal to generate a second integration signal X2, and outputs the second integration signal X2 to the second adder 130.

[0027] In the second step, the switch 103 is turned off, so that the second integration circuit 120 does not receive a signal from the first integration circuit 110 and functions as a hold amplifier that holds a signal proportional to the quantization error E of the first step (the error generated when the quantizer 40 converts the first signal S1 into the first digital signal V1 in the first step), generates a fourth integration signal X2′ as the quantization error of the first step, and outputs the fourth integration signal X2′ to the second adder 130. That is, in the second step, the fourth integration signal X2′ output from the second integration circuit 120 is the same in all M2 cycles of the second step.

[0028] The second adder 130 is provided in the subsequent stage of the second integration circuit 120. The second adder 130 outputs an output signal generated by adding a plurality of signals to the quantizer 140.

[0029] In the first step, the second adder 130 generates a first signal S1 by adding the analog signal U amplified by the gain b3, the first integrated signal X1 amplified by the gain a1, and the second integrated signal X2 amplified by the gain a2, and outputs the first signal S1 to the quantizer 140.

[0030] In the second step, the second adder 130 generates a second signal S2 by adding the fourth integrated signal X2' amplified by the gain a2' and the third integrated signal X1' amplified by the gain a1', and outputs the second signal S2 to the quantizer 140.

[0031] The quantizer 140 is provided after the second adder 130 .

[0032] In the first step, the quantizer 140 converts the first signal S1 output from the second adder 130 into a first digital signal V1 of, for example, three levels (-1, 0, +1), and outputs the first digital signal V1 to the output terminal Q.

[0033] In the second step, the quantizer 140 converts the second signal S2 output from the second adder 130 into a second digital signal V2 of, for example, three levels (-1, 0, +1), and outputs the second digital signal V2 to the output terminal Q.

[0034] <Configuration of Digital Filter 200 > The digital filter 200 has a first digital integrating circuit 210 and a second digital integrating circuit 220 .

[0035] The first digital integration circuit 210 is a so-called delay-free integrator, which integrates the output signal of the ΔΣ modulator 100 to generate a third digital signal D3 and outputs the third digital signal D3.

[0036] The second digital integration circuit 220 is a so-called delay-free integrator, which generates a fourth digital signal D4 by integrating the third digital signal D3 output from the first digital integration circuit 210, and outputs the fourth digital signal D4.

[0037] Here, the digital filter 200 has a 1 / 2 output unit 230 in the subsequent stage of the first digital integration circuit 210. The digital filter 200 also has a third adder 240 in the subsequent stage of the second digital integration circuit 220.

[0038] The 1 / 2 output unit 230 outputs a seventh digital signal D 5 which is 1 / 2 of the third digital signal D 3 output from the first digital integration circuit 210 .

[0039] In this embodiment, the 1 / 2 output unit 230 outputs a seventh digital signal D5, which is 1 / 2 of the third digital signal D3, by shifting the third digital signal D3 output from the first digital integration circuit 210 by one bit to the right. Here, the right bit shift means moving digital data by a predetermined number of bits toward the smaller digit, and the left bit shift means moving digital data by a predetermined number of bits toward the larger digit.

[0040] As a result, the AD converter 1 according to one embodiment can output the seventh digital signal D5, which is half the third digital signal D3, simply by bit shifting, without performing complex calculations, thereby enabling faster operation.

[0041] The third adder 240 generates a fifth digital signal D1 by subtracting the seventh digital signal D5 (i.e., 1 / 2 of the third digital signal D3 output from the first digital integration circuit 210) from the fourth digital signal D4 output from the second digital integration circuit 220, and outputs the fifth digital signal D1.

[0042] As a result, in the AD converter 1 according to one embodiment, as will be described later with reference to FIG. 3 , the full scale of the output of the digital filter 200 can be calculated using equation (4) described later. Therefore, the full scale of the output of the digital filter 200 can be a power of 2, and the full scale can be kept the same even when the OSR is changed.

[0043] The digital filter 200 also includes a first downsampling circuit 250 (an example of a "first circuit") at the subsequent stage of the third adder 240. The first downsampling circuit 250 receives the fifth digital signal D1 output from the third adder 240 and outputs the result of the M1th cycle (i.e., the final cycle) of the first step.

[0044] The digital filter 200 also includes a second downsampling circuit 260 (an example of a "second circuit") in the subsequent stage of the first digital integration circuit 210. The second downsampling circuit 260 receives the third digital signal D3 output from the first digital integration circuit 210, and outputs the result of the M2th cycle (i.e., the final cycle) of the second step.

[0045] The digital filter 200 also includes a fourth adder 270 that generates an eighth digital signal D by adding the output of the second downsampling circuit 260 to a signal obtained by amplifying the output of the first downsampling circuit 250 with a predetermined gain M2 (i.e., shifting it left by log2(M2) bits), and outputs the eighth digital signal D.

[0046] Although not shown, the AD converter 1 further includes a control unit. For example, the control unit is configured by a digital circuit (ASIC). The control unit switches the switches 101 to 104 on and off, resets the first integrating circuit 110, the second integrating circuit 120, the first digital integrating circuit 210, the second digital integrating circuit 220, the first downsampling circuit 250, and the second downsampling circuit 260. The control unit may be configured by a microcontroller (MCU).

[0047] (Circuit Configuration of the ΔΣ Modulator 100) FIG. 6 is a diagram showing an example of the circuit configuration of the ΔΣ modulator 100 according to an embodiment.

[0048] As shown in FIG. 6, in the ΔΣ modulator 100, the first amplifying and integrating circuit 10, the second amplifying and integrating circuit 20, the second adder 30, and the digital-to-analog converter DAC each include a plurality of switches.

[0049] Specifically, the first amplifying / integrating circuit 10 includes switches SW11 to SW16. The second amplifying / integrating circuit 20 includes switches SW21 to SW27. The second adder 30 includes switches SW31 to SW39. The digital-to-analog converter DAC includes switches SW41 to SW45.

[0050] In Fig. 6, the switch marked with "Φ1" is a switch that is turned on during a first operation Φ1 in Fig. 2, which will be described later. Also, in Fig. 6, the switch marked with "Φ2" is a switch that is turned on during a second operation Φ2 in Fig. 2, which will be described later.

[0051] In addition, in Fig. 6, the switch marked "S1·Φ1" is a switch that is turned on during a first operation Φ1 in the first step in Fig. 2, which will be described later. In addition, in Fig. 6, the switch marked "S1·Φ2" is a switch that is turned on during a second operation Φ2 in the first step in Fig. 2, which will be described later.

[0052] 6, the switch marked with "S2·Φ1" is a switch that is turned on during a first operation Φ1 in the second step of FIG. 2, which will be described later. Also, in FIG. 6, the switch marked with "S2·Φ2" is a switch that is turned on during a second operation Φ2 in the second step of FIG. 2, which will be described later. Here, switches SW21 and SW22 in FIG. 6 correspond to switch 103 in FIG. 1.

[0053] The first amplifying and integrating circuit 10 has a first variable capacitor Cs1 and a third variable capacitor Cf1, and the digital-to-analog converter DAC has a second variable capacitor Cdac.

[0054] The second amplifying and integrating circuit 20 also includes a capacitor Cs2 and a capacitor Cf2. The capacitor Cs2 is composed of two capacitors Cs2 / 2 connected in parallel, each having half the capacitance of the capacitor Cs2.

[0055] The capacitor Cf2 is an example of a configuration that holds the charge of the eighth capacitance, and can continue to hold the fourth integrated signal output from the second amplifying and integrating circuit 20 in the second step.

[0056] The second adder 30 also has a capacitor Cb3 and a capacitor Ca1a2. The second adder 30 also has a threshold setting circuit 31, which has a capacitor Cth and switches SW36 and SW37. The second adder 30 also has an anti-kickback circuit 32, which has a capacitor Chold and switches SW38 and SW39.

[0057] To explain each circuit configuration in detail, the first amplifying and integrating circuit 10 has a capacitor Cs1, a switch SW13, a capacitor Cf1, and a switch SW14 provided in this order on the output side of a switch SW11 to which the output of the second amplifying and integrating circuit 20 is input, and a switch SW12 to which the input voltage Vin is input. A switch SW15 is provided between the switches SW11 and SW12 and the capacitor Cs1. A voltage V ＩＣＭ The output of the digital-to-analog converter DAC and the input terminal of the operational amplifier OP are connected between the switch SW13 and the capacitor Cf1, and the output side of the switch SW14 is connected to the output terminal of the operational amplifier OP.

[0058] In the second amplifying / integrating circuit 20, a capacitor Cs2 / 2 is connected to the output side of a switch SW21 to which the output of the first amplifying / integrating circuit 10 is input. A switch SW24 to which a voltage Vcm is input is provided between the switch SW21 and the capacitor Cs2 / 2. In addition, a capacitor Cs2 / 2 is connected to the output side of a switch SW22 to which the output of the first amplifying / integrating circuit 10 is input. A switch SW23 to which a voltage Vcm is input is provided between the switch SW22 and the capacitor Cs2 / 2. In addition, a switch SW26, a capacitor Cf2, and a switch SW27 are provided in this order on the output sides of the two capacitors Cs2 / 2. A voltage Vcm is connected between the capacitor Cs2 and the switch SW26. ＩＣＭ An input terminal of an operational amplifier OP is connected between the switch SW26 and the capacitor Cf2, and an output terminal of the operational amplifier OP is connected to the output side of the switch SW27.

[0059] The digital-to-analog converter DAC also uses a reference voltage V ＲA second variable capacitor Cdac is provided on the output side of the switches SW41 and SW42 to which a voltage V is input. Also, switches SW44 and SW45 are provided on the output side of the second variable capacitor Cdac. Also, a voltage V is applied between the second variable capacitor Cdac and the switches SW44 and SW45. ＩＣＭ A switch SW43 is provided to which the signal is input.

[0060] The second adder 30 calculates the voltage V Ｒ A capacitor Cth is provided on the output side of switches SW36 and SW37 to which the input voltage Vin is input. A capacitor Cb3 is provided on the output side of switch SW31 to which input voltage Vin is input. A switch SW32 to which voltage Vcm is input is provided between switch SW31 and capacitor Cb3. A capacitor Ca1a2 is provided on the output side of switch SW33 to which the output of second amplifying-integrating circuit 20 is input and switch SW34 to which the output of first amplifying-integrating circuit 10 is input. A kickback prevention circuit 32 is connected to the output sides of capacitors Cth, Cb3, and Ca1a2. A switch SW35 to which voltage Vcm is input is provided between capacitors Cth, Cb3, and Ca1a2 and kickback prevention circuit 32.

[0061] 6, the delta-sigma modulator 100 has the same circuit configuration on the side where Vin+ is input (upper side in the figure) and the side where Vin- is input (lower side in the figure). That is, each of the side where Vin+ is input (upper side in the figure) and the side where Vin- is input (lower side in the figure) has the above-mentioned multiple switches and the above-mentioned multiple capacitors. Therefore, the delta-sigma modulator 100 performs the same signal processing at the same timing on the side where Vin+ is input (upper side in the figure) and the side where Vin- is input (lower side in the figure), except that the input voltage Vin is positive or negative.

[0062] As shown in FIG. 6, the ΔΣ modulator 100 according to one embodiment has an operational amplifier OP shared by the first amplifying and integrating circuit 10 and the second amplifying and integrating circuit 20 .

[0063] Specifically, the first amplifying and integrating circuit 10 is composed of switches SW11 to SW16, a first variable capacitor Cs1, a third variable capacitor Cf1, and a shared operational amplifier OP.

[0064] The second amplifying and integrating circuit 20 is composed of switches SW21 to SW27, a capacitor Cs2, a capacitor Cf2, and a shared operational amplifier OP.

[0065] As a result, the delta-sigma modulator 100 according to one embodiment can reduce the number of operational amplifiers for the integration circuits, which in conventional delta-sigma modulators must be provided for each integration circuit, to just one. Therefore, the delta-sigma modulator 100 according to one embodiment can achieve reduced circuit area and power consumption in the delta-sigma modulator 100 that can operate as both a second-order incremental AD converter and a first-order incremental AD converter.

[0066] In particular, the ΔΣ modulator 100 of one embodiment can be applied to an incremental ADC in a configuration in which the number of operational amplifiers for the integration circuit is one, thereby achieving the advantages of incremental ADCs, such as simplified digital filters and reduced conversion time, and thus enabling further reduction in current consumption in such incremental ADCs.

[0067] Furthermore, the ΔΣ modulator 100 of one embodiment is provided with a first variable capacitor Cs1, a second variable capacitor Cdac, and a third variable capacitor Cf1 so as to satisfy the following mathematical formula (6), and the capacitance of each of these variable capacitors can be changed between a first step and a second step.

[0068] c1' / b1'=c1c2...(6)

[0069] Specifically, in the ΔΣ modulator 100 according to one embodiment, the capacitance of the first variable capacitor Cs1 is variable between a first capacitance Cs1 and a second capacitance Cs1′. The capacitance of the second variable capacitor Cdac is variable between a third capacitance Cdac and a fourth capacitance Cdac′. The capacitance of the third variable capacitor Cf1 is variable between a fifth capacitance Cf1 and a sixth capacitance Cf1′.

[0070] Furthermore, in the delta-sigma modulator 100 according to one embodiment, the second amplifying and integrating circuit 20 includes a seventh capacitor Cs2 and an eighth capacitor Cf2.

[0071] In the ΔΣ modulator 100 according to one embodiment, the gain c1 in the first step is proportional to the third capacitance Cdac / the fifth capacitance Cf1, as shown in Fig. 1. Also, the first gain c2 in the first step is proportional to the seventh capacitance Cs2 / the eighth capacitance Cf2, as shown in Fig. 1.

[0072] Furthermore, the gain c1' in the second step is proportional to the fourth capacitance Cdac' / sixth capacitance Cf1', and the gain b1' in the second step is proportional to the second capacitance Cs1' / sixth capacitance Cf1'.

[0073] Therefore, in the delta-sigma modulator 100 according to one embodiment, by appropriately setting each of the first capacitance Cs1, the second capacitance Cs1′, the third capacitance Cdac, the fourth capacitance Cdac′, the fifth capacitance Cf1, the sixth capacitance Cf1′, the seventh capacitance Cs2, and the eighth capacitance Cf2, the above formula (6) can be satisfied, and thus a conversion result with small error can be obtained. Note that the symbols of the capacitors in the calculation formulas for each gain shown in FIG. 1 are the same as those described above.

[0074] (Operation of the ΔΣ Modulator 100) FIG. 2 is a timing chart showing the operation timing of each control signal in the ΔΣ modulator 100 according to one embodiment.

[0075] As shown in Figure 2, in the first step in which the ΔΣ modulator 100 operates as a second-order incremental AD converter, it has M1 consecutive cycles (where M1 is a natural number), and each cycle includes a first operation Φ1 and a second operation Φ2.

[0076] In the first step, in the first operation Φ1, the first amplifying and integrating circuit 10 samples the input voltage Vin of the analog signal U, the second amplifying and integrating circuit 20 performs an integration operation, and the second adder 30 generates a first signal S1 by adding the input voltage Vin, the output of the first amplifying and integrating circuit 10, and the output of the second amplifying and integrating circuit 20, and outputs the first signal S1 to the quantizer 40.

[0077] In the first step, in the second operation Φ2, the first amplifying and integrating circuit 10 performs an integration operation, the second amplifying and integrating circuit 20 samples the output of the first amplifying and integrating circuit 10, and the second adder 30 samples the output of the first amplifying and integrating circuit 10.

[0078] As shown in FIG. 2, in the first step, the first amplifying and integrating circuit 10 and the second amplifying and integrating circuit 20 are reset by the first reset signal reset1 in the 0th cycle.

[0079] As described above, in the first step, in each of the M1 cycles, during the first operation Φ1, the second adder 30 outputs the first signal S1 to the quantizer 40. Therefore, in the first step, M1 first digital signals V1 are obtained from the quantizer 40.

[0080] Also, as shown in Figure 2, in the second step in which the ΔΣ modulator 100 operates as a first-order incremental AD converter, it has M2 consecutive cycles (where M2 is a natural number), and each cycle includes a first operation Φ1 and a second operation Φ2.

[0081] In the second step, in the first operation Φ1, the first amplifying and integrating circuit 10 samples the output of the second amplifying and integrating circuit 20, the second amplifying and integrating circuit 20 performs a hold operation, and the second adder 30 generates a second signal S2 by adding the output of the first amplifying and integrating circuit 10 and the output of the second amplifying and integrating circuit 20, and outputs the second signal S2 to the quantizer 40.

[0082] In the second step, in the second operation Φ2, the first amplifying and integrating circuit 10 performs an integration operation, the second amplifying and integrating circuit 20 does not perform sampling, and the second adder 30 samples the output of the first amplifying and integrating circuit 10.

[0083] As shown in FIG. 2, in the second step, the first amplifying and integrating circuit 10 is reset by the second reset signal reset2 in the 0th cycle.

[0084] As described above, in the second step, during the first operation Φ1, the second adder 30 outputs the second signal S2 to the quantizer 40 in each of the M2 cycles. Therefore, in the second step, M2 second digital signals V2 are obtained from the quantizer 40.

[0085] (Operation of the ΔΣ Modulator 100) Hereinafter, an example of the operation of the ΔΣ modulator 100 according to one embodiment will be described with reference to FIGS.

[0086] <At the Time of First Operation Φ1 in the First Step> FIG. 7 is a diagram showing an example of the state of the circuit at the time of the first operation Φ1 in the first step of the ΔΣ modulator 100 according to one embodiment.

[0087] As shown in FIG. 7, during the first operation Φ1 in the first step operating as a second-order incremental AD converter, switches SW12, SW16, SW23, SW24, SW26, SW27, SW31, SW33, SW37, SW38, SW42, and SW43 are switched on.

[0088] At this time, in the first amplifying and integrating circuit 10, the switches SW12 and SW16 are turned on, and the analog signal U input from the input terminal Vin+ is sampled by the first variable capacitor Cs1.

[0089] At this time, in the second amplifying and integrating circuit 20, the switches SW23, SW24, SW26, and SW27 are turned on, so that the charge in the capacitor Cs2 is transferred to the capacitor Cf2 and an integrating operation is performed.

[0090] <At the Time of Second Operation Φ2 in the First Step> FIG. 8 is a diagram showing an example of the state of the circuit at the time of the second operation Φ2 in the first step of the ΔΣ modulator 100 according to one embodiment.

[0091] As shown in Fig. 8, during the second operation Φ2 in the first step operating as a second-order incremental AD converter, switches SW13, SW14, SW15, SW21, SW22, SW25, SW32, SW34, SW35, SW36, SW39, and SW41 are switched on. Also, SW44 and SW45 are selectively switched on by the quantizer output Q. Specifically, as the calculation circuit 46 shows the result of calculating the quantizer output Q, the result of ANDing Q[0] and Q[1] is calculated as Q. ＋１ , the result of AND operation of barQ[0] and barQ[1] is Q －１ Let's say. ＋１ When is at high level, SW44 is turned on and Q －１ is at a high level, the SW45 is turned on. Note that "bar" means negative logic.

[0092] At this time, in the first amplifying and integrating circuit 10, the switches SW15, SW13, and SW14 are turned on, so that the charge in the first variable capacitor Cs1 is transferred to the third variable capacitor Cf1, and an integration operation is performed.

[0093] Also, at this time, in the first amplifying and integrating circuit 10, switch SW14 is turned on, and in the second amplifying and integrating circuit 20, switches SW21, SW22, and SW25 are turned on, so that the output of the first amplifying and integrating circuit 10 is sampled by capacitor Cs2 of the second amplifying and integrating circuit 20.

[0094] Here, since the capacitor Cs2 of the second amplifying and integrating circuit 20 is configured to have two capacitors Cs2 / 2 connected in parallel (the part surrounded by dashed lines in the figure), the output of the first amplifying and integrating circuit 10 is sampled half by each of the two capacitors Cs2 / 2 of the second amplifying and integrating circuit 20.

[0095] <At the Time of First Operation Φ1 in the Second Step> FIG. 9 is a diagram showing an example of the state of the circuit at the time of the first operation Φ1 in the second step of the ΔΣ modulator 100 according to one embodiment.

[0096] As shown in FIG. 9, during the first operation Φ1 in the second step operating as a primary incremental AD converter, switches SW11, SW16, SW23, SW26, SW27, SW33, SW37, SW38, SW42, and SW43 are turned on.

[0097] At this time, in the second amplifying and integrating circuit 20, the switch SW27 is turned on, and in the first amplifying and integrating circuit 10, the switches SW11 and SW16 are turned on, so that the output of the second amplifying and integrating circuit 20 is sampled by the first variable capacitor Cs1. Here, the output of the second amplifying and integrating circuit 20 (fourth integrated signal X2') is the result of the hold operation of the second amplifying and integrating circuit 20, and is therefore the same in all M2 cycles of the second step.

[0098] At this time, in the second amplifying and integrating circuit 20, the switches SW23, SW26, and SW27 are turned on, so that the charge sampled in the capacitor Cs2 is transferred to the capacitor Cf2 and an integration operation is performed. However, as will be described later, during the second operation Φ2 in the second step, nothing is sampled in the capacitor Cs2, so no charge is transferred to Cf2, and a hold operation is performed in which the charge on Cf2 is kept constant.

[0099] The second amplifying / integrating circuit 20 integrates the first integrated signal X1 output by the first amplifying / integrating circuit 10 in the second operation Φ2 of the M1th time in the first step, and the signal amplified by the second gain c2' in the first operation Φ1 of the second step, to generate and output a fourth integrated signal X2'. This signal is held in the capacitor Cf2. Next, the first amplifying / integrating circuit 10 integrates the signal held in the capacitor Cf2 (the fourth integrated signal X2') in the first operation Φ1 after cycle 1 in the second step, and the signal amplified by the fifth gain b1' in the second operation Φ2, to generate and output a third integrated signal X1'.

[0100] Here, of the two capacitors Cs2 / 2 (enclosed by dashed lines in the figure) that make up capacitor Cs2, the charge of one (upper in the figure) capacitor Cs2 / 2 is not transferred to capacitor Cf2 because switch SW24 is off, and the charge of the other (lower in the figure) capacitor Cs2 / 2 is transferred to capacitor Cf2, resulting in half of the charge output from first amplifying and integrating circuit 10 being transferred to capacitor Cf2. With this configuration, in the gain of the signal input from the output of first amplifying and integrating circuit 10 to second amplifying and integrating circuit 20, gain c2' in the second step can be set to half of gain c2 in the first step.

[0101] In the second step, the control unit changes the capacitance of each of the first variable capacitor Cs1, the second variable capacitor Cdac, and the third variable capacitor Cf1 (the areas surrounded by dotted lines in the figure) so as to satisfy the above-mentioned formula (6). As a result, according to the delta-sigma modulator 100 of one embodiment, the relationship between the gain c1′ and gain b1′ used in the second step and the gain c1 and first gain c2 used in the first step can satisfy the above-mentioned formula (6), thereby making it possible to obtain a conversion result with a small error.

[0102] <At the Time of Second Operation Φ2 in the Second Step> FIG. 10 is a diagram showing an example of the state of the circuit at the time of the second operation Φ2 in the second step of the ΔΣ modulator 100 according to one embodiment.

[0103] 10, during the second operation Φ2 in the second step operating as a primary incremental AD converter, switches SW13, SW14, SW15, SW25, SW34, SW35, SW36, SW39, and SW41 are switched on. Also, SW44 and SW45 are selectively switched on by the quantizer output Q. Specifically, as the calculation circuit 46 shows the result of calculating the quantizer output Q, the result of ANDing Q[0] and Q[1] is calculated as Q. ＋１ , the result of AND operation of barQ[0] and barQ[1] is Q －１ Let's say. ＋１ When is at high level, SW44 is turned on and Q －１ is at a high level, the SW45 is turned on. Note that "bar" means negative logic.

[0104] At this time, in the first amplifying and integrating circuit 10, the switches SW15, SW13, and SW14 are turned on, so that the charge in the first variable capacitor Cs1 is transferred to the third variable capacitor Cf1, and an integration operation is performed.

[0105] At this time, in the second amplifying / integrating circuit 20, the switches SW21 and SW22 remain off, and nothing is sampled onto the capacitor Cs2. Therefore, in the second step, the capacitor Cf2 continues to hold the output (fourth integrated signal X2′) of the second amplifying / integrating circuit 20.

[0106] As shown in Figures 8 and 10, in both the first step and the second step, during the second operation Φ2, the second adder 30 samples the output of the first amplifying and integrating circuit 10 by switching on the switches SW34 and SW35.

[0107] 7 , during the first operation Φ1 in the first step, the second adder 30 receives the input voltage Vin as a result of the switch SW31 being turned on, and receives the output of the second amplifying and integrating circuit 20 as a result of the switch SW33 being turned on. The second adder 30 adds the output of the first amplifying and integrating circuit 10, the input voltage Vin, and the output of the second amplifying and integrating circuit 20, and outputs the result to the quantizer 40.

[0108] 9 , during the first operation Φ1 in the second step, the switch SW33 is turned on, and the output of the second amplifying and integrating circuit 20 is input to the second adder 30. The second adder 30 then adds the output of the first amplifying and integrating circuit 10 and the output of the second amplifying and integrating circuit 20, and outputs the result to the quantizer 40.

[0109] In the first step, the first gain c2 is used as the gain when amplifying the output of the first integrating circuit 110 (first integrated signal X1). Meanwhile, in the second step, the second integrating circuit 120 generates a fourth integrated signal by integrating the signal obtained by amplifying the output of the first integrating circuit 110 (first integrated signal X1) with the second gain c2' in the first cycle. That is, in the second step, the second gain c2' is used instead of the first gain c2 as the gain when amplifying the output of the first integrating circuit 110. The second gain c2' is half the first gain c2. As a result, the AD converter 1 according to one embodiment can solve the problem of the width of 1 LSB (Least Significant Bit) of the digital output becoming inconsistent, which occurs when the full scale of the output of the digital filter 200 is raised to a power of 2, and can make the width of 1 LSB of the digital output evenly spaced.

[0110] For example, the ΔΣ modulator 100 has two capacitors Cs2 / 2 that determine the gain when amplifying the output (first integrated signal X1) of the first amplifying and integrating circuit 10, and in a first step, transfers charge from both of the two capacitors Cs2 / 2, and in a second step, transfers charge from only one of the two capacitors Cs2 / 2, thereby changing the gain when amplifying the output (first integrated signal X1) of the first amplifying and integrating circuit 10 from the first gain c2 (= Cs2 / Cf2) to the second gain c2' (= Cs2 / 2 / Cf2).

[0111] It should be noted that the band limiting effect of the digital filter 200 is obtained only in the first step, and the second step is operated to make the full scale of the output of the digital filter 200 a power of two.

[0112] For this reason, in the AD converter 1 according to one embodiment, the number of cycles M2 of the second step is preferably less than the number of cycles M1 of the first step, thereby enabling the AD converter 1 according to one embodiment to enhance the band limiting effect achieved by the digital filter 200.

[0113] Furthermore, in the AD converter 1 according to one embodiment, when the quantization level of the quantizer 140 is even, it is preferable that the number of cycles in the second step M2 = 1, and when the quantization level of the quantizer 140 is odd, it is preferable that the number of cycles in the second step M2 = 2. This allows the AD converter 1 according to one embodiment to minimize the number of cycles in the second step, thereby maximizing the band limiting effect achieved by the digital filter 200.

[0114] Here, the problem of the AD converter of the comparative example will be described with reference to Fig. 5. Fig. 5 is a diagram for explaining an example of the problem of the AD converter of the comparative example. Note that the configuration of the conventional AD converter is the same as that of AD converter 1 shown in Fig. 1 except that 1 / 2 output unit 230 of digital filter 200 is removed.

[0115] In the AD converter of the comparative example, the full scale of the output of the digital filter is calculated by the following formula (1).

[0116] b1 / c1・M1(M1+1) / 2・M2...(1)

[0117] where b1 is the gain used when amplifying the input signal, c1 is the gain used when amplifying the first feedback analog signal output from the digital-to-analog converter, M1 is the number of cycles in the first step, and M2 is the number of cycles in the second step.

[0118] For this reason, in conventional digital filters, the full scale of the output of the digital filter cannot be a power of 2. This causes a problem in that when the OSR (Oversampling Ratio) is changed, the magnitude of the full scale of the output of the digital filter changes.

[0119] For example, as shown in Figure 5(a), when b1 / c1 = 1, M1 = 64, and M2 = 32, the full scale of the output of the digital filter is -66566 to +66566 according to the above formula (1), and therefore cannot be expressed as a power of 2. In this case, if the value is shifted 2 bits to the right when stored in a 16-bit register, it becomes -16641 to +16641. Therefore, in this case, the formula for calculating the analog input voltage is the following formula (2).

[0120] Analog input voltage = digital value / 16641 × Vref (2)

[0121] Also, for example, as shown in Figure 5(b), if b1 / c1 = 1, M1 = 32, and M2 = 16, the full scale of the output of the digital filter will be -8448 to +8448 according to the above formula (1), and cannot be expressed as a power of 2. In this case, if the value is shifted one bit to the left when stored in a 16-bit register, it will become -16896 to +16896. Therefore, in this case, the formula for calculating the analog input voltage is the following formula (3).

[0122] Analog input voltage = digital value / 16896 × Vref (3)

[0123] In this way, in a conventional AD converter, when the OSR is changed, the full-scale magnitude of the output of the digital filter changes, and therefore the formula for calculating the analog input voltage also changes. Note that the technology of Patent Document 1 cannot solve this problem.

[0124] (Effects of the Digital Filter 200) FIG. 3 is a diagram for explaining an example of the effects of the digital filter 200 according to an embodiment.

[0125] In the AD converter 1 according to one embodiment, as described above, by subtracting half of the output of the first digital integration circuit 210 of the digital filter 200 from the output of the second digital integration circuit 220, the full scale of the output of the digital filter 200 is calculated by the following equation (4), and is therefore a power of 2.

[0126] b1 / c1・M1 ２ / 2・M2...(4)

[0127] For example, as shown in Figure 3A, when b1 / c1 = 1, M1 = 64, and M2 = 32, the full scale of the output of the digital filter 200 according to one embodiment is -65536 to +65536, and can therefore be expressed as a power of 2. In this case, if the value is shifted one bit to the right when stored in a 16-bit register, it becomes -32768 to +32768. Therefore, in this case, the formula for calculating the analog input voltage is the following formula (5).

[0128] Analog input voltage = digital value / 32768 × Vref (5)

[0129] 3B, for example, when b1 / c1 = 1, M1 = 32, and M2 = 16, the full scale of the output of the digital filter 200 according to one embodiment is −8192 to +−8192, which can be expressed as a power of 2. In this case, if the value is shifted left by 2 bits when stored in a 16-bit register, it becomes −32768 to +32768. Therefore, in this case, the formula for calculating the analog input voltage is the above formula (5).

[0130] In this way, in the AD converter 1 according to one embodiment, when the OSR is changed, the full-scale magnitude of the output of the digital filter can be made equal, and therefore the formula for calculating the analog input voltage can be made the same.

[0131] (Signal Processing by Digital Filter 200) Fig. 4 is a diagram for explaining an example of signal processing by the digital filter 200 according to an embodiment. Fig. 4 illustrates signal processing by the digital filter 200 when b1 / c1 = 1, M1 = 64, and M2 = 32.

[0132] In FIG. 4, the signal processing from the first stage to the fourth stage from the top is performed in the first step.

[0133] The first row from the top shows an example of the output range of the third digital signal D3 output from the first digital integration circuit 210. In this example, M1=64, and the third digital signal D3 is anywhere from −64 to +64.

[0134] The second row from the top shows an example of the output range of the seventh digital signal D5, which is half the third digital signal D3 and is generated by shifting the third digital signal D3 to the right by one bit using the 1 / 2 output unit 230. In this example, the seventh digital signal D5 is anywhere from −32 to +32, with the minimum resolution being 0.5.

[0135] The third row from the top shows an example of the output range of the fourth digital signal D4 output from the second digital integration circuit 220. In this example, the fourth digital signal D4 is M1×(M1+1) / 2=2080, which is either −2080 to +2080.

[0136] The fourth row from the top shows an example of the output range of the fifth digital signal D1 generated by subtracting half of the third digital signal D3 from the fourth digital signal D4. In this example, the fifth digital signal D1 is 2080-32=2048, which is anywhere from -2048 to +2048. However, the minimum resolution is 0.5. Here, the full scale of the fifth digital signal is 2048*2=2^12, which is a power of 2.

[0137] In Figure 4, the fifth signal processing step from the top is the signal processing performed in the second step. In this example, M2 = 32, and the fifth digital signal D1 is shifted left by 5 bits (log2(M2) bits) to generate the ninth digital signal D6. This processing adds the sixth digital signal D2 obtained in the second step to the fifth digital signal D1 obtained in the first step. Note that the lower seven bits where the ninth digital signal D6 and the sixth digital signal D2 overlap are input as the result of adding the lower three bits of the fifth digital signal D1 and the upper three bits of the sixth digital signal D2. As a result, the quantization error of the first step is corrected with the result of further integration in the second step, thereby reducing the final quantization error. Here, the ninth digital signal D6 is anywhere from -2048*2^5 to +2048*2^5. However, the minimum resolution is 2^4.

[0138] The sixth row from the top shows an example of the output range of the sixth digital signal D2 output from the first digital integration circuit 210 in the second step. In this example, M2=32, and the sixth digital signal D2 is anywhere from −32 to +32.

[0139] The seventh row from the top shows the eighth digital signal D generated by adding the fifth digital signal D1 obtained in the first step to the sixth digital signal D2 obtained in the second step. Here, the sixth digital signal D2 is −32 to +32 (7 bits), and the ninth digital signal D6 is the fifth digital signal D1 shifted left by 5 bits. There is a three-bit overlap between the sixth digital signal D2 and the ninth digital signal D6. This portion is where the digital signal obtained in the first step is corrected with the digital signal obtained in the second step. In this example, the full scale of the eighth digital signal D is 65536*2=2^17, which is a power of 2.

[0140] The eighth and ninth rows from the top show the process for storing the eighth digital signal D in a 16-bit register. A bit shift circuit (not shown) included in the digital filter 200 shifts the sixth digital signal D2 to the right by one bit, and then truncates the most significant bit by overflow processing before storing it in the 16-bit register. In this example, the eighth digital signal D stored in the register is any value between −32768 and +32767 (16 bits).

[0141] In this way, the AD converter 1 according to one embodiment can store the eighth digital signal D, whose full scale is a power of 2, in a register by simply performing simple calculations using bit shifts and addition / subtraction, without performing complex calculations.

[0142] Although one embodiment of the present invention has been described in detail above, the present invention is not limited to these embodiments, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

[0143] This international application claims priority based on Japanese Patent Application No. 2024-143426, filed on August 23, 2024, the entire contents of which are incorporated herein by reference.

[0144] 1 AD converter 100 ΔΣ modulator 101 to 104 Switch Vin Input terminal U Analog signal Q Output terminal 105 First adder 110 First integrator circuit 120 Second integrator circuit 130 Second adder 140 Quantizer DAC Digital-to-analog converter VF1 First digital signal UF1 First feedback analog signal VF2 Second digital signal UF2 Second feedback analog signal S1 First signal S2 Second signal X0 First sum signal X0' Second sum signal X1 First integrated signal X2 Second integrated signal X1' Third integrated signal X2' Fourth integrated signal a1, a1', a2, a2', b1, c1, c1', b3 Gain c2 First gain c2' Second gain 200 Digital filter 210 First digital integrating circuit 220 Second digital integrating circuit 230 1 / 2 output unit 240 Third adder 250 First downsampling circuit (first circuit) 260 Second downsampling circuit (second circuit) 270 Fourth adder M1, M2 Number of cycles D Eighth digital signal D1 Fifth digital signal D2 Sixth digital signal D3 Third digital signal D4 Fourth digital signal D5 Seventh digital signal D6 Ninth digital signal

Claims

1. A delta-sigma modulator having an input terminal to which an input signal is input, a first amplifying and integrating circuit, a second amplifying and integrating circuit, an adder, a quantizer, and a digital-to-analog converter; and a digital filter having a first digital integrating circuit that outputs a third digital signal generated by integrating the output signal of the delta-sigma modulator, and a second digital integrating circuit that outputs a fourth digital signal generated by integrating the third digital signal, wherein the delta-sigma modulator has, in a first step, the digital-to-analog converter converts the first digital signal output from the quantizer into a first feedback analog signal; the first amplifying and integrating circuit generates a first integrated signal by integrating a signal obtained by adding a signal obtained by amplifying the input signal with a predetermined gain and a signal obtained by amplifying the first feedback analog signal with a predetermined gain; and the second amplifying and integrating circuit generates a second integrated signal by integrating a signal obtained by amplifying the first integrated signal with a first gain. the adder outputs a first signal generated by adding a signal obtained by amplifying the input signal with a predetermined gain, a signal obtained by amplifying the first integrated signal with a predetermined gain, and a signal obtained by amplifying the second integrated signal with a predetermined gain; the quantizer outputs a first digital signal generated by converting the first signal output from the adder; in a second step, the digital-to-analog converter converts the second digital signal output from the quantizer into a second feedback analog signal; the second amplifying and integrating circuit generates a fourth integrated signal by integrating a signal obtained by amplifying the first integrated signal with a second gain; the first amplifying and integrating circuit generates a third integrated signal by integrating a signal obtained by adding a signal obtained by amplifying the fourth integrated signal with a predetermined gain and a signal obtained by amplifying the second feedback analog signal with a predetermined gain; the adder adds the signal obtained by amplifying the third integrated signal with a predetermined gain and the signal obtained by amplifying the fourth integrated signal with a predetermined gain; the quantizer outputs a second digital signal generated by converting the signal output from the adder; and the digital filteran AD converter that outputs a fifth digital signal generated by subtracting half of the third digital signal from the fourth digital signal; 2. The AD converter according to claim 1, wherein the digital filter generates the fifth digital signal by shifting the third digital signal one bit to the right and subtracting the third digital signal after the one-bit shift from the fourth digital signal.

3. The AD converter described in claim 1, characterized in that the first step is performed consecutively M1 times (M1 is a natural number) in cycles, the second step is performed consecutively M2 times (M2 is a natural number) in cycles, the second amplifying and integrating circuit generates the fourth integrated signal in the second step, and the second gain is 1 / 2 of the first gain.

4. The AD converter described in claim 1, characterized in that the first step is performed in succession M1 cycles (M1 is a natural number), the second step is performed in succession M2 cycles (M2 is a natural number), the digital filter further comprises a first circuit to which the fifth digital signal is input, and the first circuit outputs the result of the M1th cycle of the first step.

5. The AD converter according to claim 4, characterized in that the digital filter further comprises a second circuit to which the third digital signal is input, and the second circuit outputs the result of the M2th cycle of the second step.

6. The AD converter according to claim 5, characterized in that the digital filter includes an adder that generates an eighth digital signal by adding a signal obtained by shifting the output of the first circuit left by log2 (M2) bits to the output of the second circuit, and outputs the eighth digital signal.

7. The AD converter according to claim 6, wherein the digital filter comprises a bit-shift circuit that bit-shifts the eighth digital signal and stores the bit-shifted eighth digital signal in a register.

8. The AD converter according to claim 1, characterized in that the first step is performed in cycles M1 times (M1 is a natural number) consecutively, and the second step is performed in cycles M2 times (M2 is a natural number) consecutively, and M2 is less than M1.

9. The AD converter according to claim 8, wherein M2=1 when the quantization level of the quantizer is an even number, and M2=2 when the quantization level of the quantizer is an odd number.

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