Circuit and method of operation of circuit

Abstract

To provide a circuit including a penetration protection, and an operation method for the same.SOLUTION: A circuit includes: first and second transistors that are connected in series; a third transistor (TT) having a source connected to a source of the second transistor (ST), a gate connected to a gate of the second transistor (ST), and a drain connected to a gate of the first transistor (FT); and a gate driver circuit connected to the gates of FT, ST, and TT, in which (i) FT is transited between an ON state and an OFF state by provision of a first driving signal to the gate of FT, and (ii) ST and TT are transited between an ON state and an OFF state by provision of a second driving signal to the gates of ST and TT. TT is configured to prevent a penetration state in the circuit by lowering the first driving signal to the level of the source of ST when ST is in the ON state.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a shoot-through protection circuit. [Background technology]

[0002] Electrical circuits, such as those used in satellites and spacecraft, have a variety of power requirements. Direct current (DC) to alternating current (AC) conversion and DC to DC conversion involve a bridge circuit using two pairs of series-arranged transistors that are alternately switched to provide the appropriate power conversion. Each series-arranged transistor pair includes an upper switch and a lower switch. Circuit shoot-through, or short-circuiting, occurs when both the upper and lower switches are turned on simultaneously. This can occur, for example, in space applications, as a result of high-energy particles striking drive circuit components. The duration of such a condition can reach 10 μs, resulting in the affected switches overheating and failing. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE INVENTION The object of the present invention is therefore to improve a circuit of the kind mentioned at the outset so that the above-mentioned disadvantages are reduced. [Means for solving the problem]

[0004] The present specification relates to a circuit comprising: first and second transistors connected in series; a third transistor having a source connected to the source of the second transistor, a gate connected to the gate of the second transistor, and a drain connected to the gate of the first transistor; and a gate driver circuit connected to the gates of the first, second, and third transistors and configured to (i) provide a first drive signal to the gate of the first transistor to transition the first transistor between an on state and an off state, and (ii) provide a second drive signal to the gates of the second and third transistors to transition the second and third transistors between an on state and an off state, wherein the third transistor is configured to prevent a short-through condition in the circuit by pulling the first drive signal down to the level of the source of the second transistor when the second transistor is in an on state.

[0005] This specification also relates to implementations of systems and methods for operating a circuit, the method including providing, by a gate driver circuit, a first high drive signal to a gate of a first transistor and a first low drive signal to a gate of a second transistor and to a gate of a third transistor connected in series with the first transistor (to transition the first transistor to an ON state and the second and third transistors to an OFF state), simultaneously providing a second high drive signal from the gate driver circuit to the gates of the second and third transistors to transition the second and third transistors from an OFF state to an ON state while the first transistor is still in an ON state, and using the second transistor to prevent shoot-through by pulling down the voltage of the first high drive signal output from the gate driver circuit to a level that transitions the first transistor from an ON state to an OFF state while the third transistor is in an ON state.

[0006] The present specification further relates to a circuit comprising first and second transistors of a P-channel type connected in series, a third transistor having a source connected to the source of the second transistor, a gate connected to the gate of the second transistor, and a drain connected to the gate of the first transistor, and a gate driver circuit connected to the gates of the first, second, and third transistors and configured to (i) provide a first drive signal to the gate of the first transistor to transition the first transistor between an on state and an off state, and (ii) provide a second drive signal to the gates of the second and third transistors to transition the second and third transistors between an on state and an off state, The third transistor is also of a P-channel type and configured to prevent shoot-through conditions in the circuit by pulling the first drive signal to the level of the source of the second transistor when the second transistor is in an on state.

[0007] The present disclosure will be readily understood by reference to the following drawings, in which like numbers represent like items throughout. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating a satellite. [Figure 2] FIG. 1 is a diagram illustrating a transistor active bridge circuit. [Figure 3] FIG. 1 illustrates a pair of series transistors. [Figure 4] FIG. 4 illustrates a pair of series transistors shown in FIG. 3 with shoot-through protection. [Figure 5] FIG. 4 illustrates a pair of series transistors shown in FIG. 3 with shoot-through protection. [Figure 6] FIG. 1 shows a bridge converter implementing the solution. [Figure 7] FIG. 1 illustrates a flow diagram of a method for operating a circuit. [Figure 8] FIG. 4 illustrates a pair of series transistors shown in FIG. 3 with shoot-through protection. DETAILED DESCRIPTION OF THE INVENTION

[0009] It will be readily understood that the solutions described herein and illustrated in the accompanying figures may include a variety of different configurations. Accordingly, the following more detailed description, as illustrated in the figures, is not intended to limit the scope of the disclosure but merely represents specific implementations in various scenarios. While various aspects are illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0010] The solution may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are intended in all respects to be illustrative only and not restrictive. The scope of the solution is therefore indicated by the appended claims, rather than by this detailed description. All changes that come within the meaning and range of equivalency of the claims are embraced within their scope.

[0011] References to features, advantages, or similar terms throughout this specification do not imply that all features and advantages that may be realized should or are present in any single embodiment of the invention. Rather, terms referring to features and advantages are understood to mean that the particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Thus, discussions of features and advantages and similar terms throughout this specification do not necessarily refer to the same embodiment, but may.

[0012] References throughout this specification to "one embodiment," "an embodiment," or similar terms mean that a particular feature, structure, or characteristic described in connection with the illustrated embodiment is included in at least one embodiment of the solution. Thus, references throughout this specification to "in one embodiment," "in an embodiment," and similar terms do not necessarily refer to the same embodiment, but may.

[0013] As used herein, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. As used herein, the term "comprising" means "including, but not limited to."

[0014] As used herein, when terms such as "first" and "second" are used to modify nouns, such use is intended merely to distinguish one item from another and is not intended to require sequential order, unless otherwise specified.

[0015] As mentioned above, shoot-through or short-circuiting in a bridge converter occurs when both the upper and lower switches are turned on simultaneously. This can occur, for example, in space applications as a result of high-energy particles striking drive circuit components. Noise or other events can additionally or alternatively cause a shoot-through condition. The duration of such a shoot-through condition can reach 10 μs, leading to overheating and failure of the affected switch. Shoot-through protection is typically based on a very fast-acting current-sensing circuit. The current-sensing circuit is often connected in series with the bridge converter's transistors, below the lower transistor. The current-sensing circuit is specially designed to be insensitive to normal currents and only detect relatively high currents above one or more thresholds. The current-sensing circuit increases the complexity, mass, and cost of the bridge converter.

[0016] The present solution provides a new shoot-through protection circuit that addresses the shortcomings of conventional current sensing solutions. The present solution can be used in a variety of applications, including, but not limited to, transistor active bridge applications, transistor bridge converter applications, transistor switching circuit applications, and / or any other application where shoot-through protection is required. The present solution can be used in transistor circuits designed for terrestrial, aeronautical, and / or space applications.

[0017] FIG. 1 is a diagram of a satellite 100 implementing the present solution. The satellite 100 includes a power source 102 that provides power to a load 104 via a power distribution circuit 106. The load 104 may include, but is not limited to, an electric propulsion unit. One or more transistor active bridge circuits are used in the power distribution circuit 106 to condition and distribute power from the power source 102 to the load 104. If a shoot-through overcurrent condition occurs in one or more of the transistor active bridge circuits, the power distribution circuit 106 may be damaged. The present solution can be added to the transistor active bridge circuits to protect the power distribution circuit 106. The present solution is described in more detail below. However, an exemplary architecture of a transistor active bridge circuit will first be briefly described.

[0018] FIG. 2 shows a diagram of an example architecture of a transistor active bridge circuit 200. The transistor active bridge circuit 200 is useful for a variety of purposes, such as AC to DC conversion and DC to DC conversion. As can be seen from FIG. 2, a voltage waveform is supplied to the transistor active bridge circuit 200. The voltage waveform may be an AC voltage waveform or a DC voltage waveform. Thus, the transistor active bridge circuit 200 is connectable to at least one voltage source 202 via two input lines 204 and 206. The transistor active bridge circuit 200 is also connected between a pair of output lines 264 and 266. The output lines 264 and 266 may be connected across a load (e.g., load 104 in FIG. 1), thereby allowing the transistor active bridge circuit 200 to provide an output voltage to the load.

[0019] The transistor active bridge circuit 200 includes multiple field-effect transistors (FETs) 208, 210, 212, and 214 of either the N-channel type (shown in FIG. 2) or the P-channel type (shown in FIG. 8). Each FET may include a metal-oxide semiconductor FET (MOSFET). The MOSFETs may be enhancement-mode MOSFETs. Each FET 208, 210, 212, and 214 may include, but is not limited to, a gallium nitride FET. In some scenarios, each FET 208, 210, 212, and 214 is selected to comprise a transistor with part number EPC7020, available from EPC Space LLC of Andover, Massachusetts. Other FETs may also be selected depending on the expected voltage and current handling requirements of the transistor active bridge circuit 200. Similar shoot-through protection (both N-channel and P-channel) can be achieved with bipolar junction transistors (BJTs) (both NPN and PNP) and an insulated gate bipolar transistor (IGBT) for the third switch (in which case a FET may be used instead of an IGBT).

[0020] Each FET 208, 210, 212, and 214 has three terminals defined as a source, a gate, and a drain. For FET 208, the source, gate, and drain terminals are identified by reference numerals 216, 218, and 220, respectively. For FET 210, the source, gate, and drain terminals are identified by reference numerals 222, 224, and 226, respectively. The source, gate, and drain terminals of FETs 212 and 214 are identified as 228, 230, 232, and 234, 236, and 238, respectively.

[0021] An electrical path is provided from the source to the drain of each FET 208, 210, 212, 214. This path is generally referred to herein as the source-drain path. The source-drain path of the first FET 208 is connected in series with the source-drain path of the second FET 210. The series-connected transistor pair 208, 210 form a first series transistor combination connected between the input lines 204, 206. The source-drain path of the third FET 212 is connected in series with the source-drain path of the fourth FET 214 to form a second series transistor combination connected between the input lines 204, 206.

[0022] The transistor active bridge circuit 200 may have outputs defined by output lines 264, 266. A first one of the output lines 264 may be connected to the first series combination 208, 210 at an interconnection point 254 between the first field effect transistor 208 and the second field effect transistor 210. A second one of the output lines 266 may be connected to the second series combination 212, 214 at an interconnection point 256 between the third field effect transistor 212 and the fourth field effect transistor 214.

[0023] Each FET 208, 210, 212, 214 is provided with a gate driver circuit 270, 272, 274, 276. Each gate driver circuit 270, 272, 274, 276 is typically configured to apply a voltage to the gate 218, 224, 230, 236 of the respective FET 208, 210, 212, 214 at a particular time to switch the FET to an "on" or "off" state. The voltage applied to the gate 218, 224, 230, 236 of each FET 208, 210, 212, 214 has an "on" or "off" state voltage value selected depending on the particular field effect transistor application. Each gate driver circuit 270, 272, 274, 276 is also typically configured to remove voltage from the gate 218, 224, 230, 236 of each FET 208, 210, 212, 214 at a particular time to switch the FET to an "on" or "off" state. Gate driver circuits are well known. Any known or future known gate driver circuit can be used herein.

[0024] Transistor active bridge circuit 200 also includes devices that ensure each FET 208, 210, 212, 214 switches to an "on" state and / or an "off" state at the desired times.

[0025] The operation of transistor active bridge circuit 200 will now be described. In some scenarios, one FET will be switched to the "on" state while the other three FETs are in the "off" state. In other scenarios, two FETs (one from each series transistor pair) will be switched to the "on" state simultaneously or in parallel while the other two FETs are in the "off" state. The latter case will be described in more detail below.

[0026] When the gate driver circuits 270, 276 transmit gate control signals to the FETs 208, 214, the FETs 208, 214 are biased and switched to an "on" state. In effect, current flows between the drains 220, 238 and sources 216, 234 of these FETs 208, 214. When the gate driver circuits 270, 276 no longer output gate control signals, the FETs 208, 214 return to an "off" state.

[0027] Similarly, gate driver circuits 272, 274 transmit gate control signals to FETs 210, 212, biasing them to an "on" state. In effect, current flows between the drains 226, 232 and sources 222, 228 of these FETs 208, 214. When the gate control signals are no longer output from gate driver circuits 272, 274, FETs 210, 212 return to an "off" state.

[0028] The gate driver circuits 270, 272, 274, and 276 are configured to prevent the two FETs in each series pair 208 / 210 and 212 / 214 from being "on" simultaneously or in parallel. The FETs 208, 210, 212, and 214 are alternately switched by the gate driver circuits 270, 272, 274, and 276 to provide a constant power output on the output lines 264 and 266.

[0029] However, there may be cases where both FETs in one or more pairs are turned "on" simultaneously or in parallel, for example, as a result of a high-energy particle striking the gate driver circuit, creating a shoot-through condition in the transistor active bridge circuit 200. If this condition persists, the affected FETs may overheat and fail.

[0030] The present solution addresses this shoot-through problem by adding an additional switch to each pair of FETs. The solution is described below in relation to a single pair of FETs; this description is sufficient to understand the solution in relation to both FET pairs in transistor active bridge circuit 200.

[0031] A pair of FETs 300 is shown in FIG. 3 as comprising FETs 208 and 210 of FIG. 2. The solution is not limited in this respect. The pair of FETs may also include FETs 212 and 214 of FIG. 2 or other types of FETs. The solution is described below with reference to pair of FETs 300. This description is sufficient to understand the solution with reference to FETs 212 and 214 of FIG. 2 or other types of FETs.

[0032] 4 provides an illustration of a circuit 400 with shoot-through protection for a pair of FETs 300. The shoot-through protection is provided by including a transistor 402 that is configured to prevent the voltage at the gate 218 of the upper switch 208 from being positive with respect to the source 216 of the upper switch 208 when the gate 224 of the lower switch 210 is positive with respect to the source 222 of the lower switch 210.

[0033] The transistor 402 includes an N-channel (shown in FIG. 4) or P-channel (shown in FIG. 8) FET. The FET 402 may comprise a MOSFET. The MOSFET may be an enhancement-mode MOSFET. The FET 402 may include, but is not limited to, a gallium nitride FET. The FET 402 has three terminals defined as a source, a gate, and a drain. With respect to the FET 402, the source, gate, and drain terminals are identified by reference numerals 404, 406, and 408, respectively. The source 404 is connected to the source 222 of the FET 210. The gate 406 is connected to a drive line 282 extending from the output of the gate driver circuit 272 and the gate of the lower FET 210 of the pair 400. The drain 408 is connected to a drive line 280 extending from the output of the gate driver circuit 270 and the gate 218 of the upper FET 208 of the pair 400. Optionally, resistors 410, 412 may be placed between the drain 408 of the FET 402 and the gate 218 of the FET 208 to limit or regulate the flow of current.

[0034] In operation, a high drive signal is provided by gate driver circuit 270 to gate 218 of upper FET 208 of the series pair, and a low drive signal is provided by gate driver circuit 272 to gate 224 of lower FET 210 of the series pair. Thus, upper FET 208 is in an "on" state, and lower FET 210 is in an "off" state. Note that a low drive signal is also provided by gate driver circuit 272 to gate 406 of feed-through protection FET 402. Thus, feed-through protection FET 402 is in an "off" state, upper FET 208 is in an "on" state, and lower FET 210 is in an "off" state.

[0035] When an event occurs (e.g., a noise or high radiation event) that causes the gate driver circuit 272 to provide a high drive signal to the gate 224 of the lower FET 210, the FET 210 transitions from an "off" state to an "on" state, and a shoot-through condition occurs because both series FETs 208, 210 are simultaneously in the "on" state.

[0036] In particular, a high drive signal is also provided from the gate driver circuit 272 to the gate 406 of the feed-through protection FET 402. In response to the high drive signal, the feed-through protection FET 402 transitions to an "on" state. At this time, the feed-through protection FET 402 pulls down the drive signal provided to the gate 218 of the upper FET 208. In effect, a low drive signal is provided to the gate 218 of the upper FET 208, even though the gate driver circuit 270 is still configured to continue to output a high drive signal to the drive line 280. The low drive signal on the gate 218 causes the upper FET 208 to transition to an "off" state, while the lower FET 210 remains in an "on" state. This prevents potential damage to the upper FET 208 and the lower FET 210 by actively removing, interrupting, or preventing the feed-through condition.

[0037] In another scenario, a high drive signal is provided by the gate driver circuit 272 to the gate 224 of the lower FET 210, and a low drive signal is provided by the gate driver circuit 270 to the gate 218 of the upper FET 208. At this time, the lower FET 210 is in an "on" state, and the upper FET 208 is in an "off" state. In particular, the gate driver circuit 272 also provides a high drive signal to the gate 406 of the feed-through protection FET 402. Because the feed-through protection FET 402 is in an "on" state, it prevents the high drive signal from being provided to the gate 218 of the upper FET 208. In other words, the feed-through protection FET 402 prevents the upper FET 208 from being turned "on" when the lower FET 210 is in an "on" state.

[0038] As is apparent from the above description, feed-through protection FET 402 ensures that a low drive signal is provided to gate 218 of upper FET 208 whenever lower FET 210 is in the "on" state. This is accomplished by pulling gate 218 of upper FET 208 down to the level of source 222 of lower FET 210 whenever lower FET 210 is in the "on" state. This feature of feed-through protection FET 402 reduces or eliminates the possibility of damage to series FETs 208, 210 during operation of circuit 400.

[0039] 5 is a diagram of a circuit 500 with shoot-through protection for a pair of FETs 300. The shoot-through protection is provided by incorporating a transistor 402 configured to prevent the voltage at the gate 218 of the upper switch 208 from going positive with respect to the source 216 of the upper switch 208 when the gate 224 of the lower switch 210 is positive with respect to the source 222 of the lower switch 210. The circuit 500 is similar to the circuit 400, except that it includes an additional optional diode 502. The diode 502 includes, but is not limited to, a Schottky diode. The diode 502 is provided to limit negative voltages at the gate 218 of the upper FET 208 with respect to the source 216 of the upper FET 208.

[0040] Diode 502 may be provided based on the relative speeds of the "on / off" state transitions by FETs 208, 210, and 402. For example, if FET 402 is relatively fast and transistors 208 and 210 are relatively slow, an undesirable condition can occur where gate 218 of upper FET 208 is pulled low while source 216 remains high. Diode 502 prevents this undesirable condition by ensuring that transistor 402 simultaneously pulls gate 218 and source 216 low.

[0041] FIG. 6 is a diagram of a bridge converter 600 implementing the present solution. The bridge converter 600 includes a transistor active bridge circuit electrically connected to a transformer 602 having a primary winding 604 connected to output lines 264 and 266. The transistor active bridge circuit may include the transistor active bridge circuit 200 of FIG. 2 modified to include the feedthrough protection circuit of FIG. 4 and / or FIG. 5. In this regard, each branch 620, 622 of the transistor active bridge circuit includes a pair of series transistors 208 / 210 or 212 / 214 and at least a feedthrough protection transistor 402. Thus, branch 620 includes circuit 400 of FIG. 4 or circuit 500 of FIG. 5. Branch 622 includes either (i) a circuit 400' that is similar to or identical to circuit 400, except that series transistors 208, 210 are replaced with series transistors 212, 214, or (ii) a circuit 500' that is similar to or identical to circuit 500, except that series transistors 208, 210 are replaced with series transistors 212, 214.

[0042] In operation, two series pairs of FETs 208 / 210 and 212 / 214 are used to symmetrically drive the transformer primary winding 604. FETs 208 and 214 conduct during the first switching period, and the other FETs 210 and 212 conduct during the next switching period. When one set of FETs (e.g., FETs 208 and 214) conducts, the other set of FETs (e.g., FETs 210 and 212) remains in the "off" state. The output voltage Vs(t) is determined by the transistor duty cycle, the transformer turns ratio, and the input voltage Vg.

[0043] 7 shows a flow diagram of an exemplary method 700 for operating a circuit. Method 700 begins at 702 and proceeds to 704, where a first high drive signal is provided from a first gate driver circuit (e.g., gate driver circuit 270 or 274 of FIG. 2) to a gate (e.g., gate 218 or 230 of FIG. 2) of a first transistor (e.g., transistor 208 or 212 of FIG. 2). As shown in block 706, a first low drive signal is provided from a second gate driver circuit (e.g., gate driver circuit 272 or 276 of FIG. 2) to a gate of a third transistor (e.g., gate 406 of FIGS. 4-5) and a gate of a second transistor (e.g., gate 224 or 236 of FIG. 2). The first and second gate driver circuits may constitute sub-circuits of the gate driver circuit. The second transistor is connected in series with the first transistor via first and second input lines (e.g., input lines 204, 206 in FIG. 2 ). The first transistor transitions to an ON state in block 704, and the second and third transistors transition to an OFF state in block 706. The operations of blocks 704, 706 may occur simultaneously or in parallel rather than sequentially, as shown in FIG. 7 . The first, second, and / or third transistors may include, but are not limited to, gallium nitride field effect transistors.

[0044] In a next block 708, a second high drive signal is simultaneously provided from a second gate driver circuit (e.g., gate driver circuit 272 or 276 in FIG. 2) to the gates (e.g., gate 406 in FIG. 4 and gate 224 or 236 in FIG. 2) of the second and third transistors (e.g., transistor 402 in FIG. 4 and transistor 210 or 214 in FIG. 2). The second high drive signal may be provided from the second driver circuit in response to a radiation or noise event in the surrounding environment. The second high drive signal transitions the second and third transistors from an off state to an on state while the first transistor is still in an on state.

[0045] At block 710, a third transistor is used to prevent shoot-through. The third transistor operates to pull down the voltage of the first high drive signal output from the first gate driver circuit to a level at which the first transistor transitions from an on state to an off state when the second transistor is in an on state. The third transistor also operates at 712 to prevent the first transistor from transitioning to an on state when the second transistor is in an on state.

[0046] In block 714, a diode (e.g., diode 502 of FIG. 5) is optionally used to limit the negative voltage at the gate of the first transistor relative to the source of the first transistor while the third transistor is used to prevent shoot-through. The diode is selectively provided in the circuit based on the relative state transition speeds of the first, second, and third transistors.

[0047] In block 716, the first and second gate driver circuits are operated to turn off the second and third transistors. The first and second gate driver circuits are then operated in block 718 to transition the second transistor to an on state while the first transistor is in an off state. The third transistor is used in 720 to prevent the first transistor from transitioning from an off state to an on state, for example, in the event of a radiation or noise event in the surrounding environment that affects the operation of the first gate driver circuit. The method 700 then proceeds to block 722, where it may end or other operations may be performed (e.g., returning to block 702).

[0048] In light of the above, this specification relates to a circuit (e.g., circuit 400 of FIG. 4, circuit 500 of FIG. 5, and / or circuit 600 of FIG. 6) including first and second transistors (e.g., transistors 208, 210, or 212, 214) connected in series across first and second input lines (e.g., input lines 204, 206) of the circuit, a source (e.g., source 404) connected to a source (e.g., source 222 or 234) of the second transistor, a gate (e.g., gate 406) connected to a gate (e.g., gate 224 or 236) of the second transistor, and a gate (e.g., gate 408) connected to a gate (e.g., gate 224 or 236) of the first transistor. a third transistor (e.g., transistor 402) including a drain (e.g., drain 408) connected to the gates of the first, second, and third transistors (e.g., gate 218 or 230); and a gate driver circuit (e.g., circuit 270 / 272 or 274 / 276) connected to the gates of the first, second, and third transistors and configured to (i) provide a first drive signal to the gate of the first transistor to transition the first transistor between an on state and an off state, and (ii) provide a second drive signal to the gates of the second and third transistors to transition the second and third transistors between an on state and an off state. The third transistor is configured to prevent a shoot-through condition in the circuit by pulling the first drive signal down to the level of the source of the second transistor when the second transistor is in an on state. The third transistor is also configured to prevent the first transistor from transitioning from an off state to an on state when the third transistor is in an on state.

[0049] In some scenarios, when the first gate drive signal has a first voltage value, the first transistor is in an ON state, and when the second gate drive signal has a second voltage value that is lower than the first voltage value, the second and third transistors are in an OFF state. The gate driver circuit may increase the second voltage value of the second gate drive signal due to a radiation event occurring in the surrounding environment. The third transistor prevents shoot-through when the second gate drive signal has the increased second voltage value.

[0050] The circuit may further include a diode (e.g., diode 502) configured to limit a negative voltage at the gate of the first transistor relative to the source of the second transistor while the third transistor is being used to prevent a shoot-through condition. The diode may be selectively provided in the circuit based on the relative state transition speeds of the first, second, and third transistors.

[0051] In these or other scenarios, the gate driver circuit is operable to place the third transistor in an on state while the first transistor is in an off state, and the third transistor is configured to prevent the first transistor from transitioning from an off state to an on state when a radiation event occurs in the ambient environment that affects operation of the gate driver circuit.

[0052] In these or other scenarios, the first, second, and third transistors are bipolar junction transistors with an emitter instead of a source, a collector instead of a drain, and a base instead of a gate. Alternatively, the first and second transistors are insulated gate bipolar transistors with an emitter instead of a source and a collector instead of a drain, and the third transistor comprises a field effect transistor.

[0053] The present specification also relates to a method of operating a circuit, the method including providing a first high drive signal from a first gate driver circuit to a gate of a first transistor, providing a first low drive signal from a second gate driver circuit to the gate of the second transistor and to the gate of a third transistor connected in series with the first transistor across first and second input lines, thereby transitioning the first transistor to an ON state and the second and third transistors to an OFF state, simultaneously providing a second high drive signal from the second gate driver circuit to the gates of the second and third transistors, transitioning the second and third transistors from an OFF state to an ON state while the first transistor is still in an ON state, and using the second transistor to prevent shoot-through by reducing the voltage of the first high drive signal output from the first gate driver circuit to a level that transitions the first transistor from an ON state to an OFF state while the third transistor is in an ON state. The second high drive signal may be provided from the second driver circuit in response to a radiation event in the surrounding environment. The second transistor may include, but is not limited to, a gallium nitride field effect transistor. The method includes preventing, by the second transistor, the first transistor from transitioning from an off state to an on state when the third transistor is in an on state.

[0054] The method may further comprise selectively providing a diode in the circuit based on relative state transition rates of the first, second, and third transistors, and / or using a diode to limit negative voltages at the gate of the first transistor relative to the source of the third transistor when the second transistor is being used to prevent shoot-through.

[0055] Additionally or alternatively, the method comprises operating the first and second gate driver circuits to cause the third transistor to be in an on state when the first transistor is in an off state, and / or using the second transistor to prevent the first transistor from transitioning from an off state to an on state when a radiation event occurs in the ambient environment that affects operation of the first gate driver circuit.

[0056] This specification also relates to a circuit comprising first and second P-channel transistors connected in series, a third transistor having a source connected to the source of the second transistor, a gate connected to the gate of the second transistor, and a drain connected to the gate of the first transistor, and a gate driver circuit connected to the gates of the first, second, and third transistors and configured to (i) provide a first drive signal to the gate of the first transistor to transition the first transistor between an on state and an off state, and (ii) provide a second drive signal to the gates of the second and third transistors to transition the second and third transistors between an on state and an off state. The third transistor is also P-channel and configured to prevent shoot-through in the circuit by pulling the first drive signal up to the level of the source of the second transistor when the second transistor is in an on state. In some scenarios, the first, second, and third transistors may be bipolar junction transistors with an emitter instead of a source, a collector instead of a drain, and a base instead of a gate.

[0057] The described features, advantages, and characteristics disclosed herein may be combined in any suitable manner. Those skilled in the art will recognize in light of the description herein that the disclosed systems and / or methods may be practiced without one or more of the specific features. In other instances, additional features and advantages may be recognized in certain scenarios that may not be present in all instances.

[0058] While the systems and methods have been illustrated and described with respect to one or more implementations, equivalent changes and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. Moreover, while a particular feature may be disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of other implementations, as may be desirable and advantageous for any particular application. Thus, the breadth and scope of the disclosure herein should not be limited by any of the above descriptions. Rather, the scope of the present invention should be defined according to the following claims and their equivalents.

Claims

1. first and second transistors connected in series; a third transistor including a source connected to the source of the second transistor, a gate connected to the gate of the second transistor, and a drain connected to the gate of the first transistor; a gate driver circuit connected to the gates of the first, second, and third transistors and configured to (i) provide a first drive signal to the gate of the first transistor to transition the first transistor between an on state and an off state, and (ii) provide a second drive signal to the gates of the second and third transistors to transition the second and third transistors between an on state and an off state; A circuit comprising: the third transistor is configured to prevent a shoot-through condition in the circuit by pulling the first drive signal down to a level of a source of the second transistor when the second transistor is in an on state; the gate driver circuit is operable to turn on the third transistor while the first transistor is off; the third transistor is configured to prevent the first transistor from transitioning from an off state to an on state when a radiation or noise event occurs in the ambient environment that affects operation of the gate driver circuit.

2. 2. The circuit of claim 1, wherein the first transistor is in an on state when the first gate drive signal has a first voltage value, and the second and third transistors are in an off state when the second gate drive signal has a second voltage value that is lower than the first voltage value.

3. 3. The circuit of claim 2, wherein the gate driver circuit increases the second voltage value of the second gate drive signal in response to a radiation event occurring in the surrounding environment.

4. 4. The circuit of claim 3, wherein the third transistor prevents a shoot-through condition when the second gate drive signal has the increased second voltage value.

5. The circuit of claim 1 , wherein at least the third transistor comprises a gallium nitride field effect transistor.

6. 2. The circuit of claim 1, wherein the third transistor is further configured to prevent the first transistor from transitioning from an off state to an on state while the third transistor is in an on state.

7. The circuit described in claim 1, wherein the first, second and third transistors are bipolar junction transistors having an emitter instead of a source, a collector instead of a drain, and a base instead of a gate.

8. The circuit described in claim 1, wherein the first and second transistors are insulated gate bipolar transistors having an emitter instead of a source and a collector instead of a drain, and the third transistor comprises a field effect transistor.

9. A semiconductor device comprising: first and second transistors connected in series; a third transistor including a source connected to the source of the second transistor, a gate connected to the gate of the second transistor, and a drain connected to the gate of the first transistor; a gate driver circuit connected to the gates of the first, second, and third transistors and configured to (i) provide a first drive signal to the gate of the first transistor to transition the first transistor between an on state and an off state, and (ii) provide a second drive signal to the gates of the second and third transistors to transition the second and third transistors between an on state and an off state; A circuit comprising: the third transistor is configured to prevent a shoot-through condition in the circuit by pulling the first drive signal down to a level of a source of the second transistor when the second transistor is in an on state; a diode configured to limit a negative voltage of the gate of the first transistor relative to the source of the second transistor while the third transistor is being used to prevent a shoot-through condition; The diode is selectively provided within the circuit based on the relative state transition rates of the first, second and third transistors.

10. 1. A method of operating a circuit, comprising: a gate driver circuit providing a first high drive signal to the gate of a first transistor and a first low drive signal to the gate of a third transistor and to the gate of a second transistor connected in series with the first transistor, thereby transitioning the first transistor to an ON state and the second and third transistors to an OFF state; providing second high drive signals simultaneously from the gate driver circuit to the gates of the second and third transistors to transition the second and third transistors from an off state to an on state while the first transistor is still in an on state; using the third transistor to prevent shoot-through by reducing the voltage of the first high drive signal output from the gate driver circuit to a level that causes the first transistor to transition from an ON state to an OFF state while the second and third transistors are in an ON state; Prepare for this. The method of operating a circuit, wherein the second high drive signal is provided from the gate driver circuit in response to a radiation or noise event in the surrounding environment.

11. The method of claim 10 wherein the second transistor comprises a gallium nitride field effect transistor.

12. 11. The method of claim 10, further comprising: preventing, with the third transistor, the first transistor from transitioning from an off state to an on state while the second transistor is in an on state.

13. 11. The method of claim 10, further comprising using a diode to limit a negative voltage at the gate of the first transistor relative to the source of the second transistor while the third transistor is being used to prevent a shoot-through condition.

14. 14. The method of claim 13, further comprising selectively placing the diode in the circuit based on relative state transition rates of the first, second and third transistors.

15. 11. The method of claim 10, further comprising operating the gate driver circuit to turn the third transistor on while the first transistor is off.

16. 16. The method of claim 15, further comprising: using the second transistor to prevent the first transistor from transitioning from an off state to an on state when a radiation event occurs in the ambient environment that affects operation of the gate driver circuit.

17. first and second transistors of the P-channel type connected in series; a third transistor including a source connected to the source of the second transistor, a gate connected to the gate of the second transistor, and a drain connected to the gate of the first transistor; a gate driver circuit connected to the gates of the first, second, and third transistors and configured to (i) provide a first drive signal to the gate of the first transistor to transition the first transistor between an on state and an off state, and (ii) provide a second drive signal to the gates of the second and third transistors to transition the second and third transistors between an on state and an off state; A circuit comprising: the third transistor is also P-channel, and is configured to prevent shoot-through conditions in the circuit by pulling the first drive signal up to a source of the second transistor when the second transistor is in an on state; the gate driver circuit is operable to turn on the third transistor while the first transistor is off; the third transistor is further configured to prevent the first transistor from transitioning from an off state to an on state when a radiation or noise event occurs in the ambient environment that affects operation of the gate driver circuit.

18. The circuit of claim 17, wherein the first, second and third transistors are bipolar junction transistors having an emitter instead of a source, a collector instead of a drain, and a base instead of a gate.

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