Memory circuit

Abstract

To provide a storage circuit capable of controlling a current flowing through a memory element in a set operation and a reset operation.SOLUTION: A memory cell C includes a memory element 20 having two terminals, a first transistor M0, and a second transistor M1. A power supply voltage VDD is applied to a gate terminal of the first transistor M0, a drain terminal is connected to a gate terminal of the second transistor M1, and a drain terminal of the second transistor M1 is connected to a first terminal of the storage element 20.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a memory circuit. [Background technology]

[0002] A typical nonvolatile resistance change memory includes a 1T1R memory cell configured by one cell transistor and one storage element, and a memory array in which memory cells are arranged two-dimensionally (for example, Patent Document 1).

[0003] Furthermore, Non-Patent Document 1 discloses a type of memory element having a structure in which a solid electrolyte is sandwiched between an active electrode and an inactive electrode (see Figures 9A and 9B). As shown in Figure 9A, when a set voltage VSET and a ground GND are applied to the active electrode and the inactive electrode, respectively, a metal bridge is formed and the memory element transitions to a low resistance (ON) state. This operation is called a set operation.

[0004] 9B, when a reset voltage VRST and a ground GND are applied to the inactive and active electrodes, respectively, the generated bridge disappears and the memory element transitions to a high-resistance (OFF) state. This operation is called a reset operation.

[0005] This 1T1R memory cell can be divided into two types based on the connection method between the cell transistor and the memory element (Figures 10A, 10B, 11A, and 11B). The cell transistor can be configured with either an N-type MOS (NMOS) transistor or a P-type MOS (PMOS) transistor, but the following will explain the case where an NMOS transistor is used. As shown in Figure 10A, in the connection method where the NMOS transistor is connected to the inactive electrode, during set, the set voltage VSET and ground GND are applied to the active electrode and the drain terminal of the NMOS transistor, respectively, and the set current can be controlled by adjusting the voltage of the select signal VG input to the gate terminal of the NMOS transistor.

[0006] In addition, as shown in FIG. 11B, in the connection method in which the NMOS transistor is connected to the active electrode, during reset, the reset voltage VRST and ground GND are applied to the inactive electrode and the drain terminal of the NMOS cell transistor, respectively, and the reset current can be controlled by adjusting the voltage of the selection signal VG input to the gate terminal of the NMOS transistor.

[0007] In this way, the set current or reset current is controlled using the transistor of the memory cell. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-119958 [Non-patent literature]

[0009] [Non-Patent Document 1] M. Tada, K. Okamoto, T. Sakamoto, M. Miyamura, N. Banno, and H. Hada, "Polymer Solid-Electrolyte (PSE) Switch Embedded on CMOS for Nonvolatile Crossbar Switch", IEEE TRANSACTION ON ELECTRON DEVICES, Vol. 58, No. 12, pp.4398-4405, (2011). Summary of the Invention [Problem to be solved by the invention]

[0010] When resetting and setting the 1T1R memory cells of FIGS. 10A, 10B, 11A, and 11B, respectively, a reset voltage VRST and a set voltage VSET are applied to the memory element via an NMOS transistor.

[0011] At this time, to avoid the NMOS threshold voltage drop problem, the voltage of the selection signal VG input to the gate terminal of the NMOS transistor is set to a voltage (overdrive voltage) higher than the standard voltage. For example, as shown in Figure 10B, in a connection method in which the NMOS transistor is connected to the inactive electrode, the voltage of the selection signal VG input to the gate terminal of the NMOS transistor is set to an overdrive voltage to avoid the NMOS threshold voltage drop problem of the reset voltage VRST during reset. This poses a problem in that the reset current cannot be controlled by adjusting the voltage of the selection signal VG.

[0012] 11A, in the connection method in which the NMOS transistor is connected to the active electrode, in order to avoid the problem of the set voltage VSET dropping due to the NMOS threshold voltage, the voltage of the selection signal VG input to the gate terminal of the NMOS transistor is set to an overdrive voltage. This causes a problem in that the reset current cannot be controlled by adjusting the voltage of the selection signal VG.

[0013] 12 shows a memory circuit 300 having a memory array structure of 1T1R memory cells in which an NMOS transistor is connected to an inactive electrode. Each word line WL0 to WL2 is connected to all transistors in the same row, and when a selected memory cell C01 is reset, an overdrive voltage is also applied to a non-selected memory cell C11 in the same row. When the reset time is T and the number of memory cells to be reset in the same row is N, the overdrive voltage is applied to all transistors in the same row for a time of T×N, which can reduce the reliability of the transistors.

[0014] FIG. 13 also shows a storage circuit 400 having a memory array structure of 1T1R memory cells in a connection manner in which an NMOS transistor is connected to an active electrode.

[0015] Each word line WL0 to WL2 is connected to all transistors in the same row, and when memory cell C01, the selected cell, is set, an overdrive voltage is also applied to memory cell C11, the unselected cell in the same row. If the set time is T and the number of memory cells to be set in the same row is N, the overdrive voltage is applied to all transistors in the same row for a time of T x N, which poses a problem of reduced transistor reliability.

[0016] The present invention has been made to solve the above-mentioned problems, and has an object to provide a memory circuit that can control the current flowing through a memory element in a set operation and a reset operation. [Means for solving the problem]

[0017] In order to achieve the above object, the memory circuit according to the present invention has a memory cell including a memory element having two terminals, a first transistor, and a second transistor, wherein a power supply voltage is applied to the gate terminal of the first transistor, the drain terminal is connected to the gate terminal of the second transistor, and the drain terminal of the second transistor is connected to the first terminal of the memory element.

[0018] In the memory circuit according to the present invention, when the voltage applied to the source terminal of the second transistor rises to the set voltage during the set operation of the memory cell, the gate voltage is raised to the overdrive voltage due to capacitive coupling between the source and gate of the second transistor. Because the overdrive voltage applied to the gate terminal of the second transistor is high, the resistance of the second transistor decreases, and the set voltage is applied to the memory element. When the memory element changes from a high-resistance state to a low-resistance state, the overdrive voltage decreases, and the voltage, which is the potential difference between the two terminals of the memory element, decreases, thereby controlling the current flowing through the memory element.

[0019] Furthermore, during the reset operation of the memory cell, the voltage applied to the source terminal of the second transistor becomes high impedance, so that when the voltage applied to the memory element rises to the reset voltage, the drain terminal of the second transistor also rises to the reset voltage, and the gate voltage is raised to the overdrive voltage due to capacitance coupling between the source and gate. Then, the voltage applied to the source terminal of the second transistor becomes ground, and a high reset current flows through the memory element in the low resistance state, transitioning the memory element from the low resistance state to the high resistance state. In this way, the current flowing through the memory element can be controlled during the set operation and reset operation.

[0020] In the memory circuit of the present invention, the memory element has a structure in which a solid electrolyte is sandwiched between an active electrode and an inactive electrode, and the active electrode can be a first terminal of the memory element, and the inactive electrode can be a second terminal of the memory element.

[0021] The memory circuit of the present invention may have a plurality of the memory cells, the source terminal of the first transistor being the first terminal of the memory cell, the source terminal of the second transistor being the second terminal of the memory cell, the second terminal of the memory element being the third terminal of the memory cell, the plurality of memory cells being arranged two-dimensionally, the first terminals of the plurality of memory cells arranged in the same row being connected to the same word line, the second terminals of the plurality of memory cells arranged in the same column being connected to the same bit line, and the third terminals of the plurality of memory cells arranged in the same column being connected to the same source line.

[0022] In this memory circuit, when a memory cell that is a selected cell is set or reset, an overdrive voltage is applied to the gate terminal of the second transistor of the selected cell, but no overdrive voltage is applied to the gate terminal of the second transistor of a memory cell that is an unselected cell in the same row. This memory circuit can improve the reliability of the transistors of the memory cells.

[0023] In the memory circuit of the present invention, the memory cell may further include a third transistor, the gate terminal of which is connected to the drain terminal of the first transistor, and the drain terminal of which is connected to the source terminal of the second transistor. In this memory circuit, the second transistor and the third transistor are connected in series, so that the set voltage or the reset voltage can be divided. This allows the area of ​​the memory cell to be reduced.

[0024] The memory circuit of the present invention can have a plurality of the memory cells, the source terminal of the first transistor being the first terminal of the memory cell, the source terminal of the third transistor being the second terminal of the memory cell, the second terminal of the memory element being the third terminal of the memory cell, the plurality of memory cells being arranged two-dimensionally, the first terminals of the plurality of memory cells arranged in the same row being connected to the same word line, the second terminals of the plurality of memory cells arranged in the same column being connected to the same bit line, and the third terminals of the plurality of memory cells arranged in the same column being connected to the same source line.

[0025] In this memory circuit, when a memory cell that is a selected cell is set or reset, an overdrive voltage is applied to the gate terminals of the second and third transistors of the selected cell, but no overdrive voltage is applied to the gate terminals of the second and third transistors of memory cells that are unselected cells in the same row. This memory circuit can improve the reliability of the transistors of the memory cells. [Effects of the Invention]

[0026] As described above, the memory circuit of the present invention has the effect of being able to control the current flowing through the memory element in the set operation and reset operation. [Brief explanation of the drawings]

[0027] [Figure 1]2 is a circuit diagram showing a circuit of a memory cell portion of the memory circuit according to the first embodiment. FIG. [Figure 2] 4A to 4C are schematic diagrams of waveforms of signals for explaining a set operation of a memory cell of the memory circuit according to the first embodiment. [Figure 3A] 10 is a graph showing the relationship between the resistance of a memory element and the bootstrap voltage. [Figure 3B] 10 is a graph showing the relationship between the resistance of a memory element and the voltage applied to the memory element. [Figure 4] FIG. 3 is a circuit diagram for explaining a set operation of a memory cell of the memory circuit according to the first embodiment. [Figure 5] 5A and 5B are schematic diagrams of waveforms of signals for explaining a reset operation of a memory cell of the memory circuit according to the first embodiment. [Figure 6] 1 is a circuit diagram illustrating a memory circuit according to a first embodiment. [Figure 7] FIG. 10 is a circuit diagram showing a circuit of a memory cell portion of a memory circuit according to a second embodiment. [Figure 8] FIG. 10 is a circuit diagram illustrating a memory circuit according to a second embodiment. [Figure 9A] FIG. 10 is a diagram for explaining a set operation of a memory cell. [Figure 9B] FIG. 10 is a diagram for explaining a reset operation of a memory cell. [Figure 10A] FIG. 10 is a circuit diagram for explaining a set operation of a memory cell in a memory circuit according to the prior art. [Figure 10B] FIG. 1 is a circuit diagram for explaining a reset operation of a memory cell of a memory circuit according to the prior art. [Figure 11A] FIG. 10 is a circuit diagram for explaining a set operation of a memory cell in a memory circuit according to the prior art. [Figure 11B] FIG. 1 is a circuit diagram for explaining a reset operation of a memory cell of a memory circuit according to the prior art. [Figure 12] FIG. 1 is a circuit diagram showing a memory circuit according to a conventional technique. [Figure 13] FIG. 1 is a circuit diagram showing a memory circuit according to a conventional technique. DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

[0029] [First embodiment] FIG. 1 is a circuit diagram showing a circuit of a memory cell C portion of a memory circuit according to a first embodiment.

[0030] The memory cell C includes a memory element 20, a first transistor M0, and a second transistor M1. This memory cell C is called a 2T1R memory cell. The memory element 20 has a structure in which a solid electrolyte 20A is sandwiched between an active electrode 20B and a non-active electrode 20C. A power supply voltage VDD is applied to the gate terminal of the transistor M0, and the drain terminal is connected to the gate terminal of the transistor M1. The drain terminal of the second transistor M1 is connected to the active electrode 20B of the memory element 20. Note that the following description will be given taking as an example a case in which the first transistor M0 and the second transistor M1 are NMOS transistors.

[0031] Next, the set operation of memory cell C will be described using Figures 1 and 2. The set operation begins when the select signal VG input to the source terminal of the first transistor M0 rises from ground GND to the power supply voltage VDD. If the threshold voltage of an NMOS transistor is VTH, the gate voltage VBST of the second transistor M1 becomes VDD-VTH. After this, when the voltage BL applied to the source terminal of the second transistor M1 rises from ground GND to a set voltage VSET that is higher than the power supply voltage VDD but lower than the drain-to-source (DS) breakdown voltage of the NMOS transistor, the gate voltage VBST is raised to an overdrive voltage VBOOT, which is higher than the set voltage VSET, due to capacitance coupling between the source and gate of the second transistor M1. The voltage level of the overdrive voltage VBOOT can be controlled by adjusting the power supply voltage VDD.

[0032] Thereafter, the voltage SL applied to the inactive electrode 20C of the memory element 20 changes from high impedance (Hi-Z) to ground GND, the set voltage VSET and ground GND are applied to both ends of the memory element 20, and the memory element 20 transitions from a high resistance (OFF) state to a low resistance (ON) state. Thereafter, the voltage SL applied to the inactive electrode 20C returns to high impedance (Hi-Z), the voltage BL applied to the source terminal of the second transistor M1 and the selection signal VG fall to ground GND in sequence, and the set operation is completed.

[0033] Next, control of the set current of memory cell C will be described using Figures 3A and 3B. As shown in Figure 3A, the increased overdrive voltage VBOOT decreases as the resistance RNB of memory element 20 decreases. As shown in Figure 3B, when memory element 20 is in a high-resistance state (>100 kΩ), the overdrive voltage VBOOT is sufficiently high, so the resistance of second transistor M1 decreases and the set voltage VSET is applied to memory element 20. Then, when memory element 20 changes from a high-resistance state to a low-resistance state, the overdrive voltage VBOOT decreases, and the voltage VNB, which is the potential difference between active electrode 20B and inactive electrode 20C of memory element 20, decreases, thereby controlling the current flowing through memory element 20.

[0034] In this way, the overdrive voltage VBOOT raised by the bootstrap decreases in accordance with the decrease in the resistance of the storage element 20, so that the voltage applied to and current flowing through the storage element 20 can be automatically controlled during the set operation.

[0035] Next, the control of the reset current of memory cell C will be explained using Figure 4. During the reset operation, the reset current can be controlled by adjusting the voltage of the selection signal VG, just like the conventional reset operation shown in Figure 11B. In other words, the reset current can be controlled by adjusting the voltage level of VDD applied as the selection signal VG.

[0036] Furthermore, to obtain a high reset current, the signal sequence shown in Figure 5 is applied. The reset operation begins when the select signal VG rises from ground GND to the power supply voltage VDD. If the threshold voltage of the NMOS transistor is VTH, the gate voltage VBST of the second transistor M1 becomes VDD-VTH. Because the voltage BL applied to the source terminal of the second transistor M1 becomes Hi-Z, when the voltage SL applied to the inactive electrode 20C of the storage element 20 rises from ground GND to a reset voltage VRST that is higher than the power supply voltage VDD but lower than the breakdown voltage between the D and C of the NMOS transistor, the drain terminal of the second transistor M1 also rises from ground GND to the reset voltage VRST. Capacitive coupling between the source and gate of the second transistor M1 raises the gate voltage VBST to an overdrive voltage VBOOT, which is higher than the reset voltage VRST. The voltage level of the overdrive voltage VBOOT can be controlled by adjusting the power supply voltage VDD.

[0037] Then, the voltage BL applied to the source terminal of the second transistor M1 changes from Hi-Z to ground GND, a high reset current flows through the memory element 20 in the low resistance state, and the memory element 20 transitions from the low resistance state to the high resistance state. Then, the voltage SL applied to the inactive electrode 20C and the selection signal VG fall to ground GND in sequence, and the reset operation ends.

[0038] Here, the reason for controlling the reset current will be explained. During the reset operation, the memory element 20 transitions from a low-resistance (ON) state to a high-resistance (OFF) state, and the resistance value of the high-resistance (OFF) state is determined by the current (reset current) that flows during the reset operation. That is, the larger the reset current, the larger the resistance value of the high-resistance (OFF) state. Furthermore, the required OFF resistance value varies depending on the application. For example, when used as a memory, the OFF resistance value is 10 KΩ or less, but when used as a routing switch for an FPGA, the OFF resistance value must be 1 MΩ or more.

[0039] FIG. 6 is a circuit diagram of a memory circuit 100 according to this embodiment. The memory circuit 100 includes a plurality of memory cells C00-C12 arranged two-dimensionally, and the memory cells C00-C12 are connected to word lines WL0-WL2, bit lines BL0 and BL1, and source lines SL0 and SL1. While FIG. 6 illustrates an example in which the memory circuit 100 includes six memory cells, the number of memory cells is not limited to six, and the number of memory cells may be five or fewer, or seven or more. When referring to the memory cells C00-C12 collectively rather than a specific memory cell, they are also referred to as memory cells C. When referring to the word lines WL0-WL2, bit lines BL0 and BL1, and source lines SL0 and SL1 collectively rather than a specific word line, bit line, or source line, they are also referred to as word lines WL, bit lines BL, and source lines SL, respectively.

[0040] In each memory cell C, the source terminal of the first transistor M0 becomes the first terminal of the memory cell C, the source terminal of the second transistor M1 becomes the second terminal of the memory cell C, and the second terminal of the memory element 20 becomes the third terminal of the memory cell C.

[0041] In addition, the first terminals of multiple memory cells C arranged in the same row are connected to the same word line WL, the second terminals of multiple memory cells C arranged in the same column are connected to the same bit line BL, and the third terminals of multiple memory cells C arranged in the same column are connected to the same source line SL.

[0042] Next, the principle of improving the reliability of the second transistor M1 will be described.

[0043] When the memory cell C01 is set as the selected cell, signals are input to the word line WL1, bit line BL0, and source line SL0 in the sequence shown in FIG.

[0044] That is, the word line WL1 causes the selection signal VG input to the source terminal of the first transistor M0 to rise from ground GND to the power supply voltage VDD. Also, the bit line BL0 causes the voltage BL applied to the source terminal of the second transistor M1 to rise from ground GND to the set voltage VSET. Also, the source line SL0 causes the voltage SL applied to the inactive electrode 20C of the storage element 20 to change from high impedance (Hi-Z) to ground GND.

[0045] Moreover, when the memory cell C01 is reset as a selected cell, signals are input to the word line WL1, bit line BL0, and source line SL0 in the sequence shown in FIG.

[0046] That is, the word line WL1 causes the selection signal VG input to the source terminal of the first transistor M0 to rise from ground GND to the power supply voltage VDD. Also, the bit line BL0 causes the voltage BL applied to the source terminal of the second transistor M1 to become Hi-Z. Also, the source line SL0 causes the voltage SL applied to the inactive electrode 20C of the memory element 20 to rise from ground GND to the reset voltage VRST.

[0047] In the above set and reset operations, the ground GND is applied by the other word lines WL0 and WL2, bit line BL1, and source line SL1.

[0048] As described above, the overdrive voltage VBOOT is applied to the second transistor M1 of the memory cell C01, which is the selected cell. On the other hand, since no coupling occurs in the memory cell C11, which is the unselected cell in the same row, the gate voltage of the second transistor M1 of the memory cell C11 becomes VDD-VTH.

[0049] In this way, when a memory cell C is provided with a first transistor M0 and a second transistor M1 and a signal is input in the sequence shown in Figure 2 or 5, coupling occurs in the second transistor M1 of the selected cell, causing a set operation or a reset operation. Because ground GND is applied by the bit line BL1 and source line SL1 corresponding to unselected cells in the same row, even if power supply voltage VDD is applied to the gate terminal and source terminal of the first transistor M0, coupling of the second transistor M1 does not occur, and the gate voltage of the second transistor M1 becomes VDD-VTH.

[0050] Furthermore, when the reset or set time is T and the number of memory cells to be reset or set in the same row is N, the overdrive voltage VBOOT is applied only to the second transistor M1 of the selected cell for the time T, thereby improving the reliability of the second transistor M1.

[0051] As described above, the memory circuit 100 according to this embodiment has a memory cell including a memory element having two terminals, a first transistor, and a second transistor, and a power supply voltage is applied to the gate terminal of the first transistor, the drain terminal is connected to the gate terminal of the second transistor, and the drain terminal of the second transistor is connected to the first terminal of the memory element. This makes it possible to control the current flowing through the memory element in the set operation and the reset operation.

[0052] In addition, in the memory circuit 100, when a memory cell that is a selected cell is set or reset, an overdrive voltage is applied to the gate terminal of the second transistor of the selected cell, but no overdrive voltage is applied to the gate terminal of the second transistor of a memory cell that is an unselected cell in the same row, thereby improving the reliability of the transistor of the memory cell.

[0053] [Second embodiment] A memory circuit according to the second embodiment will be described below. Note that parts having the same configuration as those in the first embodiment will be given the same reference numerals and detailed description thereof will be omitted.

[0054] When the set voltage and reset voltage of the memory element are higher than the drain-source breakdown voltage of the transistor, the transistors of the 1T1R memory cell and 2T1R memory cell must be configured with high-voltage transistors. Therefore, in the second embodiment, in order to reduce the area of ​​the high-voltage transistor, a series circuit of the second transistor and a third transistor is used instead of the second transistor.

[0055] FIG. 7 is a circuit diagram showing the circuit of the memory cell C portion of the memory circuit according to the second embodiment of the present invention.

[0056] The memory cell C includes a memory element 20, a first transistor M0, a second transistor M1, and a third transistor M2. This memory cell C is called a 3T1R memory cell. The memory element 20 has a structure in which a solid electrolyte 20A is sandwiched between an active electrode 20B and a non-active electrode 20C. A power supply voltage VDD is applied to the gate terminal of the first transistor M0, and the drain terminal is connected to the gate terminals of the second transistor M1 and the third transistor M2. The source terminal of the third transistor M2 is connected to the drain terminal of the second transistor M1, and the drain terminal is connected to the active electrode 20B of the memory element 20.

[0057] FIG. 8 is a circuit diagram of a memory circuit 200 according to this embodiment. The memory circuit 200 includes a plurality of memory cells C00-C12 arranged two-dimensionally and connected to word lines WL0-WL2, bit lines BL0 and BL1, and source lines SL0 and SL1. While FIG. 8 illustrates an example in which the memory circuit 100 includes six memory cells, the number of memory cells is not limited to six and may be five or fewer, or seven or more. When referring to the memory cells C00-C12 collectively rather than a specific memory cell, they are also referred to as memory cells C. When referring to the word lines WL0-WL2, bit lines BL0 and BL1, and source lines SL0 and SL1 collectively rather than a specific word line, bit line, or source line, they are also referred to as word lines WL, bit lines BL, and source lines SL.

[0058] In each memory cell C, the source terminal of the first transistor M0 becomes the first terminal of the memory cell C, the source terminal of the second transistor M1 becomes the second terminal of the memory cell C, and the second terminal of the memory element 20 becomes the third terminal of the memory cell C.

[0059] In addition, the first terminals of multiple memory cells C arranged in the same row are connected to the same word line WL, the second terminals of multiple memory cells C arranged in the same column are connected to the same bit line BL, and the third terminals of multiple memory cells C arranged in the same column are connected to the same source line SL.

[0060] As in the first embodiment, when setting, signals are input to the word line WL1, bit line BL0, and source line SL0 in the sequence shown in FIG.

[0061] That is, the word line WL1 causes the selection signal VG input to the source terminal of the first transistor M0 to rise from ground GND to the power supply voltage VDD. Also, the bit line BL0 causes the voltage BL applied to the source terminal of the second transistor M1 to rise from ground GND to the set voltage VSET. Also, the source line SL0 causes the voltage SL applied to the inactive electrode 20C of the storage element 20 to change from high impedance (Hi-Z) to ground GND.

[0062] Furthermore, similarly to the first embodiment, when resetting, signals are input to the word line WL1, bit line BL0, and source line SL0 in the sequence shown in FIG.

[0063] That is, the word line WL1 causes the selection signal VG input to the source terminal of the first transistor M0 to rise from ground GND to the power supply voltage VDD. Also, the bit line BL0 causes the voltage BL applied to the source terminal of the second transistor M1 to become Hi-Z. Also, the source line SL0 causes the voltage SL applied to the inactive electrode 20C of the memory element 20 to rise from ground GND to the reset voltage VRST.

[0064] In the above set and reset operations, the ground GND is applied by the other word lines WL0 and WL2, bit line BL1, and source line SL1.

[0065] As described above, in the set and reset operations, the overdrive voltage VBOOT is applied to the second transistor M1 and the third transistor M2 of the memory cell C01, which is the selected cell. If the memory element 20 of the memory cell C02, which is the unselected cell, is in a low-resistance (ON) state, a set voltage VSET or a reset voltage VRST higher than the drain-source breakdown voltage of the transistor is applied across the series circuit of the second transistor M1 and the third transistor M2. Because the second transistor M1 and the third transistor M2 are connected in series, the set voltage VSET or the reset voltage VRST is divided, and the drain-source voltages of the second transistor M1 and the third transistor M2 are within the safe operating range.

[0066] Using Table 1, we will explain the results of comparing the areas of a 1T1R memory cell with a high-voltage transistor, a 2T1R memory cell with a high-voltage transistor, and a 3T1R memory cell with a core-voltage transistor.

[0067] [Table 1]

[0068] When the area of ​​a 1T1R memory cell with high-voltage transistors is taken as 1, the areas of a 2T1R memory cell with high-voltage transistors and a 3T1R memory cell with core-voltage transistors are 1.24 and 0.76, respectively. In this way, it was found that the area of ​​a memory cell can be reduced by using a structure using a series circuit of two transistors.

[0069] As described above, the memory circuit 200 according to the second embodiment has a memory cell including a memory element having two terminals, a first transistor, a second transistor, and a third transistor, wherein a power supply voltage is applied to the gate terminal of the first transistor, the drain terminal is connected to the gate terminals of the second transistor and the third transistor, the drain terminal of the third transistor is connected to the source terminal of the second transistor, and the drain terminal of the second transistor is connected to the first terminal of the memory element. This makes it possible to control the current flowing through the memory element in set and reset operations.

[0070] In the memory circuit 200, when a memory cell that is a selected cell is set or reset, an overdrive voltage is applied to the gate terminals of the second and third transistors of the selected cell, but no overdrive voltage is applied to the gate terminals of the second and third transistors of memory cells that are unselected cells in the same row, thereby improving the reliability of the transistors of the memory cells.

[0071] Furthermore, in the memory circuit 200, the second transistor and the third transistor are connected in series, so that the set voltage or the reset voltage can be divided, thereby reducing the area of ​​the memory cell.

[0072] In the first and second embodiments, the NMOS transistor is connected to the active electrode, but the present invention is not limited to this. Alternatively, the NMOS transistor may be connected to the inactive electrode.

[0073] In the first and second embodiments, the cell transistors are configured using NMOS transistors, but the present invention is not limited to this. The cell transistors may be configured using PMOS transistors. [Explanation of symbols]

[0074] 20 Memory element 20A solid electrolyte 20B active electrode 20C inactive electrode 100, 200 memory circuit 200 Memory circuit BL bit line C Memory Cell M0 First transistor M1 Second transistor M2 Third transistor SL Source Line WL Word Line

Claims

1. a memory element having two terminals; a first transistor; a second transistor; and a storage cell comprising: a power supply voltage is applied to a gate terminal of the first transistor, and a drain terminal of the first transistor is connected to a gate terminal of the second transistor; The drain terminal of the second transistor is connected to the first terminal of the storage element. A memory circuit, the memory cell further comprises a third transistor; A memory circuit in which the gate terminal of the third transistor is connected to the drain terminal of the first transistor and the drain terminal is connected to the source terminal of the second transistor.

2. 2. The memory circuit according to claim 1, The memory element has a structure in which a solid electrolyte is sandwiched between an active electrode and an inactive electrode, the active electrode being a first terminal of the memory element; The inactive electrode serves as the second terminal of the memory element. memory circuit.

3. 2. The memory circuit according to claim 1, a plurality of the memory cells; a source terminal of the first transistor serving as a first terminal of the storage cell; a source terminal of the third transistor serving as a second terminal of the storage cell; the second terminal of the memory element becomes the third terminal of the memory cell; the plurality of memory cells are arranged two-dimensionally, the first terminals of the memory cells arranged in the same row are connected to the same word line; the second terminals of the memory cells arranged in the same column are connected to the same bit line; The third terminals of the plurality of memory cells arranged in the same column are connected to the same source line. memory circuit.

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