Information processing device and information processing method

Abstract

This information processing device (100) comprises a plurality of CPUs (1), a plurality of cache memories (2) corresponding to the plurality of CPUs (1), and a main memory (3). Each of the plurality of CPUs (1) acquires a lock for exclusively accessing data in the main memory (3) and then accesses the data. Data pertaining to access by a corresponding CPU (1) and a lock ID for identifying a lock pertaining to said access are written in association with one another to the respective cache lines of the plurality of cache memories (2). The respective cache lines of the plurality of cache memories (2) are flushed when a CPU (1) other than the corresponding CPU (1) acquires the lock identified by the lock ID that is written to the relevant cache line.

Description

[Technical Field]

[0001] The present disclosure relates to an information processing device and an information processing method. [Background technology]

[0002] For example, as shown in Patent Documents 1 and 2, a method is known in which a plurality of CPUs access the same memory to perform data processing, thereby improving processing speed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-11580 [Patent Document 2] International Publication No. 2008 / 155844 Summary of the Invention [Problem to be solved by the invention]

[0004] It is necessary to maintain consistency (cache coherency) between the cache memories of each CPU. For example, one method is to use a snooping unit to monitor data accesses from each CPU, but this poses challenges in terms of the monitoring burden and the associated power consumption. There is still a demand for technology to maintain cache coherency.

[0005] One aspect of the present disclosure allows for maintaining cache coherency. [Means for solving the problem]

[0006] An information processing device according to one aspect of the present disclosure includes a plurality of CPUs, a plurality of cache memories corresponding to the plurality of CPUs, and a main memory, wherein each of the plurality of CPUs acquires a lock for exclusive access to data in the main memory before accessing the data, and data related to access by the corresponding CPU and a lock ID identifying the lock related to the access are written in a cache line of each of the plurality of cache memories in association with each other, and the cache line of each of the plurality of cache memories is flushed when a CPU other than the corresponding CPU acquires a lock identified by the lock ID written in the cache line.

[0007] An information processing method according to one aspect of the present disclosure includes each of a plurality of CPUs obtaining a lock for exclusive access to data in a main memory before accessing the data; writing data related to the access by the corresponding CPU and a lock ID identifying the lock related to the access into a cache line of each of a plurality of cache memories corresponding to the plurality of CPUs, in association with each other; and flushing the cache line of each of the plurality of cache memories when a CPU other than the corresponding CPU obtains a lock identified by the lock ID written in the cache line. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating an example of a schematic configuration of an information processing apparatus according to an embodiment. [Figure 2] FIG. 10 is a diagram illustrating an example of an operation of the information processing device. [Figure 3] FIG. 10 is a diagram illustrating an example of an operation of the information processing device. [Figure 4] FIG. 10 is a diagram illustrating an example of an operation of the information processing device. [Figure 5] FIG. 10 is a diagram illustrating an example of an operation of the information processing device. [Figure 6] FIG. 10 is a diagram illustrating an example of an operation of the information processing device. [Figure 7] FIG. 10 is a diagram illustrating an example of an operation of the information processing device. [Figure 8] FIG. 10 is a diagram illustrating an example of an operation of the information processing device. [Figure 9] FIG. 10 is a diagram illustrating an example of an operation of the information processing device. [Figure 10] 1 is a flowchart showing an example of a process (information processing method) executed in an information processing device. [Figure 11] FIG. 10 is a diagram illustrating an example of an operation of the information processing device. [Figure 12] FIG. 10 is a diagram illustrating an example of an operation of the information processing device. [Figure 13] FIG. 10 is a diagram illustrating an example of an operation of the information processing device. [Figure 14] FIG. 10 is a diagram illustrating an example of an operation of the information processing device. [Figure 15] 1 is a flowchart showing an example of a process (information processing method) executed in an information processing device. [Figure 16] FIG. 10 is a diagram showing an example of a lock ID that identifies multiple locks. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same elements will be designated by the same reference numerals, and redundant description will be omitted.

[0010] The present disclosure will be described in the following order: 1. Embodiment 2. Variations 2.1 First Modification 2.2 Second variant 2.3 Other 3.Example of effects

[0011] 1. Embodiment 1 is a diagram illustrating an example of a schematic configuration of an information processing device according to an embodiment. The information processing device 100 includes a plurality of CPUs 1, a plurality of cache memories 2 corresponding to the plurality of CPUs 1, a main memory 3, and a semaphore register 4.

[0012] Each of the multiple CPUs 1 accesses data from the main memory 3. It can also be said that the multiple CPUs 1 share (commonly use) the main memory 3. The CPUs 1 execute data processing, etc. by operating according to a program (software). Parallel processing of the same data by multiple CPUs 1 improves processing speed. Data may be interpreted to include data structure, and data may be appropriately interpreted as data structure within the scope of no contradiction. Figure 1 shows two CPUs 1 as examples of the multiple CPUs 1. To distinguish between the CPUs 1, they are illustrated as CPU1-1 and CPU1-2.

[0013] Each of the multiple cache memories 2 corresponds to a respective one of the multiple CPUs 1. The cache memory 2 that corresponds to CPU 1-1 and is accessed by CPU 1-1 is referred to as cache memory 2-1 and is illustrated. The cache memory 2 that corresponds to CPU 1-2 and is accessed by CPU 1-2 is referred to as cache memory 2-2 and is illustrated. It can also be said that CPU 1 has (uses) the corresponding cache memory 2. The data access speed to cache memory 2 by CPU 1 is faster than the data access speed to main memory 3 by CPU 1.

[0014] As described above, the information processing device 100 in which the multiple CPUs 1 each have a cache memory 2, share the main memory 3, and process data in the main memory 3 in parallel is also called an SMP (Symmetric Multiprocessing) system.

[0015] The cache memory 2 holds data related to accesses to the main memory 3 by the corresponding CPU 1. The data related to the access includes data read from the main memory 3 by the access. The data related to the access may also be interpreted to include data processed (e.g., rewritten) by the CPU 1 after being read. In the example shown in FIG. 1, the cache memory 2 includes an instruction cache 21 and a data cache 22.

[0016] The instruction cache 21 internally holds instructions for the CPU 1. Instructions may be read from the main memory 3, but they are never rewritten or overwritten in the main memory 3.

[0017] Data in the instruction cache 21 is illustrated as cache data 21a. In response to a data access to the main memory 3 by the corresponding CPU 1, a tag related to the access and the instruction data related to the access are written in a cache line of the cache data 21a in association with each other. The tag related to the access includes information such as the address (address value, etc.) of the accessed address in the main memory 3.

[0018] The data cache 22 internally holds data that can be processed by the CPU 1. Data is not only read from the main memory 3, but also rewritten or overwritten in the main memory 3.

[0019] Data in the data cache 22 is illustrated as cache data 22a. In response to a data access to the main memory 3 by the corresponding CPU 1, a tag related to the access, data related to the access, and a lock ID identifying a lock related to the access are written in association with each other into a cache line of the cache data 22a. The lock related to the access is a lock acquired for the access. Details of the lock and lock ID will be described later.

[0020] The data cache 22 includes an ID setting register 22b. A lock ID is set (a value is written) in the ID setting register 22b. The lock ID set in the ID setting register 22b is written, together with the tag and data related to the access, to a cache line of the cache data 22a in the same cache memory 2 (the cache memory 2 including the ID setting register 22b).

[0021] The main memory 3 is a RAM (Random Access Memory) provided for multiple CPUs 1. Note that, in Fig. 1, data datA and data datB are illustrated as examples of data stored in the main memory 3 that can be processed by the CPU 1.

[0022] The semaphore register 4 performs exclusive control using a semaphore. The semaphore register 4 provides a lock for the CPU 1 to have exclusive access to data in the main memory 3. A lock is provided for each access to the data to be locked, for example, for each access to data datA and data datB. The lock ID mentioned above is identification information that identifies a lock. The lock ID is determined based on a lock number (for example, a semaphore number) that is provided along with the lock. The lock number is, for example, the memory address value where the lock exists. The lock ID may be the same as the lock number, or may be different.

[0023] The semaphore register 4 is an example of an exclusive control mechanism. Various other exclusive control mechanisms may be used other than the semaphore register 4. Examples of other exclusive control mechanisms include exclusive control mechanisms configured to perform exclusive control using a spinlock or a mutex.

[0024] The CPU 1 acquires a lock from the semaphore register 4 and then accesses data in the main memory 3. A lock ID that identifies the lock is set in the ID setting register 22b of the cache memory 2 that corresponds to the CPU 1 that accessed the data. Only the CPU 1 that has acquired the lock can access the locked data.

[0025] After completing the data access, the CPU 1 releases the acquired lock. The lock ID set in the ID setting register 22b of the cache memory 2 corresponding to the CPU 1 is erased (the value is cleared). Any CPU 1 can now acquire the released lock and access the locked data.

[0026] When multiple CPUs 1 each have a cache memory 2 and share the main memory 3, a problem of lack of cache coherency can occur. For example, when CPU 1-1 accesses data datA in main memory 3, data datA is written to a cache line in cache memory 2-1. Subsequent accesses to data datA by CPU 1-1 are made to the data datA written to the cache line in cache memory 2-1, rather than the data datA in main memory 3.

[0027] Even if CPU1-2 rewrites data datA in main memory 3, data datA written to the cache line of cache memory 2-1 is not rewritten. CPU1-1 still accesses data datA written to the cache line of cache memory 2-1 (data datA before rewriting).

[0028] To avoid such a lack of cache coherency and maintain cache coherency, it is necessary to flush the data written to the cache line. Flushing may be interpreted to include erasing the data written to the cache line and overwriting (writing back) that data to the main memory 3.

[0029] As described above, in the information processing device 100 according to the embodiment, a lock ID is written to a cache line of the data cache 22 of the cache memory 2. The written lock ID is used to flush the cache line. Specifically, a cache line of the data cache 22 of each of the multiple cache memories 2 is flushed when a CPU 1 other than the corresponding CPU 1 acquires a lock identified by the lock ID written in the cache line.

[0030] For example, a flush instruction to flush cache lines in which a lock ID corresponding to the lock ID of a lock acquired by CPU1 is written is sent to a CPU1 other than the CPU1 that acquired the lock. An example of a corresponding lock ID is the same lock ID. Another example of a corresponding lock ID is a lock ID in which at least some of the identified multiple locks overlap, which will be described later with reference to FIG. 16. Upon receiving the flush instruction, CPU1 flushes cache lines in which the corresponding lock ID is written, from among the cache lines of the data cache 22 of the corresponding cache memory 2. This will be described specifically with reference to FIGS. 2 to 9.

[0031] 2 to 9 are diagrams showing an example of the operation of an information processing device. FIG. 2 schematically shows the lock acquisition and lock ID setting by CPU1-1. CPU1-1 acquires a lock for exclusive access to data datA in main memory 3. As indicated by the white arrow, CPU1-1 acquires the lock from semaphore register 4. A lock number is also acquired. A lock ID determined based on this lock number is called lock ID "idA." As indicated by the black arrow, CPU1-1, which has acquired the lock, sets lock ID "idA" in ID setting register 22b of cache memory 2-1. Data datA in main memory 3 is locked so that only CPU1-1 can access it.

[0032] FIG. 3 shows a schematic representation of a flush instruction from CPU1-1. After acquiring the lock, CPU1-1 instructs a CPU other than itself, CPU1-2 in this example, to flush. A flush instruction instructing a flush is sent from CPU1-1 to CPU1-2. In this example, the cache line to be flushed is a cache line written with the same lock ID as the lock ID "idA" set in the ID setting register 22b of cache memory 2-1. At the time of FIG. 3, there is no cache line written with lock ID "idA" in the data cache 22 of cache memory 2-2 corresponding to CPU1-2. Therefore, a flush is not performed.

[0033] 4 shows a schematic diagram of data access by CPU1-1. As indicated by the white arrow, CPU1-1 accesses data datA in main memory 3. A tag "tagA" relating to the access of data datA, the data datA, and a lock ID "idA" are written in association with each other into a cache line of data cache 22 in cache memory 2-1.

[0034] 5 shows a schematic diagram of the lock release by CPU 1-1. As indicated by the black arrow, CPU 1-1 erases (clears) the lock ID set in ID setting register 22b of cache memory 2-1. Data datA in main memory 3 is released so that any CPU 1 can acquire the lock and access it.

[0035] FIG. 6 shows a schematic diagram of lock acquisition and lock ID setting by CPU1-2. CPU1-2 acquires a lock for exclusive access to data datA stored in main memory 3. As indicated by the white arrow, CPU1-2 acquires the lock from semaphore register 4. A lock number is also acquired. The lock ID is "idA" as before. As indicated by the black arrow, CPU1-2, which has acquired the lock, sets lock ID "idA" in the ID setting register 22b of cache memory 2-2. Data datA in main memory 3 is locked so that only CPU1-2 can access it.

[0036] FIG. 7 shows a schematic diagram of a flush instruction from CPU1-2. Having acquired the lock, CPU1-2 instructs a CPU other than itself, CPU1, in this example, CPU1-1, to flush. The flush instruction is sent from CPU1-2 to CPU1-1. In this example, the cache line to be flushed is the one written with the same lock ID as the lock ID "idA" set in the ID setting register 22b of cache memory 2-2. Upon receiving the flush instruction, CPU1-1 flushes the cache line of the data cache 22 of cache memory 2-1 into which the lock ID "idA" has been written, as indicated by the black arrow.

[0037] 8 shows a schematic diagram of data access by CPU1-2. As indicated by the white arrow, CPU1-2 accesses data datA in main memory 3. A tag "tagA" relating to the access of data datA, the data datA, and a lock ID "idA" are written in association with each other into a cache line of data cache 22 in cache memory 2-2.

[0038] 9 shows a schematic diagram of the lock release by CPU1-2. As indicated by the black arrow, CPU1-2 erases the lock ID set in the ID setting register 22b of cache memory 2-2. Data datA in main memory 3 is released so that any CPU1 can acquire the lock and access it.

[0039] For example, a cache line is flushed in the manner described above. Even if data datA in main memory 3 is rewritten by a previous data access by CPU1-2, the pre-rewrite data datA will not remain in cache memory 2-1 corresponding to CPU1-1 due to the prior flush. Thereafter, when CPU1-1 accesses data datA, CPU1-1 accesses data from main memory 3, i.e., accesses the rewritten data datA, rather than from cache memory 2-1. Therefore, cache coherency is maintained.

[0040] In the information processing device 100, when a lock is acquired before a data access, only the cache line in which the lock ID that identifies the lock is written is flushed. For example, compared to using a snooping unit that constantly monitors data access, this method is more likely to reduce the monitoring burden and the associated power consumption. For example, this method is suitable for installation in IoT (Internet of Things) devices, etc., which require low power consumption.

[0041] Furthermore, when the same CPU 1 accesses the same data consecutively, the data is accessed from the corresponding cache memory 2, so that it is still possible to speed up data access using the cache memory 2.

[0042] 10 is a flowchart showing an example of processing (information processing method) executed in an information processing device. The flowchart illustrates several processes executed from when one CPU 1 starts data access to when it finishes data access. The explanation of the same content as above will be omitted as appropriate.

[0043] In step S1, the CPU 1 acquires from the semaphore register 4 a lock for exclusive access to data in the main memory 3.

[0044] In step S2, the CPU 1 sets a lock ID that identifies the lock in the ID setting register 22b of the corresponding cache memory 2.

[0045] In step S3, the CPU 1 instructs the CPU 1 other than the CPU 1 (its own CPU) to flush. The cache lines to be flushed are those written with, for example, the same lock ID as the lock ID set in the previous step S2. For example, a flush instruction is sent. The CPU 1 that has received the flush instruction flushes the cache lines in the data cache 22 of the corresponding cache memory 2, into which the same lock ID has been written.

[0046] In step S4, the CPU 1 accesses the data in the main memory 3. In response to the data access, the tag, data, and lock ID related to the access are written in association with each other into a cache line of the data cache 22.

[0047] In step S5, the CPU 1 erases the lock ID set in the ID setting register 22b of the corresponding cache memory 2, and releases the lock.

[0048] 2. Variations One embodiment of the disclosed technology has been described above. The disclosed technology is not limited to the above embodiment. Some modifications will be described.

[0049] 2.1 First Modification Some processes may be executed by the semaphore register 4 instead of the CPU 1. By executing some processes by the hardware (semaphore register 4), the processing load on the software (CPU 1) can be reduced. For example, there is a higher possibility of speeding up the processing.

[0050] Setting of the lock ID in the ID setting register 22b and a flush instruction to the CPU 1 may be performed by the semaphore register 4 instead of the CPU 1. This will be described with reference to FIGS.

[0051] 11 to 14 are diagrams showing an example of the operation of an information processing device. FIG. 11 schematically shows the acquisition of a lock by CPU 1-1 and the setting of a lock ID by semaphore register 4. As in FIG. 2 described above, CPU 1-1 acquires a lock for exclusive access to data datA stored in main memory 3. A lock number is also acquired. Meanwhile, in the example shown in FIG. 11, as indicated by the white arrow, semaphore register 4 sets a lock ID "idA" in the ID setting register 22b of cache memory 2-1 corresponding to CPU 1-1 that has acquired the lock, rather than CPU 1-1.

[0052] FIG. 12 schematically shows a flush instruction by the semaphore register 4. Unlike the previously described FIG. 3, in the example shown in FIG. 12, the semaphore register 4 (not the CPU 1-1 that acquired the lock) instructs a CPU 1 other than the CPU 1-1 that acquired the lock, in this example, CPU 1-2, to flush. The flush instruction is sent from the semaphore register 4 to CPU 1-2. In this example, the cache line to be flushed is a cache line written with the same lock ID as the lock ID "idA" set in the ID setting register 22b of the cache memory 2-1. At the time of FIG. 12, there is no cache line written with the lock ID "idA" in the data cache 22 of the cache memory 2-2 corresponding to CPU 1-2. Therefore, flushing is not performed.

[0053] 13 schematically shows the lock acquisition by CPU1-2 and the lock ID setting by semaphore register 4. As in the previously described FIG. 6, CPU1-2 acquires a lock to exclusively access data datA stored in main memory 3. Meanwhile, in the example shown in FIG. 13, it is not CPU1-2 but semaphore register 4 that sets the lock ID "idA" in the ID setting register 22b of cache memory 2-2 corresponding to CPU1-2, as indicated by the white arrow.

[0054] FIG. 14 schematically shows a flush instruction by semaphore register 4. Unlike the previously described FIG. 7, in the example shown in FIG. 14, semaphore register 4 (not CPU1-2 that has acquired the lock) instructs a CPU 1 other than CPU1-2 that has acquired the lock, in this example, CPU1-1, to flush. The flush instruction is sent from semaphore register 4 to CPU1-1. In this example, the cache line to be flushed is a cache line written with the same lock ID as the lock ID "idA" set in the ID setting register 22b of cache memory 2-2. Upon receiving the flush instruction, CPU1-1 flushes the cache line of the data cache 22 of cache memory 2-1 into which the lock ID "idA" has been written, as indicated by the black arrow.

[0055] 15 is a flowchart showing an example of a process (information processing method) executed in an information processing device, illustrating several processes executed by one CPU 1 from when the CPU 1 starts data access to when the CPU 1 ends the data access.

[0056] The process of step S11 is the same as step S1 described above in Fig. 10. The CPU 1 acquires from the semaphore register 4 a lock for exclusive access to data in the main memory 3.

[0057] Although not shown in Fig. 15, the same processes as those in steps S2 and S3 in Fig. 10 described above are executed by the semaphore register 4. The semaphore register 4 sets a lock ID that identifies the lock in the ID setting register 22b of the cache memory 2 that corresponds to the CPU 1 that acquired the lock. The semaphore register 4 instructs the CPUs 1 other than that CPU 1 to flush.

[0058] The process of step S12 is the same as the process of step S4 in Fig. 10 described above. The CPU 1 accesses data in the main memory. In response to the data access, the tag, data, and lock ID related to the access are written in association with each other into a cache line of the data cache 22.

[0059] In step S13, the CPU 1 releases the lock. Although not shown in Fig. 15, the semaphore register 4 erases the lock ID set in the ID setting register 22b of the cache memory 2 corresponding to that CPU 1.

[0060] 2.2 Second variant Multiple locks may be acquired to access multiple pieces of data in the main memory 3. The lock ID is expressed as, for example, a bit field so as to identify multiple locks. This will be specifically described with reference to FIG. 16.

[0061] Fig. 16 is a diagram showing an example of a lock ID that identifies multiple locks. The lock ID is represented by a bit field containing multiple bits. Note that, although the number of bits is 8 in the example shown in Fig. 16, the number of bits may be set appropriately depending on the number of locks, etc.

[0062] Each of the multiple bits indicates whether the corresponding lock has been acquired. In this example, bit "1" indicates that the corresponding lock has been acquired. Bit "0" indicates that the corresponding lock has not been acquired. Such a bit field can also be called a bit flag.

[0063] A plurality of locks are associated with any of the plurality of bits based on the hash value of the respective lock number. For example, a lock is associated with a bit of a bit number determined based on the hash value of the lock number.

[0064] In the example shown in FIG. 16, a lock for exclusive access to data datA and a lock for exclusive access to data datB are acquired. The lock number of each lock is given by semaphore register 4. The lock number corresponding to data datA is schematically illustrated as lock number "xxx." The lock number corresponding to data datB is schematically illustrated as lock number "yyy."

[0065] The hashing unit 5 hashes the lock number to set one of the bits in the bit field to "1" (turns on the flag). In this example, the hashing unit 5 hashes the lock number "xxx" to set the second bit to "1". The hashing unit 5 hashes the lock number "yyy" to set the sixth bit to "1". The bit field thus obtained, i.e., the lock ID "01000100", identifies two locks: the lock corresponding to data datA and the lock corresponding to data datB. Using a similar principle, three or more locks can also be identified.

[0066] As explained above, a lock ID that identifies multiple locks is set in the ID setting register 22b of the cache memory 2. The setting may be performed by the CPU 1 or the semaphore register 4, as explained above, or by the hashing unit 5.

[0067] Naturally, the hashing unit 5 may also be a component of the information processing device 100. The hashing unit 5 may be provided separately from the CPU 1 or the semaphore register 4, or the functions of the hashing unit 5 may be incorporated into the CPU 1 or the semaphore register 4.

[0068] As described above, a command is issued to flush cache lines in which a lock ID corresponding to the lock ID of a lock acquired by CPU 1 is written. When a lock ID identifies multiple locks as described above, the corresponding lock IDs are lock IDs with which at least some of the identified multiple locks overlap. A cache line in each of multiple cache memories 2 is flushed when a CPU 1 other than the corresponding CPU 1 acquires at least one of the multiple locks identified by the lock ID written in the cache line. This allows cache coherency to be maintained even when multiple locks are acquired to access multiple data in main memory 3.

[0069] 2.3 Other In the above embodiment, two CPUs 1, CPU1-1 and CPU1-2, are used as an example of the multiple CPUs 1. However, the number of CPUs 1 may be three or more. The same applies to the number of cache memories 2.

[0070] As mentioned above, various known exclusive control mechanisms other than the semaphore register 4 may be used as the exclusive control mechanism.

[0071] The information processing device 100 is mounted in, for example, an electronic device. An example of the electronic device is an IoT device or other device that requires low power consumption. An electronic device mounted with the information processing device 100 is also one of the embodiments.

[0072] 3.Example of effects The techniques described above can be specified, for example, as follows. One of the techniques disclosed is an information processing device 100. As described with reference to FIGS. 1 to 16, the information processing device 100 includes a plurality of CPUs 1, a plurality of cache memories 2 corresponding to the plurality of CPUs 1, and a main memory 3. Each of the plurality of CPUs 1 acquires a lock for exclusive access to data in the main memory 3 (for example, data datA or data datB) before accessing the data. Data related to access by the corresponding CPU 1 and a lock ID identifying the lock related to the access are written in a cache line (of the data cache 22) of each of the plurality of cache memories 2 in association with each other. A cache line (of the data cache 22) of each of the plurality of cache memories 2 is flushed when a CPU 1 other than the corresponding CPU 1 acquires a lock identified by the lock ID written in the cache line.

[0073] In the information processing device 100, data related to an access by the corresponding CPU 1 and a lock ID that identifies the lock related to the access are written to a cache line in association with each other. The cache line is flushed when a CPU 1 other than the corresponding CPU 1 acquires the lock identified by the lock ID written in the cache line. By flushing the cache line based on the lock ID in this way, cache coherency can be maintained.

[0074] According to the information processing device 100, when a lock is acquired before a data access, only the cache line in which the lock ID identifying the lock is written is flushed. This increases the possibility of reducing power consumption compared to, for example, using a snooping unit that constantly monitors data access. The information processing device 100 may be installed in, for example, an electronic device such as an IoT device that requires low power consumption. This increases the possibility of reducing the power consumption of the electronic device.

[0075] 3, 7, 12, and 14, a flush command to flush a cache line in which a lock ID corresponding to the lock ID of the lock acquired by CPU 1 is written may be sent to a CPU 1 other than the CPU 1 that acquired the lock. For example, a flush command can be issued in this manner.

[0076] 1, 2, 4, 6, 8, 11, 13, etc., each of the multiple cache memories 2 includes an ID setting register 22b in which a lock ID is set, and the lock ID set in the ID setting register 22b may be written to a cache line (of the data cache 22) of the same cache memory 2. For example, by using such an ID setting register 22b, the lock ID can be written to a cache line.

[0077] 2 and 6, the CPU 1 that has acquired the lock may set a lock ID in the ID setting register 22b of the corresponding cache memory 2. Also, as described with reference to Figures 3 and 7, the CPU 1 that has acquired the lock may instruct a CPU 1 other than itself to flush. This allows the setting of the lock ID and the flush instruction to be realized by software processing.

[0078] 1, 11, 13, etc., the information processing device 100 may include an exclusive control mechanism (for example, semaphore register 4) that grants a lock, and the exclusive control mechanism may set a lock ID in the ID setting register 22b of the cache memory 2 corresponding to the CPU 1 that has acquired the lock. Also, as described with reference to FIGS. 12, 14, etc., the exclusive control mechanism may instruct a CPU 1 other than the CPU 1 that has acquired the lock to flush. This allows the setting of the lock ID and the flush instruction to be realized by hardware processing.

[0079] As described with reference to FIG. 16 etc., the lock ID may be represented by a bit field including multiple bits to identify multiple locks, and each of the multiple bits may indicate whether a corresponding lock among the multiple locks has been acquired. In this case, the multiple locks may be associated with one of the multiple bits based on the hash value of each lock number. This makes it possible to maintain cache coherency even when multiple locks are acquired to access multiple data in the main memory 3.

[0080] The information processing method described with reference to Figures 10 and 15 is also one of the disclosed techniques. The information processing method includes the steps of each of multiple CPUs 1 acquiring a lock for exclusive access to data (e.g., data datA, data datB) in main memory 3 and then accessing the data (e.g., steps S1, S4, S11, and S12), writing data related to the access by the corresponding CPU 1 and a lock ID identifying the lock related to the access to a cache line of each of multiple cache memories 2 corresponding to the multiple CPUs 1 in association with each other (e.g., steps S4 and S12), and flushing the cache line of each of the multiple cache memories 2 when a CPU 1 other than the corresponding CPU 1 acquires a lock identified by the lock ID written in the cache line (e.g., step S3). As described above, cache coherency can be maintained by such an information processing method as well.

[0081] The effects described in this disclosure are merely examples and are not limited to the disclosed contents. Other effects may also be obtained.

[0082] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, components of different embodiments and modifications may be combined as appropriate.

[0083] The present technology can also be configured as follows. (1) Multiple CPUs and a plurality of cache memories corresponding to the plurality of CPUs; The main memory; Equipped with each of the plurality of CPUs acquires a lock for exclusive access to data in the main memory and then accesses the data; data relating to the access by a corresponding CPU and a lock ID identifying a lock relating to the access are written in a cache line of each of the plurality of cache memories in association with each other; A cache line of each of the plurality of cache memories is flushed when a CPU other than the corresponding CPU acquires a lock identified by a lock ID written in the cache line. Information processing device. (2) A flush instruction is sent to a CPU other than the CPU that acquired the lock, instructing it to flush the cache line in which the lock ID corresponding to the lock ID of the lock acquired by the CPU is written. An information processing device according to (1). (3) each of the plurality of cache memories includes an ID setting register in which a lock ID is set; The lock ID set in the ID setting register is written to a cache line in the same cache memory. An information processing device according to (1) or (2). (4) The CPU that has acquired the lock sets the lock ID in the ID setting register of the corresponding cache memory. (3) An information processing device according to the present invention. (5) The CPU that acquired the lock instructs the CPUs other than itself to perform the flush. An information processing device according to any one of (1) to (4). (6) It has an exclusive control mechanism that gives locks, the exclusive control mechanism sets a lock ID in the ID setting register of the cache memory corresponding to the CPU that has acquired the lock; An information processing device according to (3) or (5) citing (3). (7) It has an exclusive control mechanism that gives locks, the exclusive control mechanism instructs a CPU other than the CPU that has acquired the lock to perform the flush; The information processing device according to any one of (1) to (4) and (6). (8) The lock ID is represented by a bit field including multiple bits so as to identify multiple locks; each of the plurality of bits indicating whether a corresponding lock among the plurality of locks has been acquired; The information processing device according to any one of (1) to (7). (9) The plurality of locks are associated with any one of the plurality of bits based on a hash value of each lock number. (8) An information processing device according to (8). (10) The information processing device according to any one of (1) to (9) above, which is installed in an electronic device. (11) each of the plurality of CPUs acquires a lock for exclusive access to the data in the main memory and then accesses the data; writing data relating to the access by the corresponding CPU and a lock ID identifying a lock relating to the access into a cache line of each of a plurality of cache memories corresponding to the plurality of CPUs in association with each other; Flushing a cache line of each of the plurality of cache memories when a CPU other than the corresponding CPU acquires a lock identified by a lock ID written in the cache line; Including, Information processing methods. [Explanation of symbols]

[0084] 1 CPU 2. Cache memory 21 Instruction Cache 21a Cached Data 22 Data Cache 22a Cached Data 22b ID setting register 3. Main memory 4 Semaphore register (exclusive control mechanism) 5 Hashing section 100 Information processing device

Claims

1. A plurality of CPUs; a plurality of cache memories corresponding to the plurality of CPUs; The main memory; Equipped with each of the plurality of CPUs acquires a lock for exclusive access to data in the main memory and then accesses the data; data relating to the access by a corresponding CPU and a lock ID identifying a lock relating to the access are written in a cache line of each of the plurality of cache memories in association with each other; A cache line of each of the plurality of cache memories is flushed when a CPU other than the corresponding CPU acquires a lock identified by a lock ID written in the cache line. Information processing device.

2. A flush instruction is sent to a CPU other than the CPU that acquired the lock, the flush instruction instructing the flushing of a cache line in which a lock ID corresponding to the lock ID of the lock acquired by the CPU is written. The information processing device according to claim 1 .

3. each of the plurality of cache memories includes an ID setting register in which a lock ID is set; The lock ID set in the ID setting register is written to a cache line in the same cache memory. The information processing device according to claim 1 .

4. The CPU that has acquired the lock sets a lock ID in the ID setting register of the corresponding cache memory. The information processing device according to claim 3 .

5. The CPU that has acquired the lock instructs the CPUs other than itself to perform the flush. The information processing device according to claim 1 .

6. It has an exclusive control mechanism that gives locks, the exclusive control mechanism sets a lock ID in the ID setting register of the cache memory corresponding to the CPU that has acquired the lock; The information processing device according to claim 3 .

7. It has an exclusive control mechanism that gives locks, the exclusive control mechanism instructs a CPU other than the CPU that has acquired the lock to perform the flush; The information processing device according to claim 1 .

8. The lock ID is represented by a bit field including multiple bits so as to identify multiple locks, each of the plurality of bits indicating whether a corresponding lock among the plurality of locks has been acquired; The information processing device according to claim 1 .

9. The plurality of locks are associated with any one of the plurality of bits based on a hash value of each lock number. The information processing device according to claim 8 .

10. The information processing device according to claim 1 , which is installed in an electronic device.

11. each of the plurality of CPUs acquires a lock for exclusive access to the data in the main memory and then accesses the data; writing data relating to the access by the corresponding CPU and a lock ID identifying a lock relating to the access into a cache line of each of a plurality of cache memories corresponding to the plurality of CPUs in association with each other; Flushing a cache line of each of the plurality of cache memories when a CPU other than the corresponding CPU acquires a lock identified by a lock ID written in the cache line; Including, Information processing methods.

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