MEMORY DEVICE PERFORMING TEMPERATURE COMPENSATION AND METHOD OF OPERATING THE SAME

Abstract

To provide a memory device performing temperature compensation and a method for operating the same.SOLUTION: A memory device includes: a memory array which includes a plurality of memory cells; a page buffer circuit which is coupled to the memory array via a plurality of bit lines, includes a page buffer coupled to each of the bit lines, and carries out precharge operation on the bit lines in precharge sections for data reading; and a control logic which controls the precharge operation of the page buffer circuit in various manners in accordance with a detected temperature. The precharge sections include: a first section for overdriving the bit lines; and a second section for driving the bit lines with a voltage lower than that in the first section. The first section when the detected temperature is a first temperature is set shorter than the first section when the detected temperature is a second temperature higher than the first temperature.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a memory device, and more particularly to a memory device that performs temperature compensation and an operating method thereof. [Background technology]

[0002] Recently, the increasing multi-functionality of information and communication devices has led to a demand for larger capacity and higher integration of memory devices. Memory devices include a page buffer connected to a line (e.g., a bit line) of a memory cell to store data in the memory cell or output data from the memory cell, and the page buffer may include a semiconductor element such as a transistor. Temperature changes in the memory device can cause fluctuations in the operating characteristics of the page buffer, which can result in operational errors during data write and / or read processes or reduced data reliability. Summary of the Invention [Problem to be solved by the invention]

[0003] The technical idea of ​​the present invention provides a memory device and an operating method thereof that can reduce operation errors and improve data read speed by driving a page buffer while applying compensation for temperature changes. [Means for solving the problem]

[0004] A memory device according to the technical idea of ​​the present invention includes a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines, the page buffer circuit including a page buffer connected to each bit line, and performing a precharge operation on the bit lines in a precharge period for reading data; and control logic for differently controlling the precharge operation of the page buffer circuit according to a detected temperature, wherein the precharge period includes a first period in which the bit lines are overdriven and a second period in which the bit lines are driven with a voltage lower than that of the first period, and the first period when the detected temperature is a first temperature is set shorter than the first period when the detected temperature is a second temperature higher than the first temperature.

[0005] In addition, a memory device according to the technical idea of ​​the present invention includes a memory cell array including a plurality of memory cells, and a page buffer circuit connected to the memory cell array through a plurality of bit lines, the page buffer circuit being connected to each bit line and performing a precharge operation on the bit lines in a precharge period for reading data, each page buffer including a shut-off transistor controlling an electrical connection between a sensing node and the bit line, a bit line shut-off signal being provided to a gate of the shut-off transistor, the precharge period including an initial first period for performing overdrive and a subsequent second period, wherein a first offset corresponding to a voltage change amount of the bit line shut-off signal between the first period and the second period when the temperature of the memory device is relatively low is smaller than a second offset corresponding to a voltage change amount of the bit line shut-off signal between the first period and the second period when the temperature is relatively high.

[0006] In addition, a memory device according to the technical idea of ​​the present invention includes a memory cell region including a plurality of memory cells and a first metal pad, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region through the first metal pad and the second metal pad, the peripheral circuit region being connected to the memory cells through a plurality of bit lines and including a page buffer connected to each bit line, the page buffer circuit performing a precharge operation on the bit lines in a precharge period for reading data, and control logic for differently controlling the precharge operation of the page buffer circuit according to temperature, the precharge period including an initial first period for performing overdrive and a subsequent second period, and when the temperature of the memory device is relatively low, a first offset corresponding to a voltage change amount of the bit line shutoff signal between the first period and the second period is smaller than a second offset corresponding to a voltage change amount of the bit line shutoff signal between the first period and the second period when the temperature is relatively high. [Effects of the Invention]

[0007] According to the memory device and its operating method that performs temperature compensation according to the technical concept of the present invention, various parameters that control the precharge operation of the bit line are adjusted differently according to temperature, thereby reducing the time required for the precharge operation and improving data reliability.

[0008] In addition, according to the memory device and its operating method that perform temperature compensation of the technical concept of the present invention, by providing optimal parameters for temperature compensation in various modes of the memory device, it is possible to provide an optimal read environment across various modes, thereby improving the performance of the memory device. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram illustrating a memory device according to an embodiment of the present invention; [Figure 2] 2 is a diagram illustrating a schematic structure of the memory device of FIG. 1 according to an embodiment of the present invention; [Figure 3] 2 is a diagram illustrating an example of the memory cell array of FIG. 1 according to an embodiment of the present invention; [Figure 4] 4 is a perspective view of the memory block of FIG. 3 according to one embodiment of the present invention. [Figure 5] 1 is a circuit diagram illustrating an example of a page buffer according to an embodiment of the present invention; [Figure 6A] 10 is a graph showing an example of a change in cell current depending on temperature. [Figure 6B] 10 is a graph showing an example of fluctuation of a sensing reference current depending on temperature. [Figure 7] 1 is a graph showing the characteristics of a general shut-off transistor. [Figure 8] 10 is a graph illustrating an example of bit line control during a precharge period according to an exemplary embodiment of the present invention; [Figure 9A] 9A and 9B are diagrams showing an example of a comparison of reading performance when an embodiment of the present invention is not applied and when it is applied. [Figure 9B] 9A and 9B are diagrams showing an example of a comparison of reading performance when an embodiment of the present invention is not applied and when it is applied. [Figure 10] 1 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the present invention. [Figure 11] 1 is a block diagram illustrating an example of a memory device for driving a page buffer according to an exemplary embodiment of the present invention; [Figure 12] 10 is a waveform diagram showing an example of adjusting a first section and a second section in a precharge section. FIG. [Figure 13] 1 is a circuit diagram illustrating a specific example of a page buffer according to an exemplary embodiment of the present invention; [Figure 14] 14 is a diagram showing an example of waveforms of various control signals provided to the page buffer shown in FIG. 13; [Figure 15]1 is a diagram illustrating a memory device and an example of its operation according to an exemplary embodiment of the present invention; [Figure 16] 1 is a diagram illustrating a memory device according to another exemplary embodiment of the present invention; [Figure 17] 10 is a diagram illustrating an example of the operation of a memory device according to another exemplary embodiment of the present invention; [Figure 18] 1 is a block diagram illustrating an example in which a memory device according to an embodiment of the present invention is applied to an SSD system. [Figure 19] 1 is a cross-sectional view illustrating a memory device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0011] FIG. 1 is a block diagram illustrating a memory device 10 according to one embodiment of the present invention.

[0012] 1, the memory device 10 includes a memory cell array 100 and a peripheral circuit 200, which includes a page buffer circuit 210, a control logic 220, a voltage generator 230, and a row decoder 240. Although not shown in FIG. 1, the peripheral circuit 200 further includes a data input / output circuit or an input / output interface, etc. The peripheral circuit 200 may also include a column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc.

[0013] The memory cell array 100 may be connected to a page buffer circuit 210 through bit lines BL and to a row decoder 240 through word lines WL, string select lines SSL, and ground select lines GSL. The memory cell array 100 may include a plurality of memory cells, which may be flash memory cells, for example. Hereinafter, an embodiment of the present invention will be described in detail using an example in which the plurality of memory cells are NAND flash memory cells. However, the present invention is not limited thereto, and in some embodiments, the plurality of memory cells may be a resistive RAM (ReRAM), a phase change RAM (PRAM), a ferroelectric RAM (FRAM), or the like. RAM) or MRAM (magnetic It may also be a resistive memory cell such as a RAM.

[0014] In one embodiment, memory cell array 100 includes a three-dimensional memory cell array including multiple NAND strings, each including memory cells coupled to a word line stacked vertically on a substrate, as described below with reference to FIGS. 3 and 4. U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648 are incorporated herein by reference for details of suitable configurations for three-dimensional memory arrays in which the three-dimensional memory array is configured with multiple levels and word lines and / or bit lines are shared between the levels. However, the present invention is not limited thereto, and in some embodiments, memory cell array 100 may include a two-dimensional memory cell array including multiple NAND strings arranged along rows and columns.

[0015] The control logic 220 can output various control signals, such as a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR, for writing or programming data to the memory cell array 100, reading data from the memory cell array 100, or erasing data stored in the memory cell array 100, based on the command CMD, the address ADDR, and the control signal CTRL. Thus, the control logic 220 can generally control various operations within the memory device 10.

[0016] The voltage generator 230 may generate various types of voltages for performing program, read, and erase operations on the memory cell array 100 based on the voltage control signal CTRL_vol. Specifically, the voltage generator 230 may generate word line voltages, such as a program voltage, a read voltage, a pass voltage, an erase verify voltage, or a program verify voltage. The voltage generator 230 may also generate a string select line voltage and a ground select line voltage based on the voltage control signal CTRL_vol. The voltage generator 230 may also generate one or more voltages for driving or controlling the page buffer circuit 210 according to an exemplary embodiment of the present invention.

[0017] The row decoder 240 selects one of a plurality of memory blocks in response to a row address X-ADDR, selects one of the word lines WL of the selected memory block, and selects one of a plurality of string select lines SSL. The page buffer circuit 210 selects some of the bit lines BL in response to a column address Y-ADDR. Specifically, the page buffer circuit 210 can operate as a write driver or a sense amplifier depending on the operation mode.

[0018] The page buffer circuit 210 includes a plurality of page buffers PB connected to a plurality of bit lines BL. Each page buffer PB may be connected to a corresponding bit line BL among the plurality of bit lines BL. The page buffer circuit 210 temporarily stores data read from the memory cell array 100 or temporarily stores data to be written to the memory cell array 100. For example, each page buffer PB may include one or more latches. The latches may temporarily store data.

[0019] As an example, each page buffer PB includes one or more transistors and one or more latches for temporarily storing data. For example, each page buffer PB performs a precharge operation on a bit line BL based on the switching operation of one or more transistors, and senses data through a sensing node (not shown) electrically connected to the bit line BL. Also, based on the switching operation of the transistors, data stored in one latch can be moved to another latch, and data to be written can be provided to the memory cell array 100 through the bit line BL, or data to be read can be provided to the outside of the memory device 10 through the bit line BL.

[0020] In one embodiment, each page buffer PB includes one or more transistors for controlling a precharge operation, and the characteristics of the transistors may vary depending on the temperature of the memory device 10 or a system in which the memory device 10 is used. For example, each page buffer PB includes a shut-off transistor electrically connecting a bit line BL and a sensing node, and the shut-off transistor may be controlled by a bit line shut-off signal BLSHF applied to its gate. The level of current flowing through the shut-off transistor may vary depending on the temperature of the memory device 10 or a system in which the memory device 10 is used. For example, the shut-off transistor operates in a saturation region, and in this case, the level of current flowing through the shut-off transistor may increase as the temperature decreases. Meanwhile, a Charge Trap Flash (CTF)-based vertical NAND VNAND cell included in the memory cell array 100 may experience a decrease in cell current as the temperature decreases.

[0021] Meanwhile, in order to reduce the time required for the precharge operation, overdrive is applied to the bit line BL. For example, the precharge period includes a first period in which the bit line shutoff signal BLSHF is applied at a relatively high level to perform overdriving, and a second period in which the bit line shutoff signal BLSHF is applied at a relatively low level and maintained at that level to bias the bit line BL to a target level. In this case, in order to compensate for the characteristic that the cell current decreases at low temperatures, when overdriving is performed in the first period, the level of the bit line shutoff signal BLSHF at low temperatures may be set to a higher value than that at high temperatures.

[0022] According to an exemplary embodiment of the present invention, the memory device 10 may include a temperature sensor (not shown) for detecting temperature, and the control logic 220 may generate an internal control signal (not shown) for controlling at least one component of the peripheral circuit 200 so that a data read operation according to an embodiment of the present invention is performed based on the temperature information Temp. For example, the temperature compensation controller 221 may include control information for differently controlling various circuits in the page buffer circuit 210 or for differently setting the times of the first and second periods depending on the temperature, and the control logic 220 may control a precharge operation and / or a data sensing operation for the bit line BL based on the control information of the temperature compensation controller 221.

[0023] According to one embodiment, the level of the bit line shut-off signal BLSHF is set in the first and second sections of the precharge operation, and the level difference between the bit line shut-off signal BLSHF in the first and second sections (or the BLSHF level vBLSHF offset) may be set differently depending on the temperature. For example, the lower the temperature, the smaller the vBLSHF offset may be set. For example, at a low temperature, the difference between the level of the bit line shut-off signal BLSHF in the first section and the level of the bit line shut-off signal BLSHF in the second section may be set relatively small so that the degree to which the bit line BL is over-precharged in the first section is reduced. On the other hand, at a high temperature, the effect of over-driving on the bit line BL is relatively small, and therefore, at a high temperature, the vBLSHF offset may be set relatively larger compared to a low temperature.

[0024] In addition, the duration of the first section within the precharge section may be set differently depending on the temperature. For example, the lower the temperature, the shorter the first section within the precharge section may be, and the higher the temperature, the longer the first section within the precharge section may be. Alternatively, according to exemplary embodiments, the second section may be set to have the same duration depending on the temperature change. In this case, the lower the temperature, the shorter the overall duration of the precharge section may be. Alternatively, according to various embodiments, the duration of the data sensing section may be set differently depending on the temperature change. For example, the lower the temperature, the longer the data sensing section may be. As a result, the overall time period for data reading may be substantially the same or similar at high and low temperatures.

[0025] According to the exemplary embodiment of the present invention, temperature compensation related to the level of the bit line shut-off signal BLSHF and the duration of the first and second intervals is applied differently for the first and second intervals, thereby allowing the page buffer circuit 210 to be optimally driven in response to temperature changes and maintaining a low error ratio. For example, as described above, the current level of the shut-off transistor increases as the temperature decreases. In this case, the bit line BL is over-precharged in the first interval, causing a problem of the second interval for biasing the bit line BL to a target level becoming longer. However, according to the exemplary embodiment of the present invention, this problem can be solved by adjusting the vBLSHF offset or the duration of the first interval differently depending on the temperature. That is, by performing temperature compensation in the first interval taking into account the characteristics of a transistor (e.g., a shut-off transistor) included in the page buffer PB, unnecessary lengthening of the second interval for biasing the bit line BL to a target level can be prevented, thereby reducing the overall time required for data read and improving read performance.

[0026] Meanwhile, the memory device 10 in the embodiment illustrated in FIG. 1 may also be referred to as a storage device. For example, a storage device is a device that stores data under the control of a host device such as a computer, a smartphone, or a smart pad. The storage device may be a device that stores data in a semiconductor memory, particularly a non-volatile memory device, such as a solid-state drive (SSD) or a memory card. Although not illustrated in FIG. 1, the storage device further includes a controller that controls the memory device 10. The controller controls data storage and read operations for the memory device 10 in response to a request from the host device. For example, the controller may provide the above-described command CMD, address ADDR, and control signal CTRL to the memory device 10.

[0027] 2 is a diagram illustrating a schematic structure of the memory device 10 of FIG. 1 according to one embodiment of the present invention. While FIG. 2 illustrates a cell over periphery (COP) structure as an example of the implementation of the memory device 10, the present invention is not limited thereto, and the memory device 10 may be implemented using various structures.

[0028] 2, the memory device 10 may include a first semiconductor layer L1 and a second semiconductor layer L2, where the first semiconductor layer L1 may be stacked in a vertical direction VD relative to the second semiconductor layer L2. Specifically, the second semiconductor layer L2 may be disposed below the first semiconductor layer L1 in the vertical direction VD, such that the second semiconductor layer L2 may be disposed close to the substrate.

[0029] In one embodiment, the memory cell array 100 of FIG. 1 may be formed on a first semiconductor layer L1, and the peripheral circuit 200 of FIG. 1 may be formed on a second semiconductor layer L2. As a result, the memory device 10 has a structure in which the memory cell array 100 is disposed above the peripheral circuit 200, i.e., a COP structure. The COP structure may effectively reduce the horizontal area and improve the integration density of the memory device 10.

[0030] In one embodiment, the second semiconductor layer L2 includes a substrate, and a metal pattern (e.g., first and third lower metal layers LM0 and LM2 in FIG. 9) for wiring transistors and the transistors may be formed on the substrate to form the peripheral circuit 200 in the second semiconductor layer L2. After the peripheral circuit 200 is formed in the second semiconductor layer L2, a first semiconductor layer L1 including the memory cell array 100 may be formed, and a metal pattern may be formed to electrically connect the word lines WL and bit lines BL of the memory cell array 100 to the peripheral circuit 200 formed in the second semiconductor layer L2. For example, the bit lines BL extend in a first horizontal direction HD1, and the word lines WL extend in a second horizontal direction HD2.

[0031] FIG. 3 is a diagram illustrating an example of the memory cell array 100 of FIG. 1 according to an embodiment of the present invention.

[0032] Referring to FIG. 3, the memory cell array 100 includes a plurality of memory blocks BLK0 through BLKi, where i may be a positive integer. Each of the memory blocks BLK0 through BLKi may have a three-dimensional structure (or a vertical structure). Specifically, each of the memory blocks BLK0 through BLKi may include a plurality of NAND strings extending along a vertical direction VD. In this case, the NAND strings may be provided spaced apart by a specific distance along first and second horizontal directions HD1 and HD2. The memory blocks BLK0 through BLKi may be selected by a row decoder (240 of FIG. 1). For example, the row decoder 240 may select a memory block corresponding to a block address from among the memory blocks BLK0 through BLKi.

[0033] FIG. 4 is a perspective view showing memory block BLKa of FIG. 3 according to one embodiment of the present invention.

[0034] 4, the memory block BLKa is formed in a vertical direction relative to a substrate SUB. The substrate SUB has a first conductivity type (e.g., p-type). A common source line CSL is provided on the substrate SUB, extending along a second horizontal direction HD2 and doped with impurities of a second conductivity type (e.g., n-type). A plurality of insulating layers IL are provided in a region of the substrate SUB between two adjacent common source lines CSL, extending along the second horizontal direction HD2, in the vertical direction VD. The insulating layers IL are spaced apart by a specific distance along the vertical direction VD. For example, the insulating layers IL may include an insulating material such as silicon oxide.

[0035] A plurality of pillars P are provided on a region of the substrate SUB between two adjacent common source lines CSL, sequentially arranged along a first horizontal direction HD1 and penetrating a plurality of insulating films IL along a vertical direction VD. For example, the plurality of pillars P contact the substrate SUB by penetrating the plurality of insulating films IL. Specifically, a surface layer S of each pillar P may include a silicon material having a first type and function as a channel region. Meanwhile, an inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap.

[0036] A charge storage layer CS is provided along the insulating film IL, the pillar P, and the exposed surfaces of the substrate SUB in a region between two adjacent common source lines CSL. The charge storage layer CS may include a gate insulating layer (also referred to as a "tunneling insulating layer"), a charge trapping layer, and a blocking insulating layer. For example, the charge storage layer CS may have an ONO (oxide-nitride-oxide) structure. Furthermore, gate electrodes GE, such as select lines GSL, SSL, and word lines WL0-WL7, are provided on the exposed surfaces of the charge storage layer CS in the region between two adjacent common source lines CSL.

[0037] Drains or drain contacts DR are provided on the pillars P. For example, the drains or drain contacts DR may include a silicon material doped with impurities having a second conductivity type. Bit lines BL1 to BL3 are provided on the drains DR, extending in a first horizontal direction HD1 and spaced apart from each other along a second horizontal direction HD2.

[0038] FIG. 5 is a circuit diagram illustrating an example of a page buffer according to an embodiment of the present invention.

[0039] Referring to FIG. 5, the page buffer PB may include a cache latch unit CLU and a data latch unit DLU. The cache latch unit CLU may include a cache latch CL. For example, the cache latch CL may store data DATA to be written to a memory cell. The cache latch CL may also store data DATA transmitted from the data latch DL. The cache latch CL may be connected to a coupled sensing node SOC. The cache latch CL transmits and receives data DATA through the cache latch node SOC. Although one cache latch CL is illustrated in FIG. 5, the cache latch unit CLU may include two or more cache latches CL. The cache latch node SOC may be connected to a sensing node SO through a pass transistor T_P.

[0040] The pass transistor T_P may be turned on or off by a pass signal SO_PASS. When the pass transistor T_P is turned on, data DATA may be transmitted between the cache latch CL and the data latch DL. For example, the data latch DL may be connected to the sensing node SO and store data DATA transmitted from the cache latch CL. The data latch DL may also store data DATA read from a memory cell and transmit the data DATA to the cache latch CL. Although one data latch DL is illustrated in FIG. 5, two or more data latches DL may be included in the data latch unit DLU.

[0041] The sensing node SO is precharged during a read, write, or erase operation of the memory device 10. For example, the sensing node SO is precharged by the internal supply voltage IVC through a setup transistor T_STP. The setup transistor T_STP may be turned on or off by a bit line setup signal BLSETUP. The setup transistor T_STP may be a P-type transistor. However, the type of the setup transistor T_STP is not limited thereto. For example, the sensing node SO may be connected to the bit line BL through a shut-off transistor T_SHF. The shut-off transistor T_SHF may be turned on or off by a bit line shut-off signal BLSHF. The shut-off transistor T_SHF may be an N-type transistor. However, the type of the shut-off transistor T_SHF is not limited thereto.

[0042] According to the above-described embodiment, the page buffer PB may be controlled differently in response to temperature changes, and as an example, the shut-off transistor T_SHF may be controlled differently in the first and second sections of the precharge operation. For example, the offset (vBLSHF offset) of the bit line shut-off signal BLSHF may be controlled differently in response to temperature changes, and the lower the temperature, the smaller the vBLSHF offset may be set compared to a higher temperature. Also, at least one of the first and second sections may be adjusted differently in response to temperature, and as an example, the lower the temperature, the shorter the first section performing overdrive may be set.

[0043] 6A and 6B are graphs showing examples of changes in cell current and sensing reference current with temperature, respectively.

[0044] 5 and 6A, the cell current Id of a CTF-based vertical NAND VNAND cell decreases as the temperature decreases. The memory cell has the voltage Vg-cell current Id characteristic shown in FIG. 6A, and depending on the program state of the adjacent cell, the change (slope) of the cell current Id can be large or relatively gentle, as shown by the dotted line. In other words, when determining data based on a specific sensing reference current iCell, the level of the cell current Id varies depending on the program state of the adjacent cell, resulting in an increase in the dispersion of the threshold voltage.

[0045] As shown in Figure 6A, when a cell is read at a high temperature, the dispersion width is relatively small when determining data based on a specific sensing reference current iCell. On the other hand, when a cell is read at a low temperature without increasing the level vBLSHF of the bit line shut-off signal, the level of the cell current Id varies greatly depending on the program state of the adjacent cell, as shown by the dotted line. This results in a relatively increased dispersion width of the threshold voltage, which reduces the accuracy of data sensing. Therefore, to improve the increase in dispersion width due to changes in the cell current Id with temperature, the level vBLSHF of the bit line shut-off signal must be increased as the temperature decreases. Figure 6A shows an example in which the dispersion width of the threshold voltage decreases when the level vBLSHF of the shut-off signal is increased.

[0046] Meanwhile, FIG. 6B illustrates an example in which the sensing reference current iCell is decreased by increasing the time tSODEV of the data sensing period while increasing the level of the bit line shut-off signal BLSHF at a low temperature. As described above, programmed cells have different cell current Id characteristics depending on the threshold voltage distribution of adjacent cells. As shown in FIG. 6B, when data is read at a low temperature, the threshold voltage dispersion may be reduced when data is determined based on a relatively small sensing reference current iCell compared to when data is read at a high temperature. When a specific capacitance value and voltage Vg are applied to a cell, the cell current Id characteristically decreases over time. Therefore, by increasing the time tSODEV of the data sensing period, the level of the sensing reference current iCell for data determination is reduced. In other words, to address the problem of increased dispersion due to temperature changes, the data sensing period tSODEV should be increased as the temperature decreases, and the sensing reference current iCell should be variably set.

[0047] FIG. 7 is a graph showing the characteristics of a general shut-off transistor, and FIG. 8 is a graph showing an example of bit line control during a precharge period according to an exemplary embodiment of the present invention.

[0048] 5 to 7, unlike the cell, the shut-off transistor T_SHF has a characteristic that its current level increases as the temperature decreases. The section for precharging the bit line BL includes a first section and a second section, and the shut-off transistor T_SHF is controlled differently in the first and second sections. In the first section, which corresponds to the initial section, the bit line BL is overdriven with a bias higher than the target level for a certain period of time, thereby reducing the overall time of the pre-charge section. In this case, the shut-off transistor T_SHF operates in the saturation region of the current Id-voltage Vg curve, and in this section, the current Id level increases as the temperature decreases.

[0049] Due to the above characteristics, if the bit line BL is precharged by setting the vBLSHF offset to be the same at high and low temperatures (or if the BLSHF voltage level is significantly increased in the first section at low temperatures), the bit line BL is over-precharged, causing the dispersion to shift to the right, which leads to characteristic degradation due to an increase in the dispersion width. In one embodiment of the present invention, in the first section where overdrive is performed regardless of the target level of the bit line BL, temperature compensation is performed based on the characteristics of the transistors in the page buffer, thereby providing a method for reducing or preventing degradation due to the dispersion shift.

[0050] 5 to 8, Fig. 8 illustrates an example of the level of the bit line shut-off signal BLSHF in the precharge period and the time periods of the first and second periods, and Fig. 8 also illustrates an example of the change in the level of the bit line shut-off signal BLSHF at low and high temperatures.

[0051] In the following embodiments, the criteria for distinguishing between high and low temperatures may be set in various ways. For example, various parameter values ​​(e.g., voltage levels, time intervals, etc.) described herein may be changed in an analog manner as the temperature changes, and the parameter values ​​may be changed accordingly as the temperature changes. Alternatively, in various embodiments, a predetermined reference value related to temperature may be set, and if the detected temperature is higher than the reference value, it may be determined to be a high temperature, and if the detected temperature is lower than the reference value, it may be determined to be a low temperature, and the parameter values ​​may be changed based on the comparison with the reference value. For example, assuming that the normal temperature range of a memory device is -40°C to 105°C, a reference value may be set to any temperature or any temperature range between 40°C to 105°C at which the characteristics of memory cells (or read operation characteristics) are relatively significantly different, and a high temperature or a low temperature may be determined based on the reference value.

[0052] Alternatively, if two or more reference values ​​are set, the temperature is determined to fall into at least three ranges, and accordingly, in embodiments of the present invention, the adjustment operation related to the voltage level and / or time period is adjusted in multiple steps. In addition, whether the memory device operates at a low temperature or a high temperature may be determined based on various other criteria, and embodiments of the present invention are not necessarily limited to a specific method for determining the temperature.

[0053] In the case of low-temperature CT, the bit line shut-off signal BLSHF may increase to a first level VL_1 during a first interval tPRE_1 of the precharge period and then maintain the first level VL_1. Thereafter, as the precharge period enters a second interval tPRE_2, the level of the bit line shut-off signal BLSHF may decrease to a second level VL_2 and maintain the second level VL_2 during the second interval tPRE_2. In the case of low-temperature CT, the vBLSHF offset VL_1-VL_2, ΔV1, has a first value.

[0054] In the case of high temperature HT, the bit line shut-off signal BLSHF increases to a third level VH_1 during a first interval tPRE_1 of the precharge period and then maintains the third level VH_1. Thereafter, as the precharge period enters a second interval tPRE_2, the level of the bit line shut-off signal BLSHF decreases to a fourth level VH_2 and may maintain the fourth level VH_2 during the second interval tPRE_2. In the case of high temperature HT, the vBLSHF offset VH_1-VH_2, ΔV2, has a second value, which is greater than the first value.

[0055] 8, when the memory device is a low-temperature CT, the first interval tPRE_1 is shorter than the first interval tPRE_1 when the memory device is a high-temperature HT. Also, according to an exemplary embodiment, the second interval tPRE_2 when the memory device is a low-temperature CT and the second interval tPRE_2 when the memory device is a high-temperature HT are substantially the same or similar. Therefore, when the memory device is a low-temperature CT, the total time of the precharge interval is shorter than when the memory device is a high-temperature CT. Also, as described above, the data sensing interval tSODEV may be set longer when the memory device is a low-temperature CT than when the memory device is a high-temperature HT. In an exemplary embodiment, the data sensing interval tSODEV is set relatively longer when the memory device is a low-temperature CT, so that the total time required to read data may be substantially the same or similar between the low-temperature CT and the high-temperature HT.

[0056] According to the exemplary embodiment of the present invention, the degree to which the bit line BL is over-precharged in the low temperature CT is reduced, and therefore, the time of the second interval tPRE_2 in the low temperature CT can be prevented from being excessively increased. Also, in the exemplary embodiment, the time of the second interval tPRE_2 can be set to be the same in the low temperature CT and the high temperature HT, but since there is less need to set the second interval tPRE_2 long in the low temperature CT, it is possible to prevent the second interval tPRE_2 from being unnecessarily long even in the high temperature HT.

[0057] 8 illustrates an example in which both the vBLSHF offset and the time of the first interval tPRE_1 are applied, but the present invention is not limited thereto. For example, in an exemplary embodiment, a memory device may be implemented such that only the vBLSHF offset is adjusted according to temperature changes, or only the time of the first interval tPRE_1 is adjusted according to temperature changes.

[0058] 9A and 9B are diagrams showing an example of a comparison of reading performance when an embodiment of the present invention is not applied and when it is applied.

[0059] In Figure 9A, the vBLSHF offset is illustrated in the cases of high temperature HT and low temperature CT, and the level of the bit line shutoff signal BLSHF decreases in the first section tPRE_1 of the low temperature CT compared to when an embodiment of the present invention is not applied (the level shown by the dotted line), and therefore the vBLSHF offset ΔV1 at the low temperature CT can be set smaller than the vBLSHF offset ΔV2 at the high temperature HT.

[0060] 9B also shows a first interval tPRE_1, a second interval tPRE_2, and a data sensing interval tSODEV in the cases of high temperature HT and low temperature CT. When an embodiment of the present invention is not applied, the first interval tPRE_1 in the low temperature CT and the first interval tPRE_1 in the high temperature HT have the same time as shown by the dotted line. However, according to an embodiment of the present invention, the first interval tPRE_1 in the low temperature CT may be set shorter than the first interval tPRE_1 in the high temperature HT. Also, according to an embodiment of the present invention, the second interval tPRE_2 in both the low temperature CT and the high temperature HT may be set shorter than when an embodiment of the present invention is not applied. Also, in an exemplary embodiment, the data sensing interval tSODEV in the low temperature CT may be set longer than when the high temperature HT.

[0061] FIG. 10 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the present invention.

[0062] Referring to FIG. 10, the memory device performs a data read operation in response to a read request received from a host (or memory controller) (S11), and according to the above-described embodiment, the precharge period may include a first period for overdriving the initial bit line and a subsequent second period.

[0063] The memory device performs a data read operation according to a previously set state and determines whether the temperature has increased or decreased based on an internal temperature sensor or externally provided temperature information (S12). If it is determined that the temperature has decreased, the level of a bit line shut-off signal BLSHF applied to the gate of a transistor (e.g., a shut-off transistor) in the page buffer during the first period of the precharge period is increased to a first level Lev1 and maintained at that level (S13). On the other hand, if it is determined that the temperature has increased, the level of the bit line shut-off signal BLSHF during the first period of the precharge period is increased to a second level Lev2 and maintained at that level (S16). If the previously set level of the bit line shut-off signal BLSHF during the first period is defined as a reference level Lev0, the first level Lev1 is higher than the reference level Lev0, and the second level Lev2 is lower than the reference level Lev0.

[0064] Meanwhile, if the time of the first interval is set differently according to a temperature change and the temperature drops, it may be determined whether the elapsed time of the first interval is equal to or greater than the set first time T1 (S14). If the elapsed time is less than the first time T1, the first interval is maintained. On the other hand, if the elapsed time of the first interval is equal to or greater than the set first time T1, a first offset ΔV1 may be applied to lower the level of the bit line shut-off signal BLSHF (S15). For example, if the previously set time of the first interval is defined as a reference time T0, the first time T1 may be shorter than the reference time T0. Also, if the previously set vBLSHF offset is defined as a reference offset ΔV0, the first offset ΔV1 may be smaller than the reference offset ΔV0.

[0065] On the other hand, if the temperature rises, it may be determined whether the elapsed time of the first interval is equal to or greater than a set second time T2 (S17). The second time T2 is set to be longer than a reference time T0. If the elapsed time is less than the second time T2, the first interval is maintained. If the elapsed time of the first interval is equal to or greater than the set second time T2, a second offset ΔV2 may be applied to lower the level of the bit line shut-off signal BLSHF (S18). The second offset ΔV2 may be greater than the reference offset ΔV0.

[0066] As described above, the level of the bit line shut-off signal BLSHF decreases, and the memory device enters the second period of the precharge period (S19). According to an exemplary embodiment, the time of the second period is set to be the same regardless of temperature changes, and therefore, it is determined whether the elapsed time of the second period is equal to or greater than the set third time T3 (S20). If the elapsed time is less than the third time T3, the second period is maintained. On the other hand, if the elapsed time of the second period is equal to or greater than the set third time T3, the precharge operation ends, and the memory device enters the data sensing period (S21). Data is sensed by sensing the level of a node (e.g., a sensing node) connected to the bit line (S22).

[0067] In the above embodiment, an example is shown in which the time of the second section is set to be the same regardless of temperature changes, but the embodiment of the present invention is not limited thereto. Since the time of the first section is relatively shorter as the temperature is lower, the second section can be set to be slightly longer at low temperatures than at high temperatures.

[0068] 11 is a block diagram illustrating an example of a memory device according to an exemplary embodiment of the present invention. The various control information and setting information illustrated in FIG. 11 are merely an example, and the memory device may operate in various other ways to implement the above-described embodiment.

[0069] 11, the memory device 300 may include a page buffer 310 connected to a plurality of bit lines BL0 to BL[N-1], a scheduler 320, a clock generator (OSC) 330, a temperature sensor 340, and a voltage generator 350. According to an exemplary embodiment, transistors receiving a bit line select signal BLSLT and a bit line shut-off signal BLSHF in the page buffer 310 are simply illustrated. The scheduler 320 performs a function of scheduling various operations for reading data and may be configured, for example, as included in the control logic in the above-described embodiments. The voltage generator 350 generates the bit line shut-off signal BLSHF, and although not shown in FIG. 11, the bit line select signal BLSLT may also be generated by the voltage generator 350.

[0070] The temperature sensor 340 generates temperature information ZTC and NTC based on the detected temperature. The temperature information ZTC may have a constant level regardless of temperature, while the temperature information NTC may be a signal whose level varies linearly with temperature. The scheduler 320 provides information indicating a first interval tPRE1 and a data sensing interval tSODEV to the clock generator (OSC) 330. The clock generator (OSC) 330 may vary the period of the clock signal CLK during the first interval tPRE1 and during the data sensing interval tSODEV according to temperature. For example, the clock generator (OSC) 330 may vary the period of the clock signal CLK based on the temperature information ZTC and NTC and the period information Info_T(tPRE1) and Info_T(tSODEV). In one embodiment, the period information Info_T(tPRE1) and Info_T(tSODEV) may include coefficient information indicating an amount of period adjustment according to temperature changes.

[0071] Meanwhile, the scheduler 320 may set the first interval tPRE1 and the second interval tPRE2. For example, the first interval tPRE1 and the second interval tPRE2 may be set based on the setting information Set_T(tPRE1) and Set_T(tPRE2) and the clock signal CLK. For example, the setting information Set_T(tPRE1) and Set_T(tPRE2) may include counting information for the first interval tPRE1 and the second interval tPRE2, respectively, and intervals in which the clock signal CLK is counted a predetermined number of times may be set as the first interval tPRE1 and the second interval tPRE2. As described above, the period of the clock signal CLK is changed in the first interval tPRE1 according to changes in temperature, and the time of the first interval tPRE1 may be changed in response to changes in temperature depending on the period of the clock signal CLK. Although not shown in FIG. 11, the scheduler 320 may further receive setting information related to the data sensing period tSODEV and set the time of the data sensing period based on the clock signal CLK and the setting information.

[0072] Meanwhile, the voltage generator 350 generates the bit line shut-off signal BLSHF based on various control information and can change the level of the bit line shut-off signal BLSHF according to the temperature and the period. For example, the voltage setting information Set_V(tPRE1) and Set_V(tPRE2) may include information for setting the level of the bit line shut-off signal BLSHF in the first period tPRE1 and the second period tPRE2, and the voltage adjustment information Info_V(tPRE1) and Info_V(tPRE2) may include coefficient information indicating how much the voltage level is changed in each period according to a temperature change. The voltage generator 350 can adjust the voltage level in each period according to the above-described embodiment based on the temperature information ZTC and NTC and the voltage adjustment information Info_V(tPRE1) and Info_V(tPRE2) for the bit line shut-off signal BLSHF generated based on the voltage setting information Set_V(tPRE1) and Set_V(tPRE2).

[0073] FIG. 12 is a waveform diagram showing an example of adjusting the first and second sections in the precharge section.

[0074] 12 shows an example in which the period of the clock signal CLK is set differently between the high temperature HT and the low temperature CT, and an example in which the period of the clock signal CLK is set relatively short in the low temperature CT. The scheduler 320 sets the first interval tPRE1 according to a predetermined set counting value, and an example in which the first interval tPRE1 is relatively short in the low temperature CT because the period of the clock signal CLK is relatively short in the low temperature CT is shown. In addition, the voltage generator 350 can operate to generate the bit line shut-off signal BLSHF such that the vBLSHF offset ΔV1 in the low temperature CT is relatively smaller than the vBLSHF offset ΔV2 in the high temperature HT.

[0075] FIG. 13 is a circuit diagram showing a specific example of a page buffer according to an exemplary embodiment of the present invention, and FIG. 14 is a diagram showing an example of waveforms of various control signals provided to the page buffer shown in FIG. 13.

[0076] 13 illustrates a data latch unit of the page buffer PB. For example, the page buffer PB may include a bit line selection transistor T_SLT connected to the bit line BL and driven by a bit line selection signal BLSLT. The bit line selection transistor T_SLT may be implemented using a high voltage transistor.

[0077] Meanwhile, the page buffer PB may further include one or more latches, such as a sensing latch SL, a force latch FL, a most significant bit latch ML, and a least significant bit latch LL, connected to the sensing node SO. The page buffer PB may also include transistors disposed between the sensing node SO and the latches and operating in response to various control signals SOGND, MON_F, MON_M, and MON_L. The page buffer PB may also include a precharge circuit PC that controls a precharge operation for the bit line BL or the sensing node SO based on a bit line clamping control signal BLCLAMP, and a setup transistor T_STP driven by a bit line setup signal BLSETUP. The latches store various information. For example, the sensing latch SL may store data stored in a memory cell or a sensing result of a threshold voltage of the memory cell during a read or program verify operation. The force latch FL may be used to improve threshold voltage dispersion during a program operation. The most significant bit latch ML, the least significant bit latch LL, and a cache latch (not shown) may be used to store externally input data during a program operation.

[0078] Meanwhile, the page buffer PB may further include one or more other transistors. For example, the page buffer PB may further include a bit line shut-off transistor T_SHF and a bit line connection control transistor T_BLK connected in series between the bit line selection transistor T_SLT and the sensing node SO. The page buffer PB may also include a precharge transistor PM driven by a load signal LOAD. In an exemplary embodiment, the page buffer PB may further include a transistor that controls connection with the cache latch node SOC of the cache latch unit in response to a pass control signal SO_PASS.

[0079] An example of the operation of the page buffer PB shown in FIG. 13 will be described below with reference to FIG.

[0080] 13, the bit line shut-off signal BLSHF may have a predetermined offset between a first interval tPRE1 and a second interval tPRE2, and the level of the signal may be changed so that the offset of the bit line shut-off signal BLSHF is smaller as the temperature decreases.

[0081] 14, the setup transistor T_STP may be turned on for a portion of the period immediately before the start of the data sensing period tSODEV, and the bit line connection control transistor T_BLK may be turned on. In addition, the setup transistor T_STP may be turned off again, thereby starting the data sensing period tSODEV.

[0082] 14, temperature compensation according to an embodiment of the present invention may be applied to at least one other signal, the bit line clamping control signal BLCLAMP and the bit line connection control signal CLBLK, in addition to the bit line shut-off signal BLSHF. For example, as shown in FIG. 14, the levels of these signals have a relationship of vBLSHF≦vBLCLAMP≦vCLBLK. By applying temperature compensation, the levels of the bit line clamping control signal BLCLAMP and the bit line connection control signal CLBLK may vary depending on the temperature. Furthermore, the amount of compensation may be adjusted differently depending on the temperature. For example, the offset and the first and second intervals during the precharge operation may be adjusted differently for the bit line clamping control signal BLCLAMP and the bit line connection control signal CLBLK depending on the temperature.

[0083] Meanwhile, during the precharge operation, the level of the bit line clamping control signal BLCLAMP may be maintained constant, or as shown in FIG. 14, the level of the bit line clamping control signal BLCLAMP may also have a predetermined offset in the first period tPRE1 and the second period tPRE2, and by applying an embodiment of the present invention, the offset of the bit line clamping control signal BLCLAMP may be set to be smaller as the temperature decreases.

[0084] 15 is a diagram illustrating a memory device and an example of its operation according to an exemplary embodiment of the present invention, in which temperature detection is performed outside the memory device.

[0085] 15, the memory system 400 includes a memory controller 410 and a memory device 420, and the memory device 420 may be any of the memory devices described in the above-described embodiments. The memory controller 410 may include a temperature sensor 411 and a temperature code generator 412, and the memory device 420 may include a memory cell array 421, a page buffer circuit 422, and control logic 423. The control logic 423 may include a temperature compensation controller 423_1, and a command CMD, an address ADDR, and data DATA are transmitted and received between the memory controller 410 and the memory device 420. The memory controller 410 may provide a read command RD, as an example of the command CMD, to the memory device 420, and the memory device 420 may read data DATA based on the precharge operation and data sensing operation according to the above-described embodiments.

[0086] The temperature sensor 411 in the memory controller 410 may detect a temperature, convert the detected temperature into a digital code, and provide temperature code information CODE_T to the memory device 420. According to an exemplary embodiment, the temperature code generator 412 may generate and provide temperature code information CODE_T when the temperature fluctuates by more than a certain reference value, and may also include reference information Ref_T associated with the temperature code information CODE_T. For example, when a difference between a temperature corresponding to previously provided temperature code information CODE_T and a currently detected temperature is equal to or greater than the reference information Ref_T, the temperature code information CODE_T may be provided to the memory device 420. The control logic 423 may generate an internal control signal Ctrl_I based on various information set in the temperature compensation controller 423_1 and the temperature code information CODE_T, and provide the internal control signal Ctrl_I to the page buffer circuit 422.

[0087] Meanwhile, according to an exemplary embodiment, since the precharge operation and the data sensing operation are performed during the data read process, the memory controller 410 can also provide the temperature code information CODE_T when providing a read command RD to the memory device 420.

[0088] According to the exemplary embodiment described above, the temperature sensor and the associated bias variable circuit are removed from the memory device 420, thereby reducing the peripheral circuit area of ​​the memory device 420.

[0089] 16 and 17 are diagrams illustrating a memory device according to another exemplary embodiment of the present invention and an example of its operation, in which an example of temperature compensation in a data read mode is described.

[0090] The memory device 500 includes a memory cell array 510, a page buffer circuit 520, and control logic 530, and the control logic 530 may include a temperature compensation controller 531. According to one embodiment, the memory cell array 510 includes memory cells corresponding to a page size of 16 KB and may operate in various modes, such as a 16 KB read mode, an 8 KB read mode, and a 4 KB read mode. If the memory device 500 operates in the 4 KB read mode, one of four adjacent bit lines BL is selected to read data. The control logic 530 reads data according to the selected read mode and may provide the internal control signal Ctrl_I for the read operation described in the above embodiment to the page buffer circuit 520.

[0091] In the 4 KB read mode and the 8 KB read mode, one or more adjacent bit lines BL are grounded, while in the 16 KB read mode, adjacent bit lines BL are simultaneously precharged. Therefore, the amount of bit line BL coupling varies depending on the biasing level of the adjacent bit lines BL, and the time required for precharge may vary. Therefore, the level of the bit line shut-off signal BLSHF is controlled differently in the first and second sections depending on the read mode. In addition, according to exemplary embodiments of the present invention, temperature compensation for the bit line shut-off signal BLSHF may be applied to each read mode. In addition, according to exemplary embodiments of the present invention, a control operation is performed so that temperature compensation is applied differently depending on the read mode. For example, temperature compensation may be applied differently in the 16 KB read mode, the 4 KB read mode, and the 8 KB read mode.

[0092] Figure 17 illustrates an example of an operation of the memory device 500 illustrated in Figure 16. For convenience of explanation, Figure 17 illustrates only the 4 KB read mode and the 16 KB read mode, and the compensation amount applied to the 8 KB read mode may have a value between the compensation amount in the 4 KB read mode and the compensation amount in the 16 KB read mode.

[0093] 17, the capacitance value due to the adjacent grounded bit line BL increases in the 4 KB read mode, and the overdrive amount may be set larger than in other read modes. Therefore, at the same temperature (e.g., assuming a high temperature HT), the level vBLSHF of the bit line shutoff signal increases significantly in the 4 KB read mode during the first period, whereas the level vBLSHF of the bit line shutoff signal increases relatively less in the 16 KB read mode during the first period. Also, at the same temperature, the level vBLSHF of the bit line shutoff signal may decrease to the same value in the 4 KB read mode and the 16 KB read mode during the second period. Therefore, the vBLSHF offset may be set larger in the 4 KB read mode than in the 16 KB read mode. While the first period in the 4 KB read mode is set shorter than the first period in the 16 KB read mode in one embodiment, the present invention is not limited thereto, and the first periods may be set to the same length for both read modes.

[0094] Meanwhile, according to exemplary embodiments of the present invention, temperature compensation may be applied to various read modes. For example, in a 16 KB read mode, as the temperature decreases, the level vBLSHF of the bit line shut-off signal in the first period increases more significantly than in the high temperature period, and the level vBLSHF of the bit line shut-off signal in the second period decreases by a predetermined vBLSHF offset. In this case, the vBLSHF offset may be smaller in the low temperature period than in the high temperature period, and the first period in the low temperature period may be shorter than the first period in the high temperature period.

[0095] Also, in the case of 4KB read mode, as described above, when the temperature is low, the vBLSHF offset is set smaller than when the temperature is high, and the first interval when the temperature is low can be set shorter than the first interval when the temperature is high.

[0096] By applying an embodiment of the present invention to each of the 4 KB read mode, 8 KB read mode, and 16 KB read mode, temperature compensation can be performed so that the vBLSHF offset at low temperatures is smaller than the vBLSHF offset at high temperatures in each mode. Also, the vBLSHF offset in a relatively small size read mode at a given temperature can be set larger than the vBLSHF offset in a relatively large size read mode. For example, as shown in FIG. 17, the vBLSHF offset in the 4 KB read mode can be set larger than the vBLSHF offset in the 16 KB read mode at the same temperature.

[0097] Meanwhile, the bit line biasing level (BL Biasing Level) in the 16KB read mode also varies depending on the magnitude relationship between the selected word line bias (WL Bias) and the threshold voltage of the cell connected to the bit line BL. In one embodiment, the time of the first interval tPRE1 and the temperature compensation amount for the vBLSHF offset can be set differently depending on the selected word line bias.

[0098] FIG. 18 is a block diagram illustrating an example in which a memory device according to an embodiment of the present invention is applied to an SSD system 600. As shown in FIG.

[0099] 18, the SSD system 600 may include a host 610 and an SSD 620. The SSD 620 exchanges signals with the host 610 through a signal connector and receives power through a power connector. The SSD 620 may include an SSD controller 621, an auxiliary power supply 622, and memory devices 623_1 to 623_n. The memory devices 623_1 to 623_n may be vertically stacked NAND flash memory devices. In this case, the SSD 620 may be implemented using the embodiments described above with reference to FIGS. 1 to 17. That is, each of the memory devices 623_1 to 623_n included in the SSD 620 may apply temperature compensation to various elements, such as settings for the first and second sections of the precharge section and the vBLSHF offset.

[0100] FIG. 19 is a cross-sectional view of a memory device according to an embodiment of the present invention.

[0101] Referring to FIG. 19, the memory device 900 may have a C2C (chip to chip) structure. The C2C structure refers to fabricating an upper chip including a cell region CELL on a first wafer, fabricating a lower chip including a peripheral circuit region PERI on a second wafer different from the first wafer, and then connecting the upper and lower chips to each other by a bonding method. For example, the bonding method refers to electrically connecting a bonding metal formed on the top metal layer of the upper chip to a bonding metal formed on the top metal layer of the lower chip. For example, if the bonding metal is formed of copper (Cu), the bonding method is Cu-Cu bonding, and the bonding metal may also be formed of aluminum or tungsten. The embodiments illustrated in FIGS. 1 through 18 may be implemented by the memory device 900. For example, the page buffer circuit described above with reference to FIGS. 1 through 18 may be disposed in the peripheral circuit region PERI.

[0102] The peripheral circuit region PERI and the cell region CELL of the memory device 900 may each include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA. The peripheral circuit region PERI may include a first substrate 710, an interlayer insulating layer 715, a plurality of circuit elements 720a, 720b, and 720c formed on the first substrate 710, first metal layers 730a, 730b, and 730c connected to the plurality of circuit elements 720a, 720b, and 720c, respectively, and second metal layers 740a, 740b, and 740c formed on the first metal layers 730a, 730b, and 730c. In one embodiment, the first metal layers 730a, 730b, and 730c may be formed of tungsten, which has a relatively high resistance, and the second metal layers 740a, 740b, and 740c may be formed of copper, which has a relatively low resistance.

[0103] Although only first metal layers 730a, 730b, and 730c and second metal layers 740a, 740b, and 740c are illustrated and described herein, the present invention is not limited thereto, and at least one more metal layer may be formed on the second metal layers 740a, 740b, and 740c. At least a portion of the one or more metal layers formed on the second metal layers 740a, 740b, and 740c may be formed of aluminum, which has lower resistance than copper, which forms the second metal layers 740a, 740b, and 740c.

[0104] An interlayer insulating layer 715 is disposed on the first substrate 710 to cover the plurality of circuit elements 720a, 720b, 720c, the first metal layers 730a, 730b, 730c, and the second metal layers 740a, 740b, 740c, and may include an insulating material such as silicon oxide or silicon nitride.

[0105] Lower bonding metals 771b and 772b may be formed on the second metal layer 740b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 771b and 772b in the peripheral circuit region PERI are electrically connected to the upper bonding metals 871b and 872b in the cell region CELL by bonding, and the lower bonding metals 771b and 772b and the upper bonding metals 871b and 872b may be formed of aluminum, copper, or tungsten. The upper bonding metals 871b and 872b in the cell region CELL are also referred to as first metal pads, and the lower bonding metals 771b and 772b in the peripheral circuit region PERI are also referred to as second metal pads.

[0106] The cell region CELL may provide at least one memory block. The cell region CELL includes a second substrate 810 and a common source line 820. A plurality of word lines 831-838 (830) are stacked on the second substrate 810 along the vertical direction VD on the upper surface of the second substrate 810. A string select line and a ground select line are respectively arranged above and below the word lines 830, and a plurality of word lines 830 may be arranged between the string select line and the ground select line.

[0107] In the bit line bonding region BLBA, the channel structure CH extends vertically above the top surface of the second substrate 810, passing through the word lines 830, the string select lines, and the ground select lines. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 850c and the second metal layer 860c. For example, the first metal layer 850c may be a bit line contact, and the second metal layer 860c may be a bit line. In one embodiment, the bit line extends along a first horizontal direction HD1 parallel to the top surface of the second substrate 810.

[0108] 19, a region in which the channel structure CH and the bit lines are disposed may be defined as a bit line bonding region BLBA. The bit lines may be electrically connected to circuit elements 720c constituting the page buffer 893 in the peripheral circuit region PERI in the bit line bonding region BLBA. For example, the bit lines may be connected to upper bonding metals 871c and 872c in the peripheral circuit region PERI, and the upper bonding metals 871c and 872c may be connected to lower bonding metals 771c and 772c connected to the circuit elements 720c of the page buffer 893. In an exemplary embodiment of the present invention, the circuit elements 720c constituting the page buffer 893 include at least one transistor involved in a precharge operation and data sensing, the at least one transistor including a shut-off transistor, and the bit line shut-off signal BLSHF provided to the shut-off transistor may have a vBLSHF offset according to the above-described embodiment. In addition, based on the control of circuit element 720c included in page buffer 893, a precharge operation for the bit line is performed through upper bonding metal 871c, 872c and / or lower bonding metal 771c, 772c, and in the case of low temperature, the degree to which the bit line is over-precharged in the above-mentioned first period is reduced, so that the vBLSHF offset corresponding to the difference between the level of bit line shutoff signal BLSHF in the first period and the level of bit line shutoff signal BLSHF in the second period can be set relatively small compared to the case of high temperature.

[0109] In the word line bonding region WLBA, the word lines 830 may extend along a second horizontal direction HD2 parallel to the top surface of the second substrate 810 and may be connected to a plurality of cell contact plugs 841-847 (840). The word lines 830 and the cell contact plugs 840 may be connected to each other through pads provided by at least portions of the word lines 830 extending by different lengths in the second horizontal direction. A first metal layer 850b and a second metal layer 860b may be sequentially connected to an upper portion of the cell contact plug 840 connected to the word line 830. The cell contact plug 840 may be connected to the peripheral circuit region PERI through upper bonding metals 871b and 872b of the cell region CELL and lower bonding metals 771b and 772b of the peripheral circuit region PERI in the word line bonding region WLBA.

[0110] The cell contact plug 840 may be electrically connected to a circuit element 720b constituting a row decoder 894 in the peripheral circuit region PERI. In one embodiment, the operating voltage of the circuit element 720b constituting the row decoder 894 may be different from the operating voltage of the circuit element 720c constituting the page buffer 893. For example, the operating voltage of the circuit element 720c constituting the page buffer 893 may be higher than the operating voltage of the circuit element 720b constituting the row decoder 894.

[0111] A common source line contact plug 880 may be disposed in the external pad bonding region PA. The common source line contact plug 880 may be formed of a conductive material such as metal, metal compound, or polysilicon and may be electrically connected to the common source line 820. A first metal layer 850a and a second metal layer 860a may be sequentially stacked on the common source line contact plug 880. For example, the region where the common source line contact plug 880, the first metal layer 850a, and the second metal layer 860a are disposed may be defined as the external pad bonding region PA.

[0112] 19, a lower insulating film 701 is formed under a first substrate 710 to cover the lower surface of the first substrate 710, and a first I / O pad 705 is formed on the lower insulating film 701. The first I / O pad 705 may be connected to at least one of a plurality of circuit elements 720a, 720b, and 720c disposed in the peripheral circuit region PERI through a first I / O contact plug 703 and may be separated from the first substrate 710 by the lower insulating film 701. In addition, a side insulating film may be disposed between the first I / O contact plug 703 and the first substrate 710 to electrically separate the first I / O contact plug 703 from the first substrate 710.

[0113] 19, an upper insulating film 801 covering the upper surface of the second substrate 810 may be formed on the second substrate 810, and a second I / O pad 805 may be disposed on the upper insulating film 801. The second I / O pad 805 may be connected to at least one of a plurality of circuit elements 720a, 720b, and 720c disposed in the peripheral circuit region PERI through a second I / O contact plug 803.

[0114] According to the embodiment, the second substrate 810 and the common source line 820 are not disposed in the region where the second I / O contact plug 803 is disposed. In addition, the second I / O pad 805 does not overlap with the word line 830 in the third direction (Z-axis direction). Referring to Fig. 19, the second I / O contact plug 803 is separated from the second substrate 810 in a direction parallel to the top surface of the second substrate 810 and may be connected to the second I / O pad 805 through the interlayer insulating layer 815 of the cell region CELL.

[0115] Depending on the embodiment, the first I / O pad 705 and the second I / O pad 805 may be selectively formed. For example, the memory device 900 may include only the first I / O pad 705 disposed on the first substrate 710, or only the second I / O pad 805 disposed on the second substrate 810. Alternatively, the memory device 900 may include both the first I / O pad 705 and the second I / O pad 805.

[0116] In each of the external pad bonding area PA and the bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, the metal pattern of the top metal layer may exist as a dummy pattern, or the top metal layer may not exist.

[0117] In the memory device 900, a lower metal pattern 773a having the same shape as the upper metal pattern 872a of the cell region CELL may be formed in the uppermost metal layer of the peripheral circuit region PERI in the external pad bonding region PA, corresponding to the upper metal pattern 872a formed in the uppermost metal layer of the cell region CELL. The lower metal pattern 773a formed in the uppermost metal layer of the peripheral circuit region PERI is not connected to a separate contact in the peripheral circuit region PERI. Similarly, an upper metal pattern having the same shape as the lower metal pattern of the peripheral circuit region PERI may be formed in the upper metal layer of the cell region CELL in the external pad bonding region PA, corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI.

[0118] Lower bonding metals 771b and 772b may be formed on the second metal layer 740b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 771b and 772b in the peripheral circuit region PERI may be electrically connected to the upper bonding metals 871b and 872b in the cell region CELL by bonding.

[0119] In addition, in the bit line bonding region BLBA, an upper metal pattern 892 having the same shape as the lower metal pattern 752 in the peripheral circuit region PERI may be formed in the uppermost metal layer of the cell region CELL in correspondence with the lower metal pattern 752 formed in the uppermost metal layer of the peripheral circuit region PERI. No contact is formed on the upper metal pattern 892 formed in the uppermost metal layer of the cell region CELL.

[0120] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical idea of ​​the present invention and are not used to limit the meaning or the scope of the present invention as described in the claims. Therefore, a person skilled in the art will understand that various modifications and equivalent embodiments are possible. Therefore, the true technical scope of protection of the present invention should be determined by the technical idea of ​​the claims. [Explanation of symbols]

[0121] 10 Memory Device 100 memory cell array 200 Peripheral Circuits 210 Page buffer circuit 220 Control Logic 230 Voltage Generator 240 Row Decoder BL Bit Line WL Word Line SSL String Selection Line GSL Ground Select Line CMD command ADDR Address CTRL control signal CTRL_vol voltage control signal X-ADDR Row address Y-ADDR Column Address

Claims

1. a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines, the page buffer circuit including a page buffer connected to each bit line, for performing a precharge operation on the bit lines during a precharge period for reading data; and control logic for differently controlling a precharge operation of the page buffer circuit according to the detected temperature; the precharge interval includes a first interval in which the bit line is overdriven and a second interval in which the bit line is driven at a voltage lower than the first interval, and the first interval when the detected temperature is a first temperature is set shorter than the first interval when the detected temperature is a second temperature higher than the first temperature.

2. The page buffer includes a shut-off transistor for controlling an electrical connection between a sensing node and the bit line, and a bit line shut-off signal is provided to a gate of the shut-off transistor; At the first temperature, the bit line shut-off signal rises to a first level in the first period, and at the second temperature, the bit line shut-off signal rises to a second level in the first period; 2. The memory device of claim 1, wherein the first level is higher than the second level.

3. At the first temperature, the bit line shut-off signal is decreased to a third level in the second period, and at the second temperature, the bit line shut-off signal is decreased to a fourth level in the second period; 3. The memory device of claim 2, wherein a first offset corresponding to a difference between the first level and the third level is smaller than a second offset corresponding to a difference between the second level and the fourth level.

4. 4. The memory device of claim 1, wherein the second period at the first temperature has the same duration as the second period at the second temperature.

5. After the precharge period, a data sensing period is performed. The memory device of claim 1 , wherein the data sensing period at the first temperature is set to be longer than the data sensing period at the second temperature.

6. Receives temperature information along with a read command from an external controller, 2. The memory device of claim 1, wherein the control logic controls a precharge operation of the page buffer circuit differently based on temperature information provided by the external controller.

7. a temperature sensor for detecting the temperature of the memory device; a clock generator for generating clock signals having different periods according to the temperature detection result from the temperature sensor; a voltage generator that generates a bit line shut-off signal that is provided to a gate of a shut-off transistor that controls an electrical connection between the sensing node and the bit line; 2. The memory device of claim 1, wherein the control logic adjusts the time of the first period based on counting the clock signal having different periods according to the temperature.

8. a period of the clock signal corresponding to the first temperature is shorter than a period of the clock signal corresponding to the second temperature; 8. The memory device of claim 7, wherein the time required to count the clock signal N times (where N is an integer greater than or equal to 1) is set to the time of the first interval, so that the first interval at the first temperature is set shorter than the first interval at the second temperature.

9. the memory cell array includes a number of pages, and the size of data read from each page is variable according to an operation mode; The page buffer includes a shut-off transistor for controlling an electrical connection between a sensing node and the bit line, and a bit line shut-off signal is provided to a gate of the shut-off transistor; 2. The memory device of claim 1, wherein a level of the bit line shut-off signal in the first period in a first operation mode in which the size of the read data is smaller is higher than a level of the bit line shut-off signal in the first period in a second operation mode in which the size of the read data is larger.

10. 1. A memory device, comprising: a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines, including a page buffer connected to each bit line, for performing a precharge operation on the bit lines during a precharge period for reading data; Each page buffer includes a shut-off transistor that controls an electrical connection between a sensing node and the bit line, and a bit line shut-off signal is provided to a gate of the shut-off transistor; the precharge section includes an initial first section for performing overdrive and a subsequent second section; a first offset corresponding to a voltage change amount of the bit line shutoff signal between the first interval and the second interval when the temperature of the memory device is low is smaller than a second offset corresponding to a voltage change amount of the bit line shutoff signal between the first interval and the second interval when the temperature is high.

11. At the low temperature, the bit line shut-off signal rises to a first level in the first period, and at the high temperature, the bit line shut-off signal rises to a second level in the first period; 11. The memory device of claim 10, wherein the first level is higher than the second level.

12. At the low temperature, the bit line shut-off signal drops to a third level in the second section, and at the high temperature, the bit line shut-off signal drops to a fourth level in the second section; 12. The memory device of claim 11, wherein a difference between the first level and the second level is smaller than a difference between the third level and the fourth level.

13. 13. The memory device according to claim 10, wherein the first section at the low temperature is set to be shorter than the first section at the high temperature.

14. 14. The memory device of claim 13, wherein the second interval at the low temperature has the same duration as the second interval at the high temperature.

15. Each of the page buffers includes: a first transistor connected between the shut-off transistor and the sensing node; a precharge circuit connected to a node between the shut-off transistor and the first transistor, and configured to control a precharge operation based on a bit line clamping control signal; 11. The memory device of claim 10, wherein the bit line clamping control signal has a higher level than the bit line shut-off signal during the precharge period.

16. 16. The memory device of claim 15, wherein compensation for temperature changes is applied to the bit line clamping control signal, so that the bit line clamping control signal has different levels at the low temperature and the high temperature.

17. the first transistor electrically connects the shut-off transistor and the sensing node in response to a first gate signal; 16. The memory device of claim 15, wherein compensation for temperature change is applied to the first gate signal, so that the first gate signal has different levels at the low temperature and the high temperature.

18. a temperature sensor for detecting the temperature of the memory device; and a control logic for controlling a precharge operation of the page buffer circuit differently according to the temperature detected by the temperature sensor.

11. The memory device of claim 10, wherein the control logic increases the level of the bit line shut-off signal in the first period, decreases an offset of the bit line shut-off signal, and shortens the first period as the temperature detected by the temperature sensor decreases.

19. 1. A memory device, comprising: a memory cell region including a plurality of memory cells and a first metal pad; a peripheral circuit region including a second metal pad and vertically connected to the memory cell region through the first metal pad and the second metal pad; The peripheral circuit region includes: a page buffer circuit connected to the memory cells through a plurality of bit lines, the page buffer circuit including a page buffer connected to each bit line, for performing a precharge operation on the bit lines during a precharge period for reading data; and a control logic for differently controlling a precharge operation of the page buffer circuit according to temperature; The page buffer includes a shut-off transistor for controlling an electrical connection between a sensing node and the bit line, and a bit line shut-off signal is provided to a gate of the shut-off transistor; the precharge period includes an initial first period in which overdrive is performed and a subsequent second period, and a first offset corresponding to a voltage change amount of the bit line shutoff signal between the first period and the second period when the temperature of the memory device is low is smaller than a second offset corresponding to a voltage change amount of the bit line shutoff signal between the first period and the second period when the temperature is high.

20. 20. The memory device of claim 19, wherein the first metal pad and the second metal pad are made of copper.

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