Switching devices, electronic devices, vehicles

Abstract

A switch device 1 comprises: an N-type semiconductor substrate 201; a power MISFET 9 having the N-type semiconductor substrate 201 as a drain; an input electrode 13 which accepts an input signal IN; a control circuit 10 which generates a gate control signal SG for the power MISFET 9 in accordance with the input signal IN; and a negative current preventing circuit 100 provided between the input electrode 13 and the control circuit 10. The negative current preventing circuit 100 includes: a P-channel type MISFET P1 which is connected between the input electrode 13 and the control circuit 10 with a drain on the input electrode 13 side and a source and a back gate both on the control circuit 10 side, a constant potential being applied to a gate, and the potential of the back gate being separated from the potential of the N-type semiconductor substrate 201; and a diode D1 connected between the input electrode 13 and the control circuit 10 with an anode on the input electrode 13 side and a cathode on the control circuit 10 side.

Description

[Technical Field]

[0001] The invention disclosed in this specification relates to a switch device, and an electronic device and a vehicle using the same. [Background technology]

[0002] The applicant of the present application has proposed many new technologies relating to switching devices such as in-vehicle IPDs (intelligent power devices) (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2017 / 187785 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the conventional switch device, there is room for further consideration regarding the negative current prevention function.

[0005] In view of the above-mentioned problems discovered by the inventors of the present application, the invention disclosed in this specification aims to provide a switch device that can prevent the generation of negative current, and an electronic device and a vehicle that use the same. [Means for solving the problem]

[0006] For example, a switch device disclosed in this specification includes an N-type semiconductor substrate, a power MISFET configured to use the N-type semiconductor substrate as a drain, an input electrode configured to receive an input signal, a control circuit configured to generate a gate control signal for the power MISFET in response to the input signal, and a negative current prevention circuit provided between the input electrode and the control circuit and configured to prevent a negative current from flowing toward the input electrode, wherein the negative current prevention circuit includes a P-channel MISFET connected between the input electrode and the control circuit with its drain on the input electrode side and its source and back gate on the control circuit side, and with a constant potential applied to its gate so that the potential of the back gate is separated from the potential of the N-type semiconductor substrate, and a diode configured to be connected between the input electrode and the control circuit with its anode on the input electrode side and its cathode on the control circuit side.

[0007] Still other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto. [Effects of the Invention]

[0008] According to the invention disclosed in this specification, it is possible to provide a switch device that can prevent the generation of negative current, and an electronic device and a vehicle that use the same. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a perspective view of a semiconductor device seen from one direction. [Figure 2] FIG. 2 is a block circuit diagram showing the electrical structure of the semiconductor device. [Figure 3] FIG. 3 is a circuit diagram for explaining the normal operation and active clamp operation of the semiconductor device. [Figure 4] FIG. 4 is a waveform diagram of the main electrical signals. [Figure 5]FIG. 5 is a diagram showing a comparative example of a negative current prevention circuit. [Figure 6] FIG. 6 is a diagram showing a first embodiment of a negative current prevention circuit. [Figure 7] FIG. 7 is a diagram showing the device structure of a P-channel MISFET. [Figure 8] FIG. 8 is a diagram illustrating an example of the operation of the negative current prevention circuit. [Figure 9] FIG. 9 shows the results of latch-up verification. [Figure 10] FIG. 10 is a diagram showing a second embodiment of the negative current prevention circuit. [Figure 11] FIG. 11 is a diagram showing an example of connections of the gate control circuit. [Figure 12] FIG. 12 is a diagram illustrating an example of operation at the time of normal startup. [Figure 13] FIG. 13 is a diagram illustrating an example of operation when a startup failure occurs. [Figure 14] FIG. 14 is a diagram showing the relationship between the channel width and the body diode current. [Figure 15] FIG. 15 is an external view showing an example of the configuration of a vehicle. DETAILED DESCRIPTION OF THE INVENTION

[0010] <Semiconductor device> Various embodiments of a semiconductor device will be described below with reference to the accompanying drawings.

[0011] 1 is a perspective view seen from one direction of the semiconductor device 1. In the following, an embodiment in which the semiconductor device 1 is a low-side switch device (a so-called low-side switch LSI) will be described.

[0012] 1, semiconductor device 1 includes a semiconductor layer 2. Semiconductor layer 2 includes silicon. Semiconductor layer 2 is formed in the shape of a rectangular parallelepiped chip. Semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting first main surface 3 and second main surface 4.

[0013] The first major surface 3 and the second major surface 4 are formed in a quadrangular shape in a plan view (hereinafter simply referred to as "plan view") as viewed from their normal direction Z. The side surfaces 5A and 5C extend along the first direction X and face each other in the second direction Y that intersects the first direction X. The side surfaces 5B and 5D extend along the second direction Y and face each other in the first direction X. More specifically, the second direction Y is orthogonal to the first direction X.

[0014] An output region 6 and an input region 7 are set in the semiconductor layer 2. The output region 6 is set in the region on the side surface 5C side. The input region 7 is set in the region on the side surface 5A side. In a plan view, the area SOUT of the output region is not less than the area SIN of the input region (SIN≦SOUT).

[0015] The ratio SOUT / SIN of the area SOUT to the area SIN may be not less than 1 and not more than 10 (1<SOUT / SIN≦10). The ratio SOUT / SIN may be not less than 1 and not more than 2, not less than 2 and not more than 4, not less than 4 and not more than 6, not less than 6 and not more than 8, or not less than 8 and not more than 10. The planar shape of the input region 7 and the planar shape of the output region 6 are arbitrary and are not limited to a specific shape. Of course, the ratio SOUT / SIN may also be more than 0 and less than 1.

[0016] The output region 6 includes a power MISFET [Metal Insulator Semiconductor Field Effect Transistor] 9 as an example of an insulated gate type power transistor. The power MISFET 9 includes a gate, a drain, and a source.

[0017] The input region 7 includes a controller 10 as an example of a control circuit for controlling the power MISFET 9. The controller 10 includes multiple types of functional circuits for realizing various functions. The multiple types of functional circuits include a circuit for generating a gate control signal SG for driving and controlling the power MISFET 9 based on an external electrical signal. The controller 10 and the power MISFET 9 form a so-called IPD (Intelligent Power Device). The IPD is also called an IPM (Intelligent Power Module).

[0018] The input region 7 is electrically isolated from the output region 6 by a region isolation structure 8. In Fig. 1, the region isolation structure 8 is indicated by hatching. Although a detailed description is omitted, the region isolation structure 8 may have a trench isolation structure in which an insulator is buried in a trench.

[0019] A plurality of electrodes 11, 12, and 13 (three in this embodiment) are formed on the semiconductor layer 2. In Fig. 1, the plurality of electrodes 11 to 13 are indicated by hatching. The plurality of electrodes 11 to 13 are formed as terminal electrodes that are connected to the outside by conductive wires (e.g., bonding wires) or the like. The number, arrangement, and planar shape of the plurality of electrodes 11 to 13 are arbitrary and are not limited to the form shown in Fig. 1.

[0020] The number, arrangement and planar shape of the plurality of electrodes 11 to 13 are adjusted according to the specifications of the power MISFET 9 and the controller 10. In this embodiment, the plurality of electrodes 11 to 13 include a drain electrode 11 (output electrode), a source electrode 12 (reference voltage electrode) and an input electrode 13.

[0021] The drain electrode 11 is formed on the second main surface 4 of the semiconductor layer 2. The drain electrode 11 transmits the electric signal generated by the power MISFET 9 to the outside.

[0022] The drain electrode 11 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The drain electrode 11 may have a single-layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer. The drain electrode 11 may have a stacked structure in which at least two of the Ti layer, the Ni layer, the Au layer, the Ag layer, and the Al layer are stacked in any manner.

[0023] The source electrode 12 is formed on the output region 6 on the first main surface 3. The source electrode 12 provides a reference voltage (such as a ground voltage) to various functional circuits of the power MISFET 9 and the controller 10.

[0024] The input electrode 13 is formed on the input region 7 on the first main surface 3. The input electrode 13 transmits an input voltage for driving the controller 10.

[0025] On the semiconductor layer 2, a gate control wiring 17 as an example of a control wiring is further formed. The gate control wiring 17 is selectively routed to the output region 6 and the input region 7. The gate control wiring 17 is electrically connected to the gate of the power MISFET 9 in the output region 6 and is electrically connected to the controller 10 in the input region 7.

[0026] The gate control wiring 17 transmits a gate control signal SG generated by the controller 10 to the gate of the power MISFET 9. The gate control signal SG includes an on signal Von and an off signal Voff, and controls the on state and the off state of the power MISFET 9.

[0027] The on signal Von is higher than the gate threshold voltage Vth of the power MISFET 9 (Vth < Von). The off signal Voff is lower than the gate threshold voltage Vth of the power MISFET 9 (Voff < Vth). The off signal Voff may be a reference voltage (such as a ground voltage).

[0028] In this embodiment, two gate control wirings 17 are routed to different regions. The number, arrangement, shape, etc. of the gate control wirings 17 are arbitrary and are adjusted according to the transmission distance of the gate control signal SG, the branching paths of the gate control signal SG to be transmitted, etc.

[0029] The source electrode 12, the input electrode 13, and the gate control wiring 17 may each contain at least one of nickel, palladium, aluminum, copper, an aluminum alloy, and a copper alloy.

[0030] The source electrode 12, the input electrode 13, and the gate control wiring 17 may each contain at least one of an Al-Si-Cu (aluminum-silicon-copper) alloy, an Al-Si (aluminum-silicon) alloy, and an Al-Cu (aluminum-copper) alloy.

[0031] The source electrode 12, the input electrode 13, and the gate control wiring 17 may contain the same kind of electrode material, or may contain different electrode materials.

[0032] Fig. 2 is a block circuit diagram showing the electrical structure of the semiconductor device 1 shown in Fig. 1. The following description will be given taking as an example a case where the semiconductor device 1 is mounted on a vehicle.

[0033] The semiconductor device 1 includes a drain electrode 11 as an output electrode, a source electrode 12 as a reference voltage electrode, an input electrode 13, a gate control wiring 17, a power MISFET 9, and a controller 10.

[0034] The drain electrode 11 is electrically connected to the drain of the power MISFET 9. The drain electrode 11 is connected to a load. The source electrode 12 is electrically connected to the source of the power MISFET 9. The source electrode 12 provides a reference voltage (e.g., ground voltage GND) to the power MISFET 9 and the controller 10.

[0035] The input electrode 13 may be connected to an MCU (Micro Controller Unit), a DC / DC converter, an LDO (Low Drop Out), or the like. The input electrode 13 provides an input voltage to the controller 10. The input voltage input to the input electrode 13 can also be understood as an input signal IN for controlling the on / off of the power MISFET 9. For example, the power MISFET 9 is turned on when the input signal IN is at a high level, and turned off when the input signal IN is at a low level. The gate of the power MISFET 9 is connected to the controller 10 (particularly, the gate control circuit 25 described below) via the aforementioned gate control wiring 17.

[0036] In this embodiment, the controller 10 includes a current / voltage control circuit 23, a protection circuit 24, a gate control circuit 25, and an active clamp circuit 26.

[0037] The current / voltage control circuit 23 is connected to the source electrode 12, the input electrode 13, the protection circuit 24, and the gate control circuit 25. The current / voltage control circuit 23 generates various currents and voltages in response to the electrical signals from the input electrode 13 and the electrical signals from the protection circuit 24. In this embodiment, the current / voltage control circuit 23 includes a constant voltage generation circuit 32 and a reference voltage / reference current generation circuit 33.

[0038] The constant voltage generating circuit 32 generates a constant voltage VREG for driving various circuits integrated in the semiconductor device 1. The constant voltage generating circuit 32 may include a Zener diode or a regulator circuit. The constant voltage VREG may be equal to or greater than 1 V and equal to or less than 5 V. The constant voltage VREG is input to, for example, the protection circuit 24.

[0039] The reference voltage / reference current generation circuit 33 generates a reference voltage VREF and a reference current IREF for the various circuits integrated in the semiconductor device 1. The reference voltage VREF may be 1 V or more and 5 V or less. The reference current IREF may be 1 mA or more and 1 A or less. The reference voltage VREF and the reference current IREF are input to, for example, the protection circuit 24. If the various circuits described above include a comparator, the reference voltage VREF and the reference current IREF may be input to the comparator.

[0040] The protection circuit 24 is connected to the current / voltage control circuit 23, the gate control circuit 25, and the source of the power MISFET 9. The protection circuit 24 includes an overcurrent protection circuit 34 and an overheat protection circuit 36.

[0041] The overcurrent protection circuit 34 protects the power MISFET 9 from an overcurrent. The overcurrent protection circuit 34 is connected to the gate control circuit 25. The overcurrent protection circuit 34 may include a current monitor circuit. A signal generated by the overcurrent protection circuit 34 is input to the gate control circuit 25.

[0042] The overheat protection circuit 36 ​​protects the power MISFET 9 from an excessive temperature rise. The overheat protection circuit 36 ​​is connected to the current / voltage control circuit 23. The overheat protection circuit 36 ​​monitors the temperature of the semiconductor device 1. The overheat protection circuit 36 ​​may include a temperature-sensing device such as a temperature-sensing diode or a thermistor. A signal generated by the overheat protection circuit 36 ​​is input to the current / voltage control circuit 23.

[0043] The gate control circuit 25 controls the on and off states of the power MISFET 9. The gate control circuit 25 is connected to the current / voltage control circuit 23, the protection circuit 24, and the gate of the power MISFET 9.

[0044] The gate control circuit 25 generates a gate control signal SG for the power MISFET 9 in response to the electrical signal from the current / voltage control circuit 23 and the electrical signal from the protection circuit 24. The gate control signal SG is input to the gate of the power MISFET 9 via the gate control wiring 17.

[0045] The active clamp circuit 26 protects the power MISFET 9 from back electromotive force. The active clamp circuit 26 is connected to the drain electrode 11 and the gate of the power MISFET 9. The active clamp circuit 26 may include a plurality of diodes.

[0046] The active clamp circuit 26 may include a plurality of diodes connected together in a forward bias. The active clamp circuit 26 may include a plurality of diodes connected together in a reverse bias. The active clamp circuit 26 may include a plurality of diodes connected together in a forward bias and a plurality of diodes connected together in a reverse bias.

[0047] The multiple diodes may include p-n junction diodes, Zener diodes, or a combination of p-n junction diodes and Zener diodes. The active clamp circuit 26 may include multiple Zener diodes connected to each other in a biased manner. The active clamp circuit 26 may include a Zener diode and a p-n junction diode connected to each other in a reverse biased manner.

[0048] Fig. 3 is a circuit diagram for explaining the normal operation and active clamp operation of the semiconductor device 1 shown in Fig. 1. Fig. 4 is a waveform diagram of main electrical signals applied to the circuit diagram shown in Fig. 3.

[0049] Here, normal operation and active clamp operation of the semiconductor device 1 will be described using an example circuit in which an inductive load L is connected to the drain of a power MISFET 9. Examples of the inductive load L include devices that use a winding (coil), such as a solenoid, a motor, a transformer, and a relay. The inductive load L is also referred to as an L load.

[0050] Referring to FIG. 3, the source of the power MISFET 9 is connected to the ground. The drain of the power MISFET 9 is electrically connected to the inductive load L. The gate and drain of the power MISFET 9 are connected to the active clamp circuit 26. The gate and source of the power MISFET 9 are connected to the resistor R. The active clamp circuit 26 includes k zener diodes DZ (k is a natural number) that are biased to each other in this circuit example.

[0051] Referring to FIGS. 3 and 4, when an on signal Von is input to the gate of the off-state power MISFET 9, the power MISFET 9 switches from the off state to the on state (normal operation). The on signal Von has a voltage equal to or higher than the gate threshold voltage Vth (Vth≦Von). The power MISFET 9 is maintained in the on state for a predetermined on time TON.

[0052] When the power MISFET 9 switches to the on state, the drain current ID starts to flow from the drain to the source of the power MISFET 9. The drain current ID increases in proportion to the on time TON of the power MISFET 9. The inductive load L accumulates inductive energy due to the increase in the drain current ID .

[0053] When an off signal Voff is input to the gate of the power MISFET 9, the power MISFET 9 switches from the on state to the off state. The off signal Voff has a voltage lower than the gate threshold voltage Vth (Voff<Vth). The off signal Voff may be a reference voltage (for example, the ground voltage). When the power MISFET 9 switches to the off state, the inductive energy of the inductive load L is applied to the power MISFET 9 as a back electromotive force.

[0054] As a result, the power MISFET 9 enters the active clamp state (active clamp operation). When the power MISFET 9 enters the active clamp state, the drain voltage VDS rapidly rises to the clamp voltage VDSSCL.

[0055] When the clamp voltage VDSSCL exceeds the maximum rated drain voltage VDSS (VDSS < VDSSCL), the power MISFET 9 will be damaged. The power MISFET 9 is designed such that the clamp voltage VDSSCL is less than or equal to the maximum rated drain voltage VDSS (VDSSCL ≤ VDSS).

[0056] When the clamp voltage VDSSCL is less than or equal to the maximum rated drain voltage VDSS (VDSSCL ≤ VDSS), the reverse current IZ flows into the active clamp circuit 26. As a result, a limiting voltage VL is formed between the terminals of the active clamp circuit 26. In this form, the limiting voltage VL is the sum of the terminal voltages VZ of the Zener diode DZ in the active clamp circuit 26 (VL = k·VZ).

[0057] Also, the reverse current IZ passes through the resistor R and reaches the ground. As a result, a terminal voltage VR is formed between the terminals of the resistor R. The terminal voltage VR of the resistor R (= IZ × R) is adjusted to be greater than or equal to the gate threshold voltage Vth (Vth ≤ VR). The terminal voltage VR is applied as the clamp-on voltage VCLP between the gate and source of the power MISFET 9. Therefore, the power MISFET 9 maintains an on state in the active clamp state. The clamp-on voltage VCLP (terminal voltage VR) may have a voltage less than the on signal Von.

[0058] As a result, the inductive energy of the inductive load L is consumed (absorbed) by the power MISFET 9. The drain current ID decreases from the peak value IAV just before the power MISFET 9 turns off to zero after passing through the active clamp time TAV. Thereby, the gate voltage VGS becomes the ground voltage, the drain voltage VDS becomes the power supply voltage VB, and the power MISFET 9 switches from the on state to the off state.

[0059] <Consideration regarding negative current> If the aforementioned input electrode 13 becomes negative in potential for some reason, a negative current may flow from inside the semiconductor device 1 toward the input electrode 13. Therefore, in order to protect an ECU (electronic control unit) or the like externally connected to the input electrode 13, it is necessary to prevent the negative current from flowing.

[0060] In particular, in a semiconductor device 1 that is required to have a large current supply capability (and therefore a low on-resistance), a vertical structure in which an N-type semiconductor substrate serves as the drain electrode 11 (=output electrode) is generally adopted as the element structure of the power MISFET 9. In this case, as explained above, the drain voltage VDS rises sharply to the clamp voltage VDSSCL (several tens of volts) due to the active clamp operation when an L load is connected, and this may cause a large negative current to flow from the N-type semiconductor substrate toward the input electrode 13.

[0061] A negative current prevention circuit capable of preventing the generation of a negative current will be described below.

[0062] <Negative current prevention circuit (comparative example)> FIG. 5 is a diagram showing a comparative example of a negative current prevention circuit mounted on the semiconductor device 1 (=a general configuration example to be compared with the embodiments described later).

[0063] The negative current prevention circuit 100 of this comparative example includes a diode D0 (such as a polysilicon diode). The anode of the diode D0 is connected to an input electrode 13 for receiving an input signal IN. The cathode of the diode D0 is connected to a power supply node (an application terminal of an input voltage V10) of the controller 10. The controller 10 is an example of a control circuit that generates a gate control signal SG for the power MISFET 9 in response to the input signal IN.

[0064] According to the negative current prevention circuit 100 of this comparative example, the diode D0 is reverse biased when the input electrode 13 has a negative potential. Therefore, the generation of a negative current flowing toward the input electrode 13 can be prevented.

[0065] However, in the negative current prevention circuit 100 of this comparative example, the input voltage V10 supplied from the input electrode 13 to the controller 10 during steady state drops by the forward voltage drop Vf(D0) of the diode D0 (V10=IN-Vf(D0)).

[0066] For example, when the input voltage V10 is used as the high level of the gate control signal SG, the lower the input voltage V10, the higher the on-resistance of the power MISFET 9. Furthermore, when the input voltage V10 is used as the internal power supply voltage, the operating dynamic range of the internal circuits (such as the reference voltage source, operational amplifier, and comparator) that operate upon receiving the input voltage V10 becomes narrower.

[0067] A new embodiment that can solve these problems will be proposed below.

[0068] <Negative Current Prevention Circuit (First Embodiment)> 6 is a diagram showing a first embodiment of a negative current prevention circuit. The negative current prevention circuit 100 of the first embodiment is a circuit block provided between the input electrode 13 and the controller 10 to prevent a negative current from flowing toward the input electrode 13, and includes a P-channel MISFET P1 (hereinafter abbreviated as transistor P1), a diode D1, and a resistor R1.

[0069] A first terminal of the resistor R1 is connected to the input electrode 13. A second terminal of the resistor R1 is connected to the drain of the transistor P1 and the anode of the diode D1. The source and back gate of the transistor P1 and the cathode of the diode D1 are all connected to the power supply node (= the application terminal of the input voltage V10) of the controller 10. The gate of the transistor P1 is connected to the source electrode 12 (= the ground terminal).

[0070] In this way, the transistor P1 is connected between the input electrode 13 and the controller 10, with its drain on the input electrode 13 side and its source and back gate on the controller 10 side. Also, the diode D1 is connected between the input electrode 13 and the controller 10, with its anode on the input electrode 13 side and its cathode on the controller 10 side. A constant potential (ground potential) is applied to the gate of the transistor P1.

[0071] Furthermore, a resistor R1 that functions as a current limiting resistor is provided between the input electrode 13 and the controller 10 (in this figure, upstream of the transistor P1 and diode D1 and closer to the input electrode 13). Therefore, even if a negative current flows toward the input electrode 13, it is possible to limit the negative current so that it does not become excessive. The resistance value of the resistor R1 is preferably set to several hundred ohms to 1 kΩ to suppress the voltage drop that occurs across the resistor R1 in a steady state.

[0072] Furthermore, the semiconductor device 1 has a Zener diode ZD1 that functions as an electrostatic breakdown protection element between the input electrode 13 and the source electrode 12. The cathode of the Zener diode ZD1 is connected to the input electrode 13. The anode of the Zener diode ZD1 is connected to the source electrode. With this configuration, even if an excessively large positive surge is applied to the input electrode 13, the internal propagation of the positive surge can be clamped with the breakdown voltage of the Zener diode ZD1 as the upper limit, thereby making it possible to prevent breakdowns in the semiconductor device 1.

[0073] <Element structure of transistor P1> 7 is a diagram showing the element structure of the transistor P1. When a vertical structure in which the N-type semiconductor substrate 201 serves as the drain electrode 11 (=output electrode) is adopted as the element structure of the power MISFET 9, the transistor P1 is also formed on the N-type semiconductor substrate 201.

[0074] Specifically, with reference to this figure, transistor P1 includes an N-type semiconductor substrate 201, an N-type epitaxial layer 202, a high-voltage P-type well 203, an N-type well 204, a P-type contact region 205, a drain region 206, a source region 207, an N-type contact region 208, a gate insulating layer 209, and a gate metal layer 210.

[0075] As described above, the N-type semiconductor substrate 201 is electrically connected to the drain electrode 11 of the power MISFET 9 .

[0076] The N-type epitaxial layer 202 is an N-type semiconductor region formed over the entire surface of the N-type semiconductor substrate 201 .

[0077] High-voltage P-type well 203 is a P-type semiconductor region formed in a well shape from the surface to a predetermined depth in a partial region of N-type epitaxial layer 202. High-voltage P-type well 203 is connected to a constant potential end (e.g., a ground end) via P-type contact region 205. Therefore, high-voltage P-type well 203 functions as a potential isolation layer for isolating the potential of N-type semiconductor substrate 201 and N-type epitaxial layer 202 from the potential of N-type well 204.

[0078] The N-type well 204 is an N-type semiconductor region formed in a well shape from the surface to a predetermined depth in a partial region of the high-voltage P-type well 203. The N-type well 204 corresponds to the back gate of the transistor P1, and is connected to the power supply node (=the application terminal of the input voltage V10) of the controller 10 via an N-type contact region 208. In addition, the previously mentioned high-voltage P-type well 203 is interposed between the N-type well 204 and the N-type epitaxial layer 202. Therefore, the potential of the back gate of the transistor P1 is isolated from the potentials of the N-type semiconductor substrate 201 and the N-type epitaxial layer 202.

[0079] The P-type contact region 205 is a high-concentration P-type semiconductor region formed in a region of the surface of the high-voltage P-type well 203 where the N-type well 204 is not formed. The P-type contact region 205 is connected to a constant potential terminal (for example, a ground terminal).

[0080] The drain region 206 is a high-concentration P-type semiconductor region formed on the surface of the N-type well 204. The drain region 206 corresponds to the drain of the transistor P1, and is connected to the input electrode 13 together with the anode of the diode D1 via a resistor R1.

[0081] The source region 207 is a high-concentration P-type semiconductor region formed on the surface of the N-type well 204, separated by a predetermined channel length from the drain region 206. The source region 207 corresponds to the source of the transistor P1, and is connected to the power supply node (= the application terminal of the input voltage V10) of the controller 10 together with the cathode of the diode D1.

[0082] The N-type contact region 208 is a high-concentration N-type semiconductor region formed on the surface of the N-type well 204. As described above, the N-type contact region 208 is connected to the power supply node (=the application terminal of the input voltage V10) of the controller 10.

[0083] A gate insulating layer 209 is formed on the surface of the channel region separating the drain region 206 and the source region 207 .

[0084] The gate metal layer 210 is formed on the surface of the gate insulating layer 209. The gate metal layer 210 corresponds to the gate of the transistor P1, and is connected to a constant potential terminal (for example, a ground terminal).

[0085] Furthermore, a pnp-type parasitic transistor Q1 and an npn-type parasitic transistor Q2 are associated with the transistor P1 having the above-described element structure. The parasitic transistor Q1 has the drain region 206 as its emitter, the high-voltage P-type well 203 as its collector, and the N-type well 204 and the N-type contact region 208 as its base. The parasitic transistor Q2 has the N-type well 204 as its collector, the N-type epitaxial layer 202 as its emitter, and the high-voltage P-type well 203 and the P-type contact region 205 as its base. These parasitic transistors Q1 and Q2 form a pnpn-type parasitic thyristor.

[0086] Furthermore, the transistor P1 is also accompanied by a body diode D2. As mentioned above, the back gate of the transistor P1 is short-circuited to the source region 207 on the controller 10 side, not to the drain region 206 on the input electrode 13 side. That is, in a typical P-channel MISFET, the back gate is short-circuited to a high-potential node (the drain region 206 in this figure), whereas in the transistor P1, the back gate is short-circuited to a low-potential node (the source region 207 in this figure). Therefore, the body diode D2 is parasitic on the transistor P1, with the drain region 206 as the anode and the N-type well 204 and the N-type contact region 208 as the cathodes.

[0087] <Example of operation> 8 is a diagram showing an example of the operation of the negative current prevention circuit 100. The solid line in this diagram indicates the input signal IN applied to the input electrode 13, and the dashed line in this diagram indicates the input voltage V10 applied to the power supply node of the controller 10. Note that this diagram shows the behavior of the input signal IN rising from a negative potential to a positive potential and then falling from the positive potential to a negative potential again as time passes from left to right on the page.

[0088] In the following description, the on-threshold voltage of transistor P1 is defined as Vth(P1), the on-threshold voltage of parasitic transistor Q1 (and therefore the on-threshold voltage of the parasitic thyristor) as Vth(Q1), the drain-source voltage of transistor P1 as Vds(P1), the forward drop voltage of diode D1 as Vf(D1), and the forward drop voltage of Zener diode ZD1 as Vf(ZD1).

[0089] The forward voltage drop Vf(D1) of the diode D1 is lower than the on-threshold voltages Vth(P1) and Vth(Q1) of the transistor P1 and the parasitic transistor Q1, respectively. The drain-source voltage Vds(P1) of the transistor P1 is also sufficiently lower than the forward voltage drop Vf(D1) of the diode D1.

[0090] During period (1) (before time t11 and after time t16), IN≦−Vf(ZD1). At this time, in the negative current prevention circuit 100, transistor P1 is turned off, and both diode D1 and body diode D2 are reverse-biased. Therefore, no negative current flows from the controller 10 to the input electrode 13. In addition, the source and backgate of transistor P1 (= the application terminal of input voltage V10) are pulled down to ground potential (0 V) (see resistor R2 in FIG. 11). Note that during period (1), a negative current flows through the current path from the ground terminal to the input electrode 13 via Zener diode ZD1 (see dashed arrow (1) in FIG. 7), but this does not pose any particular problem.

[0091] During period (2) (times t11 to t12 and times t15 to t16), -Vf(ZD1) < IN ≤ Vf(D1). At this time, in the negative current prevention circuit 100, similar to period (1), the transistor P1 is turned off, and both the diode D1 and the body diode D2 are reverse-biased. Therefore, no negative current flows from the controller 10 toward the input electrode 13. Also, the source and back gate of the transistor P1 are pulled down to the ground potential (0V), similar to period (1). Note that in period (2), since the Zener diode ZD1 is also reverse-biased, no negative current flows through the Zener diode ZD1.

[0092] During period (3) (times t12 to t13 and times t14 to t15), Vf(D1) < IN ≤ Vth(P1). At this time, in the negative current prevention circuit 100, while the transistor P1 remains off, the diode D1 is forward-biased, so a positive current flows through the current path from the input electrode 13 through the diode D1 toward the controller 10 (see the dashed arrow (3) in FIG. 7). As a result, the input voltage V10 becomes a value (= IN - Vf(D1)) that is lower than the input signal IN by the forward voltage drop Vf(D1) of the diode D1.

[0093] During period (4) (time t13 to t14), Vth(P1) < IN. At this time, in the negative current prevention circuit 100, the transistor P1 is turned on, so a positive current flows through the current path from the input electrode 13 through the transistor P1 toward the controller 10 (see the dashed arrow (4) in FIG. 7). As a result, the input voltage V10 becomes a value (= IN - Vds(P1)) that is lower than the input signal IN by the drain-source voltage Vds(P1) of the transistor P1. Generally, the forward voltage drop Vf(D1) of the diode D1 is several hundred mV (about 0.6 to 0.7V). In contrast, the drain-source voltage Vds(P1) of the transistor P1 is several tens of mV (about 0.02 to 0.07V). Therefore, the voltage drop in the negative current prevention circuit 100 is significantly improved, and the input voltage V10 can supply the input signal IN to the subsequent controller 10 almost as it is.

[0094] <Role of diode D1> Next, we will explain the reason why diode D1 is connected in parallel with transistor P1. As mentioned above, transistor P1 is accompanied by a pnpn-type parasitic thyristor (i.e., parasitic transistors Q1 and Q2). Therefore, if the input voltage V10 remains pulled down until transistor P1 turns on when the input signal IN goes high, a potential difference greater than or equal to the on-threshold voltage Vth(Q1) will occur between the base and emitter of parasitic transistor Q1, which could turn on the parasitic thyristor.

[0095] On the other hand, if a diode D1 is connected in parallel to the transistor P1, the potential difference generated between the base and emitter of the parasitic transistor Q1 can be clamped by the forward voltage drop Vf of the diode D1. Therefore, by setting the forward voltage drop Vf(D1) of the diode D1 to a voltage value lower than the on-threshold voltage Vth(Q1) of the parasitic transistor Q1, the parasitic thyristor described above will not turn on.

[0096] <Voltage drop across resistor R1> Next, we will briefly explain the voltage drop across resistor R1. As mentioned above, the resistance value of resistor R1, which functions as a current-limiting resistor, is desirably set to several hundred ohms to 1 kΩ to suppress the voltage drop across resistor R1 in steady state. For example, consider a case where resistor R1 is 1 kΩ and the circuit current flowing from input electrode 13 to controller 10 via resistor R1 is 80 μA. In this case, the voltage drop across resistor R1 is approximately 80 mV, which, when combined with the drain-source voltage Vds(P1) of transistor P1, amounts to only approximately 100 mV. On the other hand, the forward drop voltage of diode D0 in the comparative example is several hundred mV (approximately 0.6 to 0.7 V), so inserting resistor R1 sufficiently reduces the voltage drop across negative current prevention circuit 100.

[0097] <Verification of latch-up> As mentioned several times before, a pnpn-type parasitic thyristor is associated with transistor P1. Therefore, when the voltage applied to N-type semiconductor substrate 201, i.e., the output voltage OUT (=drain voltage VDS of power MISFET 9) applied to drain electrode 11, is at a low potential (e.g., ground potential, negative potential, or open state) equal to or lower than a latch-up recovery voltage Vrec (described later), the parasitic thyristor may turn on, causing latch-up. Below, the results of latch-up verification will be described with reference to the drawings.

[0098] FIG. 9 is a diagram showing the results of latch-up verification, depicting, from the top, an input signal IN and an output voltage OUT.

[0099] As shown at times t21 and t22, during normal startup of the semiconductor device 1, the input signal IN rises from low to high while the output voltage OUT is at high level (≈load power supply voltage). In this case, the parasitic thyristor of the transistor P1 does not turn on, and therefore latch-up does not occur.

[0100] On the other hand, consider a case where, as shown at time t23, the input signal IN momentarily falls to a low level due to the application of a negative surge or the like after the normal startup of the semiconductor device 1. In this case, the input signal IN rises from a low level to a high level while the output voltage OUT has fallen to the ground potential (0 V), which may turn on the parasitic thyristor of the transistor P1 and cause latch-up.

[0101] In particular, as a result of more detailed verification by the inventors of the present application, it was discovered that when the output voltage OUT is at a low potential below the latch-up recovery voltage Vrec (e.g., 3.8 V), if the input signal IN is raised from low level to high level, the parasitic thyristor of transistor P1 turns on, causing latch-up.

[0102] When the latch-up occurs, the semiconductor device 1 does not start up normally and the power MISFET 9 does not turn fully on, in other words, the on-resistance of the power MISFET 9 is increased more than normal. However, in this state, the output voltage OUT increases, and when OUT>Vrec, the latch-up is resolved and the semiconductor device 1 automatically recovers.

[0103] In view of the above verification results, it is desirable to set the maximum drive frequency fsw_max (= maximum value of drive frequency fsw) of the input signal IN to a value that prevents the input signal IN from switching from low level to high level again after the input signal IN switches from high level (= logical level when on) to low level (= logical level when off) until the drain voltage of the power MISFET 9 (i.e., output voltage OUT) exceeds at least the latch-up recovery voltage Vrec.

[0104] For example, the maximum drive frequency fsw_max of the input signal IN may be set to 10 to several tens of kHz (e.g., 18 kHz). Under these drive conditions, the output voltage OUT exceeds the latch-up recovery voltage Vrec during the period from when the input signal IN falls to low level to when the input signal IN rises to high level in the next cycle. Therefore, the semiconductor device 1 can be properly started up without causing the above-mentioned latch-up.

[0105] <Negative Current Prevention Circuit (Second Embodiment)> 10 is a diagram showing a second embodiment of the negative current prevention circuit. The negative current prevention circuit 100 of the second embodiment is based on the first embodiment (FIG. 6) and includes P-channel MISFETs P1a and P1b (hereinafter referred to as transistors P1a and P1b, respectively), diodes D1a and D1b, and resistors R1a and R1b between the input electrode 13 and the current / voltage control circuit 23, and between the input electrode 13 and the gate control circuit 25, respectively.

[0106] A first terminal of the resistor R1a is connected to the input electrode 13. A second terminal of the resistor R1a is connected to the drain of the transistor P1a and the anode of the diode D1a. The source and back gate of the transistor P1a and the cathode of the diode D1a are all connected to the power supply node (=application terminal of the input voltage IN_CNT) of the current / voltage control circuit 23. The gate of the transistor P1a is connected to the source electrode 12 (=equivalent to the ground terminal).

[0107] A first terminal of the resistor R1b is connected to the input electrode 13. A second terminal of the resistor R1b is connected to the drain of the transistor P1b and the anode of the diode D1b. The source and back gate of the transistor P1b and the cathode of the diode D1b are all connected to the power supply node (=application terminal of the input voltage IN_GATE) of the gate control circuit 25. The gate of the transistor P1b is connected to the source electrode 12 (=equivalent to the ground terminal).

[0108] The ratio of the channel width W to the channel length L of the transistor P1a (so-called W / L) may be designed to be approximately 100 μm / 1.2 μm. The resistor R1a may be designed to be approximately 800 Ω. The voltage drop across the transistor P1a (= the drain-source voltage of the transistor P1a when it is on) may be designed to be approximately 0.07 V.

[0109] This design reduces the voltage drop of the input voltage IN_CNT, which corresponds to the internal power supply voltage of the current / voltage control circuit 23. Therefore, for example, it is not necessary to narrow the operating dynamic range of the internal circuits (such as a reference voltage source, an operational amplifier, and a comparator) that form the current / voltage control circuit 23, and it becomes possible to operate with a lower input signal IN supplied. In other words, it becomes possible to use a microcomputer that can be driven at a lower voltage (such as a 3.3V microcomputer) as the supply source of the input signal IN.

[0110] On the other hand, the W / L of transistor P1b may be designed to be approximately 10 μm / 1.2 μm. Resistor R1b may be designed to be approximately 1 kΩ. The voltage drop across transistor P1b (= the drain-source voltage of transistor P1b when it is on) may be designed to be approximately 0.02 V.

[0111] This design can reduce the voltage drop of the input voltage IN_GATE, which corresponds to the internal power supply voltage of the gate control circuit 25. Therefore, for example, when the input voltage IN_GATE is used as the high level of the gate control signal SG, the higher the input voltage IN_GATE is, the more the on-resistance of the power MISFET 9 can be reduced, making it possible to suppress loss (heat generation) during large current output.

[0112] <Circuit design considerations> 11 is a diagram showing a connection example of the gate control circuit 25. The gate control circuit 25 of this configuration example includes, as circuit elements forming an output stage of the gate control signal SG, a P-channel MISFET P2 (hereinafter abbreviated as transistor P2), resistors R2 to R5, and an analog switch SW.

[0113] The first terminals of the analog switch SW and resistor R2 are both connected to the output terminal (= application terminal of input voltage IN_GATE) of the negative current prevention circuit 100. The second terminal of the analog switch SW is connected to the first terminal of resistor R3. The second terminal of resistor R3 and the source of transistor P2 are both connected to the first terminal of resistor R5. The second terminal of resistor R5 is connected to the gate of power MISFET 9 as the output terminal of gate control signal SG. The drain of transistor P2 is connected to the first terminal of resistor R4. The second terminals of resistors R2 and R4 are both connected to the ground terminal (= source electrode 12).

[0114] The negative current prevention circuit 100 is basically the same as that of the first embodiment, except that the transistor P1, diode D1, and resistor R1 in FIG. 7 are replaced with a transistor P1b, a diode D1b, and a resistor R1b, respectively.

[0115] In the gate control circuit 25 of this configuration example, when the input signal IN is at a high level, the analog switch SW is turned on and the transistor P2 is turned off. Therefore, a charging current Ichg flows from the input electrode 13 to the gate of the power MISFET 9 via the negative current prevention circuit 100, the analog switch SW, and resistors R3 and R5. As a result, the gate capacitance (not shown) is charged, causing the gate control signal SG to rise to a high level and turning on the power MISFET 9. At this time, an output current Iout flows through the power MISFET 9.

[0116] On the other hand, when the input signal IN is at a low level, the analog switch SW is turned off and the transistor P2 is turned on. Therefore, a discharge current Idchg flows from the gate of the power MISFET 9 to the ground terminal via the resistor R5, the transistor P2, and the resistor R4. As a result, the gate capacitance (not shown) is discharged, so the gate control signal SG falls to a low level and the power MISFET 9 is turned off. At this time, the input voltage IN_GATE is pulled down to the ground terminal via the resistor R2.

[0117] Figure 12 is a diagram showing an example of operation of the semiconductor device 1 at normal startup (for example, Ta=160°C, IN=5V), and depicts, from top to bottom, the input signal IN, the gate control signal SG, the output voltage OUT, and the output current Iout.

[0118] As shown in the figure, when the semiconductor device 1 is started up normally, the input signal IN rises to a high level, and the gate control signal SG rises to a high level, the power MISFET 9 is in a fully on state, and the output current Iout flows. At this time, the output voltage OUT drops to near the ground potential (0 V).

[0119] 13 is a diagram showing an example of operation of the semiconductor device 1 during startup failure (for example, Ta=160°C, IN=7.5V), and depicts, from top to bottom, the input signal IN, the gate control signal SG, the output voltage OUT, and the output current Iout, as in the above-mentioned FIG. 12. The dashed lines in the diagram indicate behavior during normal startup (behavior in FIG. 12).

[0120] As shown in the figure, when the high-level potential of the input signal IN increases at high temperatures, the gate control signal SG does not rise all the way to its intended high level, and stagnates near the gate threshold voltage Vth of the power MISFET 9 (SG≧Vth). As a result, although the output current Iout flows, the power MISFET 9 falls into a state where it is not fully on. The likely cause of this is latch-up when the gate capacitance is charged.

[0121] More specifically, when the gate capacitance of the power MISFET 9 is charged immediately after the semiconductor device 1 is turned on, a charging current Ichg (on the order of mA) that is far larger than the circuit current (several tens of μA) during steady-state operation flows transiently through the transistor P1b. At this time, if the drain-source voltage Vds(P1b) of the transistor P1b becomes higher than the forward drop voltage Vf(D2) of the body diode D2, the parasitic transistor Q1 may be turned on.

[0122] Furthermore, as described above, the gate control signal SG exceeds the gate threshold voltage Vth of the power MISFET 9, turning on the power MISFET 9 and decreasing the output voltage OUT. As a result, it is thought that when the output voltage OUT falls below the latch-up recovery voltage Vrec described above, the parasitic thyristor associated with the transistor P1b turns on, leading to latch-up.

[0123] In order to prevent latch-up at the start-up of the semiconductor device 1 described above, it is effective to take measures such as (1) placing a resistor R3 for limiting the charging current in front of the transistor P1b on the current path through which the charging current Ichg flows, or (2) increasing the channel width W of the transistor P1b.

[0124] 14 is a diagram showing the relationship between the channel width W of transistor P1b and the body current I(D2) flowing through body diode D2. In particular, this diagram illustrates the behavior when IN=5V, 5.5V, 6V, 6.5V, 7V, 7.5V, and 8V.

[0125] In this diagram, the direction in which the charging current Ichg flows (toward the gate of the power MISFET 9) is defined as negative, and the positive and negative polarities of the body current I(D2) are defined. In other words, this diagram shows that the larger the channel width W of transistor P1b, the smaller the current value (absolute value) of the body current I(D2) flowing through body diode D2.

[0126] For example, consider a case where it has been confirmed that latch-up does not occur when the semiconductor device 1 is started up if the current value of the body current I(d2) is smaller than a predetermined threshold i (e.g., approximately 35 μA). In this case, if the maximum value of the input signal IN (= the maximum voltage that can be applied as the high level of the input signal IN) is 6 V, it is sufficient to design the channel width W so that W≧w1 (e.g., approximately 10 μm). Also, if the maximum value of the input signal IN is 8 V, it is sufficient to design the channel width W so that W≧w2 (e.g., approximately 18 μm).

[0127] In this way, it is desirable to design the device so that the transistor P1b provided between the input electrode 13 and the gate control circuit 25 has a channel width W that corresponds to the maximum value of the input signal IN.

[0128] On the other hand, an excessive rush current does not flow through the transistor P1a provided between the input electrode 13 and the current / voltage control circuit 23 when the semiconductor device 1 starts up. Therefore, it is not essential to design the device taking into account measures against latch-up at startup.

[0129] <Application to vehicles> 15 is an external view showing an example of a vehicle configuration. Vehicle X of this configuration example is equipped with a battery (not shown in this figure) and various electronic devices X11 to X18 that operate by receiving power supply from the battery.

[0130] Vehicle X includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0131] It should be noted that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual positions for the sake of convenience.

[0132] The electronic device X11 is an electronic control unit that performs engine-related controls (such as injection control, electronic throttle control, idling control, oxygen sensor heater control, and auto-cruise control) or motor-related controls (such as torque control and power regeneration control).

[0133] The electronic device X12 is a lamp control unit that controls the turning on and off of HID (high intensity discharged lamp) and DRL (daytime running lamp).

[0134] The electronic device X13 is a transmission control unit that controls transmission-related functions.

[0135] The electronic device X14 is a body control unit that performs control related to the movement of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

[0136] The electronic device X15 is a security control unit that controls the operation of door locks, burglar alarms, and the like.

[0137] The electronic device X16 is an electronic device that is installed in the vehicle X at the time of shipment from the factory as a standard equipment or a manufacturer option, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat.

[0138] The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0139] The electronic device X18 is an electronic device equipped with a high-voltage motor, such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.

[0140] The semiconductor device 1 (=low-side switch LSI) described above can be incorporated into any of the electronic devices X11 to X18.

[0141] <Summary> The various embodiments described above will be generally described below.

[0142] For example, a switch device disclosed in this specification has an N-type semiconductor substrate, a power MISFET configured to use the N-type semiconductor substrate as a drain, an input electrode configured to receive an input signal, a control circuit configured to generate a gate control signal for the power MISFET in response to the input signal, and a negative current prevention circuit provided between the input electrode and the control circuit and configured to prevent a negative current from flowing toward the input electrode, wherein the negative current prevention circuit is configured to include a P-channel MISFET connected between the input electrode and the control circuit with its drain on the input electrode side and its source and back gate on the control circuit side, with a constant potential applied to its gate so that the back gate is electrically isolated from the N-type semiconductor substrate, and a diode connected between the input electrode and the control circuit with its anode on the input electrode side and its cathode on the control circuit side (first configuration).

[0143] In the switch device according to the first configuration, the forward voltage drop of the diode may be lower than the on-threshold voltage of a parasitic thyristor associated with the P-channel MISFET (second configuration).

[0144] Furthermore, in the switch device according to the first or second configuration, the maximum drive frequency of the input signal may be set to a value that prevents the input signal from switching from the off logic level to the on logic level again until the drain voltage of the power MISFET exceeds at least a latch-up recovery voltage after the input signal switches from the on logic level to the off logic level (third configuration).

[0145] Furthermore, in the switch device according to any one of the first to third configurations, the control circuit may be configured (fourth configuration) to include a current / voltage control circuit configured to generate various currents and voltages as electrical signals corresponding to the input signal, and a gate control circuit configured to generate the gate control signal according to the electrical signal from the current / voltage control circuit.

[0146] In addition, in the switch device according to the fourth configuration, the negative current prevention circuit may be configured (fifth configuration) to include one P-channel MISFET and one diode between the input electrode and the current / voltage control circuit, and between the input electrode and the gate control circuit.

[0147] In addition, in the switch device according to the fifth configuration, the P-channel MISFET provided between the input electrode and the gate control circuit may be configured (sixth configuration) to have a channel width corresponding to the maximum value of the input signal.

[0148] Furthermore, in the switch device according to any one of the first to sixth configurations, the negative current prevention circuit may be configured (seventh configuration) to further include a resistor provided between the input electrode and the control circuit and configured to limit the negative current.

[0149] Furthermore, the switch device according to any one of the first to seventh configurations may be configured (eighth configuration) to further include an electrostatic breakdown protection element configured to be connected between the input electrode and a ground terminal.

[0150] Furthermore, for example, the electronic device disclosed in this specification has a configuration (ninth configuration) including a switch device having any one of the first to eighth configurations above and a load connected to the switch device.

[0151] Furthermore, for example, the vehicle disclosed in this specification has a configuration (tenth configuration) that includes the electronic device according to the ninth configuration.

[0152] <Other variations> In the above embodiment, an in-vehicle low-side switch LSI is exemplified, but the application of the negative current prevention circuit disclosed in this specification is in no way limited to this, and the circuit can also be applied to low-side switch LSIs for applications other than in-vehicle applications.

[0153] Furthermore, in addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention is defined by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0154] 1. Semiconductor device (switching device) 2. Semiconductor layer 3 First main surface 4 Second main surface 5A~5D Side 6 Output Area 7 Input Area 8 area separation structure 9 Power MISFET 10 Controller (control circuit) 11 Drain electrode 12 Source electrode 13 Input electrode 17 Gate control wiring 23 Current / Voltage Control Circuit 24 Protection circuit 25 Gate control circuit 26 Active clamp circuit 32 Constant voltage generation circuit 33 Reference voltage and reference current generation circuit 34 Overcurrent protection circuit 36 Overheat protection circuit 100 Negative current prevention circuit 201 N-type semiconductor substrate 202 N-type epitaxial layer 203 High-voltage P-well 204 N-type well 205 P-type contact area 206 Drain region (P type) 207 Source region (P type) 208 N-type contact area 209 Gate insulating layer 210 Gate Metal Layer D1, D1a, D1b diodes D2 body diode DZ Zener diode L Inductive load P1, P1a, P1b, P2 P-channel MISFET Q1, Q2 parasitic transistors R, R1~R5, R1a, R1b resistance SW Analog switch X vehicle X11~X18 Electronic equipment ZD1 Zener diode (electrostatic breakdown protection element)

Claims

1. an N-type semiconductor substrate; a power MISFET configured to use the N-type semiconductor substrate as a drain; an input electrode configured to receive an input signal; a control circuit configured to generate a gate control signal for the power MISFET in response to the input signal; a negative current prevention circuit disposed between the input electrode and the control circuit and configured to prevent a negative current from flowing toward the input electrode; and The negative current prevention circuit includes: a P-channel MISFET having a drain connected to the input electrode and a source and a back gate connected to the control circuit, the drain being on the input electrode side and the source and back gate being on the control circuit side, the P-channel MISFET being configured so that a constant potential is applied to the gate and the potential of the back gate is separated from the potential of the N-type semiconductor substrate; a diode configured to be connected between the input electrode and the control circuit, with its anode on the input electrode side and its cathode on the control circuit side; Including, a maximum drive frequency of the input signal is set to a value at which the input signal does not switch again from the logic level at the off time to the logic level at the on time until the drain voltage of the power MISFET exceeds at least a latch-up recovery voltage after the input signal switches from the logic level at the on time to the logic level at the off time; the latch-up recovery voltage is a voltage at which latch-up occurs when the input signal is switched from the logic level at the off state to the logic level at the on state while the drain voltage of the power MISFET is equal to or lower than the latch-up recovery voltage, and at which the latch-up is resolved when the drain voltage of the power MISFET becomes higher than the latch-up recovery voltage.

2. 2. The switch device according to claim 1, wherein a forward drop voltage of said diode is lower than an on-threshold voltage of a parasitic transistor associated with said P-channel MISFET.

3. The control circuit a current / voltage control circuit configured to generate various currents and voltages as electrical signals in response to the input signal; a gate control circuit configured to generate the gate control signal in response to the electrical signal from the current and voltage control circuit; The switch device according to claim 1 or 2, comprising:

4. 4. The switch device according to claim 3, wherein the negative current prevention circuit includes one P-channel MISFET and one diode between the input electrode and the current / voltage control circuit, and one between the input electrode and the gate control circuit.

5. 5. The switch device according to claim 4, wherein the P-channel MISFET provided between the input electrode and the gate control circuit has a channel width according to a maximum value of the input signal.

6. 6. The switch device according to claim 1, wherein the negative current prevention circuit further includes a resistor provided between the input electrode and the control circuit and configured to limit the negative current.

7. 7. The switch device according to claim 1, further comprising an electrostatic breakdown protection element configured to be connected between the input electrode and a ground terminal.

8. A switch device according to any one of claims 1 to 7; a load connected to the switch device; An electronic device having:

9. A vehicle comprising the electronic device according to claim 8.

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