4H-SiC electronic devices with improved short-circuit performance and manufacturing methods thereof

Abstract

To provide a 4H-SiC electronic device with improved short-circuiting performance, and a manufacturing method for the same.SOLUTION: An electronic device (100) includes a semiconductor main body (102) formed of silicon carbide, a main body region (105) on a first surface of the semiconductor main body, a source region (108) in the main body region (105), a drain region (104) on a second surface of the semiconductor main body (102), and a doped region (120) extending seamlessly on the entire first surface (102a) of the semiconductor main body (102) and including one or more first subregions (121) with a first doping concentration and one or more second subregions (123) with a second doping concentration lower than the first doping concentration. Therefore, the electronic device includes a plurality of zones with different conduction threshold voltages and different saturation currents, the zones being disposed alternately.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to electronic devices and methods for fabricating the same, and more particularly to electronic devices having selected regions with different conduction threshold voltages or, alternatively, different saturation currents. [Background technology]

[0002] 1 shows the basic structure of a vertical MOSFET device 1 in a three-axis reference system of orthogonal axes X, Y, and Z and in cross-section. In a typical embodiment, the MOSFET device 1 includes a number of these basic structures operating together, sharing the same drain terminal (D), all of the gate terminals (G) connected together by a deposited polysilicon mesh (not shown), and all of the source terminals (S) electrically connected and linked by an upper metal layer 10.

[0003] As shown in FIG. 2, the MOSFET device 1 includes a semiconductor body 2 of semiconductor material (which includes a substrate and, optionally, one or more epitaxial layers) having a top surface 2a and a bottom surface 2b. The semiconductor body 2 is, for example, N-doped. At the bottom surface 2b, a drain region 4 is formed, for example, by implanting an N-type (N+ doped) dopant species. At the top surface 2a, a body region 5 (P doped) surrounds a source region 8 (N+ doped). A gate structure 6, including a stack formed by a gate conductive layer 6a and a gate dielectric layer 6b, extends over the top surface 2a and partially overlaps the source region 8. A respective insulating layer 9 covers the gate structure 6.

[0004] The top metal layer 10 is in electrical contact with the source and body regions 8 and 5 at surface portions 16 and 17, respectively, for biasing the source and body regions 8 and 5 to the same bias voltage during use.

[0005] To improve electrical contact between the upper metal layer 10 and the body regions 5, P-well regions (P+ doped) 14 are formed in some of the body regions 5 and facing the upper surface 2a in areas corresponding to surface portions 17. Typically, a silicide interface layer (not shown) is formed in surface portions 17 to form ohmic contact between the metal 10 and the implanted P-well regions 14. The P-well regions 14 are formed only where the metal layer 10 is designed to contact the body regions 5. The P-well regions 14 are disposed between the source regions 8 in each body region 5.

[0006] If the design dictates that a contact be made between the upper metal layer 10 and the source regions 8 (i.e. in the surface region 16), each source region 8 faces the upper surface 2a in the surface region 16 and extends continuously within the body region 5 that contains it. To improve the electrical contact between the metal 10 and the sources 8, further layers can be formed (not shown) in a manner known per se.

[0007] During the on-state of MOSFET device 1, conduction current is localized (current flow 18) within drain region 4 and within the region of semiconductor body 2 beneath gate structure 6. During the off-state of MOSFET device 1, the voltage drop between drain D and source S is maintained by the PN junction, which is in reverse bias, and a very small current (leakage) flows through the PN junction. If the voltage increases excessively and the electric field reaches a critical value, the PN junction will break down and current will begin to flow through body region 5. If excessive voltage is applied to the PN junction, current will flow through it, while MOSFET device 1 will not experience an actual drain-source breakdown voltage (BV DS The breakdown mechanism itself is not destructive to the PN junction. However, the excessive heat generated by high breakdown currents and voltages can damage the PN junction unless adequate heat sinking is provided.

[0008] By examining the MOSFET structure in more detail, it may be possible to understand that the PN junction is not a "perfect diode." The diode is the collector-base junction of a bipolar junction transistor (BJT), also called a parasitic transistor, made up of the N+ source 8, P / P+ body 5, and N+ drain 4, with the base shorted to the emitter by metal layer 10.

[0009] When designing such equipment, consideration should be given to the behavior of the equipment in fault mode in the event of a short circuit, where the simultaneous presence of high voltage and high current causes thermal runaway and leads to destruction of the equipment (e.g., a typical example event that occurs when an electric motor stalls).

[0010] As is known, some semiconductor materials are ideal for fabricating electronic components such as diodes or transistors, especially for power applications. These materials have a wide bandgap, in particular a bandgap energy value Eg greater than 1.1 eV, a low on-state resistance (R ON ), high thermal conductivity, high operating frequency, and high velocity saturation of charge carriers. A material that has the above properties and is being considered for use in manufacturing electronic components is silicon carbide (SiC). In particular, silicon carbide, in its different polytypes (e.g., 3C-SiC, 4H-SiC, 6H-SiC), is preferable to silicon as far as the above properties are concerned.

[0011] Electronic devices built on silicon carbide offer many beneficial properties compared to similar devices built on silicon, such as lower output resistance in conduction, lower leakage current, higher operating temperatures, and higher operating frequencies.

[0012] However, the above-mentioned problems are not completely solved by the use of SiC, and in order to improve the avalanche capability of MOSFET devices, the usual solution foresees an edge structure with a higher breakdown threshold compared to the active area, however, due to efficiency limitations at the edges of the device, this goal is not always feasible.

[0013] Furthermore, the resistance in the on-state is affected, since the source resistance depends on the doping value of the source region 8. Summary of the Invention [Problem to be solved by the invention]

[0014] It is an object of the present invention to provide an electronic device and method of manufacture that overcomes the shortcomings of the prior art, and in particular to provide a method of limiting thermal runaway, limiting saturation current, and dissipating power locally with minimal impact on the output resistance of the device. [Means for solving the problem]

[0015] According to the present invention, there is provided an electronic device and a method for manufacturing the same, as defined in the claims.

[0016] For a better understanding of the invention, preferred embodiments will now be described, purely by way of non-limiting example, with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a schematic diagram of a known type of MOSFET device; [Figure 2] 1 is a schematic diagram of a MOSFET device according to one embodiment of the present invention. [Figure 3] 3A and 3B are schematic diagrams illustrating the MOSFET device of FIG. 2 at various processing steps. [Figure 4]3A-3D are schematic plan views illustrating respective layouts of implant regions of the MOSFET device of FIG. 2 according to respective embodiments of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0018] 2 shows a portion of a MOSFET device 100 according to one embodiment of the present invention, taken in cross section in a three-axis reference system of orthogonal axes X, Y, and Z of FIG.

[0019] As previously discussed with respect to Figure 1, the portion shown in Figure 1 may be a basic structure, or "cell," that can be used to develop MOSFET device 100 by replicating the basic structure as many times as desired. Such basic structures work together and share a common drain terminal (D), a common gate terminal (G), and a common source terminal (S).

[0020] It will be apparent that when reproducing portions of FIG. 2, variations in the basic structure may be introduced, as would be apparent to one skilled in the art, to compromise one or more of, for example, design considerations, area occupancy, electrical considerations, manufacturing considerations, etc.

[0021] The MOSFET device 100 has a semiconductor body 102 having opposed top and bottom surfaces 102a, 102b along axis Z, and made of semiconductor material (which may include, for example, a substrate and, optionally, one or more epitaxial layers).

[0022] In particular, semiconductor body 102 is composed of silicon carbide, more particularly 4H-SiC. Semiconductor body 102 is N-doped in one embodiment.

[0023] Facing the bottom surface 102b is a drain region 104, which is formed, for example, by implanted dopant species of N type (N+ doping). A body region 105 (P doping) is located at the top surface 102a.

[0024] Source regions 108 (N+ doped) are formed by implantation in semiconductor body 102 and are within body region 105 and facing upper surface 102a. Body region 105 therefore surrounds each source region 108 formed therein.

[0025] Gate structures 106 extend over the upper surface 102a and include a stack formed by a gate conductive layer 106a (e.g., made of a metal material) and a gate dielectric layer 106b (made of an insulating or dielectric material). A respective insulating layer 109 covers each gate structure 106 and electrically insulates it from the metal layer 110. The gate structures 106 partially overlap the source regions 105 / 108, and in a manner known per se, a respective channel region 118 is formed in use in the region of the semiconductor body 102 below the gate structure 106 between the body region 105 / source region 108. The current path is shown in FIG. 2 by the dotted line 118 and runs from the source region 108 to the drain region 104 (vertical conduction).

[0026] The active area of ​​the MOSFET device 100 is the area where current conduction occurs, specifically where the channel is formed. Typically, the active area is completely or partially surrounded by an edge termination region (not shown but known per se), such as an implanted region having a P conductivity type.

[0027] In a manner not shown in detail but known per se, all of the gate structures 106 are electrically connected (for example by a polysilicon mesh) and all of the source regions 108 are electrically connected together.

[0028] The top metal layer 110 is in electrical contact with the source region 108 and the body region 105 at respective contact zones to bias the source region 108 and the body region 105 to the same bias voltage during use.

[0029] To improve electrical contact between the upper metal layer 110 and the body regions 105, electrical contact interfaces (P+ doped) 114 are formed at the upper surface 102a in one or more of the body regions 105. Typically, each electrical contact interface 114 includes a silicide interface layer (not shown) to form an ohmic contact between the upper metal layer 110 and the respective electrical contact interface 114. The electrical contact interfaces 114 are formed where the metal layer 110 reaches the upper surface 102a to contact the body regions 105.

[0030] According to one aspect of the present invention, an electrical contact interface 116 also exists between the upper metal layer 110 and a region of the semiconductor body that is designed to form contact between the upper metal layer 110 and the source region 108.

[0031] According to one aspect of the invention, device 100 provides an implanted region 120 extending along the entire length of device 100, directly facing or adjacent to top surface 102a. The implanted region 120 is N-type and functions to modulate the saturation current of device 100. In this context, the saturation current is the maximum current that the device will sustain at a given gate voltage Vg once it has reached the linear region (where the on-state resistance R ON is identified), a certain drain-source voltage V DS The saturation current remains nearly constant even above the knee voltage. The saturation current is limited by the switch-on voltage (Vth) of the device, with a higher Vth corresponding to a lower saturation current.

[0032] The implant region 120 is configured to provide a first sub-region 121 having at least a first N-type dopant value and a second sub-region 123 having at least a second N-type dopant value lower than the first value of the first sub-region 121.

[0033] Implant region 120 faces upper surface 102a and extends into body region 105, source region 108, and a zone below gate dielectric 106b intended to accommodate the conductive channel, and drain region 104.

[0034] Thus, implant region 120 is in electrical contact with body region 105 , source region 108 , and electrical contact interface 114 .

[0035] The depth of implanted region 120 within semiconductor body 102, measured from top surface 102a along the Z direction, ranges from 10 nm to 0.1 μm, and more particularly, from 20 nm to 50 nm.

[0036] Increasing the implant dose (first sub-region 121) reduces the threshold voltage Vth, i.e., the gate-source voltage V required to generate or switch on a conductive channel for the second sub-region 123. GS The threshold voltage Vth is the drain-source current I DS is 250 μA / mm 2 The gate-source voltage V is equal to GS is defined as:

[0037] By localizing the implantation near the upper surface 102a (particularly at the interface between the semiconductor body 102 and the gate dielectric layer 106b), it is possible to influence the threshold voltage Vth in that particular zone of the device 100 as a result of saturation of interface defects typically present in SiC (as shown, for example, by I. Pintilie et al., "Analysis of electron traps at the 4H-SiC / SiO2 interface; influence by nitrogen implantation prior to wet oxidation," Journal of Applied Physics 108, 024503, 2010).

[0038] Thus, during operation, the sub-region 121 having the higher dopant concentration reduces the voltage V required to switch on the sub-region 123. GS A voltage even lower than V GS As a result, the voltage V GS As voltage V increases, a conductive channel first forms in subregion 121 and then in subregion 123. Furthermore, GS is such that both channels in subregion 121 and in subregion 123 are switched on, a higher current concentration is observed in subregion 121.

[0039] The N-type dopant concentration in subregion 121 is such that it exceeds the surface concentration of body region 105 by a factor ranging from 5 to 20 times the concentration of body region 105, and the N-type dopant concentration in second subregion 123 is such that it exceeds the surface concentration of body region 105 by a factor ranging from 2 to 10 times the concentration of body region 105.

[0040] The ratio Vth2 / Vth1 between the threshold voltage Vth1 of subregion 121 and the threshold voltage Vth2 of subregion 123 ranges from 1.1 to 2.5 and is defined by the ratio of the dopant concentrations present in these two subregions.

[0041] Thus, by appropriate layout of implantation regions 120, it is possible to define zones of device 100 that are configured to carry a higher current compared to other zones of device 100; in other words, it is possible to design zones of device 100 that are limited in the current they carry, thereby limiting the saturation current in those zones. The zones designated to carry the highest current may be selected based on design considerations, selecting them from among the most robust device zones, or distributing this current evenly without excessive concentration in some zones compared to others.

[0042] The fabrication process for implant region 120 will be described with reference to Figures 3A and 3B, which show a portion of a semiconductor wafer limited to features useful for understanding the present invention. Figures 3A and 3B are solely illustrative of the fabrication steps useful for forming implant region 120; the remaining processing steps to begin and complete the fabrication of device 100 do not form part of the present invention and will not be discussed or illustrated.

[0043] 3A, after forming the body region 105 via implantation of P-doping species and the source region 105 via implantation of N-doping species, a first unmasked implantation of N-type species (e.g., nitrogen or phosphorus) is performed to form a first implanted region 130 in the interface 102a. This first implantation (indicated by the arrow in FIG. 3A) is performed with an implantation energy in the range of 10-100 keV. A protective layer 134 can be formed on the surface 102a to avoid surface damage of the semiconductor body 102 resulting from this implantation.

[0044] The implantation step of Figure 3(A) notably forms the second sub-region 123 described with reference to Figure 2 and contributes to the formation of the first sub-region 121. A second masked implantation of an N-type species (e.g., nitrogen or phosphorus) is then performed to complete the formation of the first sub-region 121, as shown in Figure 3(B).

[0045] This second implant (indicated by arrow 136 in FIG. 3B) is performed with an implant energy in the range of 10-100 keV. The mask 137 used for the second implant leaves exposed the surface portions of semiconductor body 102 corresponding to the areas where only first subregions 121 are to be formed. In one embodiment, mask 137 can be formed as a hard mask by depositing a mask layer, for example, made of silicon oxide, on surface 102a of semiconductor body 102 and shaping this mask layer to expose the surface areas of semiconductor body 102 where it is desired to implant subregions 121.

[0046] An annealing step is then carried out to activate all of the implanted species in the sub-regions 121, 123. This annealing step is carried out at a temperature in the range of 1600-1800° C. This annealing step can be exclusively for the formation of the implanted region 120 or it can be common to the implanted region 120 and the body and / or source and / or drain regions.

[0047] 4A shows, by way of example only, a plan view of a portion of device 100 limited to implantation of body region 105 and first subregion 121. (As noted above, subregion 123 is considered to be uniformly distributed over all of surface 102a of device 100 and does not encompass portions of surface 102a that are not part of device 100.) As shown, in this embodiment, a plurality of body regions 105 extend in the form of parallel strips along the Y-axis, and a plurality of first subregions 121 extend in the form of parallel strips along the X-axis and overlap the plurality of body regions 105. At the designer's option, first subregions 121 can cover a variable percentage of body region 105, i.e., a percentage ranging from 50% to 80% of body region 105.

[0048] 4(B) through 4(D) illustrate respective plan views of portions of device 100 confined to the body region 105 and first subregions 121 according to Fig. 4(A) and alternative embodiments. As shown, in these embodiments, the plurality of body regions 105 extend in the form of parallel strips along the Y-axis, as in Fig. 4(A), and the plurality of first subregions 121 extend in the form of parallel strips along the same Y-axis, partially overlapping the plurality of body regions 105.

[0049] The strips of the first sub-region 121 may extend to completely overlap the respective strips of the main body region 105, as illustrated in FIG. 4(B), or may only partially overlap them, as illustrated in FIGS. 4(C) and 4(D).

[0050] FIG. 4(B) (and similarly FIG. 4(C)) illustrates first sub-regions 121 extending to cover alternating main body regions 105 (one out of every two, i.e., the total area of ​​the first sub-regions 121 is equal to 50% of the total area of ​​the main body regions 105).

[0051] 4(C) illustrates a first sub-region 121 extending between the side-by-side strips and directly facing one another of the body regions 105, partially overlapping these side-by-side body regions 105. As with FIG. 4(B), the total length (or total area) of the first sub-region 121 is equal to 50% of the total area of ​​the body region 105.

[0052] FIG. 4(D) illustrates an implementation of a first "checkerboard" sub-region 121, where the first sub-region 121 extends intermittently along the body region 105.

[0053] From the foregoing, the advantages achieved by the present invention are clear. Embodiments of the present invention have been found to increase robustness during short circuit testing. In fact, the structure of FIG. 2 (in various described embodiments) allows for modulation of the saturation current of MOSFET device 100 in selected portions of device 100 with minimal impact on the output resistance of device 100.

[0054] The layout design is performed to eliminate zones with high current concentrations, for example in wires or clips, to limit the saturation current in order to equalize the total current circulating in the device and to avoid destruction of the device in case of a short circuit.

[0055] While specific embodiments of the present invention have been described in detail above, it should be noted that the present invention is not limited to these specific embodiments and that various modifications and alterations can be made without departing from the technical scope of the present invention. For example, although the above-described embodiments relate to N-channel MOSFETs, it will be obvious to those skilled in the art that the present invention is also applicable to P-channel MOSFETs.

Claims

1. In an electronic device (100), a semiconductor body (102) made of silicon carbide (SiC) having a first surface (102a) and a second surface (102b) opposite each other along a certain direction (Z); a body region (105) having a first conductivity type (P) extending into the semiconductor body (102) at the first surface (102a); a source region (108) extending into the body region (105) at the first surface (102a) of the semiconductor body (102) and having a second conductivity type (N) opposite to the first conductivity type (P); a drain region (104) extending at the second surface (102b) of the semiconductor body (102) and having the second conductivity type (N); and further comprising a doped region (120) having a second conductivity type (N), extending continuously across the first surface (102a) of the semiconductor body (102), and comprising one or more first sub-regions (121) having a first doping concentration and one or more second sub-regions (123) having a second doping concentration lower than the first doping concentration.

2. 2. The electronic device of claim 1, wherein the first sub-regions (121) are alternated with the second sub-regions (123) to form a plurality of alternating zones having different conduction threshold voltages (Vth1, Vth2) or, alternatively, different saturation currents.

3. 3. The electronic device according to claim 1, wherein each first sub-region (121) and each second sub-region (123) is configured such that the ratio (Vth2 / Vth1) between the conduction threshold voltage (Vth1) of each first sub-region (121) and the conduction threshold voltage (Vth2) of each second sub-region (123) is in the range of 1.1 to 2.

5.

4. 4. An electronic device according to any one of claims 1 to 3, wherein the first and second sub-regions (121, 123) have a depth in the semiconductor body from its surface (102a) in the range of 10 nm to 0.1 μm.

5. 5. The electronic device of claim 1, wherein the first doping concentrations have values ​​in the range of 5 to 20 times the respective doping concentration values ​​of the body regions (105) and the second doping concentrations have respective values ​​in the range of 2 to 10 times the respective doping concentration values ​​of the body regions (105).

6. 6. An electronic device according to any one of claims 1 to 5, wherein the first sub-regions (121) are adjacent to and electrically connected to respective second sub-regions (123).

7. 7. An electronic device according to any one of claims 1 to 6, wherein the first sub-region (121) occupies a volume of the doped region (120) in the range of 50% to 80%.

8. 8. The electronic device of claim 1, further comprising a gate structure (106) on the first surface (102a) of the semiconductor body, the gate structure including a gate dielectric layer (106b), a metal gate layer (106b) on the gate dielectric layer (106b), and an insulating layer surrounding the metal gate layer (106b), wherein the doped region (120) extends into the source region, the body region, and under the gate structure (106).

9. The electronic device of any one of claims 1 to 8, wherein the semiconductor body (102) comprises 4H-SiC.

10. 1. A method of manufacturing an electronic device, comprising: providing a semiconductor body (102) made of silicon carbide (SiC) having a first surface (102a) and a second surface (102b) opposite each other along a direction (Z); forming a body region (105) having a first conductivity type (P) in the semiconductor body (102) at the first surface (102a); forming a source region (108) having a second conductivity type (N) opposite to the first conductivity type (P) within the body region (105) at the first surface (102a) of the semiconductor body (102); forming a drain region (104) having the second conductivity type (N) in the second surface (102b); and further comprising forming a doped region (120) having the second conductivity type (N) and extending seamlessly across the first surface (102a) of the semiconductor body (102), the doped region (120) including the substeps of forming one or more first subregions (121) having a first doping concentration and forming one or more second subregions (123) having a second doping concentration that is lower than the first doping concentration.

11. 11. The method of claim 10, wherein the first sub-regions (121) are alternated with the second sub-regions (123) to form a plurality of zones having different conduction threshold voltages (Vth1, Vth2) or, alternatively, different saturation currents and alternated with each other.

12. 12. A method according to claim 10 or 11, wherein each first sub-region (121) and each second sub-region (123) is configured in such a way that the ratio (Vth2 / Vth1) between the conduction threshold voltage (Vth1) of each first sub-region (121) and the conduction threshold voltage (Vth2) of each second sub-region (123) is in the range of 1.1 to 2.

5.

13. 13. The method of any one of claims 10 to 12, wherein the first and second sub-regions (121, 123) have a depth in the semiconductor body from the surface (102a) in the range of 10 nm to 0.1 μm.

14. forming the doped region (120) performing a maskless implant across the first surface (102a) to form a uniformly doped region having the second doping concentration; providing an implantation mask (137) on the first surface (102a) exposing a surface region of the semiconductor body (102) in which the first subregion (121) is to be formed; performing a masked implant using the implant mask (137) to form a selectively doped region having the first doping concentration; 14. The method of any one of claims 10 to 13, comprising:

15. 15. The method of claim 14, wherein the first doping concentrations have values ​​in the range of 5 to 20 times the doping concentration value of each of the body regions (105), and the second doping concentrations have respective values ​​in the range of 2 to 10 times the doping concentration value of each of the body regions (105).

16. 16. A method according to any one of claims 10 to 15, wherein the first sub-regions (121) are adjacent to and electrically connected to respective second sub-regions (123).

17. 17. The method of any one of claims 10 to 16, wherein the first sub-region (121) occupies between 50% and 80% of the volume of the doped region (120).

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