Small Footprint Power Switch

Abstract

The power switch includes a pair of substantially parallel half - bridges, a printed circuit board (PCB) controller operable to turn the half - bridges on and off, power terminals for coupling a high - energy power source to the half - bridges, and power phase output terminals for connecting a load to the half - bridges. The half - bridges, the PCB, the power terminals, and the power phase output terminals are enclosed within the same encapsulation envelope having a relatively large planar first face surface where the contact surfaces of the terminals are exposed.

Description

[Technical Field]

[0001] Related Applications This application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Application No. 63 / 358,886, filed July 7, 2022, the disclosure of which is incorporated herein by reference.

[0002] Technical Field FIELD OF THE INVENTION An embodiment of the present invention relates to a power switch. [Background technology]

[0003] Nearly every type of modern optical and electronic device, from computers to powertrains, includes power switching circuits for generating timing pulses, data packets, and / or transmitting electrical power. To transmit power to electric powertrains, such as those used to transmit power to electric vehicles, power switches capable of carrying large currents and rapidly turning on and off are required to couple and isolate high-voltage power sources to loads. For example, a high-power inverter operating to transmit AC power from a DC source to an automobile's traction motor might include a half-bridge having a high-side array of GaN die connected to a low-side array of GaN die, and PCB control circuitry that controls the array and converts the DC power to AC power. Advantageously, the inverter has low inductance, a small footprint, efficient heat dissipation, and can be easily installed and expanded to meet the electrical and mechanical constraints of various electric vehicle configurations. Summary of the Invention [Means for solving the problem]

[0004] One aspect of an embodiment of the present disclosure relates to providing a power switch, also known as a Power-Mite, characterized by low inductance, a small footprint, easy expansion, simple coupling to an external electrical circuit, and the ability to be attached to a heat sink by soldering or sintering. In one embodiment, the Power-Mite includes a pair of half-bridges and a printed circuit board (PCB) controller operable to turn the half-bridges on and off to provide voltage and current pulses to a load connected to the Power-Mite. Each half-bridge optionally includes a high-side GaN die connected to a low-side GaN die. To provide the Power-Mite with relatively low inductance, the half-bridges are configured so that current flows in substantially the same parallel direction when the half-bridges are turned on to provide voltage and current pulses to the load. The total power loop inductance during transitions between the Power-Mite's on and off states may be less than approximately 2.5 nanohenries (nH).

[0005] In one embodiment, the PowerMite half bridge, PCB controller, and other electrical and mechanical components are encapsulated within a protective polymer envelope, which may be referred to as an envelope. The envelope has a substantially uninterrupted, uniform geometric outline, including a relatively large, planar, identical face and at least one relatively narrow end face. The envelope may, by way of example, be substantially rectangular, a rectangular with a rounded parallelogram face, or a solid with a rectangular face. In one embodiment, terminals providing electrical contact to one or more components within the envelope are embedded within the envelope and have electrical contact surfaces for electrical contact with terminals located on the envelope's surface. In one embodiment, the terminal contact surfaces are substantially flush with the surface on which they are located. Optionally, the contact surfaces are recessed or raised relative to the surface on which they are located. In one embodiment, the contact surfaces are located on the envelope's face. Optionally, all of the terminal contact surfaces are located on the same face.

[0006] The power mite may include terminal pins extending from an end face of the envelope and making electrical contact with one or more components within the envelope. In one embodiment, the terminal pins include terminal pins diagonally opposite each other on opposite end faces of the envelope.

[0007] This Summary is provided to introduce in a simplified form a selection of concepts that are further described below in the Brief Description of the Drawings. The Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. [Brief explanation of the drawings]

[0008] Non-limiting examples of embodiments of the present invention are described below with reference to the accompanying figures listed following this paragraph. Identical structures, elements, or parts that appear in multiple figures are typically labeled with the same reference numeral in all figures in which they appear. Dimensions of components and features shown in the figures have been chosen for convenience and clarity of presentation and are not necessarily shown to scale.

[0009] [Figure 1A] 1A and 1B schematically illustrate a top perspective view of a Power Mite power switch according to an embodiment of the present disclosure. [Figure 1B] 1A and 1B schematically illustrate a bottom perspective view of a Power Mite power switch according to an embodiment of the present disclosure. [Figure 1C] 10A-10C illustrate schematic diagrams of a variation of the Power Mite in accordance with an embodiment of the present disclosure. [Figure 2A] 1 illustrates a schematic diagram of the structure and assembly features of a Power Mite according to one embodiment of the present disclosure. [Figure 2B] 1 illustrates a schematic diagram of the structure and assembly features of a Power Mite according to one embodiment of the present disclosure. [Figure 2C] 1 illustrates a schematic diagram of the structure and assembly features of a Power Mite according to one embodiment of the present disclosure. [Figure 2D]1 illustrates a schematic diagram of the structure and assembly features of a Power Mite according to one embodiment of the present disclosure. [Figure 2E] 1 illustrates a schematic diagram of the structure and assembly features of a Power Mite according to one embodiment of the present disclosure. [Figure 2F] 1 illustrates a schematic diagram of the structure and assembly features of a Power Mite according to one embodiment of the present disclosure. [Figure 2G] 1 illustrates a schematic diagram of the structure and assembly features of a Power Mite according to one embodiment of the present disclosure. [Figure 3A] 1 shows a schematic comparison of the assembly footprint of a prior art power switch and the assembly footprint of a Power Mite according to an embodiment of the present disclosure. [Figure 3B] 1 shows a schematic comparison of the assembly footprint of a prior art power switch and the assembly footprint of a Power Mite according to an embodiment of the present disclosure. [Figure 3C] 1 shows a schematic comparison of the assembly footprint of a prior art power switch and the assembly footprint of a Power Mite according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] Unless otherwise specified, adjectives such as "substantially" and "about" used herein to modify a condition or relationship characteristic of an embodiment of the present disclosure are understood to mean that the condition or characteristic is defined within a tolerance allowed for operation for the intended use of the embodiment. Whenever a general term in the present disclosure is described by reference to an exemplary example or list of exemplary examples, the examples referred to are non-limiting examples of the general term, and the general term is not intended to be limited to the specific examples referred to. The phrase "in one embodiment," whether associated with an allowance such as "may," "optionally," or "as an example," is used to introduce, for consideration, an example, but not necessarily, configuration of a possible embodiment of the present disclosure. The verbs "comprise," "include," and "have," and each of their conjugations, are used to indicate that the object of the verb is not necessarily a complete list of components, elements, or parts of the subject of the verb. Unless otherwise indicated, the word "or" in the specification and claims is to be construed as an inclusive "or" rather than an exclusive or, indicating at least one of the items it connects, or any combination of more than one of the items.

[0011] 1A and 1B schematically illustrate top and bottom perspective views, respectively, of a Power Mite 20 optionally configured to power a phase of a traction motor in an electric vehicle, according to one embodiment of the present disclosure. Power Mite 20 includes an optionally rectangular envelope 22 having a top face surface 23, shown in FIG. 1A, a bottom face surface 24, shown in FIG. 1B, and four relatively narrow end surfaces 25. Envelope 22 may be formed by dicing multiple Power Mites 20 from a common multi-unit encapsulation mold in which the Power Mites are encapsulated in a suitable polymer.

[0012] Terminals (not shown in FIGS. 1A and 1B ), described below, that contact the components of Power Mite 20 are enclosed within envelope 22 and have exposed contact surfaces 30-1, 30-2, 30-3, and 30-4, generally referred to as contact surfaces 30, on top surface 23. Contact surfaces 30-1 and 30-2 are surfaces of power terminals 41 and 42, respectively, described below, which can be used to couple power from a high-energy power source (not shown) to the half-bridge enclosed within envelope 22. Contact surface 30-3 is a surface of power phase output terminal 43, described below, which can be used to couple voltage and current to the phases of an electric motor. Contact surface 30-4 is a surface of control terminal 44, described below, which can be used to couple control circuitry to a PCB controller, described below, enclosed within envelope 22.

[0013] Optionally, as shown schematically in FIG. 1A, contact surface 30 is coplanar and substantially flush with top surface 23. In one embodiment, contact surface 30 may be raised or recessed to electrically insulate the contact surface and / or facilitate electrical contact therewith. Contact surface 30 is formed from a material compatible with electrically and mechanically coupling thereto conductors intended to provide electrical contact between an external circuit and the surface and the respective terminals it features. In one embodiment, contact surface 30 is configured to electrically and mechanically couple to the conductors by soldering, laser welding, or ultrasonic welding. Optionally, surface 30 and its associated underlying terminals are configured to allow conductors to be threaded or press-fit into holes formed in the terminals. Bottom surface 24, shown in FIG. 1B, optionally has a conductive thermal interface 26 formed thereon. This thermal interface may be formed from any of a variety of suitable highly thermally conductive materials, such as, for example, a thermally conductive solder or adhesive, a sintered or cured silver paste, or the like.

[0014] In one embodiment, Power Mite 20 may include terminal pins in addition to or instead of contact surfaces 30. Figure 1C schematically illustrates a Power Mite 21 according to one embodiment of the present disclosure, similar to Power Mite 20, but instead of terminals with contact surfaces 30 on top face surface 23, Power Mite 21 includes a set 46 of terminal pins 47 and a set 48 of terminal pins 49. In one embodiment, set 46 of terminal pins 47 and set 48 of terminal pins 49 are diagonally opposed to each other on opposite end surfaces 25 of envelope 22. As described below with respect to Figures 3A and 3B, the diagonally opposed terminal pin sets 46 and 48 facilitate the close spacing of multiple Power Mites 20, facilitating parallel connection of Power Mites for high current switching.

[0015] It should be noted that envelope 22 in Figure 1C shows parting line 27 along which the terminal pins are arranged. While it may be advantageous to encapsulate the terminals of multiple Power Mites 20 (e.g., terminals 41-44 with contact surfaces 30) in a common multi-unit encapsulation mold and then separate the individual Power Mites 20 by dicing the circuits, it may be advantageous to individually encapsulate Power Mites with their terminal pins (e.g., terminal pins 47 and 49) in a single-unit mold. While the dicing process for encapsulating multiple units eliminates the parting line in envelope 22, encapsulating individual single units typically requires a two-piece release mold, which typically results in parting line 27 appearing in envelope 22 shown in Figure 1C.

[0016] 2A-2G show schematic diagrams of stages in the construction and assembly of Power Mite 20 according to one embodiment of the present disclosure.

[0017] 2A schematically illustrates the first stage of construction of the Powermite 20, in which a pattern of conductive traces, commonly referred to as traces 50, to which the Powermite's components are electrically connected, is formed on the top surface 41 of an optional DBC (direct bond copper) substrate 40. In one embodiment, the traces 50 include a positive power terminal trace 51, a negative power terminal trace 52, a power output phase trace 53, a control trace 54, and die connect traces 55, 56, 57, and 58. Attached to the traces 50 are connection pins 60 that can be used to electrically connect the Powermite's circuit components to a PCB controller 100 (not shown in FIG. 2A ) encapsulated within the Powermite 20. In one embodiment, conductive spacers 62 are electrically connected to the power traces 51, facilitating connection between the power traces and the metallized electrodes of the Powermite's components. As shown schematically in FIG. 2C and described below, spacers 62 facilitate making electrical connections using planar interconnects to metallized electrodes of PowerMite components that protrude above the top surfaces of traces 50 by the thickness of the components.

[0018] 2B schematically illustrates semiconductor dies directly connected to respective ones of the plurality of traces 50 to form two half bridges 70, 80 of the power mite 20. In one embodiment, the half bridge 70 includes a high-side, optionally normally-on, lateral n-channel GaN (gallium nitride) die 72, a high-side, optionally p-channel MOSFET (metal-on-silicon field-effect transistor) die 74, a low-side, optionally normally-on, lateral n-channel GaN die 76, and a low-side, optionally p-channel MOSFET die 78. Similarly, the half bridge 80 may include a high-side, optionally normally-on, lateral n-channel GaN die 82, a high-side, optionally p-channel MOSFET die 84, a low-side, optionally normally-on, lateral n-channel GaN die 86, and a low-side, optionally p-channel MOSFET die 88.

[0019] Each of the normally-on GaN dies 72, 76, 82, 86 optionally includes an array (not shown) of columns of normally-on lateral GaN transistors (not shown), which are connected to a fishbone configuration 90 of metallization layers, including a drain fishbone metallization layer 92-D having spines 93 interleaved with spines 94 of a source fishbone metallization layer 95-S. The drains (not shown) of the normally-on GaN transistors are in electrical contact with the spines 92-D of the drain fishbone 93, and the sources of the transistors are in electrical contact with the spines 94 of the source fishbone 95-S. The gates of the GaN transistors are electrically connected by wirebonds to a control trace 54, designated "54g." The gates of the MOSFET transistors are optionally connected by wirebonds to a control trace 54, designated "54g." * ". The substrates (not shown) of the GaN dies 72, 76, 82, 86 are electrically connected to the respective die traces 55, 57, 56, 58 to which the die is attached.

[0020] Each of the MOSFET dies 74, 84, 78, and 88 includes an array of MOSFET transistors (not shown) having their sources electrically connected to respective source metallization layers 74-S, 84-S, 78-S, and 88-S and their drains connected to respective drain metallization layers (not shown). The drain metallization layers of the high-side MOSFET dies 74 and 84 are electrically connected to the power output phase output trace 53. The drain metallization layers of the low-side MOSFET dies 78 and 88 are electrically connected to the negative power trace 52.

[0021] In FIG. 2C, the GaN die and MOSFET die shown in FIG. 2B are connected by relatively large-area, planar interconnect conductors. The drain fishbone metallization 92-D (FIG. 2B) of the high-side GaN die 72 is electrically connected to the conductive spacer 62 (FIG. 2B) located on the positive power trace 51 by a conductive interconnect 73, which may be planar. The source metallization 95-S (FIG. 2B) of the high-side GaN die 72 is electrically connected to the source metallization 74-S of the high-side MOSFET 70 by a conductive interconnect 75, which may be planar. Similarly, the drain metallization 92-D (FIG. 2B) of the high-side GaN die 82 is electrically connected to the conductive spacer 62 located on and connected to the positive power trace 51 by a conductive interconnect 83, which may be planar. The source metallization 95-S (FIG. 2B) of the high-side GaN die 82 is electrically connected to the source metallization 84-S of the high-side MOSFET 84 by a conductive interconnect 85, which may be planar. The source metallization 95-S of the low-side GaN die 76 is electrically connected to the source metallization 78-S of the MOSFET 78 by an interconnect 77, which may be planar, and the source metallization 95-S of the low-side GaN die 86 is electrically connected to the source metallization 88-S of the MOSFET die 88 by an interconnect 87, which may be planar. The drain metallization 92-D of the low-side GaN dies 76, 86 are connected to each other by conductive interconnects 76-86, which may be planar. The interconnects 76-86 make electrical contact with the conductive spacers 62 on the power output phase traces 53, which in turn make electrical contact with the power output phase traces.

[0022] FIG. 2D schematically illustrates the direction of current flow in half-bridge 70 and half-bridge 80 when PowerMite 20 is on and power trace 53 is energized to optionally provide voltage and current from a power source connected to positive and negative power terminal traces 51, 52 to a traction motor connected to PowerMite 20. In this illustration, the arrowed band labeled I-70 schematically represents current flow through half-bridge 70. The solid portion of the band represents current flow in I-70 through interconnects 73, 75 and conductive trace 53. The dashed area of ​​band 1-70 represents the "hidden" portion of I-70 flowing "downward" from interconnect 75 through MOSFET 74 ( FIG. 2B ) and into the portion of conductive trace 53 underneath interconnects 75, 85. Similarly, the arrowed band labeled I-80 schematically represents current flow through half-bridge 80. The solid portion of the band represents the current flow of I-80 on interconnects 83, 85 and conductive trace 53. The dashed area of ​​band I-80 represents the "hidden" portion of I-80 that flows "downward" from interconnect 85 through MOSFET 84 (FIG. 2B) and into conductive trace 53 underneath interconnects 75, 85. Note that currents I-70, I-80 flow parallel to each other in trace 53, helping to reduce the inductance of Power Mite 20 when turned on and off.

[0023] 2E shows a schematic representation of the direction of current flow in half-bridge 70 and half-bridge 80 when the power-mite 20 is turned off by turning off high-side GaN transistors 72, 82 and MOSFETs 74, 84 and turning on low-side GaN transistors 76, 86 and low-side MOSFETs 78, 88. Current from the negative power terminal trace 52 flows in current branches represented by bands I-77, I-87 through MOSFETs 78, 88 to conductive interconnects 76-86, combines with current represented by current band I-53, and flows along output phase trace 53 to the power-mite 20. The dashed portions of the bands represent current portions that are hidden from the perspective of FIG. 2E.

[0024] In one embodiment, the total power loop inductance of the power mite 20 during transition between the on and off states may be less than about 2.50 nH. Optionally, the total power loop inductance may be less than about 2.25 nH.

[0025] FIG. 2F schematically illustrates a Power-Mite 20 with power terminals 41, 42 having contact surfaces 30-1, 30-2 (FIG. 1A) attached to positive and negative power terminal traces 51 and 52 (FIG. 2A), a power phase output terminal 43 having contact surface 30-3 (FIG. 1A) attached to power output phase trace 53 (FIG. 2A), and a control PCB 100, which may be multilayer, attached to the Power-Mite 20. The PCB 100 contacts components within the Power-Mite 20 via connection pins 60 (FIGS. 2A-2E) and contacts circuitry external to the Power-Mite 20 via control terminal 44, which may be cylindrical and has contact surface 30-4 (FIG. 1A). In one embodiment, the Power-Mite 20, as schematically illustrated in FIG. 2F, is encapsulated to provide the completed Power-Mite 20 shown in FIG. 1A.

[0026] FIG. 2G shows a schematic representation of a Power-Mite variant, Power-Mite 21, in which the cylindrical control terminal 44 shown in FIG. 2F is replaced by diagonally opposed sets 46, 48 of terminal pins 47, 49, respectively, such that after encapsulation, Power-Mite 21 has the configuration shown in FIG. 1C.

[0027] Power Mites according to embodiments of the present disclosure, such as Power Mites 20 and 21 designed as shown generally in Figures 1A-2G, have a highly aesthetically pleasing configuration and a relatively small footprint. Due to their small footprint and recessed or diagonally opposed electrical terminals, Power Mites according to embodiments of the present disclosure can be easily attached to a heat sink, optionally by soldering or sintering, and connected in parallel into compact, high-density "power pack" arrays.

[0028] As an example, Figures 3A and 3B schematically illustrate the dimensions of the footprints of power pack arrays 201, 202 of six Power Mite 20, 21, respectively, according to an embodiment of the present disclosure. For comparison, Figure 3C illustrates the footprint of a power pack 220 according to an embodiment in which the terminal pin arrays are mounted directly opposite each other, rather than diagonally opposite each other as in Power Mite 21. The footprints of power pack arrays 201, 202 are substantially smaller than the footprint of power pack array 220.

[0029] The descriptions of embodiments of the present invention herein are provided by way of example and are not intended to limit the scope of the present invention. The described embodiments include different features, not all of which are required for all embodiments of the present invention. Some embodiments utilize only some of the features or possible combinations of the features. Various embodiments of the present invention, including variations of the described embodiments of the present invention and different combinations of the features mentioned in the described embodiments, will occur to those skilled in the art. The scope of the present invention is limited only by the claims.

Claims

1. 1. A power switch comprising: a pair of substantially parallel half bridges; power terminals for coupling a power source to the half-bridge; power phase output terminals for connecting a load to the half-bridge; a printed circuit board (PCB) controller having control circuitry operable to turn the half-bridges on and off to connect and disconnect the load to the power supply; a control terminal for connecting a control circuit on the PCB to a circuit external to the power switch; Including, a power switch, wherein the half bridge, the PCB, the control terminal, the power terminal, and the power phase output terminal are enclosed within a same encapsulating envelope having a planar first face surface and at least one end surface, all of the terminals having electrical contact surfaces on the first face surface that are exposed only to the first face surface, and all of the at least one end surface having no electrical contact surfaces and no terminal pins.

2. 2. The power switch of claim 1, wherein the electrical contact surfaces of the power terminal and the power phase output terminal are substantially flush with the first face surface.

3. 2. The power switch of claim 1, wherein an electrical contact surface of the power terminal and / or the power phase output terminal is raised or recessed relative to the plane of the first face surface.

4. 2. The power switch of claim 1, wherein the electrical contact surface of the control terminal is substantially flush with the first face surface.

5. 5. The power switch of claim 4, wherein an electrical contact surface of one of the control terminals is raised or recessed relative to the plane of the first face surface.

6. 2. The power switch of claim 1, wherein the electrical contact surface and the control terminal to which the electrical contact surface belongs are configured to be coupled to an electrical conductor, the coupling being achieved by soldering, ultrasonic welding or laser welding, or by pressing or screwing the electrical conductor into a hole in the control terminal.

7. The power switch of claim 1 , wherein the encapsulating envelope is a rectangular parallelepiped that encloses all components of the power switch.

8. 1. A power switch comprising: a pair of substantially parallel half bridges; power terminals for coupling a power source to the half-bridge; power phase output terminals for connecting a load to the half-bridge; a printed circuit board (PCB) controller having control circuitry operable to turn the half-bridges on and off to connect and disconnect the load to the power supply; first and second sets of control terminal pins in electrical contact with control circuitry on the PCB controller; an encapsulating envelope that encapsulates all components of the power switch except for the control terminal pin and has a rectangular parallelepiped shape with a planar first face and a plurality of end faces; Including, a power switch, wherein contact surfaces of the terminals are exposed on the first face surface, and the first and second sets of control terminal pins extend from first and second opposing end surfaces, respectively, at diagonally opposite positions, and vertical projections of the sets onto the same plane parallel to the first and second opposing end surfaces do not overlap.

9. 2. The power switch of claim 1, including a second face surface opposite the first face surface and having an electrically conductive thermal interface formed thereon.

10. The power switch of claim 1 , wherein when the power switch is turned on, current flows in parallel in the same direction in each half-bridge to the power phase output terminals.

11. The power switch of claim 1 , wherein when transitioning between an on state and an off state, the total power loop inductance is less than about 2.5 nH, less than 2.25 nH, or less than about 2.0 nH.

12. A power pack array comprising a plurality of the power switch of claim 1 butted against one another.

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