Wiring board and mounting structure

Abstract

A wiring board according to the present disclosure includes an insulating layer having a first surface and a second surface positioned on the side opposite from the first surface, and a first wiring conductor positioned on the first surface. The first surface of the insulating layer has a first region having a first arithmetic average roughness, and a second region having a second arithmetic average roughness. The second arithmetic average roughness is greater than the first arithmetic average roughness. The first wiring conductor is positioned crossing from the first region to the second region.

Description

[Technical Field]

[0001] The present invention relates to a wiring board and a mounting structure using the same. [Background technology]

[0002] In recent years, with the trend toward miniaturization of electronic devices, wiring patterns formed on wiring boards have become densely packed with fine wiring. Such fine wiring patterns are prone to peeling, and the resulting wiring boards have poor electrical reliability. For example, Patent Document 1 describes a method for making fine wiring patterns less likely to peel off by roughening the surface of a resin base material (insulating layer) to improve adhesion between the wiring pattern and the insulating layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-95828 Summary of the Invention [Means for solving the problem]

[0004] The wiring board according to the present disclosure includes an insulating layer having a first surface and a second surface located on the opposite side to the first surface, a first wiring conductor located on the first surface, and a second wiring conductor located on the second surface; The first surface of the insulating layer has a first region having a first arithmetic mean roughness and a second region having a second arithmetic mean roughness, the second arithmetic mean roughness being greater than the first arithmetic mean roughness, and the first wiring conductor is located across from the first region to the second region. In a planar perspective view, the first region is selectively formed at a position overlapping the second wiring conductor.

[0005] A mounting structure according to the present disclosure includes the above wiring board and an element located on the surface of the wiring board. [Brief explanation of the drawings]

[0006] [Figure 1]FIG. 1 is an explanatory diagram illustrating a wiring substrate according to an embodiment of the present disclosure. [Figure 2] 2 is an enlarged explanatory view for explaining one embodiment of a cross section of region X shown in FIG. 1. FIG. [Figure 3] 1. FIG. 4 is an enlarged explanatory view for explaining another embodiment of the cross section of region X shown in FIG. [Figure 4] 2 is an enlarged explanatory view for explaining a cross section of a region Y shown in FIG. 1. FIG. [Figure 5] 1 is an explanatory diagram for explaining one embodiment of a method for forming a first region 2a and a second region 2b in an insulating layer (insulating layer for build-up). FIG. [Figure 6] 10 is an explanatory view for explaining another embodiment of a method for forming a first region 2a and a second region 2b in an insulating layer (insulating layer for build-up). FIG. DETAILED DESCRIPTION OF THE INVENTION

[0007] In conventional wiring boards such as those described in Patent Document 1, although the adhesion between the wiring pattern and the insulating layer is improved, there is a problem in that the electrical properties deteriorate when the surface of the insulating layer is roughened. Therefore, there is a demand for wiring boards that have excellent electrical properties and in which the wiring conductors are less likely to peel off.

[0008] The wiring board according to the present disclosure has a configuration as described in the section on means for solving the problems, thereby reducing deterioration of electrical characteristics and making the wiring conductor less susceptible to peeling.

[0009] A wiring board according to an embodiment of the present disclosure will be described with reference to Figures 1 to 4. Figure 1 is an explanatory diagram for illustrating a wiring board 1 according to an embodiment of the present disclosure. As shown in Figure 1, the wiring board 1 according to the embodiment includes an insulating layer 2, a conductor layer 3, and a solder resist 4.

[0010] The insulating layer 2 includes a core insulating layer 21 and a build-up insulating layer 22. The core insulating layer 21 is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed. The thickness of the core insulating layer 21 is not particularly limited and is, for example, 40 μm or more and 1800 μm or less.

[0011] The core insulating layer 21 may contain a reinforcing material. Examples of reinforcing materials include insulating fabric materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more types of reinforcing materials may be used in combination. Furthermore, the core insulating layer 21 may have dispersed therein an inorganic insulating filler such as silica, barium sulfate, talc, clay, glass, calcium carbonate, or titanium oxide.

[0012] A through-hole conductor 21a is located in the core insulating layer 21 to electrically connect the top and bottom surfaces of the core insulating layer 21. The through-hole conductor 21a is located in a through-hole that penetrates from the top surface to the bottom surface of the core insulating layer 21. The through-hole conductor 21a is formed by metal plating such as copper plating. The through-hole conductor 21a is connected to the conductor layers 3 formed on both surfaces of the core insulating layer 21. The through-hole conductor 21a may be located only on the inner wall surface of the through-hole, or may fill the through-hole.

[0013] Build-up layers, in which conductor layers 3 and build-up insulating layers 22 are alternately stacked, are located on the upper and lower surfaces of the core insulating layer 21. The build-up layer has at least two conductor layers 3 and one build-up insulating layer 22 stacked on top of each other. The conductor layer 3 is not limited as long as it is made of a conductor such as a metal. Specifically, the conductor layer 3 is made of a metal foil such as copper foil, or a metal plating such as copper plating. The thickness of the conductor layer 3 is not particularly limited and is, for example, 10 μm or more and 30 μm or less.

[0014] Like the core insulating layer 21, the buildup insulating layer 22 is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed and used. The buildup insulating layer 22 may be made of the same resin or different resins. The buildup insulating layer 22 and the core insulating layer 21 may be made of the same resin or different resins.

[0015] Furthermore, inorganic insulating fillers such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide may be dispersed in the build-up insulating layers 22. The thickness of the build-up insulating layers 22 is not particularly limited and is, for example, 25 μm or more and 40 μm or less. The build-up insulating layers 22 may have the same thickness or different thicknesses.

[0016] Via-hole conductors 22a for electrically connecting layers are formed in the build-up insulating layer 22. The via-hole conductors 22a are located in via holes that penetrate the top and bottom surfaces of the build-up insulating layer 22. The via-hole conductors 22a are formed by metal plating such as copper plating. The via-hole conductors 22a are connected to conductor layers 3 that are located on both sides of the build-up insulating layer 22. The via-hole conductors 22a may fill the via holes, or may be located only on the inner wall surfaces of the via holes.

[0017] As shown in Fig. 1, a solder resist 4 may be positioned on the surface of the build-up layer. The solder resist 4 is made of a resin, such as an acrylic-modified epoxy resin. The solder resist 4 has openings for electrically connecting the conductor layer 3 to the electrodes of the element via solder 5. Examples of the element include a semiconductor integrated circuit element and an optoelectronic element.

[0018] As shown in Fig. 2, the build-up insulating layer 22 has a first surface 221 and a second surface 222 located on the opposite side of the first surface 221. Fig. 2 is an enlarged explanatory view for explaining one embodiment of a cross section of region X shown in Fig. 1. The first surface 221 has a first region 2a having a first arithmetic mean roughness and a second region 2b having a second arithmetic mean roughness.

[0019] In the wiring board 1 according to one embodiment, the second arithmetic mean roughness of the second region 2b is greater than the first arithmetic mean roughness of the first region 2a. In the conductor layer 3, the first wiring conductor 31 is located from the first region 2a to the second region 2b. By being located in regions with different arithmetic mean roughnesses, it is possible to reduce deterioration of electrical characteristics in the first region 2a, which has a small arithmetic mean roughness, and improve adhesion of the first wiring conductor 31 in the second region 2b, which has a large arithmetic mean roughness. As a result, the wiring board 1 reduces deterioration of electrical characteristics and makes the first wiring conductor 31 less susceptible to peeling.

[0020] The conductor layer 3 generally includes a power conductor, a ground conductor, and a signal conductor. The first wiring conductor 31 is, for example, a signal conductor. The arithmetic mean roughness (third arithmetic mean roughness) of the side surface and the surface opposite to the surface in contact with the first surface 221 of the first wiring conductor 31 may be smaller than the first arithmetic mean roughness. If the third arithmetic mean roughness is smaller than the first arithmetic mean roughness, the side surface and surface of the first wiring conductor 31 are relatively flat, which is advantageous in that the transmission characteristics are improved, particularly when transmitting high-frequency signals.

[0021] The second arithmetic mean roughness may be 1.5 times or more the first arithmetic mean roughness. When the second arithmetic mean roughness is 1.5 times or more the first arithmetic mean roughness, a relatively rough region and a smooth region are present, which can further improve the adhesion of the first wiring conductor 31 while reducing deterioration of electrical characteristics. The first arithmetic mean roughness may be, for example, 50 nm or more and 200 nm or less, and the second arithmetic mean roughness may be, for example, 100 nm or more and 300 nm or less.

[0022] It is sufficient that at least one first region 2a and one second region 2b exist for one first wiring conductor 31. In consideration of reducing deterioration in electrical characteristics and improving adhesion of the first wiring conductor 31, the first regions 2a and the second regions 2b may be positioned alternately along the first wiring conductor 31.

[0023] As shown in Fig. 3, the second region 2b may have recesses 2c recessed toward the second surface 222. Fig. 3 is an enlarged explanatory view illustrating another embodiment of the cross section of region X shown in Fig. 1. By having such recesses 2c, the adhesion of the first wiring conductor 31 can be further improved. The arithmetic mean roughness of the recesses 2c may be 100 nm or more and 300 nm or less, similar to the second arithmetic mean roughness of the second region 2b.

[0024] The size of the recess 2c is not limited, and for example, the depth (D in FIG. 3) is 5 μm or less at the deepest part, and the opening width (W in FIG. 3) is 10 μm or more and 200 μm or less at the widest part. If the depth D and opening width W of the recess 2c are within these ranges, the surface of the first wiring conductor 31 (the surface opposite the recess 2c) can be kept flat. As a result, the adhesion of the first wiring conductor 31 can be further improved without affecting the electrical characteristics.

[0025] The wiring board 1 may include a second wiring conductor 32 as shown in FIG. 4. FIG. 4 is an enlarged explanatory view illustrating a cross section of region Y shown in FIG. 1. The second wiring conductor 32 is located on the second surface 222 of the build-up insulating layer 22, and is located so as to overlap with the first region 2a of the build-up insulating layer 22 in a planar perspective view. In other words, in this example, the second wiring conductor 32 is located between the build-up insulating layer 22 and the core insulating layer 21, with a portion of the second wiring conductor 32 embedded in the build-up insulating layer 22, and is located below the first region 2a in a cross-sectional view. The thickness of the build-up insulating layer 22 located on the upper surface of the second wiring conductor 32 is thin. Therefore, by facing the first region 2a, which has a small arithmetic mean roughness, ionThis reduces the possibility of migration and short circuits, and reduces deterioration of electrical characteristics. The thickness of the second wiring conductor 32 is, for example, 20 μm or more and 30 μm or less. The distance between adjacent second wiring conductors 32 is, for example, 30 μm or more and 50 μm or less.

[0026] In the wiring board 1 according to one embodiment, the first region 2a and the second region 2b of the insulating layer 2 (build-up insulating layer 22) are formed, for example, as follows. First, in order to laminate the insulating layer 2 (build-up insulating layer 22) having the first region 2a and the second region 2b, an insulating layer 2 (for example, core insulating layer 21) is prepared as a base. The surface of this core insulating layer 21 (build-up insulating layer 2) is then formed. 2 is The surface to be formed ) Then, the second wiring conductor 32 is formed.

[0027] Next, a resin sheet 23 that will become the build-up insulating layer 22 is laminated on the surface of the core insulating layer 21 so as to cover the second wiring conductor 32. The resin sheet 23 used has a protective film 23a attached to the surface opposite the core insulating layer 21, and the protective film 23a has irregularities on the surface that comes into contact with the resin sheet 23. The resin sheet 23 is laminated at a relatively high temperature (120°C or higher).

[0028] Next, the resin sheet 23 is pressed from above the protective film 23a. At this time, the area where the second wiring conductor 32 is present is pressed more strongly than the other areas, with the second wiring conductor 32 serving as a base. After pressing, the protective film 23a attached to the resin sheet 23 is peeled off, thereby forming a first region 2a and a second region 2b on the surface (first surface 221) of the build-up insulating layer 22. The roughness of the area that is pressed strongly with the second wiring conductor 32 as a base is small, and becomes the first region 2a. The roughness of the other areas is large, and becomes the second region 2b, as shown in FIG. 5.

[0029] A first wiring conductor 31 is formed on the upper surface of the build-up insulating layer 22 by a semi-additive process, spanning from the first region 2a to the second region 2b. Next, metal oxide films, such as copper oxide films, are removed by acid washing. After that, tin is deposited to a thickness of approximately 100 nm. Excess tin is then removed by etching, for example, using nitric acid. This etching is performed to adjust the thickness of the tin to approximately 2 nm to 5 nm.

[0030] Next, a silane coupling agent is applied so as to cover the formed tin layer. Examples of the silane coupling agent include FC-9100Z (manufactured by MEC Co., Ltd.) and KBM-303 (manufactured by Shin-Etsu Chemical Co., Ltd.). ) , DOWSIL TM Commercially available silane coupling agents, such as Z-6040 Silane (Dow-Toray Industries, Inc.), can be used. After application, the silane coupling agent is treated at a temperature of 70°C to 100°C for 1 minute to 10 minutes to form a silane coupling agent layer on the surface of the tin layer. In this way, a first wiring conductor 31, such as that shown in FIG. 1, is formed.

[0031] If the resin sheet 23 that will become the build-up insulating layer 22 is laminated on the surface of the core insulating layer 21 at a relatively low temperature (100°C or less), depressions will form on the surface of the resin sheet 23 in the areas between adjacent second wiring conductors 32, as shown in Figure 6. After peeling off the protective film 23a, a release film is placed on the peeled surface of the resin sheet, and pressure is applied from above the release film. The resin sheet 23 used has the protective film 23a attached to the surface opposite the core insulating layer 21, and the protective film 23a has unevenness on the surface that comes into contact with the resin sheet 23.

[0032] At this time, the recessed portions on the surface of the resin sheet 23 are not easily pressurized, and the roughness tends to increase. On the other hand, the portions where the second wiring conductors 32 are present are strongly pressurized as described above, and the roughness tends to decrease. By peeling off the release film, the first region 2a and the second region 2b having the recessed portions 2c are formed on the surface (first surface 221) of the build-up insulating layer 22. The presence of the second wiring conductors 32 makes it easier for the recessed portions 2c to be formed between adjacent second wiring conductors 32.

[0033] The mounting structure according to the present disclosure includes a wiring board 1 according to one embodiment and an element S located on the surface of the wiring board 1. A conductor layer 3 in an opening of a solder resist 4 is connected to an electrode of the element S via solder 5. As described above, the element S may be a semiconductor integrated circuit element, an optoelectronic element, or the like. The element S may be located on both surfaces of the wiring board 1, or the element S may be located on one surface and, for example, a motherboard may be located on the other surface.

[0034] The wiring board according to the present disclosure is not limited to the wiring board 1 according to the embodiment described above. In the wiring board 1 according to the embodiment, the build-up insulating layer 22 located directly above the core insulating layer 21 has the first region 2a and the second region 2b. However, the first region 2a and the second region 2b of The insulating layer is not limited to the build-up insulating layer 22 located directly on the core insulating layer 21. When there are two or more build-up insulating layers, the first region 2a and the second region 2b may be present on the first surface of the build-up insulating layer 22 other than the build-up insulating layer located directly on the core insulating layer, or the first region 2a and the second region 2b may be present on the first surface of the core insulating layer 21.

[0035] Furthermore, the wiring board according to the present disclosure does not need to have the first region 2a and the second region 2b on the first surface of all insulating layers; it is sufficient that the first region 2a and the second region 2b are present on the first surface of at least one insulating layer. [Explanation of symbols]

[0036] 1. Wiring board 2. Insulation layer 21 Core insulation layer 22 Build-up insulation layer 21a through-hole conductor 22a Via hole conductor 221 Page 1 222 2nd page 2a 1st area 2b 2nd area 2c Recess 23 Resin sheet 23a Protective film 3 Conductor Layer 31 First wiring conductor 32 Second wiring conductor 4 Solder resist 5 Solder

Claims

1. an insulating layer having a first surface and a second surface opposite the first surface; a first wiring conductor located on the first surface; a second wiring conductor located on the second surface; Including, the first surface of the insulating layer has a first region having a first arithmetic mean roughness and a second region having a second arithmetic mean roughness; the second arithmetic mean roughness is greater than the first arithmetic mean roughness; the first wiring conductor is located across the first region and the second region, In a planar perspective view, the first region is selectively formed at a position overlapping the second wiring conductor. Wiring board.

2. The wiring board according to claim 1 , wherein the second region has a recessed portion recessed toward the second surface side.

3. 3. The wiring board according to claim 2, wherein the depth of the recess is 5 [mu]m or less at the deepest part.

4. The wiring board according to claim 2 , wherein the recess has a maximum opening width of 10 μm to 200 μm in plan view.

5. The wiring board according to claim 1 , wherein the second arithmetic mean roughness is 1.5 times or more the first arithmetic mean roughness.

6. The wiring board according to claim 1 , wherein the first regions and the second regions are alternately positioned along the first wiring conductor.

7. The wiring board according to claim 1 , wherein the first wiring conductor is a signal conductor.

8. The wiring board according to claim 1 , wherein a third arithmetic mean roughness of a surface of the first wiring conductor opposite to the surface in contact with the side surface and the first surface is smaller than the first arithmetic mean roughness.

9. an insulating layer having a first surface and a second surface opposite the first surface; a first wiring conductor located on the first surface; Including, the first surface of the insulating layer has a first region having a first arithmetic mean roughness and a second region having a second arithmetic mean roughness; the second arithmetic mean roughness is greater than the first arithmetic mean roughness; the first wiring conductor is located across the first region and the second region, the second region has a recess recessed toward the second surface, In a plan view, the opening width of the recess is 10 μm or more and 200 μm or less at the maximum part. Wiring board.

10. A mounting structure comprising the wiring board according to any one of claims 1 to 9 and an element located on a surface of the wiring board.

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