High-precision circuit board and preparation method therefor
By laminating conductive layers in the same process and using adhesive and auxiliary layers, the alignment and warpage problems caused by the asymmetrical structure of the factor board in AI server accelerator card products were solved, enabling the fabrication of high-precision circuit boards and promoting product development.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- DELTON TECH (GUANGZHOU) INC
- Filing Date
- 2025-11-14
- Publication Date
- 2026-06-04
Smart Images
Figure CN2025135097_04062026_PF_FP_ABST
Abstract
Description
High-precision circuit boards and their fabrication methods
[0001] This application claims priority to Chinese Patent Application No. 202411704617.1, filed with the Chinese Patent Office on November 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of printed circuit board technology, for example to a high-precision circuit board and a method for its fabrication. Background Technology
[0003] The tiered gold finger product has a wide range of applications, not only in conventional memory storage but also in trendy AI server accelerator cards, making it a very important product in the mainstream market. The world's top three server groups are all heavily investing in the development of such products in order to quickly capture the AI server accelerator card market.
[0004] The mainstream structure of the stepped gold finger printed circuit board used in AI server accelerator cards is 18 layers, consisting of 8 core boards and 2 layers of copper foil. Due to the need for buried or blind vias in product design, the conventional approach is to laminate multiple sub-boards separately, then form through-holes on the sub-boards, and then laminate multiple sub-boards again to form the final 18 conductive layers required. In this case, the through-holes on the sub-boards are made into buried or blind vias. This inevitably leads to asymmetrical pressing of the copper foil and core board during the pressing process. Because of the asymmetry between the core board and the copper foil, the sub-boards are heated and shrink unevenly in the press, which inevitably produces serious misalignment and warpage problems. This makes it impossible to meet the high alignment requirements, thus limiting the development and advancement of AI server accelerator card products. Summary of the Invention
[0005] This application provides a high-precision circuit board and its manufacturing method to solve the technical problems of alignment and warping caused by the asymmetrical structure resulting from the separate lamination of sub-boards.
[0006] According to one aspect of this application, a method for manufacturing a high-precision circuit board is provided, the high-precision circuit board including at least one blind via or buried via;
[0007] The preparation method includes:
[0008] Obtain the preset circuit diagram of the high-precision circuit board;
[0009] According to the preset circuit diagram, multiple conductive layer groups are set; wherein, a conductive layer group consists of adjacent conductive layers that need to form the same blind via or buried via, and a conductive layer group consists of adjacent conductive layers that do not need to form the same blind via or buried via; each conductive layer group includes a core board with two conductive layers.
[0010] Each of the conductive layers is stacked, and an adhesive layer is placed between the core plates in the same group or between the core plate and the conductive layer, and an auxiliary layer is placed between different and adjacent groups of conductive layers;
[0011] The conductive layer, the adhesive layer, and the auxiliary layer are laminated together, and the auxiliary layer is peeled off after lamination, so that the conductive layer assembly forms a sub-board;
[0012] Drill holes at at least one predetermined position on the sub-board to form through holes;
[0013] The sub-boards are stacked, and the adhesive layer is placed between different and adjacent sub-boards;
[0014] The sub-plate and the adhesive layer are laminated together to form the through hole as the blind hole or the buried hole.
[0015] Optionally, at least a portion of the conductive layer group comprises a single conductive layer.
[0016] Optionally, the uppermost and lowermost conductive layer groups may include an odd number of conductive layers;
[0017] According to the preset circuit diagram, multiple conductive layer groups are set, including:
[0018] According to the preset circuit diagram, multiple conductive layer groups are divided; wherein, in the uppermost and lowermost conductive layer groups, the side closest to the adjacent conductive layer group is the single conductive layer, and / or, in the uppermost and lowermost conductive layer groups, the side furthest from the adjacent conductive layer group is the core board.
[0019] Optionally, the uppermost and lowermost conductive layer groups may include an odd number of conductive layers;
[0020] According to the preset circuit diagram, multiple conductive layer groups are set, including:
[0021] According to the preset circuit diagram, multiple conductive layer groups are divided; wherein, in the uppermost and lowermost conductive layer groups, the side away from the adjacent conductive layer group is the single conductive layer, and / or, in the uppermost and lowermost conductive layer groups, the side closer to the adjacent conductive layer group is the core board.
[0022] Optionally, the auxiliary layer includes the single-layer conductive layer;
[0023] The uppermost and / or lowermost conductive layer group comprises an odd number of the conductive layers;
[0024] According to the preset circuit diagram, multiple conductive layer groups are set, including:
[0025] According to the preset circuit diagram, multiple conductive layer groups are divided; wherein, the topmost layer in the topmost conductive layer group and the bottommost layer in the bottommost conductive layer group are either the single-layer conductive layer or the core board.
[0026] The conductive layers are stacked, and an adhesive layer is placed between the core plates in the same group or between the core plate and the conductive layer, and an auxiliary layer is placed between different but adjacent groups of conductive layers, including:
[0027] The conductive layers are stacked, and an adhesive layer is placed between the core plates in the same group or between the core plate and the conductive layer. The auxiliary layer is placed between different and adjacent conductive layer groups. The auxiliary layer is also placed above the uppermost conductive layer group or below the lowermost conductive layer group, so that the upper and lower edge conductive layers of all the conductive layers are single-layer conductive layers.
[0028] Optionally, the conductive layer includes a copper layer; the auxiliary layer includes at least one copper foil.
[0029] Optionally, the auxiliary layer comprises two layers of copper foil;
[0030] An auxiliary layer is placed between different but adjacent conductive layer groups, including:
[0031] Two copper layers are placed between different but adjacent conductive layer groups, with the smooth side of the copper foil facing the adjacent conductive layer group and the rough side of the copper foil facing the inside of the auxiliary layer.
[0032] Optionally, the auxiliary layer includes two layers of copper foil and an adhesive layer located between the two layers of copper foil.
[0033] Optionally, the thickness of the copper foil is d; wherein, 12um≤d≤70um.
[0034] According to another aspect of this application, a high-precision circuit board is provided, which is prepared by the high-precision circuit board preparation method described in any of the above claims.
[0035] The technical solution of this application increases the thickness of a single press by laminating different conductive layer groups in the same process. It also incorporates some conductive layers that would otherwise be exposed during lamination into the middle of the film structure, increasing the uniformity of heating during lamination and making the expansion and contraction during lamination easier to control, effectively reducing layer misalignment and warpage. Furthermore, laminating different conductive layer groups in the same process ensures better consistency in the expansion and contraction data of the film layers, improving alignment accuracy and simplifying subsequent expansion and contraction adjustment processes. This effectively solves the technical challenges of alignment and warpage caused by asymmetrical structures when each conductive layer group is laminated separately. The embodiments of this application can effectively solve the manufacturing challenges of AI server accelerator cards, thereby promoting the rapid development of AI server accelerator card technology in the future. Attached Figure Description
[0036] Figure 1 is a flowchart of a method for manufacturing a high-precision circuit board according to an embodiment of this application;
[0037] Figure 2 is a schematic diagram of the film layer structure of a preset circuit diagram of a high-precision circuit board provided in an embodiment of this application;
[0038] Figure 3 is a schematic diagram of a film layer structure with a stacked placement method provided in an embodiment of this application;
[0039] Figure 4 is a schematic diagram of the film layer structure of a laminated subplate provided in an embodiment of this application;
[0040] Figure 5 is a schematic diagram of a membrane structure with another stacked placement method provided in the embodiments of this application;
[0041] Figure 6 is a schematic diagram of a membrane structure with another stacked placement method provided in the embodiments of this application;
[0042] Figure 7 is a schematic diagram of a membrane structure with another stacked placement method provided in an embodiment of this application;
[0043] Figure 8 is a schematic diagram of a membrane structure with another stacked placement method provided in the embodiments of this application;
[0044] Figure 9 is a schematic diagram of a membrane structure with another stacked placement method provided in an embodiment of this application;
[0045] Figure 10 is a schematic diagram of a membrane structure with another stacked placement method provided in the embodiments of this application;
[0046] Figure 11 is a schematic diagram of a membrane structure with another layered placement method provided in an embodiment of this application. Detailed Implementation
[0047] Figure 1 is a flowchart of a method for fabricating a high-precision circuit board according to an embodiment of this application. Referring to Figure 1, the fabrication method includes:
[0048] S1001. Obtain the preset circuit diagram of the high-precision circuit board.
[0049] The high-precision circuit board in this application embodiment can be applied to AI server accelerator card products, as well as computer system boards, motherboards, and other products. Specifically, it can be a stepped gold finger printed circuit board.
[0050] The preset circuit diagram includes the circuit patterns of each film layer in the high-precision circuit board, as well as the locations and connections of blind vias and / or buried vias. For example, taking a high-precision circuit board comprising 18 conductive layers 10 (L1-L18) as an example, Figure 2 is a schematic diagram of the film layer structure of a preset circuit diagram of a high-precision circuit board provided in an embodiment of the application. Referring to Figure 2, the preset circuit diagram shows the structure of each film layer, the locations and connections of blind vias and / or buried vias, and also shows an adhesive layer 102, which can bond and insulate adjacent conductive layers 10. Furthermore, the preset circuit diagram may also show the circuit patterns of each film layer structure (not shown in Figure 2).
[0051] S1002. According to the preset circuit diagram, set up multiple conductive layer groups; wherein, the conductive layers that need to form the same blind or buried via and are adjacent to each other constitute a conductive layer group, and the conductive layers that do not need to form blind or buried vias and are adjacent to each other constitute a conductive layer group; each conductive layer group includes a core board with two conductive layers.
[0052] For example, referring to FIG2, a first conductive layer group 01 and a second conductive layer group 02 can be divided according to a schematic diagram of the film layers in a preset circuit diagram. The conductive layer groups (01, 02) may include multiple core boards 22, and the core board 22 includes a substrate layer 20 and conductive layers 10 located on both sides of the substrate layer. In addition, the conductive layer groups (01, 02) may also include a single conductive layer 11. In an optional embodiment, the conductive layer 10 may be a copper layer, and the single conductive layer 11 may be a copper foil.
[0053] In an optional embodiment, multiple conductive layer groups are set according to a preset circuit diagram, including: dividing the multiple conductive layer groups according to the preset circuit diagram, and forming a preset circuit in the conductive layer 10 located inside the conductive layer group. After forming the preset circuit, the surface of the circuit can also be browned to increase the bonding force between the conductive layer 10 and the adhesive layer 102 during subsequent lamination.
[0054] The preset circuits of different conductive layers 10 can be different. The conductive layers located on the surface of the conductive layer group (such as the first layer L1, the seventh layer L7, the eighth layer L8, and the eighteenth layer L18) may not form preset circuits temporarily in order to avoid damage to the preset circuits on the surface of the conductive layer group during the pressing process.
[0055] S1003. The conductive layers are stacked and an adhesive layer is placed between the core boards in the same group or between the core board and the conductive layer, and an auxiliary layer is placed between different and adjacent conductive layer groups.
[0056] For example, Figure 3 is a schematic diagram of a film layer structure with a stacked placement method provided in an embodiment of this application. As shown in Figure 3, an adhesive layer 102 is placed between each conductive layer structure (core plate 22, single conductive layer 11) in the same conductive layer group, and an auxiliary layer 30 is placed between different conductive layer groups.
[0057] The adhesive layer 102 can be a prepreg, also known as a PP sheet, which can soften and melt at high temperatures and solidify and bond adjacent film layers after cooling. The auxiliary layer 30 must be peelable and must not introduce contaminants during lamination and pressing. The auxiliary layer 30 includes copper foil, aluminum sheet, steel plate, copper-clad laminate, etc. The auxiliary layer 30 can be a clad metal material with a certain thickness, providing a certain degree of hardness during pressing, which helps reduce misalignment and warping after pressing.
[0058] S1004, The conductive layer, adhesive layer and auxiliary layer are laminated and stacked, and the auxiliary layer is peeled off after lamination so that the conductive layer assembly forms a sub-board.
[0059] Specifically, a suitable preset temperature can be selected based on the material of the adhesive layer 102 to heat the stacked conductive layer, adhesive layer, and auxiliary layer, and apply a certain pressure to cause the adhesive layer 102 to change from a solid state to a molten state, thus bonding adjacent film structures (core board 22, single-layer conductive layer 11). Note that no adhesive layer 102 is provided between different conductive layer groups, therefore, different conductive layer groups are not bonded together.
[0060] For example, Figure 4 is a schematic diagram of the film layer structure of a pressed sub-plate provided in an embodiment of this application. Referring to Figures 3 and 4, the first conductive layer group 01 can be pressed to form the first sub-plate 91, and the second conductive layer group 02 can be pressed to form the second sub-plate 92. Before pressing, an auxiliary layer 30 is placed between the first conductive layer group 01 and the second conductive layer group 02. On the one hand, this can prevent the first sub-plate 91 and the second sub-plate 92 formed after pressing from being tightly attached and difficult to separate. On the other hand, it can prevent the tensile force during the separation of the first sub-plate 91 and the second sub-plate 92 from damaging or bending the first sub-plate 91 and / or the second sub-plate 92, thus avoiding unnecessary losses.
[0061] In an optional embodiment, before the conductive layer, adhesive layer and auxiliary layer are stacked in the lamination layer, the conductive layers 10 in each conductive layer group can be fixed together by welding and riveting. For example, the conductive layers 10 of layers L1-L7 can be fixed together, and the conductive layers 10 of layers L8-L18 can be fixed together, so as to reduce film layer displacement during the lamination process.
[0062] S1005. Drill holes at a predetermined position on at least one sub-board to form through holes.
[0063] For example, continuing to refer to Figure 4, through holes can be formed in the sub-board by mechanical drilling, and then copper can be plated into the through holes, followed by resin plugging (not shown in Figure 4). After plugging, copper can be applied to the surface to prepare solder pads (not shown in Figure 4). After plugging, a preset circuit can also be formed on the conductive layer 10 (e.g., the seventh layer L7 and the eighth layer L8) partially located on the surface. After forming the preset circuit, the surface of the circuit can be browned to increase the bonding force between the conductive layer 10 and the adhesive layer 102 during subsequent lamination.
[0064] S1006. Stack the sub-boards and place an adhesive layer between different and adjacent sub-boards.
[0065] For example, Figure 5 is a schematic diagram of a film layer structure in another stacking method provided in the embodiment of this application. As shown in Figure 5, in the second stacking, an adhesive layer 102 needs to be placed between the sub-plates (91, 92) so that the first sub-plate 91 and the second sub-plate 92 can be bonded together after subsequent pressing.
[0066] S1007, Sub-plates and adhesive layers stacked together to form blind or buried vias.
[0067] For example, after the first sub-board 91 and the second sub-board 92 are pressed and bonded together, a preset circuit can be formed on the conductive layer 10 (e.g., the first layer L1 and the eighteenth layer L18) located on the surface.
[0068] It should be noted that the figure only shows, by way of example, that two conductive layer groups are required to form a high-precision circuit board. In other embodiments, the high-precision circuit board can also be formed by laminating three or more conductive layer groups to form multiple sub-boards, and then laminating them again after forming through holes in the sub-boards. When the sub-board in the middle position is provided with through holes, the buried holes of the high-precision circuit board can be formed after laminating again (not shown in the figure).
[0069] It should also be noted that the figure only shows an example of a high-precision circuit board including 18 conductive layers. In other embodiments, the high-precision circuit board may also include fewer or more than 18 conductive layers.
[0070] In an alternative embodiment, gold fingers may also be formed on the edges of one or both surfaces of the sub-boards before or after laminating them. These gold fingers can be properly aligned and connected to connectors of other devices or circuit boards.
[0071] In this embodiment, by pressing different conductive layer groups in the same process, the thickness of the plate in one pressing can be increased. It can also include some conductive layers that should be exposed on the outside during the pressing process (such as L7 and L8 in Figures 2-5) in the middle position of the film structure, which increases the uniformity of heating during the pressing process and makes the expansion and contraction generated during the pressing process easier to control, effectively reducing the layer deviation and warping caused by the pressing. In addition, pressing different conductive layer groups in the same process makes the consistency of the film expansion and contraction data of different conductive layer groups better, which is conducive to improving the alignment accuracy and simplifying the subsequent expansion and contraction adjustment process.
[0072] It should be noted that, taking Figures 2-5 as examples, during the lamination process, the outermost layers of the first conductive layer group 01 and the second conductive layer group 02 still have an asymmetrical structure with the topmost single-layer conductive layer 11 and the bottommost core board 22. However, through the high-precision circuit board preparation method provided in this application embodiment, the first conductive layer group 01 and the second conductive layer group 02 are laminated in the same process, which improves the heating uniformity of each film layer. This can effectively reduce the layer deviation and warpage of the bottommost core board 22 in the first conductive layer group 01, as well as the layer deviation and warpage of the topmost single-layer conductive layer 11 in the second conductive layer group 02. Laminating the first conductive layer group 01 and the second conductive layer group 02 in the same process improves the consistency of expansion and contraction of different conductive layer groups. It can also simplify or even omit the expansion and contraction adjustment of the bottommost core board 22 in the first conductive layer group 01 and the topmost single-layer conductive layer 11 in the second conductive layer group 02. This can effectively solve the technical problems of alignment and warpage caused by the asymmetrical structure when each conductive layer group is laminated separately. The embodiments of this application can effectively solve the manufacturing problems of AI server accelerator cards, thereby promoting the rapid development of AI server accelerator card technology in the future.
[0073] Optionally, Figure 6 is a schematic diagram of another layered structure provided in an embodiment of this application. As shown in Figure 6, each conductive layer group includes an even number of conductive layers 10, and each conductive layer group does not include a single conductive layer 11. Thus, each conductive layer group has a symmetrical structure, which is beneficial for balancing the stress of each film layer in the first conductive layer group 01 and the second conductive layer group 02 during the high temperature and high pressure pressing process, and is beneficial for further reducing layer misalignment and warping after pressing.
[0074] However, the case where each conductive layer group includes an even number of conductive layers 10 and no single conductive layer 11 is included is only applicable to special cases. In practical applications, at least some conductive layer groups include single conductive layers 11, and the problem of structural asymmetry of the conductive layer groups still needs to be considered.
[0075] Optionally, Figure 7 is a schematic diagram of a film layer structure with another stacked placement method provided in an embodiment of this application. As shown in Figure 7, the uppermost and lowermost conductive layer groups include an odd number of conductive layers 10; multiple conductive layer groups are set according to a preset circuit diagram, including: dividing multiple conductive layer groups according to the preset circuit diagram; wherein, in the uppermost and lowermost conductive layer groups, the side closer to the adjacent conductive layer group is a single conductive layer 11, and / or, in the uppermost and lowermost conductive layer groups, the side farther from the adjacent conductive layer group is a core board 22.
[0076] For example, when the conductive layer group includes an odd number of conductive layers 10, it is inevitable to set a single conductive layer 11 in the conductive layer group. In feasible implementations, the single conductive layer 11 can be set in a position close to other conductive layer groups. For example, the single conductive layer 11 can be set in the bottom layer of the uppermost first conductive layer group 01, and / or in the top layer of the lowermost second conductive layer group 02. Thus, when multiple conductive layer groups are pressed together in the same process, the single conductive layer 11 that is prone to layer misalignment and warping can be placed in the middle position, which is beneficial to improve the uniformity of heating and expansion and contraction of the single conductive layer 11 during the pressing process, thereby effectively reducing the layer misalignment and warping of the single conductive layer 11. In addition, when multiple conductive layer groups are pressed together in the same process, the top layer (first layer L1) and the bottom layer (eighteenth layer L18) are both core boards 22, making the top layer (first layer L1) and the bottom layer (eighteenth layer L18) symmetrical, which is beneficial to reduce the layer misalignment and warping of the top layer (first layer L1) and / or the bottom layer (eighteenth layer L18).
[0077] In feasible implementations, the single conductive layer 11 can also be disposed at a position away from other conductive layer groups. Figure 8 is a schematic diagram of a film layer structure with another stacking method provided in the embodiments of this application. As shown in Figure 8, the uppermost and lowermost conductive layer groups include an odd number of conductive layers 10. According to the preset circuit diagram, multiple conductive layer groups are set, including: dividing multiple conductive layer groups according to the preset circuit diagram; wherein, in the uppermost and lowermost conductive layer groups, the side away from the adjacent conductive layer group is a single conductive layer 11, and / or, in the uppermost and lowermost conductive layer groups, the side close to the adjacent conductive layer group is a core board 22.
[0078] For example, a single conductive layer 11 can be disposed as the topmost layer of the topmost first conductive layer group 01, and / or as the bottommost layer of the bottommost second conductive layer group 02. In this way, the topmost layer (first layer L1) and the bottommost layer (eighteenth layer L18) can be made symmetrical, which helps to reduce the layer offset and warping of the topmost layer (first layer L1) and / or the bottommost layer (eighteenth layer L18).
[0079] However, for different practical needs, during lamination, it may not be possible to make the topmost layer (first layer L1) and the bottommost layer (eighteenth layer L18) symmetrical. Figure 9 is a schematic diagram of a film layer structure with another stacking method provided in an embodiment of this application. As shown in Figure 9, the topmost and / or bottommost conductive layer group includes an odd number of conductive layers 10. According to the preset circuit diagram, multiple conductive layer groups are set, including: dividing multiple conductive layer groups according to the preset circuit diagram; wherein, one of the topmost layer in the topmost conductive layer group and the bottommost layer in the bottommost conductive layer group is a single conductive layer 11, and the other is a core board 22. The auxiliary layer 30 may include a single conductive layer 11. Before laminating multiple conductive layer groups at one time, in addition to placing the auxiliary layer 30 (i.e., single conductive layer 11) between different and adjacent conductive layer groups, the auxiliary layer 30 (i.e., single conductive layer 11) can also be placed above the topmost conductive layer group or below the bottommost conductive layer group, so that the upper and lower edge conductive layers 10 in all conductive layers 10 are single conductive layers 11.
[0080] For example, according to specific design requirements, the top layer of the combination of the first conductive layer group 01 and the second conductive layer group 02 must be a single-layer conductive layer 11, and the bottom layer must be a core board 22. In this case, the single-layer conductive layer 11 can be used as an auxiliary layer 30. When stacking the film layer structures, in addition to placing the auxiliary layer 30 (i.e., the single-layer conductive layer 11) between the conductive layer groups, the auxiliary layer 30 (i.e., the single-layer conductive layer 11) can also be placed below the bottommost conductive layer 10 (i.e., the eighteenth layer L18) of the second conductive layer group 02. In this way, the bottommost auxiliary layer 30 (i.e., the single-layer conductive layer 11) can simulate the symmetrical structure of the topmost layer (the first layer L1) to reduce layer misalignment and warping after lamination.
[0081] Optionally, the conductive layer includes a copper layer; the auxiliary layer includes at least one copper foil.
[0082] For example, one or more layers of copper foil can be placed between different conductive layer groups, with the thickness of a single copper foil layer ranging from 12µm to 70µm. Using copper foil as an auxiliary layer has two advantages: firstly, the material properties of copper foil make it easier to peel off after lamination; secondly, the copper foil of the conductive layer and the auxiliary layer on the surface of the conductive layer group has the same material, so even if peeling fails, it will not introduce impurities from other materials, which helps to improve product yield.
[0083] In an optional embodiment, the auxiliary layer includes two copper foils; placing the auxiliary layer between different and adjacent conductive layer groups includes: placing two copper foils between different and adjacent conductive layer groups, with the smooth side of the copper foil facing the adjacent conductive layer group and the rough side of the copper foil facing the inside of the auxiliary layer.
[0084] For example, Figure 10 is a schematic diagram of a film layer structure with another stacked placement method provided in an embodiment of this application. As shown in Figure 10, the smooth surface of the lower copper foil in the auxiliary layer 30 can face the uppermost conductive layer 10 (eighth layer L8) of the second conductive layer group 02, and the smooth surface of the upper copper foil in the auxiliary layer 30 can face the lowermost conductive layer 10 (seventh layer L7) of the first conductive layer group 01. In this way, during the pressing process, the rough surfaces of the two copper foils in the auxiliary layer 30 can adhere to each other, while the smooth surface of the copper foil can contact the conductive layer 10 of the conductive layer group (01 or 02), which is beneficial for subsequent peeling.
[0085] In addition, placing two layers of copper foil between adjacent conductive layer groups (01 and 02) helps to simulate the symmetrical structure of the conductive layer groups (01 and 02), thereby reducing layer misalignment and warping during the lamination process.
[0086] For example, continuing to refer to Figure 10, the uppermost layer of the first conductive layer group 01 is a single conductive layer 11, such as copper foil, while the lowermost layer of the first conductive layer group 01 is a core board 22. The first conductive layer group 01 has an asymmetrical structure. The lowermost layer of the second conductive layer group 02 is a single conductive layer 11, such as copper foil, while the uppermost layer of the second conductive layer group 02 is a core board 22. The second conductive layer group 02 also has an asymmetrical structure. By placing two layers of copper foil between the first conductive layer group 01 and the second conductive layer group 02, the upper copper foil in the auxiliary layer 30 can simulate the symmetrical structure of the uppermost copper foil in the first conductive layer group 01, and the lower copper foil in the auxiliary layer 30 can simulate the symmetrical structure of the lowermost copper foil in the second conductive layer group 02. During the pressing process, the copper foil in the first conductive layer group 01 and the upper copper foil in the auxiliary layer 30 form a symmetrical structure, and the copper foil in the second conductive layer group 02 and the lower copper foil in the auxiliary layer 30 form a symmetrical structure. During the high temperature and high pressure pressing process, it is beneficial to balance the stress of each film layer in the first conductive layer group 01 and the second conductive layer group 02, and to further reduce the layer deviation and warping after pressing.
[0087] In another alternative embodiment, the auxiliary layer includes two copper foils and an adhesive layer located between the two copper foils.
[0088] For example, Figure 11 is a schematic diagram of a film layer structure with another stacked placement method provided in an embodiment of this application. As shown in Figure 11, two copper foils and an adhesive layer located between the two copper foils are placed between adjacent conductive layer groups. The number of adhesive layers can be set according to actual needs. An adhesive layer 102 is provided in the auxiliary layer 30. Utilizing the properties of the adhesive layer to soften and melt at high temperatures, it can buffer the bonding between the conductive layer 10 and the adhesive layer 102 in the conductive layer group during the pressing process. This is beneficial for the adhesive layer 102 to fill the line gaps of the conductive layer 10, improving the coating effect. It is especially suitable for cases where the conductive layer 10 in the conductive layer group is relatively thick, avoiding the situation where the adhesive layer 102 cannot fill the gaps due to the thickness of the conductive layer 10 in the conductive layer group, and can only contact the surface of the conductive layer 10. This can effectively solve the problem of easy delamination of the conductive layer 10 in the conductive layer group.
[0089] Based on the same application concept, this application also provides a high-precision circuit board. The high-precision circuit board provided in the embodiments of this application can be prepared by the preparation method of the high-precision circuit board provided in any embodiment of this application. Therefore, the high-precision circuit board provided in the embodiments of this application also has the beneficial effects of the preparation method of the high-precision circuit board provided in the embodiments of this application. The contents not described in detail in this embodiment can be referred to the above description of the preparation method of the high-precision circuit board, and will not be repeated here.
Claims
1. A method for manufacturing a high-precision circuit board, wherein the high-precision circuit board includes at least one blind via or buried via; The preparation method includes: Obtain the preset circuit diagram of the high-precision circuit board; According to the preset circuit diagram, multiple conductive layer groups are set; wherein, a conductive layer group consists of adjacent conductive layers that need to form the same blind via or buried via, and a conductive layer group consists of adjacent conductive layers that do not need to form the same blind via or buried via; each conductive layer group includes a core board with two conductive layers. Each of the conductive layers is stacked, and an adhesive layer is placed between the core plates in the same group or between the core plate and the conductive layer, and an auxiliary layer is placed between different and adjacent groups of conductive layers; The conductive layer, the adhesive layer, and the auxiliary layer are laminated together, and the auxiliary layer is peeled off after lamination, so that the conductive layer assembly forms a sub-board; Drill holes at at least one predetermined position on the sub-board to form through holes; The sub-boards are stacked, and the adhesive layer is placed between different and adjacent sub-boards; The sub-plate and the adhesive layer are laminated together to form the through hole as the blind hole or the buried hole.
2. The method for manufacturing a high-precision circuit board according to claim 1, wherein, At least a portion of the conductive layer group comprises a single conductive layer.
3. The method for preparing a high-precision circuit board according to claim 2, wherein, The topmost and bottommost conductive layer groups comprise an odd number of the conductive layers; According to the preset circuit diagram, multiple conductive layer groups are set, including: According to the preset circuit diagram, multiple conductive layer groups are divided; wherein, in the uppermost and lowermost conductive layer groups, the side closest to the adjacent conductive layer group is the single conductive layer, and / or, in the uppermost and lowermost conductive layer groups, the side furthest from the adjacent conductive layer group is the core board.
4. The method for manufacturing a high-precision circuit board according to claim 2, wherein, The topmost and bottommost conductive layer groups comprise an odd number of the conductive layers; According to the preset circuit diagram, multiple conductive layer groups are set, including: According to the preset circuit diagram, multiple conductive layer groups are divided; wherein, in the uppermost and lowermost conductive layer groups, the side away from the adjacent conductive layer group is the single conductive layer, and / or, in the uppermost and lowermost conductive layer groups, the side closer to the adjacent conductive layer group is the core board.
5. The method for manufacturing a high-precision circuit board according to claim 2, wherein, The auxiliary layer includes the single-layer conductive layer; The uppermost and / or lowermost conductive layer group comprises an odd number of the conductive layers; According to the preset circuit diagram, multiple conductive layer groups are set, including: According to the preset circuit diagram, multiple conductive layer groups are divided; wherein, the topmost layer in the topmost conductive layer group and the bottommost layer in the bottommost conductive layer group are either the single-layer conductive layer or the core board. The conductive layers are stacked, and an adhesive layer is placed between the core plates in the same group or between the core plate and the conductive layer, and an auxiliary layer is placed between different but adjacent groups of conductive layers, including: The conductive layers are stacked, and an adhesive layer is placed between the core plates in the same group or between the core plate and the conductive layer. The auxiliary layer is placed between different and adjacent conductive layer groups. The auxiliary layer is also placed above the uppermost conductive layer group or below the lowermost conductive layer group, so that the upper and lower edge conductive layers of all the conductive layers are single-layer conductive layers.
6. The method for manufacturing a high-precision circuit board according to claim 1, wherein, The conductive layer includes a copper layer; the auxiliary layer includes at least one copper foil.
7. The method for manufacturing a high-precision circuit board according to claim 6, wherein, The auxiliary layer comprises two layers of copper foil; An auxiliary layer is placed between different but adjacent conductive layer groups, including: Two copper layers are placed between different but adjacent conductive layer groups, with the smooth side of the copper foil facing the adjacent conductive layer group and the rough side of the copper foil facing the inside of the auxiliary layer.
8. The method for manufacturing a high-precision circuit board according to claim 6, wherein, The auxiliary layer comprises two layers of copper foil and an adhesive layer located between the two layers of copper foil.
9. The method for manufacturing a high-precision circuit board according to any one of claims 6-8, wherein, The thickness of the copper foil is d; where 12um≤d≤70um.
10. A high-precision circuit board, manufactured using the method for preparing a high-precision circuit board as described in any one of claims 1-9.