Method, apparatus and system for driving a transistor

Abstract

A method, apparatus, and system for driving a transistor are described. The exemplary apparatus includes a regulator (505) including a first input terminal (522) adapted to be coupled to a control terminal (172) of a transistor (150), a first output terminal (524), and a second output terminal (528), a first stage (510) including a first input terminal (530) coupled to the first output terminal of the regulator and an output terminal (534) adapted to be coupled to the control terminal of the transistor, and a second stage (515) including an input terminal (536) coupled to the second output terminal of the regulator and an output terminal (538) adapted to be coupled to the control terminal of the transistor.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION This description relates generally to transistors, and more particularly to methods, apparatus, and systems for driving transistors. [Background technology]

[0002] In some applications, a transistor, such as a field effect transistor (FET) or a metal oxide semiconductor field effect transistor (MOSFET), is connected to a load through an inductor. The transistor can be controlled to provide current to the load using a pulse width modulated (PWM) signal provided to the gate of the transistor. [Brief explanation of the drawings]

[0003] [Figure 1] 1 is a schematic diagram of an example power converter including a first example driver and a second example driver.

[0004] [Figure 2] FIG. 2 is a first schematic diagram of a first driver of a power converter.

[0005] [Figure 3] FIG. 10 is a second schematic diagram of a second driver of a power converter.

[0006] [Figure 4] FIG. 10 is a third schematic diagram of a third driver of a power converter.

[0007] [Figure 5] 2 is a block diagram of an example implementation of the first driver of FIG. 1 adapted to enable a transistor in response to an input signal at an input terminal.

[0008] [Figure 6] FIG. 6 is a diagram of an example implementation of the first driver of FIG. 1 and / or FIG. 5.

[0009] [Figure 7A] 7 is a diagram of an example implementation of the first driver of FIGS. 1, 5, and / or 6, including additional logic circuit elements relative to the implementation shown in FIG. 6. [Figure 7B] 7 is a diagram of an example implementation of the first driver of FIGS. 1, 5, and / or 6, including additional logic circuit elements relative to the implementation shown in FIG. 6.

[0010] [Figure 8] 7 is a diagram of an example implementation of the first driver of FIGS. 1, 5, and / or 6, including additional logic circuit elements relative to the implementation shown in FIG. 6.

[0011] [Figure 9] 1 is a flowchart illustrating an example process that may be implemented using executable logic or machine-readable instructions to implement an example driver.

[0012] [Figure 10] FIG. 2 is a schematic diagram of an example simulation bench for a driver in an example power converter.

[0013] [Figure 11] 1 is a signal plot illustrating a first current signal of a first transistor enabled by a first driver and a second current signal of a second transistor enabled by a second driver at various voltage offsets in a power conversion system.

[0014] [Figure 12] 1 is a signal plot illustrating a first slew rate of a transistor enabled by a first driver and a second slew rate of a transistor enabled by a second driver at various voltage offsets in a power conversion system.

[0015] [Figure 13]1 is a signal plot showing a first current signal of a transistor enabled by a first driver and a second current signal of a second transistor enabled by a second driver at various driver resistances in a power conversion system.

[0016] [Figure 14] 1 is a signal plot illustrating a first slew rate of a transistor enabled by a first driver and a second slew rate of a transistor enabled by a second driver at various driver resistances in a power conversion system.

[0017] [Figure 15] 2 is a signal plot illustrating control and output signals of the example power converter of FIG. 1 during operation to drive a transistor. DETAILED DESCRIPTION OF THE INVENTION

[0018] The drawings are not to scale. Generally, the same reference numerals are used to refer to the same or similar parts throughout the drawings and accompanying documents. As used herein, connection references (e.g., attached, coupled, connected, and joined) should be interpreted in light of the specification and, where relevant, the surrounding claim language. The interpretation of connection references herein should be consistent with the claim language and the context of the specification that describes the purpose for which various elements are connected. Thus, a connection reference does not necessarily imply that two elements are directly connected and in fixed relationship to each other.

[0019] When identifying multiple elements or components that may be referred to individually, the present application uses descriptors such as first, second, third, etc. Unless otherwise specified or understood based on the context of their use, such descriptors do not imply any sense of priority, physical order or placement in a list, or chronological order, but are merely used as labels to individually refer to multiple elements or components to facilitate understanding of the examples being described. In some instances, the descriptor "first" may be used to refer to an element in the detailed description, while the same element may be referred to in the claims using a different descriptor, such as "second" or "third." In such instances, such descriptors are used merely to facilitate referring to multiple elements or components.

[0020] Some examples described herein include methods, devices, and systems for driving transistors with a controlled slew rate. Transistors are used, for example, in power conversion circuits, electrical or power adapters, electric vehicle charging units, and electric vehicle components (e.g., battery charging circuits, traction inverters, etc.). A signal (e.g., voltage and / or current) can be applied to a transistor gate (e.g., control terminal) so that another signal can pass through another pair of transistor terminals (e.g., from the transistor's source terminal to the drain terminal). Power conversion circuits, or power converters, are used in applications that can benefit from a reliable power source. The power converter can be a step-up converter (e.g., a boost converter that produces an output voltage greater than the input voltage), a step-down converter (e.g., a buck converter that produces an output voltage less than the input voltage), etc., and / or a combination thereof.

[0021] For a power converter to be an efficient and reliable source of power, the currents flowing through various portions of the power converter circuit (e.g., inductor current, transistor current, load current, etc.) are regulated by a controller to turn switches on and / or off. The controller monitors these currents to regulate the output voltage, thus providing a reliable power source. For example, to ensure that the output voltage is within a desired range, the controller may regulate the load current by regulating the current through an inductor. The controller regulates the current through the inductor, which in turn varies the operation of the transistor, thereby regulating the output voltage.

[0022] The transistors may be controlled by a driver (e.g., a driver circuit). The driver or driver circuit may enable (e.g., turn on) and disable (e.g., turn off) the transistors in response to a PWM signal generated by a controller (e.g., a control circuit). Examples of drivers (e.g., driver circuits) as described herein include one or more transistors, such as FETs, MOSFETs, or any other switching devices, such as bipolar junction transistors (BJTs). However, other switch types or technologies may be used.

[0023] The drivers may be configured with a controller for enabling and disabling the transistors, and a power conversion circuit including such drivers may switch between high-side control using a first driver (e.g., enabling the first transistor and disabling the second transistor) and low-side control using a second driver (e.g., disabling the first transistor and enabling the second transistor) to provide a substantially stable or otherwise regulated output voltage.

[0024] In some applications (e.g., power conversion circuits, power conversion systems, etc.), the voltage at the gate of a transistor (e.g., gate voltage) may remain on (e.g., in linear mode) for an extended period of time to ensure reliable operation of the transistor while not exceeding a voltage threshold. Some transistors may exceed normal operating conditions when the gate voltage exceeds a normal operating voltage (e.g., 6 volts, 7 volts, etc.) for a short period of time. A transistor operating under normal operating conditions may have a slew rate. As used herein, the term "slew rate" and its variations encompass the change in an electrical quantity of a signal (e.g., voltage or current) per unit time. For example, when a transistor is enabled by a driver, the change in voltage at the drain terminal of the transistor has a slew rate (e.g., 20 volts per nanosecond, 100 volts per nanosecond, etc.). The slew rate of a transistor may adjust the rate at which a signal at a transistor terminal changes to a desired value (e.g., the rate at which the transistor is enabled and begins to conduct).

[0025] The slew rate of a transistor can be affected by a signal (e.g., current, voltage, etc.) provided to a control terminal of the transistor. For example, a higher current at the gate of a transistor can correspond to a higher slew rate of the transistor, and a higher slew rate can correspond to a faster change in a signal at a terminal of the transistor. Therefore, applications such as power converter circuitry can benefit from a relatively fast, controlled slew rate of a transistor. In some examples, a transistor with a maximum rated voltage (e.g., 6 volts, 7 volts, etc.) can transition from an off state (e.g., a cutoff mode in which no signal flows between the two transistor terminals) to an on state (e.g., a linear mode in which a signal flows between the two terminals) using a signal that exceeds the maximum rated voltage. During the transistor's transition to the on state, the slew rate of the signal at the two terminals can be controlled to a greater extent because the signal for activating the transistor exceeds the maximum rated voltage. For example, if a transistor includes a maximum rated voltage of 6 volts and a 12 volt signal is applied to the transistor gate until the transistor reaches linear mode, the slew rate of the transistor can be greater than the slew rate of a transistor enabled with a 6 volt signal. In some examples, to drive the transistor through a transition period, the control terminal of the transistor is driven above its rated voltage (e.g., a driver holds the transistor's gate terminal at a voltage) for a relatively short period of time (such as tens of nanoseconds) so that the transistor is not likely to degrade and / or experience reduced reliability. Also, to allow for higher slew rates for the transistor and to prevent damage to the transistor that may occur from enabling a transistor sourced by a 12 volt voltage source, the voltage at the transistor gate may be regulated (e.g., maintained between 6 volts and 12 volts, held at an 8 volt clamp voltage, etc.).

[0026] Some examples described herein include transistors fabricated using gallium nitride (GaN). Some examples described herein also include using GaN transistors and methods, apparatus, and systems for driving transistors with a controlled slew rate. Some examples described herein include the ability to drive a transistor (e.g., at a transistor gate) with a current to set the transistor's slew rate, which may be enabled by a higher headroom (e.g., a voltage of 12 volts at the gate terminal) than the on-state headroom (e.g., a maximum rated voltage of 6 volts at the gate terminal) to prevent damage to the transistor. Some examples described herein include driving the gate terminal with a constant current source based on a voltage level that exceeds the normal operating voltage level while the transistor is in the on-state. Some examples described herein include clamping (e.g., regulating) a higher gate signal to protect the transistor from stress during the transistor's transition to the on-state. For example, the driver may include a regulator for enabling and / or disabling a control signal (e.g., a current signal) provided to the gate terminal in response to the voltage at the gate terminal exceeding a clamp voltage (e.g., 8 volts). Some examples described herein include a relatively weak pull-up transistor to hold the transistor's gate signal at a maximum rated voltage (e.g., 6 volts) to prevent stress on the transistor after it is enabled by the current source. In some examples described herein, the gate drive current and / or the current provided by the driver to the gate terminal is programmable over a wide range.

[0027] In some examples, a regulator may provide a first trigger signal to a first stage in a driver to enable the transistor with a current provided by a first voltage supply node. In response to the signal at the control terminal of the transistor exceeding a threshold voltage value, the regulator may disable the first stage after a delay and provide a second trigger signal to a second stage in the driver to enable the transistor (e.g., remain in an on state) with a current provided by a second voltage supply node. The first voltage supply node may include a potential (e.g., a potential, such as 12 volts) greater than a potential (e.g., 6 volts, 7 volts, etc.) of the second voltage supply node.

[0028] 1 is a schematic diagram of an example power converter 100 including a first example driver 105 and a second example driver 110. Power converter 100 includes first driver 105, second driver 110, a controller 120, and an inverter 125. Power converter 100 is adapted to be coupled to an example bus voltage node 140, an example ground node 145, and an example load 146. In the topology of FIG. 1, power converter 100 is adapted and / or otherwise configured to drive load 146 (e.g., to power load 146 and / or to provide an output signal to load 146). For example, load 146 may correspond to an electric vehicle, one or more batteries in the electric vehicle, an electronic control unit (ECU), an electric motor in the electric vehicle, a traction inverter included in the electric vehicle, etc., and / or combinations thereof. Power converter 100 includes an example capacitor 147 , an example inductor 148 , a first example transistor 150 , and a second example transistor 151 .

[0029] The controller 120 has an output coupled to an exemplary output terminal 154. The first driver 105 has a first input coupled to an exemplary input terminal 156. The input terminal 156 is coupled to the output terminal 154 in a configuration for receiving an activation signal (IN) from the controller 120. The first driver 105 has a first output coupled to an exemplary output terminal 158. The second driver 110 has a second input coupled to an exemplary input terminal 160. The input terminal 160 is coupled to the output of the inverter 125 in a configuration for receiving an inverted activation signal (nIN). The second driver 110 has a second output coupled to an exemplary output terminal 162. The first transistor 150 has a control terminal 172 (e.g., gate terminal) coupled to the output terminal 158, a source terminal 174 (e.g., first current terminal) coupled to the ground node 145, and a drain terminal 176 (e.g., second current terminal) coupled to the inductor 148 for transitioning to an on state in response to receiving one or more control signals from the first driver 105. The second transistor 151 has a control terminal 186 coupled to the output terminal 162 of the second driver 110, a source terminal 188 coupled to the inductor 148, and a drain terminal 190 coupled to the bus voltage node 140. In the topology of FIG. 1, the bus voltage node 140 provides a voltage signal (such as the signal V).

[0030] Inverter 125 is coupled between output terminal 154 and input terminal 160 of second driver 110. Inductor 148 is coupled to source terminal 188 of second transistor 151 and to drain terminal 176 of first transistor 150. Capacitor 147 is coupled between inductor 148 and ground node 145. Load 146 (e.g., an electronic device to be powered, industrial end equipment, etc.) is coupled between inductor 148 and ground node 145.

[0031] 1, first driver 105 controls the conduction state (e.g., conducting or non-conducting) of first transistor 150, and second driver 110 controls the conduction state of second transistor 151. However, drivers 105, 110 may control the conduction state of any number of transistors or switches. Also, any number of drivers may control the conduction state of a transistor. For example, first driver 105 can transition first transistor 150 from a non-conducting state to a conducting state, and second driver 105 is coupled to control terminal 172 and can transition first transistor 150 from a conducting state to a non-conducting state.

[0032] The first transistor 150 is an N-channel metal-oxide-semiconductor (NMOS) field-effect transistor. Alternatively, the first transistor 150 may be a P-channel metal-oxide-semiconductor (PMOS) field-effect transistor, a bipolar junction transistor (BJT), or any other three-terminal device. Similarly, the second transistor 151 is an NMOS field-effect transistor. Alternatively, the second transistor 151 may be a PMOS field-effect transistor, a BJT, or any other three-terminal device. As used herein, the term "NMOS transistor" and variations thereof include NMOS field-effect transistors (FETs), GaN transistors, silicon carbide (SiC) transistors, etc. Similarly, as used herein, the term "PMOS transistor" and variations thereof include PMOS field-effect transistors, GaN transistors, SiC transistors, etc.

[0033] In operation, controller 120 generates an activation signal (e.g., a PWM signal, a voltage signal IN, etc.) at output terminal 154. Controller 120 regulates the load voltage of the power converter at load 146. In some examples, controller 120 regulates the load voltage to maintain a maximum or minimum allowable voltage, regulate the load current, and / or limit the maximum positive and / or minimum negative current of inductor 148 to avoid damage to load 146 and / or to power converter 100 more generally. Controller 120 also controls the conduction state (e.g., conductive or non-conductive) of first transistor 150 and second transistor 151 by providing activation signals (IN) to drivers 105, 110. Controller 120 may be implemented using a hardware-implemented state machine, a microcontroller, multiple discrete components, or any other suitable device.

[0034] Inverter 125 generates an inverted signal (e.g., voltage signal nIN) in response to a variation in the control signal provided by controller 120. As used herein, an inverter (e.g., inverter 125) includes control circuitry for responding to an activation signal and for providing (e.g., outputting) the inverted signal to second driver 110. For example, if controller 120 generates an activation signal (IN) voltage of 5 volts at the input terminal of inverter 125, inverter 125 may provide an activation signal (nIN) voltage of 0 volts to second driver 110.

[0035] In some examples, other components, such as level-shifting circuitry or a digital buffer, may be coupled to the output terminal 154 of the controller 120 and / or the input terminal of the first driver 105 or the second driver 110. For example, level-shifting circuitry may be coupled to the output terminal 154 of the controller 120 to shift the voltage of a control signal (such as signal IN) to a higher voltage swing. In some examples, an inverter 125 may additionally or alternatively be coupled to the input terminal 156 of the first driver 105.

[0036] Any other method for providing a signal (e.g., an activation signal, signal IN, etc.) at input terminal 156 of first driver 105 and / or input terminal 160 of second driver 110 may additionally or alternatively be used. For example, controller 120 may include control circuitry (such as an inverter) for producing an activation signal (such as signal IN or signal nIN), and controller 120 may include a first output terminal to be coupled to input terminal 156 and a second output terminal to be coupled to input terminal 160.

[0037] In some examples described herein, the first driver 105 and the second driver 110 respond to variations in an activation signal (IN) generated by the controller 120 to enable and / or disable a transistor (such as the first transistor 150 or the second transistor 151). In some examples, when the first driver 105 disables the first transistor 150, the second driver 110 enables the second transistor 151, and when the second driver 110 disables the second transistor 151, the first driver 105 enables the first transistor 150. The drivers 105, 110 may be configured to enable and / or disable the transistors 150, 151 to regulate a power signal (e.g., a current through the inductor 148) provided to the load 146.

[0038] The first driver 105 responds to variations in the activation signal obtained at the input terminal 156 by providing at least one control signal to the first transistor 150. In some examples described herein, the first driver 105 provides (e.g., carry, output, transmit, etc.) a first control signal to transition the first transistor 150 from a non-conductive state to a conductive state and a second control signal for the first transistor 150 to remain in a conductive state. Similarly, the second driver 110 responds to variations in the activation signal modified by the inverter 125 (e.g., signal nIN) by providing at least one control signal to the second transistor 151.

[0039] In some examples, first driver 105 and / or second driver 110 include a first stage and a second stage driven by different voltage levels to enable transistors 150, 151. For example, first driver 105 may include a first stage adapted to be coupled to a 12-volt source and a second stage adapted to be coupled to a 6-volt source. First driver 105 may include a regulator to enable the first stage, which may provide a gate drive current to control terminal 172 sourced by the 12-volt source. The regulator may then disable the first stage and enable the second stage, which may provide a gate drive current to control terminal 172 sourced by the 6-volt source. Additionally or alternatively, any number of control signals may be provided to either of transistors 150, 151 by either of drivers 105, 110. For example, the first driver 105 may provide a third control signal to the first transistor 150 to transition the first transistor 150 from a conducting state to a non-conducting state.

[0040] In the illustrated example of FIG. 1 , first driver 105 responds to an activation signal exceeding a threshold voltage level (e.g., a logic high level, a voltage corresponding to a logic “1,” etc.) by enabling first transistor 150. In some examples, first driver 105 disables first transistor 150 when signal n does not exceed the threshold voltage level. Similarly, second driver 110 responds to fluctuations in the signal at input terminal 160. Second driver 110 responds to the signal provided by inverter 125 by enabling second transistor 151 in response to signal n exceeding the threshold voltage level. In some examples, second driver 110 disables second transistor 151 when signal n does not exceed the threshold voltage level. In some examples, power converter 100 may include two or more drivers and / or two or more transistors to regulate the power signal provided to load 146.

[0041] Ground node 145 provides a reference voltage (e.g., 0 volts) for power converter 100. In some examples, ground node 145 may be coupled to earth ground, digital ground, or analog ground. In other examples, ground node 145 may be coupled to the source node voltage to provide a reference voltage (such as 1 volt).

[0042] Inductor 148 is a two-terminal electrical component that stores energy in a magnetic field when current flows through that magnetic field. During high-stage operation, when second transistor 151 is conducting (e.g., enabled) and first transistor 150 is not conducting (e.g., disabled), energy is stored in inductor 148. During low-stage operation, when first transistor 150 is conducting and second transistor 151 is not conducting, energy is discharged from inductor 148 through first transistor 150 to ground.

[0043] Capacitor 147 is a two-terminal electrical component that stores energy in an electric field. During high-stage operation, when second transistor 151 is conducting and first transistor 150 is not conducting, energy is stored in capacitor 147. During low-stage operation (e.g., while first transistor 150 is conducting), energy is discharged from capacitor 147 to load 146.

[0044] 2 is a first schematic diagram 200 of a driver 205 in a power converter. The first schematic diagram 200 includes a driver 205, a first transistor 210, a first voltage supply node 215, a second voltage supply node 220, a third voltage supply node 225, and a ground node 230. The driver 205 includes an inverting level shifter 235, a second transistor 240, an inverter driver 245, and a third transistor 250. The first transistor 210 is an NMOS transistor, the second transistor 240 is a PMOS transistor, and the third transistor 250 is an NMOS transistor. The first transistor includes a control terminal 260 and a source terminal 262. The source terminal 262 is coupled to the ground node 230.

[0045] Inverter driver 245 inverts signal IN and delivers the inverted voltage signal to second transistor 240. Inverter driver 245 provides a 0 volt signal when the voltage of signal IN is 5 volts. Inverter driver 245 provides a 5 volt signal when the voltage of signal IN is 0 volts. Inverter driver 245 enables and disables third transistor 250 in response to variations in signal IN.

[0046] During the on state (e.g., signal IN has a voltage of 5 volts), second transistor 240 is enabled (e.g., conducting) and third transistor 250 is disabled (e.g., not conducting). As a result, first transistor 210 is enabled during the on state. During the off state (e.g., signal IN has a voltage of 0 volts), second transistor 240 is disabled and third transistor 250 is enabled. As a result, first transistor 210 is disabled during the off state.

[0047] 2 is configured to deliver a control signal to a first transistor 210 that is sourced by a first voltage supply node 215 (e.g., sourced by a voltage of VDRV, 6 volts). Also, in the circuit of FIG. 2, the PMOS pullup (e.g., second transistor 240) has a large, and therefore inefficient, die area. Because the driver 205 is powered by VDRV (e.g., 6 volts), the gate of the first transistor 210 (e.g., the voltage at control terminal 260) reaches the maximum voltage of VDRV (e.g., 6 volts).

[0048] An exemplary equation for calculating headroom when driving a transistor is shown in Equation 1 below. HEADROOM=VDRV-V gs formula 1 In the example of Equation 1, HEADROOM represents the headroom (e.g., threshold voltage) of a control terminal (e.g., control terminal 260) at which a transistor (e.g., transistor 210) has a limited slew rate, VDRV represents the voltage at first voltage supply node 215 (e.g., VDRV, 6 volts, etc.), and V gsrepresents the difference between the voltage at the gate terminal (e.g., control terminal 260) and the voltage at the source terminal (e.g., source terminal 262). As used herein and as shown in Equation 1 above, the phrase "transistor headroom" or variations thereof encompasses the difference between (1) the voltage driving the transistor (e.g., VDRV) and (2) the difference between the gate terminal voltage and the source terminal voltage. In some examples, a larger voltage driving the transistor, such as 12 volts compared to 6 volts, allows for a larger transistor headroom and therefore allows the transistor to turn on at a larger slew rate. In some examples, the transistor headroom controls the current (e.g., gate current, gate drive current, output current, etc.) that the driver can provide when driving (e.g., transitioning) the transistor to an enabled state. Therefore, the driver headroom controls the slew rate of the transistor as it transitions to an enabled state. In some examples, such as those described below in connection with Figures 5-8, a first transistor may be enabled by a first voltage source (e.g., 12 volts) at a control terminal, and a second transistor may be enabled by a second voltage source (e.g., 6 volts) at a control terminal. Because the first transistor is powered by the first voltage source at a larger potential than the second transistor at the control terminal, the first transistor includes a larger headroom than the headroom of the second transistor. Therefore, the slew rate of the first transistor may be greater than the slew rate of the second transistor while transitioning to an enabled state.

[0049] 2, driver 205 provides a control signal (e.g., a current signal) to transistor 210 that is sourced by a voltage (VDRV) provided by first voltage supply node 215, which is the maximum rated voltage of transistor 210, such as 6 volts. As such, the gate of second transistor 210 is limited to VDRV while transitioning to an enabled state, thus limiting the slew rate of second transistor 210. Also, in the example of FIG. 2, the area of ​​transistor 240 may be larger, and therefore inefficient, in terms of die area than the topologies of FIGS. 3, 4, and / or 8, as described below.

[0050] 3 is a second schematic diagram 300 of a driver 305 in a power converter. The second schematic diagram 300 includes a driver 305, a first transistor 310, a first voltage supply node 315, a second voltage supply node 320, a third voltage supply node 325, and a ground node 330. The driver 305 includes an inverting level shifter 335, a buffer 340, a second transistor 342, a first inverter 344, a third transistor 346, a fourth transistor 348, a second inverter 350, and a fifth transistor 352. The first transistor 310 is an NMOS transistor, the second transistor 342 is a PMOS transistor, the third transistor 346 is an NMOS transistor, the fourth transistor 348 is an NMOS transistor, and the fifth transistor 352 is an NMOS transistor. The first transistor 310 includes a control terminal 353 .

[0051] The inverting level shifter 335 amplifies the signal IN, inverts the shifted voltage signal, and provides the inverted voltage signal to the buffer 340. The buffer 340 removes glitches (e.g., unwanted signal transitions) from the inverted voltage signal obtained from the inverting level shifter 335 and provides the voltage signal to a coupled component (e.g., a second transistor 342) at an output impedance level lower than the output impedance level of the buffer 340. The inverting level shifter 335 and the buffer 340 enable and disable the second transistor 342 in response to fluctuations in the signal IN. The first inverter 344 inverts the voltage signal (e.g., the voltage signal IN) and provides the inverted voltage signal to the third transistor 346. The first inverter 344 enables and disables the third transistor 346 in response to fluctuations in the signal IN. The second transistor 342 and the third transistor 346 enable and disable the fourth transistor 348 in response to variations in the signal provided by the buffer 340 and by the first inverter 344 .

[0052] The second inverter 350 inverts a voltage signal (e.g., signal IN) and provides the inverted voltage signal to the fifth transistor 352. The second inverter 350 enables and disables the fifth transistor 352 in response to variations in the signal IN. During an on state (e.g., signal IN has a voltage of 5 volts), the second transistor 342 is conductive and the third transistor 346 is not conductive. As a result, the fourth transistor 348 is conductive and the fifth transistor 352 is not conductive. As a result of the fourth transistor 348 being conductive and the fifth transistor 352 not conducting, the first transistor 310 is conductive.

[0053] During the off state (e.g., signal IN has a voltage of 0 volts), second transistor 342 is not conducting and third transistor 346 is conducting. As a result, fourth transistor 348 is not conducting and fifth transistor 352 is conducting. As a result of fourth transistor 348 not conducting and fifth transistor 352 conducting, first transistor 310 is not conducting.

[0054] 3 enables a first transistor 310 via a first voltage supply node 315 (e.g., sourced by VDRV). Therefore, the voltage at the gate of the first transistor 310 (e.g., the maximum voltage at the gate) is limited by the voltage signal VDRV, and therefore the slew rate of the first transistor 310 is limited.

[0055] In the example of FIG. 3 , the driver 305 provides a control signal (e.g., a current signal) to the first transistor 310 that is sourced by a voltage (VDRV) provided by a first voltage supply node 315, which is the maximum rated voltage of the first transistor 310, such as 6 volts. As such, the gate of the first transistor 310 is limited to VDRV while transitioning to an enabled state, and therefore the slew rate of the transistor is limited. Also in the example of FIG. 3 , the control terminals of the transistors 310, 348 are limited to VDRV. As such, the drive current provided to the first transistor 310 may decrease as the control terminal of the first transistor 310 increases. When the first transistor 310 provides a large current, the voltage (V) across the first transistor 310 increases. gs ) will be higher due to this large current, so the slew rate of the first transistor 310 may be limited.

[0056] 4 is a third schematic diagram 400 of a driver 402 in a power converter. The driver 402 is adapted to receive an input signal (e.g., a voltage signal IN), and the driver 402 enables and disables a first transistor 404 in response to variations in the signal IN. The driver 402 includes a one-shot pulse generator 412, a first buffer 414, a second transistor 416, a second buffer 418, a third transistor 420, a current source 422, a first current mirror circuit 424, and a second current mirror circuit 426. The third schematic diagram 400 includes a first voltage supply node 428, a second voltage supply node 430, and a ground node 432. The first transistor 404 and the third transistor 420 are NMOS transistors, and the second transistor 416 is a PMOS transistor. The first transistor 404 includes a control terminal 436 , a drain terminal 438 , and a source terminal 440 coupled to the ground node 432 .

[0057] The one-shot pulse generator 412 and the first buffer 414 enable and disable the second transistor 416 in response to fluctuations in the signal IN. The second transistor 416 enables the first transistor 404. When the signal IN transitions to an on state (e.g., transitions from a voltage of 0 volts to a voltage of 5 volts), the one-shot pulse generator 412 generates a pulse signal. The first buffer 414 receives the pulse signal, modifies it (e.g., removes glitches from it), and conveys the modified pulse signal to the second transistor 416. In response to the modified pulse signal, the second transistor 416 is disabled (e.g., does not begin to conduct). When the second transistor 416 is not conducting, the first transistor 404 may be conducting (e.g., may be enabled by the second current mirror circuit 426, as described below) or may not be conducting (e.g., may not be enabled by the second current mirror circuit 426).

[0058] The first current mirror circuit 424 includes a first terminal 454 coupled to the third transistor 420 and a second terminal 456. The second current mirror circuit 426 includes a first terminal 458 coupled to the second terminal 456 of the first current mirror circuit 424. The second current mirror circuit 426 includes a second terminal 460 coupled to the first transistor 404. In operation, when the signal IN transitions to an on state (e.g., transitions from a voltage of 0 volts to a voltage of 5 volts), the one-shot pulse generator 412 generates a pulse signal. The second buffer 418 obtains the pulse signal, modifies the pulse signal (e.g., removes glitches from the pulse signal), and provides the modified pulse signal to the third transistor 420. As a result, the third transistor 420 is enabled (e.g., begins conducting) in response to obtaining the modified pulse signal.

[0059] When the third transistor 420 is enabled, the current source 422 provides a current to the first current mirror circuit 424. The first current mirror circuit 424 mirrors the current from the first terminal 454 at the second terminal 456. The second current mirror circuit 426 takes the current at the first terminal 458 and mirrors the current at the second terminal 460 (and the control terminal 436). As a result, the first transistor 404 is enabled and begins to conduct.

[0060] During operation, the one-shot pulse generator 412 generates a pulse in response to the voltage of the signal IN exceeding a threshold. The first buffer 414 provides an output signal to the second transistor 416, so that the second transistor 416 is not conducting. The second buffer 418 receives the output signal of the one-shot pulse generator 412 and generates an output signal to enable the third transistor 420 (e.g., the third transistor 420 is conducting). In response to the third transistor 420 conducting, a current signal is generated at the first terminal 454 of the first current mirror circuit 424 by the current source node 422. The first current mirror circuit 424 then generates a current signal at the second terminal 456. The second current mirror circuit 426 receives this current signal at the first terminal 458 and generates an output signal at the second terminal 460 (e.g., the control terminal 436 of the first transistor 404). In response to the output signal of the second current mirror circuit 426, the first transistor 404 is enabled by a first voltage supply node 428 (e.g., a node coupled to the first current mirror circuit 424) and a second voltage supply node 430 (e.g., a node coupled to the second current mirror circuit 426).

[0061] After the one-shot pulse generator 412 generates an output signal pulse (e.g., the voltage generated by the one-shot pulse generator 412 is 0 volts), the third transistor 420 is disabled (e.g., not conducting). As a result, the first current mirror circuit 424 does not generate an output signal at the second terminal 456, and the second current mirror circuit 426 does not generate an output signal at the second terminal 460. Because the output of the first buffer 414 is at a low voltage (preferably near 0 volts), the second transistor 416 begins to conduct. As a result, the first transistor 404 is enabled by the second voltage supply node 430 (e.g., a node coupled to the second transistor 416).

[0062] Under some operating conditions, the second current mirror circuit 426 generates a current signal based on a current signal obtained from the first current mirror circuit 424 (e.g., obtained from a circuit operating at a potential of 12 volts). As a result, the control terminal 436 of the first transistor 404 is limited to VDRV (e.g., 6 volts) during the transition to the on phase. However, because the second current mirror circuit 426 (e.g., the transistor 482 included in the second current mirror circuit 426) is coupled to the second voltage supply node 430 (e.g., 6 volts), the maximum voltage of the gate of the first transistor 404 is limited. Therefore, the gate terminal (e.g., the control terminal 436) of the first transistor 404 is limited and cannot provide a large slew rate.

[0063] 4, the second terminal 460 of the second current mirror circuit 426 is limited to VDRV. Therefore, the maximum voltage of the control terminal 436 is limited when transitioning to the enabled state. Because the first transistor 404 may require a voltage greater than VDRV (e.g., the maximum voltage rating of the first transistor 404) during the transition state to maintain a high slew rate, the second current mirror circuit 426 (e.g., the transistor coupled between the second voltage supply node 430 and the second terminal 460) and / or the first transistor 404 may run out of headroom provided by VDRV and thus be unable to maintain a high slew rate (e.g., due to a weak and / or hot corner).

[0064] 5 is a block diagram of an example implementation 500 of the first driver 105 of FIG. 1 adapted to enable a transistor (e.g., transistor 150 of FIG. 1) in response to an input signal (e.g., signal IN) at an input terminal (e.g., input terminal 156 of FIG. 1). Implementation 500 includes driver 105 of FIG. 1, ground node 145, input terminal 156, output terminal 158, and transistor 150. Transistor 150 includes control terminal 172, source terminal 174, and drain terminal 176 of FIG. 1. In the illustrated example of FIG. 5, first driver 105 includes an example regulator 505, a first example stage 510, and a second example stage 515. In the topology of FIG. 5, first driver 105 is adapted to be coupled to a first example voltage supply node 516 and a second example voltage supply node 518. In some examples described herein, the first voltage source node 516 is coupled to a first voltage source, and the second voltage source node 518 is coupled to a second voltage source. The first voltage source may have a first potential, which is higher than a second potential of the second voltage source. For example, the first voltage source node 516 may be coupled to a first voltage source having a potential of 12 volts, and the second voltage source node 518 may be coupled to a second voltage source having a potential of VDRV, such as 6 volts. The voltage source nodes 516, 518 may include voltage sources. For example, the first voltage source node 516 may include a voltage source configured to deliver a potential of 10 volts.

[0065] 5 may respond to a variation in the activation signal (e.g., signal IN crossing a voltage threshold) by providing a first control signal to output terminal 158 and control terminal 172 to enable transistor 150 (e.g., transistor 150 begins to conduct). The first control signal may be provided by first stage 510 as a voltage and / or current from first voltage supply node 516. In response to the voltage at output terminal 158, first driver 105 may provide a second control signal as an alternative to the first control signal to enable transistor 150. The second control signal may be provided by second stage 515 as a voltage and / or current from second voltage supply node 518, where first voltage supply node 516 (e.g., a first voltage supply) may include a higher potential (e.g., a potential) than second voltage supply node 518 (e.g., a second voltage supply). For example, first voltage supply node 516 may provide a voltage of 12 volts, and second voltage supply node 518 may provide a voltage of 6 volts. In some examples, first driver 105 may include additional and / or alternative circuit elements for disabling transistor 150 based on a fluctuation (e.g., a drop) in the activation signal provided by controller 120 of FIG.

[0066] In operation, regulator 505 may be adapted to enable first stage 510 by providing a first trigger signal to first stage 510. First stage 510 may be adapted to enable transistor 150 by a current (e.g., a first control signal, a gate drive current, a current signal) from a first voltage source (e.g., by a current from first voltage source node 516). First stage 510 may be adapted to enable transistor 150 by providing a first control signal to control terminal 172 of transistor 150 in response to the first trigger signal provided by regulator 505 exceeding a threshold voltage level (e.g., a logic high value, 3 volts, etc.). Regulator 505 may be adapted to regulate an output (e.g., the first control signal, the gate drive current, etc.) of first stage 510 by providing a regulation signal to first stage 510 in response to the voltage at control terminal 172 exceeding a voltage threshold. For example, if the voltage at the control terminal 172 exceeds a clamp voltage (e.g., 8 volts) provided by a clamp voltage source, the regulator 505 may provide a regulation signal at the second output terminal 526 to regulate the voltage at the control terminal 172 to the clamp voltage. The regulator 505 may be adapted to disable the first stage 510 by providing a logic output signal at the first input terminal 530 in response to the signal (e.g., current and / or voltage) at the second input terminal 522 exceeding the clamp voltage for a certain amount of time (e.g., a period of time after the voltage exceeds the clamp voltage for 50 nanoseconds, etc.).

[0067] In operation, regulator 505 may be configured to enable second stage 515 by sending and / or otherwise conveying a second trigger signal to second stage 515. Second stage 515 may be adapted to enable transistor 150 by providing a current from a second source (e.g., second voltage supply node 518). Second stage 515 may be adapted to enable transistor 150 by providing a second control signal to control terminal 172 of transistor 150 in response to the second trigger signal provided by regulator 505 exceeding a threshold voltage level (e.g., a logic high value, 2 volts).

[0068] In some examples described herein, first voltage supply node 516 may provide a voltage (e.g., 12 volts) higher than the voltage of second voltage supply node 518 to improve headroom for transistor 150 during switching, such as during a transition to an enabled state. In some examples described herein, first driver 105 may include a fast current source pull-up (e.g., a transistor and / or a first stage) to set, determine, and / or otherwise regulate the slew rate of transistor 150 while limiting the voltage at control terminal 172. Advantageously, first driver 105 may limit the voltage at control terminal 172 to prevent damage to transistor 150 during a transition to an enabled state. In some examples described herein, first driver 105 may disable the fast pull-up (e.g., a transistor and / or a first stage) after the voltage at control terminal 172 reaches a plateau voltage (e.g., a clamp voltage). In some examples described herein, the first driver 105 may include a weak pull-up (such as a transistor and / or second stage) to hold the control terminal 172 at a direct current (DC) operating voltage, such as the transistor's maximum rated voltage, VDRV, 6 volts, etc.

[0069] In operation, output stage headroom (e.g., the headroom of transistor 150 provided by first driver 105) is not limited to VDRV during transition to the enabled state because first driver 105 provides a control signal to transistor 150 that is sourced by first voltage supply node 516, which includes a potential greater than the potential of second voltage supply node 518. Also, in operation, first driver 105 may limit control terminal 172 to an operating voltage (e.g., 6 volts, VDRV, etc.) to enable transistor 150 in a steady state without damaging transistor 150. In some examples described herein, most of the charge (e.g., voltage) on control terminal 172 may be provided by first voltage supply node 516 rather than second voltage supply node 518. As such, second voltage supply node 518 may not be required to source large currents during operation.

[0070] Advantageously, by driving (e.g., enabling) the control terminal 172 sourced by a current source (e.g., IDRV) from a high voltage rail (e.g., first voltage supply node 516), more headroom may be provided to transistor 150 to achieve a high slew rate. Also, a fast voltage regulation loop (e.g., regulator 505) may be included in first driver 105 to limit the gate voltage (e.g., the voltage at control terminal 172) during transients (e.g., during transition to the enabled state). For long-term reliability and low power consumption, a gate voltage detector (e.g., regulator 505, linear regulator, and / or comparator circuit) may be included in first driver 105 to turn off (e.g., disable) the fast pullup driver (e.g., first stage 510) and enable the weak pullup (e.g., second stage 515). Advantageously, in some examples described herein, the first driver 105 may provide a continuous and / or constant slew rate across process corners and / or temperatures.

[0071] In some examples, transistor 150 may transition to an enabled state in response to a first control signal in a shorter period of time than in response to a second control signal. For example, transistor 150 may transition at a first slew rate in response to a first control signal, and transistor 150 may then transition at a second slew rate in response to a second control signal, where the first slew rate may be greater than the second slew rate. In some examples, transistor 150 may be damaged and / or destroyed when driven (e.g., enabled) by the first control signal for an extended period of time. Because the first driver 105 regulates the first control signal (e.g., disables the first control signal) and enables the second control signal so that the transistor 150 remains enabled, the first driver 105 enables the transistor 150 to begin conducting at a slew rate provided by the first voltage supply node 516 that is greater than the slew rate provided by the second voltage supply node 518 and / or enables the transistor 150 for a period of time without reducing the operability of the transistor 150 (e.g., without destroying the transistor 150 in operation).

[0072] 5, regulator 505 has and / or otherwise includes a first input terminal 520, a second input terminal 522, a first output terminal 524, a second output terminal 526, and a third output terminal 528. The first input terminal 520 is coupled to input terminal 156 of driver 105 in a configuration for receiving an activation signal (IN). Regulator 505 is adapted to receive the activation signal (e.g., signal IN provided by controller 120). In some examples, regulator 505 enables first stage 510 by delivering a first trigger signal at first output terminal 524 and enables second stage 515 by delivering a second trigger signal at third output terminal 528. Regulator 505 enables first stage 510 to enable transistor 150 in response to the activation signal exceeding a threshold voltage level, such as a logic high threshold. In some examples, the regulator 505 may provide a regulation signal at the second output terminal 526 to the first stage 510, and the first stage 510 may vary the first control signal provided to the output terminal 158 in response to the regulation signal.

[0073] Regulator 505 enables second stage 515 in response to a signal (e.g., a voltage signal) acquired at second input terminal 522. For example, if the voltage acquired at second input terminal 522 (e.g., at output terminal 158 and / or control terminal 172) exceeds a voltage threshold provided by a clamp voltage supply node, regulator 505 may clamp the voltage at control terminal 172 and provide a second trigger signal to second stage 515. In some examples, regulator 505 provides the second trigger signal in response to the voltage acquired at second input terminal 522 exceeding a voltage threshold (e.g., VCLAMP) for a period of time. In some examples, regulator 505 may modify (e.g., cease) providing the first trigger signal in addition to and / or as an alternative to providing the second trigger signal.

[0074] The first stage 510 has and / or otherwise includes a first input terminal 530 coupled to the first output terminal 524 of the regulator 505 to receive a first trigger signal, a second input terminal 532 coupled to the second output terminal 526 of the regulator 505 to receive a regulation signal, and an output terminal 534 coupled to the output terminal 158 of the first driver 105 (e.g., the control terminal 172 of the transistor 150) to provide a first control signal. In FIG. 5 , the first stage 510 is adapted to be coupled to the first voltage supply node 516 and the ground node 145. The first stage 510 provides (e.g., outputs) the first control signal at the output terminal 534 (e.g., to the output terminal 158 of the first driver 105 and / or to the control terminal 172 of the transistor 150) in response to the first trigger signal received at the first input terminal 530 exceeding a threshold voltage level. As such, the first stage 510 enables the transistor 150. In some examples, the first stage 510 varies the first control signal and / or otherwise modifies the first control signal (e.g., disables the first control signal) in response to the first trigger signal not exceeding a voltage threshold, such as a logic high voltage threshold. In some examples, the first stage 510 varies the first control signal in response to a regulation signal obtained at the second input terminal 532.

[0075] The second stage 515 has and / or otherwise includes an input terminal 536 coupled to the third output terminal 528 of the regulator 505 to obtain a second trigger signal, and an output terminal 538 coupled to the output terminal 534 of the first stage 510 at an exemplary node 539 to provide a second control signal. In FIG. 5 , node 539 is coupled to the second input terminal 522 of the regulator 505, the output terminal 158 of the first driver 105, and the control terminal 172 of the transistor 150. The second stage 515 is adapted to be coupled to the second voltage supply node 518 and the ground node 145. The second stage 515 provides the second control signal at the output terminal 538 (e.g., to the output terminal 158 of the driver 105 and / or the control terminal 172 of the transistor 150) in response to the second trigger signal obtained at the input terminal 536 exceeding a threshold voltage level, such as a logic high value. As such, second stage 515 may enable transistor 150 in response to a second trigger signal provided by regulator 505 at third output terminal 528 and obtained at input terminal 536. In some examples, second stage 515 provides the second control signal in response to the second trigger signal not exceeding a threshold voltage level, such as a logic low value.

[0076] In operation, regulator 505 receives an activation signal at first input terminal 520. In response to the activation signal exceeding a threshold voltage level (such as a logic high level, 5 volts, etc.), regulator 505 is adapted to convey and / or otherwise transmit a first trigger signal at first output terminal 524 to first stage 510. In response to the first trigger signal exceeding the threshold voltage level, first stage 510 is adapted to provide and / or otherwise generate a first control signal at output terminal 534 (e.g., to node 539, output terminal 158 of driver 105, control terminal 172, etc.) to enable transistor 150 with a current provided by first voltage supply node 516. In some examples, regulator 505 provides a regulation signal at output terminal 524 to first stage 510 in response to variations in the signal received at second input terminal 522. For example, if the voltage at node 539 exceeds a threshold (such as a clamp voltage threshold), regulator 505 may vary (e.g., reduce and / or disable) the regulation signal. First stage 510 may then vary (e.g., reduce and / or disable) the first control signal that enables transistor 150 in response to the variation in the regulation signal obtained at second input terminal 532.

[0077] In response to a signal (e.g., a voltage value) at node 539 (e.g., a voltage that exceeds a voltage threshold (e.g., a clamp voltage) for a period of time), regulator 505 may provide a second trigger signal at third output terminal 528 to second stage 515. In response to the second trigger signal, second stage 515 may provide and / or otherwise output a second control signal at output terminal 538 to driver output terminal 158 (e.g., to control terminal 172) using a current provided by second voltage supply node 518. Thus, transistor 150 is first enabled by the current provided by first voltage supply node 516, and then enabled (e.g., held and maintained in an enabled mode) by the current provided by second voltage supply node 518.

[0078] 6 is a diagram of an example implementation 600 of the first driver 105 of FIGS. 1 and / or 5 adapted to enable a transistor (e.g., transistor 150 of FIG. 1) in response to an example input signal (e.g., an activation signal, signal IN, etc.) at an example input terminal (e.g., example input terminal 156 of FIG. 1). The implementation 600 of FIG. 6 includes the first driver 105 of FIGS. 1 and / or 5, a ground node 145, an input terminal 156, an output terminal 158, and a transistor 150. The transistor 150 includes the control terminal 172, the source terminal 174, and the drain terminal 176 of FIG. 1 and / or 5. In the example of FIG. 6, the first driver 105 includes the regulator 505 of FIG. 5, a first stage 510, a second stage 515, a first voltage supply node 516, and a second voltage supply node 518.

[0079] 6, regulator 505 includes logic gate 601, comparator, delay, and latch circuit 602 (hereinafter referred to as “comparator 602”), linear regulator circuit 603, and transistor 604. Regulator 505 is adapted to be coupled to an example clamp voltage supply node 605. In the example described herein, clamp voltage supply node 605 is coupled to a voltage source in a configuration to (1) drive transistor 150 at a higher slew rate, and (2) provide a potential (e.g., VCLAMP) that is higher than the potential of a voltage source (e.g., VDRV) coupled to second voltage supply node 518 and lower than the potential of first voltage supply node 516 (e.g., 12 volts). For example, a first voltage source coupled to first voltage source node 516 may provide 12 volts, a second voltage source coupled to second voltage source node 518 may provide 6 volts, and a third voltage source coupled to clamp voltage source node 605 may provide 8 volts. However, any of clamp voltage source node 605, first voltage source node 516, and / or second voltage source node 518 may be coupled to a voltage source providing any suitable voltage, such as 0 volts, 10 volts, 100 volts, etc.

[0080] 6, logic gate 601 includes a first input terminal 616 coupled to first input terminal 520 of regulator 505 for receiving an activation signal (IN), a second input terminal 617 for receiving a signal (e.g., a logic low value) from comparator circuit 602, and an output terminal 619 coupled to first output terminal 524 of regulator 505 for providing a first trigger signal. In the topology illustrated in FIG. 6, logic gate 601 is an exemplary complementary AND gate. In some examples, any suitable combination of logic gates and / or circuits may be used to implement logic gate 601. Logic gate 601 is adapted to provide and / or otherwise output the first trigger signal at output terminal 619 (e.g., at first output terminal 524 of the regulator and / or to first input terminal 530 of first stage 510). For example, logic gate 601 provides the first trigger signal in response to (1) the voltage of a signal (such as an activation signal, signal IN, etc.) acquired at first input terminal 616 and (2) the voltage at second input terminal 617 exceeding a threshold voltage level, such as a logic high threshold of 5 volts. In another example, logic gate 601 may fluctuate (e.g., decrease) the first trigger signal in response to the activation signal and / or the third trigger signal not exceeding a threshold voltage level. Logic gate 601 is configured to enable first stage 510 by conveying the first trigger signal to first input terminal 530 of first stage 510.

[0081] Linear regulator circuit 603 includes an output terminal 620 for regulating transistor 604, a first input terminal 621 (e.g., a non-inverting input) adapted to be coupled to clamp voltage source 605, and a second input terminal 622 (e.g., an inverting input) coupled to second input terminal 522 of regulator 505 to obtain a signal (e.g., a voltage) at control terminal 172. In the topology illustrated in Figure 6, linear regulator circuit 603 is an exemplary linear amplifier, such as a comparator. However, any suitable combination of circuits and / or logic gates may be used to implement linear regulator circuit 603. In operation, linear regulator circuit 603 is adapted to regulate the voltage at second input terminal 622 (e.g., at node 539, control terminal 172 of transistor 150, etc.) via transistor 604 in response to a comparison of a signal obtained at first input terminal 621 (e.g., a voltage threshold level VCLAMP provided by clamp voltage source 605) with a signal obtained at second input terminal 622 (e.g., the voltage at control terminal 172 of transistor 150). In some examples, linear regulator circuit 603 regulates (e.g., adjusts) the current through transistor 604. Thus, with transistor 604 coupled to first stage 510 (e.g., to switching circuit 633 coupled to current source 632), linear regulator circuit 603 regulates the current provided to current mirror circuit 634 at first terminal 640, and therefore the current provided by current mirror circuit 634 to control terminal 172 at second terminal 642. In some examples, linear regulator circuit 603 regulates the voltage at second input terminal 622 so that it substantially tracks (e.g., is equal to) the voltage at first input terminal 621, such as voltage VCLAMP provided by clamp voltage source node 605.For example, if the voltage at second input terminal 622 is greater than the voltage at first input terminal 621, linear regulator circuit 603 may reduce the output at output terminal 620, thereby increasing the current flow from source terminal 623 to drain terminal 624 of transistor 604. Because transistor 604 and current mirror circuit 634 are adapted to be coupled to current source node 632 via switching circuit 633, linear regulator circuit 603 and / or transistor 604 reduce the current provided to first terminal 640 of current mirror circuit 634.

[0082] Transistor 604 includes a source terminal 623 (e.g., a first current terminal) adapted to be coupled to first voltage supply node 516, a drain terminal 624 (e.g., a second current terminal) coupled to second output terminal 526 of regulator 505 to provide a regulation signal, and a control terminal 625 (e.g., a gate terminal) coupled to output terminal 620 to obtain an output from linear regulator circuit 603. In operation, transistor 604 provides a regulation signal (e.g., a current) at second output terminal 526 to first stage 510 in response to a signal provided by linear regulator circuit 603 at control terminal 625. For example, if the voltage at second input terminal 622 is higher than the voltage at first input terminal 621 (VCLAMP), linear regulator circuit 603 may increase the current provided to control terminal 625 of transistor 604. In this way, first stage 510 may drive transistor 150 with a lower control signal (e.g., with less current), and the voltage at node 539 (e.g., control terminal 172, second input terminal 522) may decrease to the voltage VCLAMP provided by clamp voltage supply node 605. In response to the regulation signal, first stage 510 may increase or decrease the first control signal (e.g., current signal, control current) at output terminal 534, thereby regulating control terminal 172 of transistor 150, such as the voltage at control terminal 172.

[0083] Comparator circuit 602 (e.g., a comparator, delay, and / or latch circuit) includes an input terminal 629 coupled to output terminal 620 to obtain an output from linear regulator circuit 603, a first output terminal 630 coupled to a third output terminal 528 of regulator 505 (e.g., to an input terminal 536 of second stage 515) to enable second stage 515, and a second output terminal 631 coupled to second input terminal 617 to provide a signal (e.g., a logic low value) to logic gate 601. Comparator circuit 602 enables second stage 515 (e.g., a transistor included in second stage 515 and coupled to input terminal 536) by providing a second trigger signal at first output terminal 630 in response to a fluctuation in the output of linear regulator circuit 603. In some examples, comparator circuit 602 obtains a signal (e.g., an analog voltage value) provided by linear regulator circuit 603 at input terminal 629. Comparator circuit 602 may convert the analog signal to a digital signal (e.g., a logic high value, a logic low value, etc.) and may output a logic low value at output terminal 630 in response to the signal at input terminal 629 not exceeding a voltage threshold for a period of time (e.g., a delay). Comparator circuit 602 may include a filter circuit (e.g., a resistor and capacitor) to respond to the signal obtained at input terminal 629 after a period of time (e.g., 20 nanoseconds). Comparator circuit 602 may include and / or be adapted to be coupled to a reference voltage node.

[0084] In operation, if the signal at input terminal 629 exceeds a threshold (e.g., a logic high voltage threshold, 2 volts, 3 volts, etc.) for a certain period of time, comparator circuit 602 provides a first voltage signal (e.g., a logic high value) at output terminals 630, 631. In operation, if the signal at input terminal 629 does not exceed a threshold (e.g., a logic high voltage threshold, 2 volts, 3 volts, etc.) for a certain period of time, comparator circuit 602 may provide a second voltage signal (e.g., a logic low value) at output terminals 630, 631. Thus, by providing the second voltage signal, comparator circuit 602 may disable logic gate 601, and therefore, first stage 510. Also, by providing a second voltage signal (eg, a second control signal) to the second stage 515 , the comparator circuit 602 may enable the second stage 515 , and therefore enable the transistor 150 .

[0085] 6, the first stage 510 is adapted to be coupled to a current source 632 and a first voltage supply node 516. The first stage 510 includes an example switching circuit 633 and an example current mirror circuit 634. The second stage 515 includes a transistor 635. In the topology shown in FIG. 6, the second stage 515 is adapted to be coupled to a second voltage supply node 518. In the topology shown in FIG. 6, the first voltage supply node 516 has a higher potential than the second voltage supply node 518. For example, the first voltage supply node 516 may have a potential of 12 volts, and the second voltage supply node 518 may have a potential of 6 volts. The current source 632 may provide a current (e.g., a mirror signal, a current mirror signal, a signal IDRV, a signal Iref, etc.) to the current mirror circuit 634 and / or the first stage 510.

[0086] The switching circuit 633 includes a first terminal 636 coupled to the first input terminal 530 of the first stage 510 to receive a first trigger signal, a second terminal 637 adapted to be coupled to the current source node 632, and a third terminal 638 for providing a current signal to the current mirror circuit 634. The switching circuit 633 electrically connects the second terminal 637 to the third terminal 638 in response to receiving a logic high value at the first terminal 636. The switching circuit 633 may be implemented with any suitable switching device (e.g., a MOSFET, a BJT, a double-pole single-throw (DPST) switch, etc.). In some examples, the switching circuit 633 may be implemented with one or more NMOS transistors. The switching circuit 633 electrically connects the second terminal 637 to the third terminal 638 in response to a signal received at the first terminal 636 (e.g., a first control signal provided by the logic gate 601) exceeding a voltage threshold.

[0087] Current mirror circuit 634 includes a first terminal 640 coupled to the third terminal 638 of switching circuit 633 and to the second input terminal 532 of first stage 510 to obtain a current signal. Current mirror circuit 634 includes a second terminal 642 coupled to the output terminal 534 of first stage 510 to provide a control signal to control terminal 172. In the example of FIG. 6 , current mirror circuit 634 provides a first control signal at second terminal 642 to control terminal 172 of transistor 150 in response to obtaining a signal (mirror signal, current mirror signal, etc.) at first terminal 640. For example, switching circuit 633 and transistor 604 may be enabled, thereby providing a mirror current (such as signal IDRV) at first terminal 640 that is sourced by current source node 632, and current mirror circuit 634 may provide the first control signal to the control terminal. For example, current mirror circuit 634 may obtain signal IDRV at first terminal 640 and provide a signal at second terminal 642 to control terminal 172 in response to switching circuit 633 being enabled. In some examples, a second current mirror circuit or any number of current mirror circuits may be coupled between second terminal 642 and node 539 to provide additional current to enable transistor 150. In some examples, regulator 505, such as linear regulator circuit 603 and / or transistor 604, may enable and / or disable current mirror circuit 634 to provide a first control signal in response to a voltage at second input terminal 522 of regulator 505.

[0088] Second stage 515 includes transistor 635. Transistor 635 includes a control terminal 644 coupled to input terminal 536 of second stage 515 for obtaining a second trigger signal, a source terminal 646 adapted to be coupled to second voltage supply node 518, and a drain terminal 648 coupled to output terminal 538 of second stage 515 for providing a second control signal. Transistor 635 provides the second control signal at output terminal 538 of second stage 515 for enabling transistor 150 in response to a second trigger signal obtained at control terminal 644 (e.g., provided at input terminal 536 by comparator circuit 602).

[0089] In operation, in response to the voltage at control terminal 172 exceeding clamp voltage supply node 605, linear regulator circuit 603 regulates and / or clamps the voltage across transistor 604 by providing a regulation signal to first stage 510. Thus, the voltage at control terminal 172 is regulated so as not to exceed a maximum voltage (e.g., VCLAMP). In response to the voltage at control terminal 172 (e.g., second input terminal 522, node 539, second input terminal 622) reaching voltage VCLAMP for a period of time (e.g., after a delay), comparator circuit 602 provides a second trigger signal (e.g., a logic low value) at output terminal 620 to second stage 515. In some examples, comparator circuit 602 delays providing the second trigger signal and / or otherwise waits until the voltage at input terminal 629 has not exceeded a threshold value (such as a logic low value) for a period of time. As a result, transistor 635 is enabled, thus enabling transistor 150 with the current provided by second voltage supply node 518. In some examples, logic gate 601 may cause the first control signal to fluctuate (e.g., reduce the signal to 0 volts) in response to the fluctuation of the second trigger signal, thus disabling switching circuit 633.

[0090] Figure 7A is a diagram of an example implementation 700 of the first driver 105 of Figures 1, 5, and / or 6, including additional logic circuit elements relative to the implementation 600 of Figure 6. Implementation 700 includes the driver 105, ground node 145, transistor 150, input terminal 156, and output terminal 158 of Figure 1. In the example of Figure 7A, the first driver 105 includes the regulator 505, first stage 510, second stage 515, first voltage source node 516, and second voltage source node 518 of Figure 5. In the topology of Figure 7A, the first driver 105 includes the clamp voltage source node 605 and current source node 632 of Figure 6.

[0091] The regulator 505 includes a logic gate 601, a comparator circuit 602, and a linear regulator circuit 603. In operation, the logic gate 601 provides a first trigger signal at the regulator's first output terminal 524 and / or to the first input terminal 530 of the first stage 510. In some examples, the logic gate 601 may provide the first trigger signal in response to an activation signal (IN) and a signal acquired at the second input terminal 617 exceeding a voltage threshold, such as a logic high value. The logic gate 601 enables the switching circuit 633 of the first stage 510 by providing the first trigger signal to the first input terminal 530 of the first stage 510.

[0092] 7A , the first transistor 702 and the second transistor 704 are each a PMOS transistor, and the third transistor 706 is an NMOS transistor. The first transistor 702 includes a source terminal 714 coupled to a first input terminal 621 of the linear regulator circuit 603 (e.g., adapted to be coupled to a clamp voltage supply node 605), a control terminal 716, and a drain terminal 718 coupled to the control terminal 716. The first resistor 708 is coupled between the drain terminal 718 of the first transistor 702 and the ground node 145. The second transistor 704 includes a control terminal 720 coupled to the drain terminal 718 of the first transistor 702, a source terminal 722 coupled to the second input terminal 622 of the linear regulator circuit 603 (e.g., to node 539) to obtain a signal at the control terminal 172, and a drain terminal 724 adapted to be coupled to the ground node 145 (e.g., via a resistor).

[0093] The third transistor 706 includes a control terminal 726 coupled to the drain terminal 724 of the second transistor 704, a drain terminal 728 coupled to the output terminals 620A, 620B of the linear regulator circuit 603 to provide the output of the linear regulator circuit 603, and a source terminal 730 adapted to be coupled to the ground node 145. The second resistor 710 is coupled between the control terminal 726 of the third transistor 706 and the ground node 145. The third resistor 712 is coupled and / or adapted to be coupled between the first voltage supply node 516 and the drain terminal 728 of the third transistor 706. Linear regulator circuit 603 regulates the voltage at node 539 (e.g., control terminal 172) by varying a regulation signal (e.g., current) through transistor 604 in response to the voltage at second input terminal 622 (e.g., node 539, control terminal 172) exceeding a voltage (VCLAMP) provided by clamp voltage supply node 605. As such, linear regulator circuit 603 regulates the first control signal (e.g., current) provided by first stage 510 so that the voltage at control terminal 172 is regulated and / or does not exceed a certain voltage. Therefore, advantageously, transistor 150 may be protected from damage caused by first stage 510 driving (e.g., enabling) transistor 150.

[0094] Comparator circuit 602 (e.g., a comparator, delay, and / or latch circuit) is coupled to logic gate 601, linear regulator circuit 603, and a third output terminal 528 of regulator 505. An input terminal 629 of comparator circuit 602 is coupled to a control terminal 625 of transistor 604 (e.g., an output terminal 620A of linear regulator circuit 603) to obtain an output signal from linear regulator circuit 603. Comparator circuit 602 is adapted to provide a second trigger signal to second stage 515 (e.g., to enable transistor 635) in response to the voltage at input terminal 629 exceeding a voltage threshold (e.g., a reference voltage for comparator circuit 602) for a period of time. The comparator circuit 602 may also provide a logic low value at the second output terminal 631 (e.g., to the logic gate 601 at the second input terminal 617) to fluctuate the first trigger signal and / or disable the first stage 510.

[0095] Transistor 604 includes a drain terminal 624 coupled to second output terminal 526 (e.g., second input terminal 532, third terminal 638), a source terminal 623 adapted to be coupled to first voltage supply node 516, and a control terminal 625 coupled to output terminal 620B of linear regulator circuit 603. Transistor 604 may respond to an output from linear regulator circuit 603 (e.g., at control terminal 625) by providing a regulation signal to first stage 510 at second output terminal 526. In operation, when the voltage at second input terminal 522 exceeds voltage VCLAMP (e.g., when the voltage at second input terminal 622 exceeds the voltage at first input terminal 621), linear regulator circuit 603 increases the current through transistor 604 (e.g., from source terminal 623 to drain terminal 624). Therefore, the current taken by the current mirror circuit 634 at the first terminal 640 is lower than previously taken, and therefore the current provided by the current mirror circuit 634 at the second terminal 642 is reduced. As a result, the voltage at the second input terminal 522 is reduced and begins to approach the voltage VCLAMP.

[0096] The first stage 510 includes the switching circuit 633 and current mirror circuit 634 of FIG. 6. In the topology of FIG. 7A, the switching circuit 633 is implemented as an NMOS transistor. For example, a control terminal of the NMOS transistor may be coupled to a first terminal 636, a source terminal of the NMOS transistor may be coupled to a second terminal 637, and a drain terminal of the NMOS transistor may be coupled to a third terminal 638. However, any other circuitry may additionally or alternatively be included to implement the switching circuit 633. The switching circuit 633 includes a first terminal 636 coupled to the first input terminal 530, a third terminal 638 coupled to a first terminal 640 of the current mirror circuit 634, and a second terminal 637 adapted to be coupled to the current source node 632.

[0097] 7A , the fourth transistor 732 and the fifth transistor 734 are each PMOS transistors. The fourth transistor 732 includes a source terminal 736 adapted to be coupled to the first voltage supply node 516, a drain terminal 738 coupled to the first terminal 640 of the current mirror circuit 634, and a control terminal 740 coupled to the first terminal 640. The fifth transistor 734 includes a control terminal 742 coupled to the control terminal 740 of the fourth transistor 732, a source terminal 744 adapted to be coupled to the first voltage supply node 516, and a drain terminal 746 coupled to the second terminal 642 of the current mirror circuit 634. In operation, current mirror circuit 634 provides a first control signal at second terminal 642 to output terminal 158 (e.g., node 539, transistor 150, etc.) in response to obtaining a signal (mirror signal, current mirror signal, etc.) at first terminal 640. For example, switching circuit 633 and transistor 604 may be enabled to provide a mirror current (e.g., signal IDRV) to first terminal 640 that is sourced by current source 632, after which current mirror circuit 634 may provide the first control signal to control terminal 172. In some examples, a second current mirror circuit may be coupled between second terminal 642 and output terminal 534 of first stage 510 (e.g., between second terminal 642 and node 539) to provide additional current to enable transistor 150.

[0098] 6. Transistor 635 is coupled to an input terminal 536 (e.g., third output terminal 528 of regulator 505) and to an output terminal 538 (e.g., node 539, output terminal 158, transistor 150, etc.) of second stage 515. Transistor 635 may enable transistor 150 by providing a second control signal, such as a current provided by second voltage source node 518, in response to obtaining a second trigger signal at input terminal 536.

[0099] 7B is a diagram of an example implementation 760 of the comparator circuit 602 (e.g., a comparator, delay, and latch circuit) of FIG. 6. The implementation 760 includes the ground node 145 of FIG. 1, the first voltage supply node 516 of FIG. 5, and a supply voltage node (V5V) 762 (e.g., a digital supply voltage node). In the example of FIG. 7B, the comparator circuit 602 includes a first transistor 764, a first resistor 766, a capacitor 768, a second transistor 770, a second resistor 772, a latch circuit 774, and a buffer circuit 776. In some examples, the comparator circuit 602 may be adapted to be coupled to the supply voltage node 762 and / or the first voltage supply node 516. In the example of FIG. 7B, the supply voltage node 762 provides a voltage of 5 volts. However, supply voltage node 762 may provide any suitable supply voltage (eg, 3.3 volts) to comparator circuit 602.

[0100] 7B , the first transistor 764 includes a control terminal 778 coupled to the input terminal 629 of the comparator circuit 602 to obtain the output from the linear regulator circuit 603, a source terminal 780 adapted to be coupled to the first voltage supply node 516, and a drain terminal 782. In the topology of FIG. 7B , the first transistor 764 is a PMOS transistor. In operation, the first transistor 764 provides a signal (e.g., a current) at the drain terminal 782 in response to a signal at the control terminal 778 (e.g., the input terminal 629). For example, when the linear regulator circuit 603 reduces the output signal provided at the output terminal 620 in response to the voltage at the second input terminal 622 exceeding the voltage VCLAMP at the first input terminal 621, the first transistor 764 may increase the current signal provided at the drain terminal 782 using the first voltage supply node 516.

[0101] 7B , a first resistor 766 and a capacitor 768 are each coupled between the drain terminal 782 and the ground node 145. In operation, the first resistor 766 and the capacitor 768 may form a filter circuit (e.g., a low-pass filter circuit) that may delay the enabling of the second transistor 770 in response to the current signal provided by the first transistor 764. For example, when the first transistor 764 is enabled, the second transistor 770 may be enabled in response to the first transistor 764, and the second transistor 770 may be enabled after a delay based on the impedance of the first resistor 766 and the capacitor 768.

[0102] 7B , the second transistor 770 includes a control terminal 784 coupled to the drain terminal 782 of the first transistor 764, a source terminal 786 adapted to be coupled to the ground node 145, and a drain terminal 788 adapted to be coupled to the supply voltage node 762 (e.g., via a resistor). In the topology shown in FIG. 7B , the second transistor 770 is an NMOS transistor. A second resistor 772 is coupled between the drain terminal 788 and the supply voltage node 762. The latch circuit 774 includes an input terminal 790 coupled to the drain terminal 788 of the second transistor 770 and an output terminal 792 for providing an output signal (e.g., a logic low value) to the logic gate 601. The latch circuit 774 sets (e.g., latches) a voltage signal at the output terminal 792 in response to a voltage obtained at the input terminal 790. For example, if the voltage at input terminal 790 decreases (e.g., transitions from a logic high value to a logic low value), latch circuit 774 may maintain the voltage (e.g., a logic low value) at output terminal 792 until the next cycle. Output terminal 792 of latch circuit 774 is coupled to second output terminal 631 of comparator circuit 602.

[0103] Buffer circuit 776 is coupled between output terminal 792 of latch circuit 774 and first output terminal 630 of comparator circuit 602. In the example of FIG. 7B , buffer circuit 776 removes glitches (e.g., unwanted signal transitions) from the voltage signal obtained from output terminal 792 of latch circuit 774 and provides the voltage signal to a component coupled at output terminal 630 of comparator circuit 602 (e.g., transistor 635 of second stage 515) at an output impedance level lower than the output impedance level of latch circuit 774. While the topology of FIG. 7B includes one buffer circuit, any number of buffer circuits may additionally or alternatively be included in comparator circuit 602 and / or, more generally, in driver 105. For example, a buffer circuit may be coupled between output terminal 792 of latch circuit 774 and output terminal 631 of comparator circuit 602.

[0104] In operation, in an initial state (e.g., when the first driver 105 is commanded to turn on in response to a signal IN acquired at the input terminal 156), the comparator circuit 602 provides a first voltage signal (e.g., a logic high value) at the first output terminal 630 and the second output terminal 631. In response to a fluctuation in the signal acquired at the input terminal 629 (e.g., the linear regulator circuit 603 reduces the voltage signal at the output terminal 620 in response to the voltage at the second input terminal 622 exceeding the voltage at the first input terminal 621), the first transistor 764 is enabled. As a result, the second transistor 770 is enabled after a delay controlled by the filter circuit (e.g., a first resistor 766 and a capacitor 768). As a result, a low voltage signal is provided at the input terminal 790 to the latch circuit 774, which causes the output at the output terminal 792 to fluctuate (e.g., provides a logic low value). In response to a variation at output terminal 792, and therefore a variation at first output terminal 630 and second output terminal 631, second stage 515 is enabled and first stage 510 is disabled. Latch circuit 774 ensures that first driver 105 remains in this state (e.g., second stage 515 is enabled and first stage 510 is disabled) until driver 105 is commanded to be disabled in response to a change (e.g., a decrease) in signal IN obtained at input terminal 156.

[0105] Figure 8 is a diagram of an example implementation 800 of driver 105 of Figures 1, 5, and / or 6 that includes additional logic circuit elements relative to the implementation of Figure 6. Implementation 800 includes driver 105, ground node 145, transistor 150, input terminal 156, and output terminal 158 of Figure 1. In the example of Figure 8, driver 105 includes regulator 505, first stage 510, second stage 515, first voltage source node 516, and second voltage source node 518 of Figure 5. In the topology of Figure 8, driver 105 includes clamp voltage source node 605 and current source node 632 of Figure 6.

[0106] 8, regulator 505 includes logic gate 601, comparator circuit 602, linear regulator circuit 603, and transistor 604. In the example of FIG. 8, linear regulator circuit 603 includes transistor 802 and resistor 804. Transistor 802 includes a drain terminal 806 coupled to an output terminal 620 (e.g., output terminals 620A, 620B) of linear regulator circuit 603 (e.g., to input terminal 629 of comparator circuit 602), a source terminal 808 coupled to a first input terminal 621 (e.g., adapted to be coupled to clamp voltage supply node 605), and a control terminal 810 coupled to a second input terminal 622. Resistor 804 is coupled and / or adapted to be coupled between drain terminal 806 of transistor 802 and first voltage supply node 516. In operation, the linear regulator circuit 603 regulates the voltage at the node 539 (e.g., the output terminal 534 of the first stage 510, the second input terminal 522, etc.) to approach the voltage VCLAMP provided by the clamp voltage supply node 605.

[0107] In the illustrated example of FIG. 8, the first stage 510 includes the switching circuit 633 of FIG. 6 and a current mirror circuit 634. In the topology of FIG. 8, the switching circuit 633 is implemented as an NMOS transistor. However, any other circuitry may additionally or alternatively be included to implement the switching circuit 633. In the example of FIG. 8, the first stage 510 includes a second current mirror circuit 812. The second current mirror circuit 812 includes a first terminal 814 coupled to a second terminal 642 of the current mirror circuit 634 and to a second input terminal 522 of the regulator 505 to obtain a signal (e.g., a current) from the current mirror circuit 634, and the second current mirror circuit 812 includes a second terminal 816 coupled to the output terminal 534 of the first stage (e.g., output terminal 158 and / or control terminal 172 of transistor 150) to provide a control signal to, and thereby enable, transistor 150.

[0108] The second current mirror circuit 812 includes a first transistor 818 and a second transistor 819. The first transistor 818 includes a drain terminal 820 coupled to the first terminal 814 for obtaining a current signal from the first current mirror circuit 634, a control terminal 822 coupled to the drain terminal 820, and a source terminal 824 coupled to the second terminal 816 of the second current mirror circuit 812 for providing a control signal to the control terminal 172. The second transistor 819 includes a control terminal 826 coupled to the control terminal 822 of the first transistor 818 for obtaining a current signal from the first current mirror circuit 634, a drain terminal 828 adapted to be coupled to the first voltage supply node 516, and a source terminal 830 coupled to the second terminal 816 of the second current mirror circuit 812 for providing a control signal to the control terminal 172. In some examples, current mirror circuit 634 may provide a current signal at a second terminal 642 (such as a first terminal 814 of second current mirror circuit 812) in response to a signal, such as signal IDRV, obtained at a first terminal 640 when switching circuit 633 is enabled by regulator 505. Second current mirror circuit 812 may then provide a second control signal at a second terminal 816 (e.g., to transistor 150 at output terminal 534) in response to obtaining the signal at the first terminal 814. In some examples, second current mirror circuit 812 may provide additional current to enable transistor 150 compared to current mirror circuit 634 and / or second current mirror circuit 812 may stabilize the current signal provided by current mirror circuit 634 at the second terminal 642.

[0109] 6. Transistor 635 is coupled to an input terminal 536 and an output terminal 538 of second stage 515. Transistor 635 enables transistor 150 by providing a second control signal, such as a current provided by second voltage supply node 518, in response to obtaining a second trigger signal at input terminal 536.

[0110] While example ways of implementing the driver 105 of Figure 1 are illustrated in Figures 5, 6, 7A, 7B, and / or 8, one or more of the elements, processes, and / or devices illustrated in Figures 5, 6, 7A, 7B, and / or 8 may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. Also, the example regulator 505, the example first stage 510, the example second stage 515, and / or, more generally, the example driver 105 of Figures 1, 5, 6, 7A, 7B, and / or 8 may be implemented by hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Thus, for example, any of the example regulator 505, the first example stage 510, the second example stage 515, and / or, more generally, the example driver 105, may be implemented by one or more analog or digital circuits, logic circuits, programmable processors, programmable controllers, graphics processing units (GPUs), digital signal processors (DSPs), application specific integrated circuits (ASICs), programmable logic devices (PLDs), and / or field programmable logic devices (FPLDs). In construing any of the apparatus or system claims herein to cover pure software and / or firmware implementations, it is expressly defined herein that at least one of the example regulator 505, the first example stage 510, the second example stage 515, and / or, more generally, the example driver 105, including software and / or firmware, includes a non-transitory computer-readable storage device or storage disk such as a memory, a digital versatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc. Additionally, the example driver 105 of FIG. 1 may include one or more elements, processes, and / or devices in addition to or instead of those illustrated in FIGS. 5, 6, 7A, 7B, and / or 8, and / or may include any or all of two or more of the illustrated elements, processes, and devices.As used herein, the term "communicating," including variations thereof, encompasses direct communication and / or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and / or one-time events.

[0111] A flowchart illustrating example hardware logic, machine-readable instructions, hardware-implemented state machines, and / or combinations thereof for implementing the example driver 105 of FIG. 1 is shown in FIG. 9. The machine-readable instructions may be one or more executable programs, or portions of executable programs, for execution by a computer processor, such as a processor. The programs may be embodied in software stored on a non-transitory computer-readable storage medium, such as a CD-ROM, floppy disk, hard drive, DVD, Blu-ray disk, or memory associated with a processor, although the entire program and / or portions thereof may alternatively be executed by devices other than a processor and / or embodied in firmware or dedicated hardware. Also, although an example program is described with reference to the flowchart illustrated in FIG. 9, many other ways of implementing the example driver 105 may alternatively be used. For example, the order of execution of the blocks may be changed, and / or some of the described blocks may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuit elements, FPGAs, ASICs, comparators, operational amplifiers (op amps), logic circuits, etc.) configured to perform the corresponding operations without executing software or firmware.

[0112] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a fragmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions as described herein may be stored as data (e.g., portions of instructions, code, representations of code, etc.) that can be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be fragmented and stored on one or more storage devices and / or computing devices (e.g., servers). The machine-readable instructions may require one or more of installing, modifying, adapting, updating, combining, supplementing, configuring, decrypting, decompressing, unpacking, distributing, reassigning, compiling, etc., so that they can be directly read, interpreted, and / or executed by computing devices and / or other machines. For example, the machine-readable instructions may be stored in multiple portions that are individually compressed, encrypted, and stored on separate computing devices, which portions, when decoded, decompressed, and combined, form a set of executable instructions that implements a program as described herein.

[0113] In another example, machine-readable instructions may be stored in a state in which they can be read by a computer, but may require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., to execute the instructions on a particular computing device or other device. In another example, the machine-readable instructions may need to be configured (e.g., to save settings, input data, record network addresses, etc.) before the machine-readable instructions and / or corresponding program can be executed in whole or in part. As such, machine-readable instructions and / or corresponding programs described encompass such machine-readable instructions and / or programs regardless of the particular format or state of the machine-readable instructions and / or programs when stored or otherwise at rest or in transition.

[0114] The machine-readable instructions described herein may be expressed in any past, present, or future command language, scripting language, programming language, etc. For example, the machine-readable instructions may be expressed using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0115] 9 may be implemented using executable instructions (e.g., computer- and / or machine-readable instructions) stored on a non-transitory computer- and / or machine-readable medium, such as a hard disk drive, flash memory, read-only memory, compact disk, digital versatile disk, cache, random access memory, and / or any other storage device or storage disk that stores information for any duration (e.g., for an extended period of time, permanently, for a brief moment, during temporary buffering, and / or during caching of information). As used herein, the term non-transitory computer-readable medium is expressly defined to include any type of computer-readable storage device and / or storage disk, and to exclude propagating signals and to exclude transmission media.

[0116] As used herein, the term "comprising" (and all variations and tenses thereof) is used as an open-ended term. Thus, whenever a claim uses any form of "comprising" (e.g., including, having, etc.) as a preamble or in a claim, any additional elements, descriptions of terms, etc. may be present without departing from the scope of the corresponding claim or description. As used herein, the phrase "at least," when used as a connective phrase, for example, in the preamble of a claim, is open-ended in the same way that the terms "comprising" and "including" are open-ended. The term "and / or," when used in the form of, for example, A, B, and / or C, refers to any combination or subset of A, B, and C, such as (1) A only, (2) B only, (3) C only, (4) A and B, (5) A and C, (6) B and C, and (7) A, B, and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A and B" refers to an implementation that includes any of (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" refers to an implementation that includes any of (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, acts, activities, and / or steps, the phrase "at least one of A and B" refers to an implementation that includes any of (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of a process, instruction, act, activity, and / or step, the phrase "at least one of A or B" refers to implementations that include any of: (1) at least one A; (2) at least one B; and (3) at least one A and at least one B.

[0117] As used herein, singular references (e.g., "a," "first," "second," etc.) do not exclude a plurality. As used herein, the term "a" entity refers to one or more of such entities. The terms "a," "one or more," and "at least one" may be used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements, or method actions may be implemented by, for example, a single unit or processor. Furthermore, although individual features may be included in different examples or claims, these may in some cases be combined, and inclusion in different examples or claims does not imply that combining features is not feasible and / or advantageous.

[0118] 9 is a flowchart representing an example process 900 that may be implemented using logic or machine-readable instructions that may be executed to implement an example driver (e.g., driver 105 of FIGS. 1, 5, 6, 7A, 7B, and / or 8). In the example process 900 of FIG. 9, regulator 505 may obtain an activation signal (e.g., signal IN) and determine whether the activation signal exceeds a voltage threshold level (e.g., a logic high voltage threshold, a 5 volt threshold, a 3 volt threshold, etc.). If regulator 505 determines that the activation signal does not exceed the voltage threshold level (e.g., block 905 returns a NO result), control returns to block 905, where regulator 505 obtains the activation signal.

[0119] If regulator 505 determines (e.g., block 905 returns a YES result) that the activation signal exceeds the voltage threshold level (e.g., the activation signal meets, satisfies, or is greater than the voltage threshold level), regulator 505 enables and regulates first stage 510 (block 910). In some examples, regulator 505 provides a first trigger signal at first output terminal 524 (e.g., to first terminal 636 of switching circuit 633) to enable first stage 510. First stage 510 obtains the first trigger signal. First stage 510 provides a first control signal at output terminal 534 in response to the first trigger signal. Thus, transistor 150 is enabled (e.g., conducts) with a current provided by first voltage supply node 516.

[0120] In some examples, regulator 505 may be adapted to regulate first stage 510 in response to a voltage signal obtained at node 539 by providing and / or varying a regulation signal at second output terminal 526. For example, if linear regulator circuit 603 determines that the voltage at second input terminal 522 (at node 539, control terminal 172, etc.) exceeds a voltage threshold (such as VCLAMP provided by clamp voltage supply node 605), linear regulator circuit 603 and / or transistor 604 may regulate the voltage at node 539. As such, the signal provided to current mirror circuit 634 may vary (e.g., decrease). In some examples, regulator 505 may be adapted to regulate the voltage at control terminal 172, second input terminal 522, etc. by providing a regulation signal at second output terminal 526. Regulator 505 may adjust the output (e.g., the first control signal) provided by first stage 510 so that the output at node 539 to control terminal 172 does not exceed normal operating conditions for an extended period of time and / or damage transistor 150.

[0121] Regulator 505 receives a voltage signal (e.g., the voltage at node 539 and / or the voltage at control terminal 172) at second input terminal 522. If regulator 505 determines that the voltage signal exceeds a threshold value (e.g., VCLAMP provided by clamp voltage supply node 605) for a certain period of time (e.g., block 925 returns a YES result), regulator 505 disables first stage 510 (block 930). Regulator 505 then enables second stage 515 (block 940). For example, if comparator circuit 602 determines that the output of linear regulator circuit 603 is activated (e.g., enabled, providing an output) for a certain period of time, comparator circuit 602 may provide a logic low value to second input terminal 617 of logic gate 601 and may provide a second trigger signal at third output terminal 528 to second stage 515.

[0122] Therefore, logic gate 601 changes (e.g., decreases) the first trigger signal provided to first input terminal 530 of first stage 510, and switching circuit 633 is disabled. Therefore, current mirror circuit 634 changes the first control signal (e.g., decreases the first control signal, or ceases providing the first control signal). Also, in response to the second trigger signal, transistor 635 of second stage 515 is enabled and provides the second control signal to control terminal 172. Therefore, transistor 150 is enabled by second stage 515. If regulator 505 determines that the voltage signal (e.g., the voltage at control terminal 172) does not exceed the threshold voltage level for a certain period of time (e.g., block 925 returns a NO result), regulator 505 enables and regulates first stage 510 (block 910).

[0123] FIG. 10 is a schematic diagram of an example simulation bench 1000 (e.g., a test bench, a circuit, etc.) of a driver in a power converter (e.g., driver 105 of FIGS. 5, 6, 7A, 7B, and / or 8, driver 205 of FIG. 2, driver 305 of FIG. 3, driver 402 of FIG. 4, etc.). Simulation bench 1000 may be used to verify the functionality of a driver, such as driver 105 of FIG. 1, to enable a transistor model using multiple stages, such as first stage 510 and second stage 515 of FIG. 5. In some examples, as described below in connection with FIGS. 11-14, simulation bench 1000 may demonstrate advantages of driver 105 of FIGS. 5, 6, 7A, 7B, and / or 8 over driver 205 of FIG. 2, driver 305 of FIG. 3, and / or driver 402 of FIG. 4. The simulation bench 1000 includes a capacitor 1005, a first voltage supply node 1010, a resistor (Rdrv) 1012, a second voltage source 1015, a driver 1020 (e.g., driver 105 of FIGS. 1, 5, 6, 7A, 7B, and / or 8, driver 205 of FIG. 2, driver 305 of FIG. 3, driver 402 of FIG. 4), a third voltage source 1035, a first inductor 1040, a transistor model 1045, a diode 1050, a second inductor 1055, a current source 1060, a fourth voltage source (VBUS) 1065, and a ground node 1070. The driver 1020 includes an output terminal 1072. 10, first voltage supply node 1010 provides 12 volts to represent first voltage supply node 516, and second voltage supply node 1015 provides 6 volts to represent second voltage supply node 518. However, any of the voltage sources / voltage supply nodes 1010, 1015, 1035, 1065 may provide any suitable voltage. In the example of FIG. 10, the clamp voltage source is generated within driver 1020, and therefore clamp voltage supply node 605 is included within driver 1020.

[0124] A capacitor 1005 is coupled between a first voltage supply node 1010 and a first inductor 1040. A resistor (Rdrv) 1012 is coupled between the driver 1020 and the first inductor 1040. In some examples, the impedance of the resistor 1012 may affect the amplitude of a current provided by a current source in the driver, such as the current source 632 in the driver 105 of FIG. 6. In some examples, the resistor (Rdrv) 1012 may adjust a fast pull-up gate drive current (e.g., IDRV, the current provided by the first stage 510) to set the slew rate of a transistor 1074 included in the transistor model 1045. A second voltage source 1015 is coupled between the driver 1020 and the first inductor 1040. The first inductor 1040 is coupled between the driver 1020 and a ground node 1070. 5. The driver 1020 is adapted to be coupled to the first voltage supply node 1010 and the second voltage supply 1015. The driver 1020 is adapted to receive an activation signal (e.g., signal IN) and to provide (e.g., output) one or more control signals to enable the transistor model 1045. In some examples, the first voltage supply node 1010 may be the first voltage supply node 516 of FIG. 5, and the second voltage supply 1015 may be the second voltage supply node 518 of FIG. 5.

[0125] A third voltage supply node 1035 is coupled between the driver 1020 and the transistor model 1045. In some examples, the third voltage supply node 1035 may represent a voltage applied to a gate of a transistor, such as a control terminal of a transistor included in the transistor model 1045. In some examples, as described below in connection with FIGS. 11 , 12 , 13 , and / or 14 , the third voltage supply node 1035 may shift the gate voltage (e.g., the voltage at the control terminal of the transistor 1074) to vary the headroom provided by the driver 1020 and to determine the effect of the headroom on the gate current and slew rate of the transistor 1074. In some examples, a more negative voltage shift by the third voltage supply node 1035 may cause the gate voltage of the transistor 1074 (V gs ), so that, as noted above in Equation 1, driver 1020 can provide more headroom to transistor 1074 through a continuous supply source voltage (such as first voltage source node 1010, first voltage source node 516 in FIG. 5 ). Voltage shifting through third voltage source 1035 (e.g., a way to obtain headroom for transistor 1074) can be difficult (and in some cases, impossible) to implement. However, voltage shifting can be achieved using simulation test bench 1000 to demonstrate example performance of driver 1020.

[0126] The exemplary transistor model 1045 includes a transistor 1074, a third inductor 1075, a fourth inductor 1076, and a fifth inductor 1078. In the example of FIG. 10, the transistor 1074 is an NMOS transistor. The transistor 1074 includes a control terminal 1080, a drain terminal 1082, and a source terminal 1084. The third inductor 1075 is coupled between the third voltage supply node 1035 and the control terminal 1080, the fourth inductor 1076 is coupled between the drain terminal 1082 and the diode 1050, and the fifth inductor 1078 is coupled between the source terminal 1084 and the ground node 1070. In some examples, the transistor model 1045 may represent a transistor such as the transistor 150 of FIG. 1. As such, the inductors 1075, 1076, and 1078 may represent internal inductances in the transistor 150. For example, the third inductor 1075 may represent the gate inductance of the transistor 1074 , the fourth inductor 1076 may represent the drain inductance of the transistor 1074 , and the fifth inductor 1078 may represent the source inductance of the transistor 1074 .

[0127] 10 , a diode 1050 is coupled between a fourth inductor 1076 and a second inductor 1055. In some examples, the diode 1050 may limit current flow toward the drain terminal 1082. A current source node 1060 is coupled between the fourth inductor 1076 and a ground node 1070. The second inductor 1055 is coupled between the diode 1050 and a fourth voltage source node 1065. The fourth voltage source node 1065 is coupled between the second inductor 1055 and the ground node 1070. In some examples, the fourth voltage source node 1065 may provide a signal (such as a voltage VBUS) to represent a voltage to supply to a power converter including the driver 1020, such as the bus voltage node 140 of FIG. 1 .

[0128] 11 is a signal plot 1100 illustrating a first current signal of a first transistor enabled by a first driver and a second current signal of a second transistor enabled by a second driver at various voltage offsets (e.g., transistor headroom) in a power conversion system. The signal plot 1100 of FIG. 11 includes a first example current signal (line 1105) and a second example current signal (line 1110). In FIG. 11, the first current signal (line 1105) may represent the current provided to the control terminal of transistor 210, 310, 404 by driver 205, 305, 402 of FIGS. 2, 3, and / or 4, such as control terminal 436 of transistor 404 by driver 402 of FIG. 4, and the second current signal (line 1110) may represent the current provided to control terminal 172 of transistor 150 by driver 105 of FIGS. 5, 6, 7A, 7B, and / or 8.

[0129] Signal plot 1100 illustrates a current that may be applied to (e.g., adapted to enable, provided to, acquired by, etc.) a control terminal of a transistor with various voltage headroom provided at the control terminal. For example, a second current signal (line 1110) illustrates the voltage at control terminal 172 of transistor 150, at which current may be provided to control terminal 172 to enable transistor 150. A voltage offset may be applied to a transistor (e.g., transistor 1074) at a source voltage (e.g., a voltage provided by third voltage source 1035). Thus, the voltage offset provided at the control terminal determines the headroom of the transistor. In the example of FIG. 11, a more negative headroom value (e.g., voltage offset) indicates additional headroom provided to the transistor compared to a less negative headroom value.

[0130] At a first example voltage offset 1120 of −3.48 volts, the first current signal (line 1105) is 750 milliamps and the second current signal (line 1110) is 800 milliamps. At a second example voltage offset 1130 of −2.4 volts, the first current signal (line 1105) is 650 milliamps and the second current signal (line 1110) is 800 milliamps. At a third example voltage offset 1140 of −1.2 volts, the first current signal (line 1105) is 500 milliamps and the second current signal (line 1110) is 725 milliamps. In this manner, signal plot 1100 shows that the current applied to the control terminal of a transistor (e.g., transistor 150) associated with the second current signal (line 1110) can be greater than the current applied to the transistor associated with the first current signal (line 1105), even if the voltage headroom is the same. Therefore, a driver associated with the second current signal (line 1110), such as driver 105, can provide a greater gate drive current to the coupled transistor than a driver associated with the first current signal (line 1105), such as when the transistor has a voltage offset of 0 volts. Signal plot 1100 also shows that the gate current that can be provided by driver 105 is less sensitive to the headroom of transistor 150 than a driver represented by the first current signal (line 1105), such as drivers 205, 305, and 402.

[0131] FIG. 12 is a signal plot 1200 illustrating a first slew rate of a transistor enabled by a first driver and a second slew rate of a transistor enabled by a second driver at various voltage offsets (e.g., transistor headroom) in a power conversion system. The signal plot 1200 of FIG. 12 includes a first example slew rate (line 1205) and a second example slew rate (line 1210). In FIG. 12, the first slew rate (line 1205) may represent a slew rate associated with a transistor, such as a change in voltage at the drain terminal 438 of transistor 404 when transistor 404 is enabled by driver 402 of FIG. 4. The first slew rate (line 1205) may also represent a slew rate associated with transistor 210 when enabled by driver 205 of FIG. 2 and / or transistor 310 when enabled by driver 305 of FIG. 3. Similarly, in FIG. 12, the second slew rate (line 1210) may represent a slew rate associated with a transistor, such as the change in voltage at drain terminal 176 of transistor 150 when transistor 150 is enabled by driver 105 of FIGS. 5, 6, 7A, 7B, and / or 8.

[0132] Signal plot 1200 illustrates slew rates that may be associated with a control terminal of a transistor with various voltage offsets provided at the control terminal. For example, the second slew rate (line 1210) may illustrate the change in voltage over time at drain terminal 176 of transistor 150 as the transistor is enabled (activated, transitioned to an on state, etc.) by driver 105. The voltage offset may be applied to a transistor (e.g., transistor 1074) via a voltage source node (e.g., third voltage source 1035). Thus, the voltage offset provided at the control terminal determines the headroom of the transistor. In the example of FIG. 12, a more negative headroom value (e.g., voltage offset) indicates additional headroom provided to the transistor compared to a less negative headroom value.

[0133] For a first example voltage offset 1220 of −3.6 volts, the first slew rate (line 1205) is 142.5 volts per nanosecond and the second slew rate (line 1210) is 130 volts per nanosecond. For a second example voltage offset 1230 of −2.8 volts, the first slew rate (line 1205) is 130 volts per nanosecond and the second slew rate (line 1210) is 133 volts per nanosecond. For a third example voltage offset 1240 of −1 volt, the first slew rate (line 1205) is 105 volts per nanosecond and the second slew rate (line 1210) is 127 volts per nanosecond. Thus, signal plot 1200 shows that, with the same voltage headroom, the slew rate (e.g., change in voltage at the drain terminal over a period of time) of a transistor (e.g., transistor 150) associated with the second slew rate (line 1210) can be greater than the slew rate of a transistor associated with the first slew rate (line 1205). Therefore, the driver associated with the second slew rate (line 1210) may enable a greater slew rate for the associated transistor than the driver associated with the first slew rate (line 1205) by providing a greater gate drive current to the transistor, such as when the transistor's voltage offset is 0 volts. Signal plot 1200 also illustrates that the slew rate of driver 105 is less sensitive to headroom than drivers represented by the first slew rate (line 1205), such as drivers 205, 305, and 402.

[0134]

[0013] Figure 13 is a signal plot 1300 illustrating a first current signal of a transistor enabled by a first driver and a second current signal of a second transistor enabled by a second driver at various driver resistances in a power conversion system. The signal plot 1300 of Figure 13 includes a first example current signal (line 1305) and a second example current signal (line 1310). In Figure 13, the first current signal (line 1305) may represent a current provided to a control terminal of a transistor 210, 310, 404 by a driver 205, 305, 402 of Figures 2, 3, and / or 4, such as the control terminal 436 of transistor 404 by driver 402 of Figure 4, and the second current signal (line 1310) may represent a current provided to the control terminal 172 of transistor 150 by driver 105 of Figures 5, 6, 7A, 7B, and / or 8.

[0135] Signal plot 1300 illustrates a current that may be applied to a control terminal of a transistor with various impedances (e.g., resistances) of a resistor (Rdrv) coupled to a driver. The resistor (e.g., resistor 1012 in FIG. 10) may proportionally affect the current provided by a current source (e.g., current source 632 in FIG. 6) in the driver. For example, a second current signal (line 1310) may illustrate a current provided to control terminal 172 to enable transistor 150. In another example, the resistor impedance may be the impedance of resistor 1012 in FIG. 10, which controls the value of the current provided by a current source node (IDRV) included in driver 1020. In some examples, adjusting resistor (Rdrv) 1012 may adjust a control signal provided by driver 1020 (e.g., a control current, a first control signal provided by first stage 510, etc.) and / or adjust the slew rate of transistor 1074.

[0136] For a first example resistor 1320 of 20 kilohms, the first current signal (line 1305) is 175 milliamps and the second current signal (line 1310) is 410 milliamps. For a second example resistor 1330 of 60 kilohms, the first current signal (line 1305) is 150 milliamps and the second current signal (line 1310) is 225 milliamps. For a third example resistor 1340 of 90 kilohms, the first current signal (line 1305) is 120 milliamps and the second current signal (line 1310) is 150 milliamps. Thus, signal plot 1300 shows that, for the same resistance (e.g., driver resistance value), the current applied to the control terminal of the transistor (e.g., transistor 150) associated with the second current signal (line 1310) can be greater than the current applied to the control terminal of the transistor associated with the first current signal (line 1305). Therefore, with a lower resistive impedance, the headroom of the driver associated with the second current signal (line 1310) is not limited and can provide a higher gate drive current than the driver associated with the first current signal (line 1305). Signal plot 1300 also shows that driver 105 can supply a larger gate current when a higher slew rate is desired (e.g., when the impedance of resistor 1012 is reduced as demand on driver 105 increases) compared to a driver associated with the first current signal (line 1305), such as drivers 205, 305, 402.

[0137] 14 is a signal plot illustrating a first slew rate of a transistor enabled by a first driver and a second slew rate of a transistor enabled by a second driver at various driver resistances in a power conversion system. Signal plot 1400 of FIG. 14 includes a first example slew rate (line 1405) and a second example slew rate (line 1410). In FIG. 14, the first slew rate (line 1405) may represent a slew rate associated with a transistor, such as a change in voltage at drain terminal 438 of transistor 404 when transistor 404 is enabled by driver 402 of FIG. 4. Also, the first slew rate (line 1205) may represent a slew rate associated with transistor 210 when enabled by driver 205 of FIG. 2 and / or transistor 310 when enabled by driver 305 of FIG. 3. Similarly, in FIG. 14, the second slew rate (line 1410) may represent a slew rate associated with a transistor, such as the change in voltage at drain terminal 176 of transistor 150 when transistor 150 is enabled by driver 105 of FIGS. 5, 6, 7A, 7B, and / or 8.

[0138] Signal plot 1400 illustrates a slew rate that may be associated with a drain terminal at various impedances (e.g., resistances) of a resistor (Rdrv) coupled to a driver. The resistor (e.g., resistor 1012 in FIG. 10) may proportionally affect the current provided by a current source (e.g., current source 632 in FIG. 6) in the driver. For example, a second slew rate (line 1410) may illustrate the change in voltage over time at drain terminal 176 of transistor 150 as the transistor is enabled. In another example, the resistor impedance may be the impedance of resistor 1012 in FIG. 10, which controls the value of the current provided by a current source node (IDRV) included in driver 1020.

[0139] For a first example resistor 1420 at 20 kilohms, the first slew rate (line 1405) is 70 volts per nanosecond and the second slew rate (line 1410) is 100 volts per nanosecond. For a second example resistor 1430 at 60 kilohms, the first slew rate (line 1405) is 52 volts per nanosecond and the second slew rate (line 1410) is 63 volts per nanosecond. For a third example resistor 1440 at 90 kilohms, the first slew rate (line 1405) is 43 volts per nanosecond and the second slew rate (line 1410) is 50 volts per nanosecond. Thus, signal plot 1400 shows that, for the same resistance (e.g., driver resistance value), the current applied to the control terminal of a transistor (e.g., transistor 150) associated with the second slew rate (line 1410) can be greater than the current applied to the control terminal of a transistor associated with the first slew rate (line 1405). Therefore, the driver associated with the second slew rate (line 1410) can enable a greater slew rate for the associated transistor than the driver associated with the first slew rate (line 1405) by providing a greater gate drive current to the transistor, such as when the transistor's voltage offset is 0 volts. Signal plot 1400 also shows that driver 105 can enable a higher slew rate for transistor 150 when desired (e.g., when the impedance of resistor 1012 is reduced as demand on driver 105 increases) compared to a driver associated with the first slew rate (line 1405), such as drivers 205, 305, 402.

[0140] FIG. 15 is an example signal plot 1500 illustrating control signals and output signals of the example power converter 100 of FIG. 1 during operation for driving a transistor, such as transistor 150 of FIG. 1. The signal plot 1500 of FIG. 15 includes a first representation 1502, a second representation 1504, a third representation 1506, a fourth representation 1508, a fifth representation 1510, and a sixth representation 1512. The first representation 1502 includes an activation signal (line 1520), which may represent a voltage at the input terminal 156 of the driver 105 of FIG. 1 and / or FIGS. 5-8. The second representation 1504 includes a first trigger signal (line 1522), which may represent a voltage at the first output terminal 524 of the regulator 505. The third representation 1506 includes a regulation signal (line 1524) that may represent the current provided by the regulator 505 (e.g., the current through transistor 604) at the second output terminal 526. The fourth representation 1508 includes a second trigger signal (line 1526) that may represent the voltage at the regulator's third output terminal 528.

[0141] The fifth representation 1510 includes an output signal (line 1528) that may represent the voltage at the regulator's output terminal 158 and / or the voltage at the control terminal 172 of transistor 150. The output signal (line 1528) may also represent a first control signal provided by the first stage 510 at output terminal 534 and / or a second control signal provided by the second stage 515 at output terminal 538. The sixth representation 1512 includes a drain signal (line 1530) that may represent the voltage at the drain terminal 176 of transistor 150. In the example signal plot 1500 of FIG. 15 , the voltage or current magnitude of any of the signals (lines 1520, 1522, 1524, 1526, 1528, 1530) may be any suitable value.

[0142] At a first example time 1550, the controller 120 increases the activation voltage signal (line 1520) to a logic high value of 5 volts. However, the logic high value may be any suitable magnitude, such as 6 volts. In response to the increase in the activation voltage signal (line 1520), the regulator 505 increases the first trigger signal (line 1522) to 5 volts. In response to the increase in the first trigger signal (line 1522), the first stage 510 provides a first control signal at the output terminal 534, which results in an increase in the output signal at the output terminal 158. In response to the increase in the voltage of the output signal (line 1528) (e.g., in response to an increase in the voltage signal acquired at the second input terminal 522), the regulator 505 provides a regulation signal (line 1524) at the second output terminal 526.

[0143] At a second example time 1560, the first stage 510 increases the output signal (line 1528) to the voltage of the clamp voltage supply node (VCLAMP) 605, and the regulator 505 increases the regulation signal (line 1524) to a value I_REG. Thus, the regulator 505 regulates a first control signal (e.g., the output signal (line 1528)) by providing the regulation signal (line 1524). The regulation signal value I_REG may be any suitable current value, such as 1 ampere. In response to the output signal (line 1528) at the control terminal 172 exceeding a threshold voltage (e.g., exceeding the voltage of VDRV and / or the voltage of VCLAMP), the transistor 150 transitions to an enabled state. Thus, the source terminal 174 and the drain terminal 176 are electrically connected, and the drain signal (line 1530) decreases from the value of VBUS. 15, the magnitude of VBUS may be any suitable voltage. For example, VBUS may represent the voltage value of bus voltage node (VIN) 140, or VBUS may represent a voltage of 10 volts.

[0144] In response to the increase in the output signal (line 1528) and therefore the increase in the voltage signal obtained at the second input terminal 522, the linear regulator circuit 603 reduces the output signal at the output terminal 620. As a result, the comparator circuit 602 obtains the output signal of the linear regulator circuit 603 at the input terminal 629 and delays it for an exemplary time period (t_delay) 1565. The length of the time period 1565 can be any suitable time period (e.g., 10 nanoseconds), and the filter circuit including resistor 766 and capacitor 768 controls the length of the time period 1565. In the example of FIG. 15 , the drain signal (line 1530) reduces to 0 volts during the time period 1565. However, the drain signal (line 1530) may reduce to any suitable voltage, such as 1 volt. The drain signal (line 1530) may also reduce to an appropriate voltage (e.g., 0 volts, 1 volt) before or after the time period 1565.

[0145] After a time period 1565 controlled by the comparator circuit 602 (e.g., controlled by resistor 766 and capacitor 768), and at a third example time 1570, the regulator 505 reduces the first trigger signal (line 1522) and the regulation signal (line 1524) to 0 volts, respectively, and the regulator 505 reduces the second trigger signal (line 1526) to a value of VDRV-5V. In some examples, the voltage at the second voltage supply node (VDRV) 518 may be 6 volts, and therefore the value of VDRV-5V may be 1 volt. In response to the reduction of the first trigger signal (line 1522), the first stage 510 reduces the first control signal at output terminal 534 (e.g., ceases providing the first control signal), and in response to the reduction of the second trigger signal (line 1526), ​​the second stage 515 increases the second control signal at output terminal 538. As a result, the output signal (line 1528) at output terminal 158 and control terminal 172 of transistor 150 reduces from the voltage of the clamp voltage supply node (VCLAMP) 605 to the voltage of the second voltage supply node (VDRV) 518. As a result of the reduction of the output signal (line 1528), transistor 150 is enabled, so that the drain signal (line 1530) remains at 0 volts.

[0146] At a fourth example time 1580, the controller 120 reduces the activation signal (IN) (line 1520) to 0 volts. In response to the reduction in the activation signal (line 1520), the regulator 505 increases the second trigger signal (line 1526) to a voltage of VDRV. As a result, the second stage 515 reduces the second control signal, so that the output signal (line 1528) reduces to 0 volts. As a result, the transistor 150 is disabled, and the drain signal (line 1530) increases to the voltage of VBUS.

[0147] Exemplary methods, apparatus, systems, and articles of manufacture for driving transistors are described herein. Further examples and combinations thereof include:

[0148] Example 1 includes an apparatus including a regulator, a first stage, and a second stage, wherein the regulator includes a first input terminal adapted to be coupled to a control terminal of a transistor, a first output terminal, and a second output terminal, the first stage includes a first input terminal coupled to the first output terminal of the regulator and an output terminal adapted to be coupled to the control terminal of the transistor, and the second stage includes an input terminal coupled to the second output terminal of the regulator and an output terminal adapted to be coupled to the control terminal of the transistor.

[0149] Example 2 includes the apparatus of Example 1, wherein the regulator includes a second input terminal and a logic gate, the logic gate including a first input terminal coupled to the second input terminal of the regulator, a second input terminal coupled to the comparator circuit, and an output terminal coupled to the first output terminal of the regulator.

[0150] Example 3 includes the apparatus of Example 1, wherein the regulator includes a comparator circuit having an input terminal coupled to the linear regulator circuit, a first output terminal coupled to the second output terminal of the regulator, and a second output terminal coupled to the logic gate.

[0151] Example 4 includes the apparatus of Example 1, wherein the transistor is a first transistor, and the regulator includes a third output terminal, a linear regulator circuit, and a second transistor, the linear regulator circuit including an output terminal, a first input terminal adapted to be coupled to a voltage source, and a second input terminal coupled to the first input terminal of the regulator, and the second transistor including a control terminal coupled to the output terminal of the linear regulator circuit, a first current terminal adapted to be coupled to the voltage source, and a second current terminal coupled to the third output terminal of the regulator.

[0152] Example 5 includes the apparatus of example 4, wherein the first stage includes a second input terminal coupled to the third output terminal of the regulator.

[0153] Example 6 includes the apparatus of Example 4, wherein the linear regulator circuit includes a second transistor, a third transistor, and a fourth transistor, the second transistor including a control terminal, a first current terminal coupled to the first input terminal of the linear regulator circuit, and a second current terminal coupled to the control terminal of the second transistor, the third transistor including a control terminal coupled to the control terminal of the second transistor and adapted to be coupled to a ground node, a first current terminal coupled to the second input terminal of the linear regulator circuit, and a second current terminal, and the fourth transistor including a control terminal coupled to the second current terminal of the third transistor and adapted to be coupled to the ground node, a first current terminal adapted to be coupled to the ground node, and a second current terminal coupled to an output terminal of the linear regulator circuit.

[0154] Example 7 includes the apparatus of example 4, wherein the linear regulator circuit includes a second transistor. The second transistor includes a control terminal coupled to the second input terminal of the linear regulator circuit, a first current terminal coupled to the first input terminal of the linear regulator circuit, and a second current terminal coupled to the output terminal of the linear regulator circuit.

[0155] Example 8 includes the apparatus of Example 1, wherein the transistor is a first transistor, the first stage includes a switching circuit and a first current mirror circuit adapted to be coupled to the voltage source node, the switching circuit including a first terminal coupled to the input terminal of the first stage, a second terminal adapted to be coupled to the current source, and a third terminal, and the first current mirror circuit including a first terminal coupled to the third terminal of the switching circuit and a second terminal coupled to the output terminal of the first stage.

[0156] Example 9 includes the apparatus of Example 8, wherein the first stage includes a second current mirror circuit coupled between the second terminal of the first current mirror circuit and the control terminal of the first transistor, the second current mirror circuit including a first terminal coupled to the second terminal of the first current mirror circuit and a second terminal adapted to be coupled to the control terminal of the first transistor.

[0157] Example 10 includes the apparatus of Example 9, wherein the second current mirror circuit includes a third transistor and a fourth transistor, the third transistor includes a control terminal coupled to the first terminal of the second current mirror circuit, a first current terminal coupled to the second terminal of the second current mirror circuit, and a second current terminal coupled to the first terminal of the second current mirror circuit, and the fourth transistor includes a control terminal coupled to the control terminal of the third transistor, a first current terminal coupled to the second terminal of the second current mirror circuit, and a second current terminal adapted to be coupled to the voltage supply node.

[0158] Example 11 includes the apparatus of Example 8, wherein the current mirror circuit includes a third transistor and a fourth transistor, the third transistor including a control terminal coupled to the first terminal of the current mirror circuit, a first current terminal adapted to be coupled to the voltage supply node, and a second current terminal coupled to the first terminal of the current mirror circuit, and the fourth transistor including a control terminal coupled to the control terminal of the third transistor, a first current terminal adapted to be coupled to the voltage supply node, and a second current terminal coupled to the second terminal of the current mirror circuit.

[0159] Example 12 includes the apparatus of Example 8, wherein the switching circuit includes a third transistor. A first terminal of the switching circuit is coupled to the first output terminal of the regulator, a second terminal of the switching circuit is coupled to the first current terminal of the third transistor, and a third terminal of the switching circuit is coupled to the second current terminal of the third transistor.

[0160] Example 13 includes the apparatus of Example 1, wherein the transistor is a first transistor and the second stage includes a second transistor having a control terminal coupled to the input terminal of the second stage, a first current terminal adapted to be coupled to the voltage supply node, and a second current terminal coupled to the output terminal of the second stage.

[0161] Example 14 includes an apparatus including a first stage, a second stage, and a regulator. The first stage includes an input terminal and an output terminal adapted to be coupled to a control terminal of a transistor and is adapted to enable the transistor using a first voltage from a first voltage source. The second stage includes an input terminal and an output terminal adapted to be coupled to the control terminal of the transistor and is adapted to enable the transistor using a second voltage from a second voltage source, the first voltage having a potential greater than the second voltage. The regulator includes a first input terminal adapted to be coupled to the control terminal of the transistor, a second input terminal, a first output terminal coupled to the input terminal of the first stage, and a second output terminal coupled to the input terminal of the second stage, and the regulator is adapted to enable the first stage based on an activation signal obtained at the second input terminal of the regulator exceeding a first threshold voltage level, and to enable the second stage based on a voltage signal at the first input terminal of the regulator exceeding a second threshold voltage level for a period of time.

[0162] Example 15 includes the apparatus of example 14, wherein the regulator includes a third output terminal. The regulator is adapted to regulate the voltage at the first input terminal by providing a regulation signal at the third output terminal of the regulator.

[0163] Example 16 includes the apparatus of Example 14, wherein the regulator is adapted to enable the first stage by providing a first trigger signal at a first output terminal of the regulator.

[0164] Example 17 includes the apparatus of Example 16, wherein the first stage is adapted to enable the transistor by providing a first control signal at an output terminal of the first stage based on the first trigger signal exceeding a third threshold voltage level.

[0165] Example 18 includes the apparatus of Example 14, wherein the regulator is adapted to be coupled to a clamp voltage source, and the regulator is adapted to disable the first stage based on the voltage signal at the first input terminal exceeding a voltage of the clamp voltage source.

[0166] Example 19 includes the apparatus of example 14, wherein the regulator is adapted to enable the second stage by providing a second trigger signal at a second output terminal of the regulator.

[0167] Example 20 includes the apparatus of Example 19, wherein the second stage is adapted to enable the transistor by providing a second control signal at the output terminal of the second stage based on the second trigger signal exceeding a third threshold voltage level.

[0168] Example 21 includes the apparatus of Example 14, wherein the transistor is a first transistor and the first stage includes a switching circuit including a first terminal coupled to the first input terminal of the first stage, a second terminal adapted to be coupled to the current source, and a third terminal, the switching circuit adapted to provide the mirror signal at the third terminal of the switching circuit based on the first trigger signal exceeding a third threshold voltage level.

[0169] Example 22 includes the apparatus of Example 21, wherein the transistor is a first transistor, and the first stage includes a current mirror circuit adapted to be coupled to the voltage supply node, the current mirror circuit including a first terminal coupled to the third terminal of the switching circuit and a second terminal coupled to the output terminal of the first stage, the current mirror circuit adapted to provide a first control signal at the second terminal of the current mirror circuit based on the mirror signal.

[0170] Example 23 includes the apparatus of Example 14, wherein the regulator is adapted to output a first trigger signal at the first output terminal in response to the activation signal exceeding a first threshold voltage level, and to output a second trigger signal at the second output terminal in response to the voltage signal exceeding a second threshold voltage level for a period of time.

[0171] Example 24 includes a system including a driver including an input terminal adapted to receive an activation signal and an output terminal, and a transistor including a control terminal coupled to the output terminal of the driver, wherein the driver is adapted to output a first control signal having a first voltage to the control terminal of the transistor and a second control signal having a second voltage to the control terminal of the transistor, the first voltage having a potential greater than the second voltage.

[0172] Example 25 includes the system of Example 24, wherein the driver includes a regulator. The regulator includes a first input terminal coupled to the input terminal of the driver, a second input terminal coupled to the control terminal of the transistor, a first output terminal, and a second output terminal, and the regulator is adapted to output a first trigger signal at the first output terminal of the regulator based on an activation signal obtained at the first input terminal of the regulator exceeding a first threshold voltage level, and to output a second trigger signal at the second output terminal of the regulator based on a voltage signal obtained at the second input terminal of the regulator exceeding a second threshold voltage level.

[0173] Example 26 includes the system of example 25, wherein the regulator includes a third output terminal, and the regulator is adapted to regulate the voltage at the input terminal of the regulator by providing a regulation signal at the third output terminal of the regulator.

[0174] Example 27 includes the system of Example 24, wherein the driver includes a first stage including an input terminal and an output terminal coupled to the control terminal of the transistor, the first stage adapted to output the first control signal at the output terminal of the first stage based on a trigger signal obtained at the input terminal of the first stage exceeding a threshold voltage level.

[0175] Example 28 includes the system of Example 24, wherein the driver includes a second stage. The second stage includes an input terminal and an output terminal coupled to the control terminal of the transistor, the second stage adapted to output a second control signal at the output terminal of the second stage based on a trigger signal obtained at the input terminal of the second stage exceeding a threshold voltage level.

[0176] From the foregoing, it will be appreciated that exemplary methods, apparatus, and articles of manufacture for driving transistors have been described. The described methods, apparatus, and articles of manufacture increase the efficiency of using computing devices by enabling drivers in power conversion systems to drive transistor gates from an off-state to an on-state using a signal that is higher than the on-state gate signal. Thus, the described methods, apparatus, and articles of manufacture result in one or more improvements in the functionality of a computer.

[0177] Although certain exemplary methods, apparatus, and articles of manufacture have been described herein, the scope of application of this application is not limited thereto. Rather, this application covers all methods, apparatus, and articles of manufacture that fairly fall within the scope of the claims of this application.

[0178] The following claims are hereby incorporated by reference into this detailed description, with each claim standing on its own as a separate embodiment of this description.

Claims

1. 1. An apparatus comprising:

1. A regulator having a first input terminal adapted to be coupled to a control terminal of a first transistor, a first output terminal, and a second output terminal, a comparator circuit having an input, a first output coupled to the second output terminal, and a second output; a linear regulator circuit coupled to an input of the comparator circuit; a logic gate coupled to a second output of the comparator circuit; the regulator, a first stage having an input terminal coupled to a first output terminal of the regulator and an output terminal adapted to be coupled to a control terminal of the first transistor; a switching circuit having a first terminal coupled to the input terminal of the first stage, a second terminal adapted to be coupled to a current source, and a third terminal; a first current mirror circuit having a first terminal coupled to the third terminal of the switching circuit and a second terminal coupled to the output terminal of the first stage; the first stage comprising: a second stage having an input terminal coupled to the second output terminal of the regulator and an output terminal adapted to be coupled to the control terminal of the first transistor; 1. An apparatus comprising:

2. 10. The apparatus of claim 1, the regulator further having a second input terminal; the logic gate having a first input coupled to the second input terminal of the regulator, a second input coupled to the comparator circuit, and an output coupled to the first output terminal of the regulator.

3. 10. The apparatus of claim 1, The apparatus, wherein the first current mirror circuit is adapted to be coupled to a voltage supply node.

4. 4. The apparatus of claim 3, the first stage further includes a second current mirror circuit coupled between a second terminal of the first current mirror circuit and a control terminal of the first transistor, the second current mirror circuit having a first terminal coupled to the second terminal of the first current mirror circuit and a second terminal adapted to be coupled to the control terminal of the first transistor.

5. 5. The apparatus of claim 4, the second current mirror circuit a third transistor having a control terminal coupled to the first terminal of the second current mirror circuit, a first current terminal coupled to the second terminal of the second current mirror circuit, and a second current terminal coupled to the first terminal of the second current mirror circuit; a fourth transistor having a control terminal coupled to the control terminal of the third transistor, a first current terminal coupled to the second terminal of the second current mirror circuit, and a second current terminal adapted to be coupled to the voltage supply node; 1. An apparatus comprising:

6. 4. The apparatus of claim 3, The first current mirror circuit comprises: a third transistor having a control terminal coupled to the first terminal of the first current mirror circuit, a first current terminal adapted to be coupled to the voltage supply node, and a second current terminal coupled to the first terminal of the first current mirror circuit; a fourth transistor having a control terminal coupled to the control terminal of the third transistor, a first current terminal adapted to be coupled to the voltage supply node, and a second current terminal coupled to the second terminal of the first current mirror circuit; 1. An apparatus comprising:

7. 4. The apparatus of claim 3, the switching circuit includes a third transistor, a first terminal of the switching circuit coupled to a first output terminal of the regulator, a second terminal of the switching circuit coupled to a first current terminal of the third transistor, and a third terminal of the switching circuit coupled to a second current terminal of the third transistor.

8. 10. The apparatus of claim 1, the second stage includes a second transistor having a control terminal coupled to an input terminal of the second stage, a first current terminal adapted to be coupled to a voltage supply node, and a second current terminal coupled to an output terminal of the second stage.

9. 1. An apparatus comprising: a first stage having an input terminal and an output terminal adapted to be coupled to a control terminal of a first transistor, the first stage adapted to enable the first transistor with a first voltage from a first voltage source; a switching circuit having a first terminal coupled to the input terminal of the first stage, a second terminal adapted to be coupled to a current source, and a third terminal; a current mirror circuit having a first terminal coupled to the third terminal of the switching circuit and a second terminal coupled to the output terminal of the first stage; the first stage comprising: a second stage having an input terminal and an output terminal adapted to be coupled to a control terminal of the first transistor, the second stage adapted to enable the first transistor with a second voltage from a second voltage source, the first voltage having a potential greater than the second voltage; 1. A regulator having a first input terminal adapted to be coupled to a control terminal of the first transistor, a second input terminal, a first output terminal coupled to the input terminal of the first stage, and a second output terminal coupled to the input terminal of the second stage, coupled to a clamp voltage source; enabling the first stage based on an activation signal obtained at the second input terminal exceeding a first threshold voltage level; enabling the second stage based on the voltage signal at the first input terminal exceeding a second threshold voltage level for a period of time; disabling the first stage based on the voltage signal at the first input terminal exceeding the voltage of the clamp voltage source; the regulator adapted to 1. An apparatus comprising:

10. 10. The apparatus of claim 9, The apparatus, wherein the regulator further has a third output terminal, the regulator adapted to regulate a voltage at the first input terminal by providing a regulation signal to the third output terminal.

11. 10. The apparatus of claim 9, The apparatus, wherein the regulator is further adapted to enable the first stage by providing a first trigger signal to the first output terminal.

12. 12. The apparatus of claim 11, the first stage is further adapted to enable the first transistor by providing a first control signal to an output terminal of the first stage based on the first trigger signal exceeding a third threshold voltage level.

13. 10. The apparatus of claim 9, The apparatus, wherein the regulator is further adapted to enable the second stage by providing a second trigger signal at the second output terminal.

14. 14. The apparatus of claim 13, the second stage is further adapted to enable the first transistor by providing a second control signal to an output terminal of the second stage based on the second trigger signal exceeding a third threshold voltage level.

15. 10. The apparatus of claim 9, The apparatus, wherein the switching circuit is adapted to provide a mirror signal to a third terminal of the switching circuit based on the first trigger signal exceeding a third threshold voltage level.

16. 16. The apparatus of claim 15, The apparatus, wherein the current mirror circuit is coupled to a voltage supply node and adapted to provide a first control signal to a second terminal of the current mirror circuit based on the mirror signal.

17. 10. The apparatus of claim 9, The regulator outputting a first trigger signal at the first output terminal in response to the activation signal exceeding the first threshold voltage level; outputting a second trigger signal at the second output terminal in response to the voltage signal exceeding the second threshold voltage level during the time period; The apparatus is further adapted to:

18. 1. An apparatus comprising:

1. A regulator having a first input terminal coupled to a control terminal of a first transistor, a first output terminal, a second output terminal, and a third output terminal, a linear regulator circuit having an output, a first input adapted to be coupled to a voltage source, and a second input coupled to the first input terminal; a second transistor having a control terminal coupled to the output of the linear regulator circuit, a first current terminal adapted to be coupled to a voltage source, and a second current terminal coupled to the third output terminal; the regulator, a first stage having a first input terminal coupled to a first output terminal of the regulator and an output terminal adapted to be coupled to a control terminal of the first transistor; a second stage having an input terminal coupled to the second output terminal of the regulator and an output terminal adapted to be coupled to the control terminal of the first transistor; 1. An apparatus comprising:

19. 19. The apparatus of claim 18, the first stage further having a second input terminal coupled to a third output terminal of the regulator.

20. 19. The apparatus of claim 18, the linear regulator circuit a third transistor having a control terminal, a first current terminal coupled to the first input terminal of the linear regulator circuit, and a second current terminal coupled to the control terminal of the second transistor; a fourth transistor having a control terminal coupled to the control terminal of the second transistor and adapted to be coupled to a ground node, a first current terminal coupled to the second input terminal of the linear regulator circuit, and a second current terminal; a fifth transistor coupled to the second current terminal of the fourth transistor and having a control terminal adapted to be coupled to the ground node, a first current terminal adapted to be coupled to the ground node, and a second current terminal coupled to an output of the linear regulator circuit; 1. An apparatus comprising:

21. 19. The apparatus of claim 18, the linear regulator circuit includes a third transistor having a control terminal coupled to a second input of the linear regulator circuit, a first current terminal coupled to a first input of the linear regulator circuit, and a second current terminal coupled to an output of the linear regulator circuit.

22. 1. A power converter operable to provide power to a load, comprising: a first transistor having a first control terminal, a first current terminal coupled to a power supply, and a second current terminal; a second transistor having a second control terminal, a third current terminal coupled to the second current terminal, and a fourth current terminal coupled to a ground node; a driver having an output coupled to the second control terminal, providing a first voltage to the second control terminal to cause the second transistor to be in an off state during a first operating state; providing a second voltage to the second control terminal during a second operating state after the first operating state, the second voltage exceeding a maximum rated voltage for the second transistor to cause the second transistor to be in an on state; providing a third voltage to the second control terminal during a third operating state after the second operating state, the third voltage being less than a maximum rated voltage for the second transistor to cause the second transistor to be in an on state; the driver operable to: a power converter.

23. 23. The power converter of claim 22, The power converter wherein the first transistor is a GaN transistor.

24. 24. The power converter of claim 23, The power converter wherein the second transistor is a GaN transistor.

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