Photoelectric conversion device, imaging system and mobile object

Abstract

To provide a photoelectric conversion device with improved flexibility of layout.SOLUTION: A photoelectric conversion device includes: a first substrate having a first face; a plurality of photodiodes arranged in the first substrate and each having a first region that generates signal charges by photoelectrically converting incident light and a second region that receives the signal charges moving from the first region; a first isolation region arranged in the first substrate at a first depth and including a first portion extending in a first direction so as to isolate the second regions from each other; and a second isolation region arranged in the first substrate at a second depth deeper than the first depth from the first face, and including a second portion extending in a second direction intersecting the first direction in plan view so as to isolate the first regions from each other. The first and second portions partially overlap with each other in plan view.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device, an imaging system, and a moving object. [Background technology]

[0002] Avalanche diodes are known that can detect weak light at the single-photon level by utilizing avalanche (electron avalanche) multiplication. Patent Document 1 discloses an imaging device in which multiple avalanche diodes are arranged in one pixel.

[0003] Furthermore, image sensors with multiple photoelectric conversion units per pixel for image plane phase detection autofocus are known. In such image sensors, the accuracy of autofocus can be reduced when the subject has a striped pattern or other pattern that does not easily exhibit parallax. Patent Document 2 discloses a technology that improves focus detection accuracy by arranging focus detection pixels in two different directions. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-157387 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-53519 Summary of the Invention [Problem to be solved by the invention]

[0005] In a photoelectric conversion device using a photodiode as described in Patent Document 1 or Patent Document 2, the required function may differ depending on the position in the thickness direction of the semiconductor substrate on which the photodiode is formed. However, neither Patent Document 1 nor Patent Document 2 considers the relationship between the position in the thickness direction of the substrate and the function.

[0006] An object of the present invention is to provide a photoelectric conversion device, an imaging system, and a moving body that can optimize the structure of a photodiode by taking into account its position in the thickness direction of a substrate. [Means for solving the problem]

[0007] According to one aspect of the present invention, there is provided a photodiode array device including: a first substrate having a first surface; a first photoelectric conversion unit and a second photoelectric conversion unit disposed on the first substrate, each having an avalanche photodiode; an isolation region provided between the first photoelectric conversion unit and the second photoelectric conversion unit; the first photoelectric conversion unit and the second photoelectric conversion unit Each of teeth, the semiconductor device is defined by a portion surrounded by the isolation region and includes a first semiconductor region provided at a first depth from the first surface, a second semiconductor region of a first conductivity type surrounding the first semiconductor region at the first depth, a third semiconductor region of a second conductivity type provided at a second depth from the first surface that is deeper than the first depth, and a fourth semiconductor region provided at a third depth from the first surface that is shallower than the first depth, Detects light incident from the first surface side and transferring charges from the fourth semiconductor region to the third semiconductor region. It is configured to Record number the area of ​​the first photoelectric conversion unit and the area of ​​the second photoelectric conversion unit in a cross section at one depth; are different ,before Record number In the cross section of 2 depth And, the first photoelectric conversion unit and the second photoelectric conversion unit have the same length in the first direction, and the first photoelectric conversion unit and the second photoelectric conversion unit The length in the second direction intersecting with the first direction is the same. A photoelectric conversion device is provided. According to another aspect of the present invention, there is provided a photoelectric conversion device comprising: a first substrate having a first surface; a photoelectric conversion unit disposed on the first substrate and having an avalanche photodiode; an isolation region surrounding the photoelectric conversion unit; The photoelectric conversion unit comprises: the semiconductor device is defined by a portion surrounded by the isolation region and includes a first semiconductor region provided at a first depth from the first surface, a second semiconductor region of a first conductivity type surrounding the first semiconductor region at the first depth, a third semiconductor region of a second conductivity type provided at a second depth from the first surface that is deeper than the first depth, and a fourth semiconductor region provided at a third depth from the first surface that is shallower than the first depth, Detects light incident from the first surface side and transferring charges from the fourth semiconductor region to the third semiconductor region. It is configured to Record number The area of ​​the photoelectric conversion portion in the cross section at one depth is Record number A photoelectric conversion device having an area smaller than the area of ​​the photoelectric conversion section in a cross section at two depths is provided. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a photoelectric conversion device, an imaging system, and a moving body that can optimize the structure of a photodiode by taking into account its position in the thickness direction of a substrate. [Brief explanation of the drawings]

[0009] [Figure 1]1 is a cross-sectional view illustrating an avalanche diode according to a first embodiment. [Figure 2] FIG. 1 is a schematic plan view of an avalanche diode according to a first embodiment. [Figure 3] FIG. 2 is a potential diagram of the avalanche diode according to the first embodiment. [Figure 4] FIG. 2 is a plan view schematically illustrating an example of a pixel array. [Figure 5] FIG. 10 is a schematic plan view showing the separation portions superimposed. [Figure 6] FIG. 10 is a block diagram of a photoelectric conversion device according to a second embodiment. [Figure 7] FIG. 10 is a block diagram of a pixel according to a second embodiment. [Figure 8] 1A and 1B are a schematic plan view and a schematic cross-sectional view of an avalanche diode according to a second embodiment. [Figure 9] FIG. 10 is a schematic plan view showing the separation portions superimposed. [Figure 10] FIG. 10 is a cross-sectional view schematically illustrating a photoelectric conversion device according to a third embodiment. [Figure 11] FIG. 10 is a cross-sectional view schematically illustrating a photoelectric conversion device according to a fourth embodiment. [Figure 12] FIG. 10 is a block diagram of a photoelectric conversion device according to a fifth embodiment. [Figure 13] FIG. 11 is an equivalent circuit diagram of a pixel according to a fifth embodiment. [Figure 14] FIG. 10 is a plan view schematically illustrating a photodiode according to a fifth embodiment. [Figure 15] FIG. 10 is a cross-sectional view illustrating a photodiode according to a fifth embodiment. [Figure 16] FIG. 10 is a cross-sectional view illustrating a photodiode according to a fifth embodiment. [Figure 17] FIG. 10 is a cross-sectional view illustrating a photodiode according to a fifth embodiment. [Figure 18] FIG. 11 is a schematic plan view of a pixel according to a fifth embodiment. [Figure 19] FIG. 13 is a schematic diagram showing a first example of the arrangement of semiconductor regions according to the fifth embodiment. [Figure 20]FIG. 13 is a schematic diagram showing a second example of the arrangement of semiconductor regions according to the fifth embodiment. [Figure 21] FIG. 11 is a plan view schematically illustrating an example of pixel arrangement according to a fifth embodiment. [Figure 22] FIG. 13 is a schematic plan view of a pixel according to a sixth embodiment. [Figure 23] FIG. 13 is a plan view schematically illustrating an example of pixel arrangement according to the sixth embodiment. [Figure 24] FIG. 13 is a schematic plan view of a pixel according to a modified example of the sixth embodiment. [Figure 25] FIG. 13 is a schematic plan view of a pixel according to a seventh embodiment. [Figure 26] FIG. 13 is a schematic plan view of a pixel according to a modified example of the seventh embodiment. [Figure 27] FIG. 13 is a cross-sectional view illustrating an avalanche diode according to an eighth embodiment. [Figure 28] FIG. 13 is a schematic perspective view of an avalanche diode according to an eighth embodiment. [Figure 29] FIG. 13 is a schematic plan view of a photodiode according to a ninth embodiment. [Figure 30] FIG. 13 is a cross-sectional view illustrating a photodiode according to a ninth embodiment. [Figure 31] FIG. 22 is a plan view schematically illustrating a photodiode according to a tenth embodiment. [Figure 32] FIG. 22 is a cross-sectional view illustrating a photodiode according to a tenth embodiment. [Figure 33] FIG. 22 is a schematic perspective view of a photodiode according to a tenth embodiment. [Figure 34] FIG. 22 is a schematic plan view of a pixel according to a tenth embodiment. [Figure 35] FIG. 22 is a plan view schematically illustrating the arrangement of semiconductor regions according to the eleventh embodiment. [Figure 36] FIG. 22 is a cross-sectional view illustrating a photodiode according to an eleventh embodiment. [Figure 37] FIG. 22 is a schematic perspective view of a photodiode according to an eleventh embodiment. [Figure 38] FIG. 23 is a plan view schematically illustrating an example of pixel arrangement according to the twelfth embodiment. [Figure 39] FIG. 23 is a block diagram of an imaging system according to a thirteenth embodiment. [Figure 40] FIG. 23 is a block diagram of an imaging system and a moving object according to a fourteenth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] [First embodiment] A photoelectric conversion device according to a first embodiment will be described. As an example, the photoelectric conversion device according to this embodiment is an imaging device for capturing an image. The photoelectric conversion device according to this embodiment has one or more pixels, and each pixel includes one or more avalanche diodes. The conductivity type of the charge pairs generated in the avalanche diodes that are used as signal charges is called the first conductivity type. The conductivity type opposite to the first conductivity type is called the second conductivity type.

[0011] FIG. 1 is a cross-sectional view of an avalanche diode according to this embodiment. The avalanche diode according to this embodiment is disposed on a semiconductor substrate 15 (first substrate). The semiconductor substrate 15 has a first surface and a second surface opposite to the first surface. For example, the first surface is the front surface of the semiconductor substrate 15, and the second surface is the back surface of the semiconductor substrate 15. In this embodiment, the direction from the first surface to the second surface is referred to as the depth direction. A gate electrode of a transistor, a multilayer wiring structure, and the like are disposed on the front surface side of the semiconductor substrate 15.

[0012] The isolation portions 16A and 16B are regions that electrically isolate the semiconductor regions. The isolation portions 16A and 16B may be insulating isolation regions formed by LOCOS (Local Oxidation Of Silicon), STI (Shallow Trench Isolation), DTI (Deep Trench Isolation), etc. Alternatively, the isolation portions 16A and 16B may be PN isolation regions formed by PN junctions between P-type semiconductor regions and N-type semiconductor regions.

[0013] As shown in FIG. 1 , a region surrounded by an isolation portion 16A that functions as a first isolation region is formed in the semiconductor substrate 15. A first semiconductor region 71 of a first conductivity type and a second semiconductor region 76 are arranged in the region surrounded by the isolation portion 16A. Furthermore, a region surrounded by an isolation portion 16B that functions as a second isolation region is formed in the semiconductor substrate 15. A third semiconductor region 74, a fourth semiconductor region 72 of a second conductivity type, and a fifth semiconductor region 75 are arranged in the region surrounded by the isolation portion 16B. Furthermore, a contact plug 77 is provided on the first surface of the semiconductor substrate 15 so as to be in contact with the first semiconductor region 71. The contact plug 77 functions as a terminal of the avalanche diode.

[0014] The first semiconductor region 71, the second semiconductor region 76, and the isolation portion 16A are arranged at a depth X (first depth). The first semiconductor region 71 and the second semiconductor region 76 are in contact with each other in a direction perpendicular to the depth direction (the lateral direction in FIG. 1). The second semiconductor region 76 is arranged between the first semiconductor region 71 and the isolation portion 16A.

[0015] Here, the first semiconductor region 71, the second semiconductor region 76, and the isolation portion 16A being arranged at depth X means, for example, that the region (peak) of the highest concentration of impurities implanted into the semiconductor substrate 15 is at depth X. However, this does not mean that the peak strictly coincides with depth X, and even when the peak deviates from depth X due to design error, manufacturing error, etc., this is still considered to be included in the state where the peak is arranged at depth X.

[0016] The third semiconductor region 74 and the fourth semiconductor region 72 are arranged at a depth Y deeper than the depth X relative to the first surface. The fifth semiconductor region 75 is arranged at a depth Z (second depth) deeper than the depth Y relative to the first surface. The isolation portion 16B is arranged at the depths Y and Z. The third semiconductor region 74 and the fourth semiconductor region 72 are in contact with each other in a direction perpendicular to the depth direction. The fourth semiconductor region 72 is arranged between the third semiconductor region 74 and the isolation portion 16B. The fifth semiconductor region 75 and the isolation portion 16B are in contact with each other in a direction perpendicular to the depth direction.

[0017] 2(a), 2(b), and 2(c) are schematic plan views of the avalanche diode according to this embodiment, showing the plan views at depths X, Y, and Z, respectively.

[0018] 2(a), at a depth X, the first semiconductor region 71 is contained within the second semiconductor region 76. The second semiconductor region 76 is contained within the isolation portion 16A. Note that the distance R in FIG. 2(a) indicates the distance between the first semiconductor region 71 and the isolation portion 16A.

[0019] 2(b), at a depth Y, the third semiconductor region 74 is included in the fourth semiconductor region 72. The fourth semiconductor region 72 is also included in the isolation portion 16B. As shown in FIG. 2(c), at a depth Z, the fifth semiconductor region 75 is included in the isolation portion 16B.

[0020] 1, 2(a), 2(b), and 2(c), in a planar view, the first semiconductor region 71 overlaps with at least a portion of the third semiconductor region 74. Furthermore, in a planar view, the third semiconductor region 74 and the fourth semiconductor region 72 overlap with at least a portion of the fifth semiconductor region 75. Furthermore, in a planar view, the second semiconductor region 76 overlaps with at least a portion of the fourth semiconductor region 72. Here, the shapes of the isolation portion 16A and the isolation portion 16B in a planar view are different from each other.

[0021] 3(a) and 3(b) are graphs showing an example of the potential of the avalanche diode according to this embodiment. FIG. 3(a) shows the potential distribution along the lines JK and GH in the cross-sectional view shown in FIG. 1. FIG. 3(b) shows the potential distribution along the lines AB and CD in the cross-sectional view shown in FIG. 1. The potential in the semiconductor region varies depending on the potential applied to the contact plug 77. The potential shown in FIGS. 3(a) and 3(b) is obtained when a potential is applied so that a reverse bias voltage is applied to the avalanche diode. This potential is supplied from a power supply voltage line provided outside the avalanche diode via a circuit such as a quench circuit. The potential level is set so that avalanche multiplication occurs in the avalanche diode.

[0022] In FIG. 3(a), dashed line 20 indicates the potential distribution at line segment GH, and solid line 21 indicates the potential distribution at line segment JK. These potentials indicate the potential for electrons, which are signal charges. Note that if the signal charges are holes, the relationship between the high and low potentials is reversed. Depths X, Y, Z, and W on the horizontal axis correspond to the depths at the positions marked with the corresponding symbols in FIG. 1. That is, X, Y, and Z in FIG. 3(a) respectively indicate depths X, Y, and Z shown in FIG. 1. Depth W is the depth between depths Y and Z.

[0023] Each level of the potential in FIG. 3(a) will be described. The XH level indicates the potential of the fourth semiconductor region 72. The H level indicates the potential of the third semiconductor region 74. The M level indicates the potential of the second semiconductor region 76. The L level indicates the potential of the first semiconductor region 71. Note that although the potential of the second semiconductor region 76 is lower than the potential of the third semiconductor region 74, the opposite may be true. Also, although the potential of the third semiconductor region 74 is lower than the potential of the fourth semiconductor region 72, the potentials may be the same. Also, although the potential of the first semiconductor region 71 is lower than the potential of the second semiconductor region 76, the potentials may be the same.

[0024] The potential at the line segment GH indicated by the dashed line 20 will be described. At depth Z, the potential is between the XH level and the H level. The potential gradually decreases from depth Z to depth W. Then, the potential gradually increases from depth W to depth Y, reaching the XH level at depth Y. Furthermore, the potential gradually decreases from depth Y to depth X. Near depth X, the potential is at the M level.

[0025] The potential at the line segment JK indicated by the solid line 21 passing through the avalanche diode will be described. At depth Z, the potential is between the XH level and the H level. The potential gradually decreases from depth Z to depth Y, and the potential gradient becomes larger near depth Y. Then, the potential reaches the H level at depth Y. The potential rapidly decreases from depth Y to depth X. In other words, a steep potential gradient is formed between depth Y and depth X. At depth X, the potential reaches the L level.

[0026] At depth Z, the potentials at line segments GH and JK are approximately the same. Furthermore, near depth Z, at the positions of line segments GH and JK, a potential gradient is formed that gradually decreases toward the first surface of semiconductor substrate 15. Therefore, charges generated in the semiconductor region within the pixel by incident light move toward the first surface due to this potential gradient.

[0027] At the line segment JK, a potential gradient is formed that gradually decreases toward the first surface of the semiconductor substrate 15 as the line segment approaches depth Y from depth W. This causes charges to move toward the first surface. On the other hand, at the line segment GH, a potential gradient is formed that gradually increases toward the first surface of the semiconductor substrate 15 as the line segment approaches depth Y from depth W. This potential gradient acts as a potential barrier against charges moving toward the first surface. This potential barrier (fourth semiconductor region 72) inhibits charges from moving from the fifth semiconductor region 75 to the second semiconductor region 76. In contrast, because the potential gradient in the lateral direction from the position of the line segment GH to the line segment JK is small, charges present near the line segment GH in the range from depth W to depth Y are likely to move toward the vicinity of the line segment JK as they move toward the first surface.

[0028] Charges that move to the vicinity of the region indicated by line segment JK are accelerated by the steep potential gradient, i.e., the strong electric field, formed in the range from depth Y to depth X. The charges accelerated by the strong electric field reach the first semiconductor region 71. In this way, avalanche multiplication occurs in the region from depth Y to depth X near line segment JK. In contrast, the region indicated by line segment GH has a potential distribution in which avalanche multiplication is less likely to occur than in the region from depth Y to depth X of line segment JK.

[0029] One example of realizing such a structure is a configuration in which the difference between the potential of the first semiconductor region 71 and the potential of the third semiconductor region 74 is made larger than the difference between the potential of the second semiconductor region 76 and the fourth semiconductor region 72. By using such a potential structure, a configuration in which avalanche multiplication occurs in the avalanche diode is realized. Furthermore, with this configuration, the decrease in sensitivity caused by the presence of areas where avalanche multiplication is difficult to occur is reduced for the following reason.

[0030] The potential of the third semiconductor region 74 is lower than the potential of the fourth semiconductor region 72. Therefore, the fourth semiconductor region 72 functions as a potential barrier against the signal charges present in the fifth semiconductor region 75. As a result, the signal charges present in the region of the fifth semiconductor region 75 that overlaps with the fourth semiconductor region 72 or the third semiconductor region 74 can easily move to the first semiconductor region 71 via the third semiconductor region 74, and the charges are collected, thereby reducing a decrease in sensitivity.

[0031] 3(a) shows the potential structure when the third semiconductor region 74 is a P-type semiconductor region. However, even when the third semiconductor region 74 is an N-type semiconductor region, the magnitude relationship between the potentials of the line segments GH and JK at depth Y remains unchanged. That is, at depth Y, the potential at line segment GH is higher than the potential at line segment JK.

[0032] 3(a) shows the potential structure when the second semiconductor region 76 is an N-type semiconductor region, but even if it is a P-type semiconductor region, the magnitude relationship of the potentials at the line segments GH and JK at the depth Y remains the same. That is, at the depth Y, the potential at the line segment GH is higher than the potential at the line segment JK.

[0033] In addition, since the charges generated in each part of the fifth semiconductor region 75 move to the vicinity of the area indicated by the line segment JK and cause avalanche multiplication, the sensitivity of one pixel is roughly proportional to the area in a planar view of the fifth semiconductor region 75 contained within the separation portion 16B.

[0034] In Figure 3(b), dashed line 22 indicates the potential distribution at line segment CD, i.e., depth Y, and solid line 23 indicates the potential distribution at line segment AB, i.e., depth X. The meanings of the XH level, H level, M level, and L level are the same as in Figure 3(a), so explanations will be omitted.

[0035] The potential indicated by the dashed line 22 varies between the XH level and the H level depending on the horizontal position. The potential is low near the third semiconductor region 74. The potential indicated by the solid line 23 varies between the XH level and the L level depending on the horizontal position. More specifically, the potential is distributed so that it gradually decreases as it approaches the first semiconductor region 71 from the isolation portion 16A. The potential of the second semiconductor region 76 located between the isolation portion 16A and the first semiconductor region 71 varies gradually from the isolation portion 16A toward the first semiconductor region 71. This potential distribution can be achieved by implanting impurities so that the impurity concentration in the second semiconductor region 76 is relatively low.

[0036] In this embodiment, by disposing the second semiconductor region 76 between the isolation portion 16A and the first semiconductor region 71, the isolation portion 16A and the first semiconductor region 71 are separated by a certain distance R. This makes it possible to lower the strength of the electric field caused by the difference in potential between the isolation portion 16A and the first semiconductor region 71 compared to the strength of the electric field caused by the difference in potential between the first semiconductor region 71 and the third semiconductor region 74. Therefore, noise caused by the tunnel effect due to avalanche multiplication occurring at the PN junction between the isolation portion 16A and the first semiconductor region 71 is suppressed.

[0037] As described above, the isolation portion 16A disposed at depth X defines an avalanche region (second region) where avalanche multiplication due to signal charge occurs. The isolation portion 16B disposed at depth Z defines a sensitive region (first region) that generates signal charge by photoelectrically converting incident light. As described above, the isolation portion 16A at depth X is designed to ensure a certain distance R between the isolation portion 16A and the first semiconductor region 71 in order to reduce noise due to the tunneling effect. In contrast, the isolation portion 16B at depth Z is designed by adjusting its shape, area, and the like so that the position and sensitivity of the sensitive region of each pixel are as desired. As described above, the shape of the avalanche region and the shape of the sensitive region are subject to different design constraints, and therefore, different shapes may be optimal for them. Therefore, in this embodiment, the shape of the isolation portion 16A and the shape of the isolation portion 16B are different from each other in a planar view. This provides a photoelectric conversion device with improved layout freedom, and the shapes of the avalanche region and the sensitive region can be designed to suit their respective properties.

[0038] As an example of a configuration in which the shapes of the separation portions 16A and 16B are different from each other, the area enclosed by the separation portions 16A and 16B may be different. For example, for a pixel where increased sensitivity is desired, the area enclosed by the separation portion 16B may be increased compared to the area enclosed by the separation portion 16A, so that the separation portion 16B overlaps a portion of an adjacent pixel. As described above, in the avalanche diode of this embodiment, signal charges present in the fifth semiconductor region 75 tend to move to the first semiconductor region 71 via the third semiconductor region 74. Therefore, since the signal charges generated in the fifth semiconductor region 75 are collected in the first semiconductor region 71, avalanche multiplication occurs even when the area enclosed by the separation portion 16B is increased compared to the area enclosed by the separation portion 16A. FIG. 4 shows an example of a configuration in which the area enclosed by the separation portion 16B of some pixels is increased.

[0039] 4(a), 4(b), and 4(c) are planar schematic diagrams showing an example of a pixel array in which the area enclosed by isolation portion 16B is larger than the area enclosed by isolation portion 16A in some pixels. FIG. 4(a) is a planar schematic diagram at depth X, FIG. 4(b) is a planar schematic diagram at depth Y, and FIG. 4(c) is a planar schematic diagram at depth Z. As shown in these figures, the pixels arranged on semiconductor substrate 15 are arranged in rows and columns. FIGS. 4(a), 4(b), and 4(c) show 4 rows and 4 columns of the pixels extracted from the plurality of pixels.

[0040] 4(a), at a depth X, the first semiconductor region 71 is contained within the second semiconductor region 76. The second semiconductor region 76 is also contained within the isolation portion 16A. The minimum distance between the first semiconductor region 71 and the isolation portion 16A is distance R in any pixel.

[0041] As shown in FIG. 4(b), at depth Y, the third semiconductor region 74 is contained within the fourth semiconductor region 72. Furthermore, the fourth semiconductor region 72 is contained within the isolation portion 16B. As shown in FIG. 4(c), at depth Z, the fifth semiconductor region 75 is contained within the isolation portion 16B. The letters "Red," "Green," and "Blue" shown within the fifth semiconductor region 75 in FIG. 4(c) indicate that the corresponding pixels are red pixels, green pixels, and blue pixels, respectively. The red pixels, green pixels, and blue pixels are pixels provided with red, green, and blue color filters, respectively. In this embodiment, the red pixels, green pixels, and blue pixels form a Bayer array.

[0042] As shown in FIG. 4(c), in this embodiment, the area enclosed by the separation portion 16B of the green pixel is larger than that of the pixels of other colors. To achieve this, the separation portion 16B of the green pixel is arranged so as to extend beyond the separation portion 16A between the adjacent red or blue pixel in a planar view. In other words, the shape of the separation portion 16A and the shape of the separation portion 16B are different from each other in a planar view. This allows the area of ​​the sensitivity region of the green pixel to be larger than the areas of the sensitivity regions of the pixels of other colors, thereby increasing the sensitivity of the green pixel. Because the human eye is more sensitive to green than to red or blue, making the area of ​​the sensitivity region of the green pixel larger than the areas of the sensitivity regions of the red or blue pixels, as shown in FIG. 4(c), effectively improves image quality.

[0043] Depending on design requirements, pixels of colors other than the green pixel may be enlarged. In other words, in more general terms, the areas of the sensitivity regions surrounded by the separator 16B of the two avalanche diodes included in the photoelectric conversion device may be different from each other. These two avalanche diodes can be referred to as a first avalanche diode that is sensitive to incident light of a first color, and a second avalanche diode that is sensitive to incident light of a second color different from the first color.

[0044] The positional relationship between the separation portion 16A and the separation portion 16B will be described in more detail with reference to FIGS. 5(a) and 5(b). FIG. 5(a) is a schematic plan view showing the separation portion 16A of FIG. 4(a) and the separation portion 16B of FIG. 4(b) overlapping each other. FIG. 5(b) is an enlarged view of an intersection W between the separation portion 16A and the separation portion 16B. As shown in FIG. 5(b), the separation portion 16A includes a first portion P1 extending in the x1 direction (first direction). The separation portion 16B also includes a second portion P2 extending in the x2 direction (second direction) that intersects with the x1 direction in a plan view. In this case, a portion of the first portion P1 and a portion of the second portion P2 overlap each other at an overlapping portion P3 in a plan view.

[0045] As described above, according to this embodiment, the shape of the isolation portion 16A that separates the avalanche regions and the shape of the isolation portion 16B that separates the sensitive regions are different from each other in a plan view. More specifically, in a plan view, a part of the first portion P1 of the isolation portion 16A and a part of the second portion P2 of the isolation portion 16B overlap each other at the overlap portion P3. This provides a photoelectric conversion device with improved layout flexibility.

[0046] Furthermore, according to this embodiment, the fourth semiconductor region 72, which functions as a third isolation region, is arranged to isolate a part of the avalanche region from the sensitive region, which makes it easier for signal charges present in the fifth semiconductor region 75 to move to the first semiconductor region 71 via the third semiconductor region 74, thereby improving sensitivity.

[0047] In the description of this embodiment, the bias voltage applied to the avalanche diode is controlled to cause avalanche multiplication. However, it may also be controlled to cause no avalanche multiplication. In other words, the avalanche diode of this embodiment may be operable in two modes: an accumulation mode in which signal charges are accumulated in the sensitive region, and a readout mode in which the signal charges accumulated in the sensitive region are read out. Here, the accumulation mode refers to a mode in which a first bias voltage is applied to the avalanche diode and the diode is controlled to cause no avalanche multiplication. When the avalanche diode is in the accumulation mode, charges generated by photoelectric conversion are accumulated in the sensitive region. The readout mode refers to a mode in which a second bias voltage different from the first bias voltage is applied and the diode is controlled to cause avalanche multiplication. Controlling the avalanche diode in these two modes enables an operation in which signal charges are accumulated in the sensitive region for a predetermined time and then a signal corresponding to the signal charges accumulated within the predetermined time is read out.

[0048] [Second embodiment] A photoelectric conversion device according to a second embodiment will be described. In the description of this embodiment, parts having the same functions as those in the first embodiment will be denoted by the same reference numerals, and detailed description may be omitted or simplified.

[0049] 6 is a block diagram of a photoelectric conversion device 10 according to this embodiment. The photoelectric conversion device 10 includes a pixel section 106, a control pulse generation section 109, a horizontal scanning circuit 104, a column circuit 105, signal lines 107, an output circuit 108, and a vertical scanning circuit 103.

[0050] The pixel section 106 has a plurality of pixels 100 arranged in a plurality of rows and a plurality of columns. Each pixel 100 includes a photoelectric conversion element 101 and a pixel signal processing unit 102. The photoelectric conversion element 101 converts light incident on the photoelectric conversion device 10 into an electric signal. The pixel signal processing unit 102 outputs the electric signal to the column circuit 105 via a signal line 107.

[0051] The vertical scanning circuit 103 supplies control pulses for driving each pixel 100 for each pixel row based on the control pulses supplied from the control pulse generating unit 109. The vertical scanning circuit 103 may include logic circuits such as a shift register and an address decoder. A signal line 107 is provided for each column of the pixel unit 106. The signal line 107 transmits signals output from the pixels 100 selected by the vertical scanning circuit 103 to the column circuit 105.

[0052] A signal from each pixel 100 is input to the column circuit 105 via a signal line 107. The column circuit 105 performs predetermined processing on the input signal. The predetermined processing may include processing such as noise removal and amplification of the input signal, as well as processing to convert the processed signal into a form that can be output externally. To achieve this function, the column circuit 105 includes, for example, a parallel-to-serial conversion circuit.

[0053] The horizontal scanning circuit 104 supplies control pulses to the column circuits 105 for sequentially outputting the signals processed by the column circuits 105 to the output circuits 108 for each column. The output circuits 108 are composed of a buffer amplifier, a differential amplifier, etc. The output circuits 108 output the signals output from the column circuits 105 to a storage unit or a signal processing unit external to the photoelectric conversion device 10.

[0054] In FIG. 6, the pixels 100 in the pixel unit 106 are arranged in a two-dimensional matrix, but this is not limiting. For example, the pixel unit 106 may include a plurality of pixels 100 arranged one-dimensionally. The pixel unit 106 may also include a single pixel 100. The vertical scanning circuit 103, the horizontal scanning circuit 104, and the column circuit 105 may be divided into a plurality of blocks, and the blocks of the pixel unit 106 may be arranged to correspond to the blocks of the vertical scanning circuit 103, the horizontal scanning circuit 104, and the column circuit 105. The horizontal scanning circuit 104 and the column circuit 105 may also be divided into blocks corresponding to each pixel column.

[0055] It is not essential that the functions of the pixel signal processing unit 102 are provided for every pixel 100 in the pixel unit 106, and for example, one pixel signal processing unit 102 may be shared by multiple pixels 100. In this case, the pixel signal processing unit 102 sequentially processes signals output from the multiple pixels 100.

[0056] 6, the semiconductor substrate 15 including the pixel array in which the photoelectric conversion elements 101 are arranged two-dimensionally and the semiconductor substrate including the other elements may be separate semiconductor substrates. This increases the ratio of the area of ​​the photoelectric conversion elements 101 to the chip area, improving the sensitivity of the photoelectric conversion elements 101. In this case, the photoelectric conversion device 10 may have a stacked structure in which multiple semiconductor substrates are bonded together.

[0057] As an example of this configuration, the pixel signal processing unit 102 may be provided on a semiconductor substrate different from the semiconductor substrate 15 on which the photoelectric conversion elements 101 are formed. In this case, the photoelectric conversion elements 101 and the pixel signal processing unit 102 are electrically connected to each other via connection wiring provided for each pixel 100. Similarly, the vertical scanning circuit 103, the horizontal scanning circuit 104, the signal lines 107, and the column circuit 105 may also be provided on a semiconductor substrate different from the photoelectric conversion elements 101, with the same effect being obtained.

[0058] Fig. 7 is an example of a block diagram of a pixel 100 according to this embodiment. In Fig. 7, one pixel 100 has a photoelectric conversion element 101 and a pixel signal processing unit 102. The photoelectric conversion element 101 has a photoelectric conversion unit 201 and a control unit 202.

[0059] The photoelectric conversion unit 201 generates charge pairs in response to incident light through photoelectric conversion. An avalanche diode is used for the photoelectric conversion unit 201. The anode of the photoelectric conversion unit 201 is connected to a potential line that supplies a potential VL. The cathode of the photoelectric conversion unit 201 is connected to one end of the control unit 202. The other end of the control unit 202 is connected to a potential line that supplies a potential VH that is higher than the potential VL.

[0060] With this configuration, a reverse bias potential that can cause avalanche multiplication is applied to the anode and cathode of the photoelectric conversion unit 201. When photoelectric conversion is performed by incident light with this reverse bias potential applied, the generated charges cause avalanche multiplication, generating an avalanche current.

[0061] When a reverse bias potential is supplied to the photoelectric conversion unit 201, if the potential difference between the anode and the cathode is larger than the breakdown voltage, the avalanche diode operates in Geiger mode. A photodiode that uses Geiger mode operation to quickly detect weak signals at the single photon level is called a SPAD (Single Photon Avalanche Diode).

[0062] Furthermore, when the potential difference between the anode and cathode of the photoelectric conversion unit 201 is equal to or greater than the potential difference at which the charge generated in the photoelectric conversion unit 201 causes avalanche multiplication, but is equal to or less than the breakdown voltage, the avalanche diode operates in linear mode. An avalanche diode that detects light in linear mode is called an avalanche photodiode (APD). In this embodiment, the photoelectric conversion unit 201 may operate as either type of avalanche diode. The potential difference at which avalanche multiplication occurs is approximately 6 V or greater.

[0063] The control unit 202 has a function of converting a change in avalanche current generated in the photoelectric conversion unit 201 into a voltage signal. Furthermore, the control unit 202 functions as a load circuit (quench circuit) during signal amplification by avalanche multiplication. This load circuit changes the voltage supplied to the photoelectric conversion unit 201 to perform a quenching operation that suppresses avalanche multiplication. The control unit 202 may include, for example, a resistive element or an active quench circuit. The active quench circuit is a circuit that actively suppresses avalanche multiplication by detecting an increase in avalanche current and performing feedback control.

[0064] The pixel signal processing unit 102 has a waveform shaping unit 203, a counter circuit 204, and a selection circuit 206. The waveform shaping unit 203 shapes a voltage change due to a single-photon level signal and outputs a pulse signal. This pulse signal indicates the incidence of a photon. The waveform shaping unit 203 may be, for example, an inverter circuit as shown in FIG. 7. Although FIG. 7 shows an example in which one inverter is used as the waveform shaping unit 203, the waveform shaping unit 203 may be a circuit in which multiple inverters are connected in series, or may be any other circuit that has a waveform shaping effect.

[0065] The pulse signal output from the waveform shaping unit 203 is counted by the counter circuit 204. The counter circuit 204 is provided with, for example, an N-bit counter (N: positive integer), which is capable of counting up to approximately 2 to the Nth power of the input pulse signal and holding the counted value. The signal obtained by the counting is held in the counter circuit 204 as a signal indicating the detection result of the incident light. In addition, a control pulse pRES is supplied to the counter circuit 204 from the vertical scanning circuit 103 via a drive line 207. When the control pulse pRES is input, the counter circuit 204 resets the signal it is holding.

[0066] A control pulse pSEL is supplied to the selection circuit 206 from the vertical scanning circuit 103 via a drive line 208. Based on the control pulse pSEL, the selection circuit 206 switches between electrical connection and disconnection between the counter circuit 204 and the signal line 107. The selection circuit 206 may include, for example, a transistor, a buffer circuit for outputting a signal to outside the pixel, or the like.

[0067] When the pixel unit 106 has a configuration in which a plurality of pixels 100 are arranged in a matrix, the imaging operation may be either a rolling shutter operation or a global electronic shutter operation. For example, the rolling shutter operation is realized by resetting the count by the counter circuit 204 sequentially for each row and outputting the signal held in the counter circuit 204 sequentially for each row.

[0068] Furthermore, a global electronic shutter operation is realized by simultaneously resetting the counts by the counter circuits 204 for all pixel rows and sequentially outputting, for each row, the signals held in the counter circuits 204. When the global electronic shutter operation is applied, it is desirable to provide a switching means such as a switch so that it is possible to switch whether or not the counter circuit 204 is to count.

[0069] 8(a) to 8(f) are schematic plan views and cross-sectional views showing an example of a configuration in which two avalanche diodes shown in FIGS. 6 and 7 are arranged diagonally within a substantially square region. The multiple avalanche diodes of the photovoltaic conversion device 10 are arranged in a matrix with multiple rows and multiple columns, with two avalanche diodes shown in FIGS. 8(a) to 8(f) forming one unit. FIG. 8(a) is a schematic plan view at depth X, FIG. 8(b) is a schematic plan view at depth Y, and FIG. 8(c) is a schematic plan view at depth Z. FIG. 8(d) is a schematic cross-sectional view taken along line SL1-SL1', FIG. 8(e) is a schematic cross-sectional view taken along line SL2-SL2', and FIG. 8(f) is a schematic cross-sectional view taken along line SL3-SL3'.

[0070] As shown in FIG. 8( a), at a depth X, two first semiconductor regions 71 are respectively contained within two second semiconductor regions 76. Furthermore, the two second semiconductor regions 76 are respectively contained within different portions of the isolation portion 16A. The first semiconductor regions 71 and the isolation portion 16A are disposed so that the distance between them is a distance R in both directions. In other words, the first semiconductor regions 71 are disposed so that the distance between them is maximized. The two first semiconductor regions 71 are disposed on diagonals of a square formed by the isolation portion 16A. Between the two first semiconductor regions 71, the isolation portion 16A is disposed extending in a diagonal direction (a direction different from both the rows and columns of the avalanche diodes) so as to diagonally separate the two second semiconductor regions 76. In this way, when two avalanche diodes are disposed in a square region, the distance R can be increased by disposing the first semiconductor regions 71 on a diagonal line. This allows the distance R to be increased by approximately 1.17 times compared to when the two first semiconductor regions 71 are arranged side by side in the horizontal direction.

[0071] 8(b), at a depth Y, the third semiconductor region 74 is contained within the fourth semiconductor region 72. Furthermore, the fourth semiconductor region 72 is contained within the isolation portion 16B.

[0072] As shown in FIG. 8(c), at depth Z, the two fifth semiconductor regions 75 are contained in different portions of the isolation portion 16B. Between the two fifth semiconductor regions 75, an isolation portion 16B is disposed extending vertically so as to separate the two second semiconductor regions 76 in the horizontal direction. Also, in FIG. 8(c), the positions of the microlenses ML that guide incident light to the two fifth semiconductor regions 75 are indicated by dashed lines. The positions of the two fifth semiconductor regions 75 are disposed symmetrically in the horizontal direction with respect to the center position of the microlens ML. That is, the two avalanche diodes of this embodiment have two sensitive regions that are optically conjugate with one microlens ML. As a result, signals obtained from the two avalanche diodes can be used as signals for phase-difference autofocus.

[0073] The positional relationship between the separation portion 16A and the separation portion 16B will be described in more detail with reference to FIG. 9. FIG. 9 is a schematic plan view showing the separation portion 16A of FIG. 8(a) and the separation portion 16B of FIG. 8(b) overlapping each other. As shown in FIG. 9, the separation portion 16A includes a first portion P1 extending in the x1 direction (first direction). The separation portion 16B includes a second portion P2 extending in the x2 direction (second direction) that intersects with the x1 direction in a plan view. In this case, a part of the first portion P1 and a part of the second portion P2 overlap each other at an overlapping portion P3 in a plan view.

[0074] As described above, in this embodiment, in a plan view, the portion of isolation portion 16A that separates the two first semiconductor regions 71 and the portion of isolation portion 16B that separates the two fifth semiconductor regions 75 intersect with each other. That is, in a plan view, the shape of isolation portion 16A and the shape of isolation portion 16B are different from each other. More specifically, in a plan view, a part of first portion P1 of isolation portion 16A and a part of second portion P2 of isolation portion 16B overlap with each other at overlapping portion P3. This provides a photoelectric conversion device 10 with improved layout freedom, and the shapes of the avalanche region and the sensitive region can be designed to suit their respective properties.

[0075] More specifically, the separator 16A of this embodiment is arranged diagonally to maximize the distance R between the two avalanche diodes in the square region. In contrast, the separator 16B of this embodiment is arranged vertically to maximize the distance R between the two avalanche diodes in the square region. In other words, the separator 16A defining the avalanche region and the separator 16B defining the sensitive region must be symmetrically arranged horizontally in the figure, taking into account the phase difference acquisition direction for phase-difference autofocusing. In other words, the separator 16A defining the avalanche region and the separator 16B defining the sensitive region have different required characteristics and design constraints, and therefore are designed with different shapes. By making the shapes of the separator 16A and the separator 16B different from each other, it is possible to simultaneously increase the distance R to reduce noise due to the tunneling effect and obtain a signal for phase-difference autofocusing. Furthermore, by arranging the two avalanche diodes diagonally within the square region, the distance R can be increased. Therefore, when the maximum value of the distance R is limited, the pixel size can be reduced by adopting the configuration of this embodiment. This allows the number of pixels to be increased, resulting in an effect of improving the quality of the resulting image.

[0076] In this embodiment, the outer periphery of the isolation portions 16A and 16B is a square, but this is not limiting. For example, the outer periphery of the isolation portions 16A and 16B may be a rectangle (including a square), and the two avalanche diodes may be arranged within the rectangular region. In this case, isolation portion 16A is also arranged to extend in the diagonal direction so that the distance R when arranging the two avalanche diodes is maximized.

[0077] [Third embodiment] A photoelectric conversion device according to a third embodiment will be described. In the description of this embodiment, parts having the same functions as those in the first or second embodiment will be denoted by the same reference numerals, and detailed description thereof may be omitted or simplified.

[0078] The photoelectric conversion device of this embodiment is a back-illuminated photoelectric conversion device obtained by applying the photoelectric conversion device of the second embodiment to a photoelectric conversion device. Fig. 10 is a cross-sectional view of the photoelectric conversion device of this embodiment. Fig. 10 shows the cross-sectional view of the photoelectric conversion device taken along line SL1-SL1' in Fig. 8, with color filters CF1 and CF2 and microlenses ML added. As shown in Fig. 10, the color filters CF1 and CF2 and the microlenses ML are disposed on the second surface side of the semiconductor substrate 15.

[0079] Incident light passes through the microlens ML and color filters CF1 and CF2 in this order and is incident on the second surface side of the semiconductor substrate 15. The color filters CF1 and CF2 allow light of different colors to pass through. The microlens ML is shared by two avalanche diodes, and light that passes through the microlens ML is guided to one of the two avalanche diodes. Note that, although one microlens ML is arranged corresponding to two avalanche diodes in FIG. 10, this is not limiting. In other words, one microlens ML may be arranged corresponding to two or more avalanche diodes.

[0080] As described above, the photoelectric conversion device of this embodiment is a back-illuminated type in which the second surface opposite to the first surface on which the wiring layer is provided serves as the light-receiving surface, thereby improving the sensitivity of the photoelectric conversion device of this embodiment compared to a front-illuminated type.

[0081] [Fourth embodiment] A photoelectric conversion device according to a fourth embodiment will be described. In the description of this embodiment, parts having the same functions as those in the first to third embodiments will be denoted by the same reference numerals, and detailed description thereof may be omitted or simplified.

[0082] The photoelectric conversion device of this embodiment is a stacked-type photoelectric conversion device obtained by applying the photoelectric conversion device of the third embodiment to the photoelectric conversion device. FIG. 11 is a cross-sectional view of the photoelectric conversion device of this embodiment. FIG. 11 is a cross-sectional view of the photoelectric conversion device taken along line SL1-SL1′ in FIG. 8, with color filters CF1 and CF2, microlenses ML, and a semiconductor substrate 17 added. As in the third embodiment, the color filters CF1 and CF2 and the microlenses ML are disposed on the second surface of the semiconductor substrate 15. The semiconductor substrate 17 is bonded to the first surface of the semiconductor substrate 15 via a bonding surface 18 and is mechanically and electrically connected to the semiconductor substrate 15. The semiconductor substrate 17 includes a signal processing circuit that processes signals output from avalanche diodes such as the pixel signal processor 102.

[0083] As described above, the photoelectric conversion device of this embodiment is a back-illuminated type similar to the third embodiment, and is also a stacked type in which semiconductor substrate 15 (first substrate) and semiconductor substrate 17 (second substrate) are stacked. An avalanche diode is disposed on semiconductor substrate 15, and a signal processing circuit is disposed on semiconductor substrate 17. This allows the sensitivity region of the avalanche diode to be wider than when the avalanche diode and the signal processing circuit are disposed on the same substrate, thereby further improving sensitivity.

[0084] [Fifth embodiment] A photoelectric conversion device according to a fifth embodiment will be described. In the description of this embodiment, parts having the same functions as those of the first to fourth embodiments will be assigned the same reference numerals, and detailed description may be omitted or simplified. Unlike the first to fourth embodiments, the photoelectric conversion device according to this embodiment is an image sensor using a photodiode that does not utilize avalanche multiplication. The photoelectric conversion device according to this embodiment has a function of outputting a signal for imaging as well as a function of outputting a signal for image plane phase difference autofocus.

[0085] 12 is a block diagram of a photoelectric conversion device 60 according to this embodiment. The photoelectric conversion device 60 has a pixel unit 61, a control pulse generation unit 109, a horizontal scanning circuit 104, a column circuit 105, signal lines 107, an output circuit 108, and a vertical scanning circuit 103. The configurations of the control pulse generation unit 109, the horizontal scanning circuit 104, the column circuit 105, the signal lines 107, the output circuit 108, and the vertical scanning circuit 103 are generally similar to those of the second embodiment, and therefore description thereof will be omitted.

[0086] The pixel section 61 has a plurality of pixels 600 arranged in a plurality of rows and a plurality of columns. Each pixel 600 has a photodiode that converts incident light into an electrical signal.

[0087] FIG. 13 is an example of an equivalent circuit diagram of a pixel 600 according to this embodiment. The pixel 600 includes photoelectric conversion units PD1 and PD2, transfer transistors M1A and M1B, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. These transistors may be N-channel MOS transistors. A control signal PTX1 is input to the gate of the transfer transistor M1A from the vertical scanning circuit 103. A control signal PTX2 is input to the gate of the transfer transistor M1B from the vertical scanning circuit 103. A control signal PRES is input to the gate of the reset transistor M2 from the vertical scanning circuit 103. A control signal PSEL is input to the gate of the selection transistor M4 from the vertical scanning circuit 103.

[0088] The photoelectric conversion units PD1 and PD2 generate charges according to incident light through photoelectric conversion and accumulate the charges. The photoelectric conversion units PD1 and PD2 are not avalanche diodes as described in the first to fourth embodiments, but are normal photodiodes that do not utilize avalanche multiplication. The anodes of the photoelectric conversion units PD1 and PD2 are connected to a ground potential line. The cathode of the photoelectric conversion unit PD1 is connected to the source of the transfer transistor M1A. The cathode of the photoelectric conversion unit PD2 is connected to the source of the transfer transistor M1B.

[0089] The connection node between the drains of the transfer transistors M1A and M1B, the source of the reset transistor M2, and the gate of the amplification transistor M3 forms a floating diffusion FD. The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a power supply potential line having a potential VDD. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to a signal line 107. A current source (not shown) is connected to the signal line 107.

[0090] When the control signal PRES goes high and the reset transistor M2 turns on, the potential of the floating diffusion FD is reset. When the control signal PTX1 goes high and the transfer transistor M1A turns on, the charge accumulated in the photoelectric conversion unit PD1 is transferred to the floating diffusion FD. When the control signal PTX2 goes high and the transfer transistor M1B turns on, the charge accumulated in the photoelectric conversion unit PD2 is transferred to the floating diffusion FD. When the control signal PSEL goes high and the selection transistor M4 turns on, the amplification transistor M3 and the current source connected to the signal line 107 form a source follower circuit. At this time, a voltage corresponding to the potential of the floating diffusion FD is output to the signal line 107.

[0091] With this configuration, the photoelectric conversion device of this embodiment can individually output signals based on the charges accumulated in the two photoelectric conversion units PD1 and PD2. The photoelectric conversion device of this embodiment can also add the charges accumulated in the two photoelectric conversion units PD1 and PD2 and output a signal based on the sum.

[0092] FIG. 14 is a schematic plan view of a photodiode according to this embodiment. FIG. 14 shows the positional relationship between two N-type semiconductor regions 601 and a microlens ML that constitute a part of the photodiode. In FIG. 14, the positions of the microlenses ML that guide incident light to the two N-type semiconductor regions 601 are indicated by dashed lines. The two N-type semiconductor regions 601 in FIG. 14 correspond to the sensitivity regions of the photoelectric conversion units PD1 and PD2 in FIG. 13, respectively. The positions of the two N-type semiconductor regions 601 are arranged symmetrically in the horizontal direction with respect to the center position of the microlens ML. In other words, the two photodiodes of this embodiment have two sensitivity regions that are optically conjugate with one microlens ML. As a result, signals obtained from the two photodiodes can be used as signals for image-plane phase-detection autofocus.

[0093] FIG. 15 is a cross-sectional view of a photodiode according to this embodiment. FIG. 15 shows a cross section taken along line SL4-SL4′ in FIG. 14. The photodiode according to this embodiment is disposed on a semiconductor substrate 15 (first substrate). The semiconductor substrate 15 has a first surface and a second surface opposite to the first surface. For example, the first surface is the front surface of the semiconductor substrate 15, and the second surface is the rear surface of the semiconductor substrate 15. In this embodiment, the direction from the first surface to the second surface is referred to as the depth direction. Transistor gate electrodes, a multilayer wiring structure, and the like are disposed on the front surface side of the semiconductor substrate 15. Microlenses ML corresponding to the two photodiodes are disposed on the rear surface side of the semiconductor substrate 15.

[0094] 15, a semiconductor substrate is formed with a P-type semiconductor region 604 and a region surrounded by the P-type semiconductor region 604. In the region surrounded by the P-type semiconductor region 604, N-type semiconductor regions 601, 602, and 603 are arranged.

[0095] The N-type semiconductor region 602 is disposed at a depth D1 (first depth). The N-type semiconductor region 603 is disposed at a depth D2 deeper than the depth D1 relative to the first surface. The N-type semiconductor region 601 is disposed at a depth D3 (second depth) deeper than the depth D2 relative to the first surface. The N-type semiconductor region 602 and the N-type semiconductor region 603 are in contact with each other in the depth direction, and the N-type semiconductor region 603 and the N-type semiconductor region 601 are in contact with each other in the depth direction.

[0096] Fig. 16 is a schematic cross-sectional view of a photodiode according to this embodiment. Fig. 16 is a view illustrating in more detail the structure of the P-type semiconductor region 604 in a cross section similar to that of Fig. 15. The P-type semiconductor region 604 includes regions 604a, 604b, 604c, 604d, 604e, and 604f.

[0097] The region 604a is disposed from the depth D1 to the depth D3 so as to surround the N-type semiconductor regions 601, 602, and 603. The region 604a functions as an isolation region between adjacent pixels.

[0098] The region 604b (first isolation region) is disposed at a depth D1 between the two N-type semiconductor regions 602. The region 604b functions as an isolation region between the two N-type semiconductor regions 602.

[0099] The region 604c (second isolation region) is disposed at a depth D3 between the two N-type semiconductor regions 601. The region 604c functions as an isolation region between the two N-type semiconductor regions 601.

[0100] The region 604d (third isolation region) is arranged so as to be in contact with the N-type semiconductor region 601 and the N-type semiconductor region 602 in the depth direction. The region 604d separates the N-type semiconductor region 601 from the N-type semiconductor region 602 except for a portion between them (the portion where the N-type semiconductor region 603 is arranged). In other words, the N-type semiconductor region 601 and the N-type semiconductor region 602 are connected via the N-type semiconductor region 603.

[0101] The region 604e is disposed on the first surface side of the two N-type semiconductor regions 602 and the region 604b. The region 604f is disposed on the second surface side of the two N-type semiconductor regions 601 and the region 604c.

[0102] When light is incident on the back surface of the semiconductor substrate 15 through the microlens ML, electrons are generated in the N-type semiconductor region 601 by photoelectric conversion. That is, the N-type semiconductor region 601 functions as a sensitive region (first region) of the photoelectric conversion device. These electrons (signal charges) move to the N-type semiconductor region 602 via the N-type semiconductor region 603. That is, the N-type semiconductor region 602 functions as an accumulation region (second region) that accumulates charges of the photoelectric conversion device. The N-type semiconductor region 603 (third region) is a path for electrons to move from the N-type semiconductor region 602 to the N-type semiconductor region 601. To achieve this, it is desirable that the potential for electrons monotonically increases on the path for electrons to move from the N-type semiconductor region 602 to the N-type semiconductor region 601.

[0103] FIG. 17 is a cross-sectional schematic diagram of a photodiode according to this embodiment. FIG. 17 illustrates a cross section similar to that of FIGS. 15 and 16 , illustrating in more detail the structure for transferring charges. The semiconductor substrate 15 includes a semiconductor region 605 that constitutes a floating diffusion FD. Furthermore, gate electrodes 606 of the transfer transistors M1A and M1B are disposed on the first surface at a position corresponding to the P-type semiconductor region 604 between the N-type semiconductor region 602 and the semiconductor region 605. By controlling the voltage of the gate electrode 606, charges accumulated in the semiconductor region 602 can be transferred to the semiconductor region 605. Although the two semiconductor regions 605 are illustrated as separate regions in FIG. 17, the two semiconductor regions 605 in FIG. 17 may be electrically connected nodes at the same potential, as shown in FIG. 13.

[0104] FIG. 18 is a schematic plan view of a pixel 600 according to this embodiment. FIG. 18 shows an example of a specific layout of the circuit of the pixel 600 shown in FIG. 13. FIG. 18 shows the positions of semiconductor regions constituting the photodiode, transistors, etc., and the microlens ML. FIG. 18 also shows gate electrodes 606 of the transfer transistors M1A and M1B, a gate electrode 607 of the reset transistor M2, a gate electrode 608 of the amplification transistor M3, and a gate electrode 609 of the selection transistor M4. FIG. 18 also shows wiring WL connecting these components.

[0105] In a plan view, a gate electrode 606 of the transfer transistors M1A and M1B is disposed between the N-type semiconductor region 602 and the semiconductor region 605. The semiconductor region 605 is connected to a semiconductor region 610 constituting the main electrode of the reset transistor M2 and a gate electrode 608 of the amplification transistor M3 via a wiring WL. The gate electrodes 606, 607, and 609 are connected to the wiring WL, and a control signal is input from the vertical scanning circuit 103 via the wiring WL.

[0106] A wiring WL that functions as a power supply potential line having a potential VDD is connected to a semiconductor region 611 that constitutes the main electrodes of the reset transistor M2 and the amplification transistor M3. A wiring WL that functions as a signal line 107 for outputting a signal voltage to the outside is connected to a semiconductor region 612 that constitutes the main electrode of the selection transistor M4.

[0107] In this embodiment, it is sufficient that the N-type semiconductor region 601 and the N-type semiconductor region 602 are connected via the N-type semiconductor region 603. This allows the N-type semiconductor region 601 and the N-type semiconductor region 602 to have different shapes in a plan view. Furthermore, since the positional relationship between the N-type semiconductor region 601 and the N-type semiconductor region 602 can be designed independently of each other, there are various possible specific aspects of the positional relationship between the N-type semiconductor region 601 and the N-type semiconductor region 602. Two examples of the arrangement of the N-type semiconductor region 601 and the N-type semiconductor region 602 will be described.

[0108] 19(a), 19(b), and 19(c) are schematic diagrams showing a first example of the arrangement of semiconductor regions according to this embodiment. FIG. 19(a) is a perspective schematic diagram showing the arrangement of N-type semiconductor regions 601, 602, and 603, a semiconductor region 605, and a gate electrode 606. As shown in FIG. 19(a), the N-type semiconductor region 601 and the N-type semiconductor region 602 each have a rectangular parallelepiped shape extending in the depth direction of the drawing. That is, the N-type semiconductor region 601 and the N-type semiconductor region 602 extend in the same direction.

[0109] FIG. 19(b) is a schematic plan view showing the arrangement of N-type semiconductor regions 601, 602, and 603, a semiconductor region 605, and a gate electrode 606. As shown in FIG. 19(b), the N-type semiconductor region 601 and the N-type semiconductor region 602 both extend vertically in the drawing. In other words, the two N-type semiconductor regions 601 are arranged side by side in the horizontal direction of the drawing, and the two N-type semiconductor regions 602 are also arranged side by side in the horizontal direction of the drawing. In this configuration, the N-type semiconductor regions 601, in which charges are generated by photoelectric conversion, are arranged at positions spaced apart in the horizontal direction, making it possible to obtain a signal for image plane phase-difference autofocus that can mainly detect horizontal parallax. In FIG. 19(b), the direction of phase-difference detection is indicated by an arrow 613.

[0110] 19(c) is a schematic plan view showing the positional relationship in a plan view between a region 604b that functions as an isolation region between the N-type semiconductor regions 602 and a region 604c that functions as an isolation region between the N-type semiconductor regions 601. As shown in FIG. 19(c), the region 604b and the region 604c both extend in the vertical direction of the drawing.

[0111] 20(a), 20(b), and 20(c) are schematic diagrams showing a second example of the arrangement of semiconductor regions according to this embodiment, which differs mainly from those shown in FIGS. 19(a), 19(b), and 19(c) in the arrangement of the semiconductor region 601.

[0112] 20(a), each of the N-type semiconductor regions 602 has a rectangular parallelepiped shape extending in the depth direction of the drawing, and each of the N-type semiconductor regions 601 has a rectangular parallelepiped shape extending in the width direction of the drawing. That is, the N-type semiconductor regions 601 and 602 extend in directions orthogonal to each other in a plan view, i.e., in different directions.

[0113] As shown in FIG. 20(b), both N-type semiconductor regions 602 extend in the vertical direction of the drawing, and both N-type semiconductor regions 601 extend in the horizontal direction of the drawing. In other words, the two N-type semiconductor regions 601 are arranged side by side in the vertical direction of the drawing, and the two N-type semiconductor regions 602 are also arranged side by side in the horizontal direction of the drawing. In this configuration, the N-type semiconductor regions 601, in which electric charges are generated by photoelectric conversion, are arranged at positions spaced apart in the vertical direction, making it possible to obtain a signal for image plane phase-difference autofocus that can mainly detect vertical parallax. In FIG. 20(b), the direction of phase-difference detection is indicated by arrow 614.

[0114] 20(c) is a schematic plan view showing the positional relationship in a plan view between a region 604b that functions as an isolation region between the N-type semiconductor regions 602 and a region 604c that functions as an isolation region between the N-type semiconductor regions 601. As shown in FIG. 20(c), the region 604b is located in the vertical direction of the drawing, and the region 604c extends in the horizontal direction of the drawing. That is, the regions 604b and 604c extend in directions orthogonal to each other in a plan view, i.e., in different directions.

[0115] 21(a) and 21(b) are planar schematic diagrams showing an example of the arrangement of pixels 600. FIG. 21(a) shows an example in which the pixels 600 of the first example shown in FIGS. 19(a), 19(b), and 19(c) are arranged in a matrix. In this example, an arrow 613 indicating the direction of phase difference detection points in the horizontal direction. FIG. 21(b) shows an example in which the pixels 600 of the second example shown in FIGS. 20(a), 20(b), and 20(c) are arranged in a matrix. In this example, an arrow 614 indicating the direction of phase difference detection points in the vertical direction.

[0116] As described above, the pixel 600 of this embodiment has an N-type semiconductor region 602 disposed at a depth D1 and an N-type semiconductor region 601 disposed at a depth D3 from the first surface that is deeper than the depth D1. By making the N-type semiconductor region 601 sufficiently thick, most of the light incident from the second surface side is absorbed by the N-type semiconductor region 601 and does not reach the N-type semiconductor region 602. As a result, the N-type semiconductor region 601 functions as a sensitive region that generates charges from incident light by photoelectric conversion. The charges generated in the N-type semiconductor region 601 move to the N-type semiconductor region 602 via the N-type semiconductor region 603 and are stored there. That is, the N-type semiconductor region 602 functions as an accumulation region that accumulates the charges generated by photoelectric conversion.

[0117] In this way, the N-type semiconductor region 601 and the N-type semiconductor region 602 have different functions due to their different positions in the thickness direction of the substrate. Therefore, the planar shapes of the N-type semiconductor region 601 and the N-type semiconductor region 602 can be designed to be different shapes depending on the purpose. From another perspective, the region 604b that functions as an isolation region between the N-type semiconductor regions 602 and the region 604c that functions as an isolation region between the N-type semiconductor regions 601 can be designed to be different shapes in planar view.

[0118] In the first example shown in FIGS. 19(b) and 21(a), two N-type semiconductor regions 601 are arranged side by side in the horizontal direction of the drawing, allowing for the acquisition of an image plane phase-detection autofocus signal capable of primarily detecting horizontal parallax. This design is more effective when the subject has a pattern similar to a vertical stripe. In contrast, in the second example shown in FIGS. 20(b) and 21(b), two N-type semiconductor regions 601 are arranged side by side in the vertical direction of the drawing, allowing for the acquisition of an image plane phase-detection autofocus signal capable of primarily detecting vertical parallax. This design is more effective when the subject has a pattern similar to a horizontal stripe. In this way, by changing the shape of the N-type semiconductor region 601 functioning as a sensitive region in consideration of the expected characteristics of the subject, the detection direction of the image plane phase-detection autofocus can be changed. In these two examples, the design of the N-type semiconductor region 602 functioning as an accumulation region is the same. Furthermore, the designs of the gate electrode 606, the semiconductor region 605, the wiring WL, etc. can also be the same in the two examples. That is, the design of the portions other than the sensitive region can be standardized without depending on the shape of the storage region, which simplifies the design.

[0119] As described above, this embodiment provides a photoelectric conversion device that can optimize the structure of the photodiode that outputs a signal for image plane phase detection autofocusing by taking into account the position in the thickness direction of the substrate, thereby providing a photoelectric conversion device that can output a signal with an appropriate parallax detection direction according to the shape of the subject.

[0120] Even in a circuit configuration using a normal photodiode as in this embodiment, a structure in which a first substrate on which a photodiode is arranged and a second substrate on which a signal processing circuit is arranged are stacked can be applied, as in Embodiment 4. In this case, the area of ​​the sensitive region of the photodiode can be increased, further improving sensitivity.

[0121] [Sixth embodiment] A photoelectric conversion device according to a sixth embodiment will be described. In the description of this embodiment, parts having the same functions as those of the first to fifth embodiments will be denoted by the same reference numerals, and detailed description may be omitted or simplified. The photoelectric conversion device according to this embodiment is a modified example of the arrangement of the pixels 600 described in the fifth embodiment.

[0122] Fig. 22 is a plan view schematic diagram of a pixel according to this embodiment. Fig. 22 illustrates four pixels in two rows and two columns, and shows the arrangement of N-type semiconductor regions 601 and 603, semiconductor regions 605, gate electrodes 606, and microlenses ML. The arrangement of the N-type semiconductor region 602 is the same as in Fig. 19(b) and Fig. 20(b), and therefore is omitted in Fig. 22.

[0123] In the upper left pixel in Fig. 22, two N-type semiconductor regions 601 (first photodiode groups corresponding to the first microlenses ML) are arranged side by side in the vertical direction of the drawing, similar to Fig. 20(b). In the pixels adjacent to the upper left pixel in Fig. 22 (the upper right pixel and the lower left pixel), two N-type semiconductor regions 601 (second photodiode groups corresponding to the second microlenses ML) are arranged side by side in the horizontal direction of the drawing, similar to Fig. 19(b).

[0124] Fig. 23 is a plan view schematic diagram showing an example of the arrangement of pixels 600. Fig. 23 shows an example in which the 2-row x 2-column, four-pixel unit shown in Fig. 22 is repeatedly arranged. In this example, the directions of arrows 613 and 614 indicating the phase difference detection directions alternate between the horizontal and vertical directions.

[0125] In this embodiment, the pixel unit 61 includes both pixels capable of primarily detecting horizontal parallax, as shown in the first example of FIG. 19(b), and pixels capable of primarily detecting vertical parallax, as shown in the second example of FIG. 20(b). Therefore, multiple sets of image-plane phase-detection autofocus signals with different detection directions can be obtained. This enables highly accurate focus detection from the multiple pixels 600 in the pixel unit 61 with little dependency on the shape of the subject. For example, if the subject has a striped pattern, stable focus detection accuracy can be achieved regardless of the direction of the stripes. As described above, this embodiment provides a photoelectric conversion device capable of achieving focus detection suitable for various situations.

[0126] In the above example, the arrows 613 and 614 indicating the phase difference detection directions are oriented in only two combinations, horizontal and vertical, but any other combination of two directions, or even three or more combinations, may be used. FIG. 24 is a schematic plan view of a pixel according to a modified example of this embodiment. As shown in FIG. 24, by forming two N-type semiconductor regions 601 into a triangular shape aligned diagonally, the phase difference detection direction indicated by the arrow 615 can be set to a diagonal direction. By including the pixel 600 having the configuration shown in FIG. 24 in the pixel unit 61, it is possible to obtain image plane phase difference autofocus signals in even more diverse detection directions.

[0127] [Seventh embodiment] A photoelectric conversion device according to a seventh embodiment will be described. In the description of this embodiment, parts having the same functions as those of the first to sixth embodiments will be given the same reference numerals, and detailed description may be omitted or simplified. The photoelectric conversion device according to this embodiment is a modified example of the arrangement of the pixels 600 described in the fifth and sixth embodiments.

[0128] Fig. 25 is a plan view schematic diagram of a pixel according to this embodiment. Similar to Fig. 22, Fig. 25 illustrates four pixels arranged in two rows and two columns, and shows the arrangement of N-type semiconductor regions 601 and 603, semiconductor regions 605, and gate electrodes 606. Note that the microlenses ML are not shown. Furthermore, Fig. 25 illustrates the arrangement of color filters CFR, CFG, and CFB provided corresponding to each pixel. Similar to Fig. 10, the color filters CFR, CFG, and CFB are provided between the second surface of the semiconductor substrate and the microlenses ML.

[0129] The color filter CFR is a color filter that transmits red light, and one filter is provided for every four pixels arranged in two rows and two columns. The color filter CFG is a color filter that transmits green light, and two filters are provided for every four pixels arranged in two rows and two columns. The color filter CFB is a color filter that transmits blue light, and one filter is provided for every four pixels arranged in two rows and two columns. The arrangement of the color filters CFR, CFG, and CFB in FIG. 25 is called a Bayer arrangement, but this is just one example, and other arrangement methods may also be used. Hereinafter, the pixels having the color filters CFR, CFG, and CFB may also be referred to as red pixels, green pixels, and blue pixels, respectively.

[0130] As shown in Fig. 25, in this embodiment, the pixels capable of mainly detecting horizontal parallax shown in the first example of Fig. 19(b) are green pixels, and the pixels capable of mainly detecting vertical parallax shown in the second example of Fig. 20(b) are red pixels or blue pixels. In this way, in this embodiment, pixels with different detection directions have color filters of different colors.

[0131] When comparing signals for image plane phase detection autofocus, it is desirable to have the same colors for each detection direction because focus detection can be performed more accurately if the colors are not mixed. Therefore, in this embodiment, the color filters are arranged so that pixels with different detection directions have color filters of different colors. As a result, this embodiment enables high-precision focus detection even in a photoelectric conversion device that is compatible with color imaging.

[0132] In the configuration of Figure 25, the signals output from the red, green, and blue pixels can all be used for image-plane phase-detection autofocus, but all of them, or one or two of them, may also be used. Because the light absorption rate of the silicon substrate is higher for green than for red or blue, green pixels have higher sensitivity than other pixels. Therefore, it is desirable to use at least the signal output from the green pixel for image-plane phase-detection autofocus.

[0133] The correspondence relationship between the color filters and the arrangement of the N-type semiconductor regions 601 in FIG. 25 is an example, and other relationships may be used. FIG. 26 is a schematic plan view of a pixel according to a modification of this embodiment. In the modification of FIG. 26, the arrangement of the N-type semiconductor regions 601 is different from that in FIG. 25. Specifically, one of the two green pixels is a pixel capable of primarily detecting horizontal parallax as shown in the first example of FIG. 19(b), and the other is a pixel capable of primarily detecting vertical parallax as shown in the second example of FIG. 20(b). In this configuration, the signal output from the highly sensitive green pixel can be used for focus detection in two detection directions. Note that signals output from one or both of the red and blue pixels may also be used for focus detection.

[0134] [Eighth embodiment] A photoelectric conversion device according to an eighth embodiment will be described. In the description of this embodiment, parts having the same functions as those of the first to seventh embodiments will be given the same reference numerals, and detailed description may be omitted or simplified. The photoelectric conversion device according to this embodiment is an example in which the photodiode of the pixel 600 described in the fifth embodiment is modified to an avalanche diode. The detailed structure of the avalanche diode, the operation of avalanche multiplication, etc. are the same as those described in the first embodiment.

[0135] 27 is a cross-sectional schematic diagram of an avalanche diode according to this embodiment. The semiconductor substrate 15 of this embodiment has a semiconductor region 616 that functions as a region for collecting charge from N-type semiconductor regions 601 and 602 and also functions as a terminal for acquiring a signal. The semiconductor region 616 corresponds to the first semiconductor region 71 of the first embodiment. Furthermore, the cross-sectional structure of the pixel 600 of this embodiment does not include the gate electrode 606 having the charge transfer function and the semiconductor region 605 that constitutes the floating diffusion FD of the fifth to seventh embodiments.

[0136] 28(a) and 28(b) are planar schematic diagrams showing the arrangement of N-type semiconductor regions 601, 602, and 603 and semiconductor region 616. FIG. 28(a) is an example of an arrangement corresponding to the first example described in FIG. 19(a). With the configuration of FIG. 28(a), it is possible to obtain a signal for image plane phase difference autofocus that can mainly detect parallax in the horizontal direction, similar to the configuration of FIG. 19(a). Also, FIG. 28(b) is an example of an arrangement corresponding to the second example described in FIG. 20(a). With the configuration of FIG. 28(b), it is possible to obtain a signal for image plane phase difference autofocus that can mainly detect parallax in the depth direction, similar to the configuration of FIG. 20(a).

[0137] Therefore, even when the photodiode is an avalanche diode that performs avalanche multiplication as in this embodiment, it is possible to realize a structure similar to that of the fifth to seventh embodiments. That is, a photoelectric conversion device is provided in which the structure of the avalanche diode can be optimized in consideration of the position in the thickness direction of the substrate.

[0138] [Ninth embodiment] A photoelectric conversion device according to the ninth embodiment will be described. In the description of this embodiment, parts having the same functions as those of the first to eighth embodiments will be given the same reference numerals, and detailed description may be omitted or simplified. The photoelectric conversion device according to this embodiment is an example in which DTI (Deep Trench Isolation) is used as an element isolation region between pixels in the pixel 600 described in the fifth embodiment.

[0139] Fig. 29 is a schematic plan view of a photodiode according to this embodiment, and Fig. 30 is a schematic cross-sectional view of the photodiode according to this embodiment. The photodiodes in Figs. 29 and 30 differ from those in Figs. 14 and 15 of the fifth embodiment in that a DTI 617 is added. As shown in Fig. 29, the DTI 617 is arranged in a lattice pattern so as to surround two N-type semiconductor regions 601 in a plan view. Furthermore, as shown in Fig. 30, the DTI 617 is arranged on the side of the N-type semiconductor regions 601 and 602.

[0140] When electrons are generated in the N-type semiconductor region 601 by incident light, they may cross the potential barrier of the P-type semiconductor region 604 and move to an adjacent pixel, resulting in crosstalk. This crosstalk can also cause color mixing in a pixel configuration capable of color imaging. Furthermore, this crosstalk can be significant when the N-type semiconductor region 601 is thick enough to prevent incident light from the second surface from reaching the N-type semiconductor region 602. Therefore, in this embodiment, the effects of crosstalk are reduced by providing a DTI 617 with excellent insulation properties on the side of the N-type semiconductor regions 601 and 602, which are the path of electron migration to adjacent pixels. It is desirable for the DTI 617 to be formed to a depth approximately equal to that of the N-type semiconductor region 601, so that it is disposed at least on the side of the N-type semiconductor region 601 where electrons are generated.

[0141] [Tenth embodiment] A photoelectric conversion device according to a tenth embodiment will be described. In the description of this embodiment, parts having the same functions as those of the first to ninth embodiments will be given the same reference numerals, and detailed description may be omitted or simplified. In the photoelectric conversion device according to this embodiment, the number of photodiodes corresponding to one microlens ML in the pixel 600 described in the fifth embodiment is reduced to one.

[0142] FIG. 31 is a schematic plan view of a photodiode according to this embodiment. FIG. 32 is a schematic cross-sectional view of the photodiode according to this embodiment. FIG. 33 is a schematic perspective view of the photodiode according to this embodiment. FIG. 34 is a schematic plan view of a pixel according to this embodiment. The pixel 600 in FIGS. 31 to 34 is provided with only one N-type semiconductor region 602 (third photodiode group corresponding to the third microlens ML). In addition, the shape of the N-type semiconductor region 601 is modified so as to cover almost the entire microlens ML. This embodiment differs from FIGS. 14, 15, etc. of the fifth embodiment in these respects.

[0143] 31 and 32, the pixel 600 has only one N-type semiconductor region 602 arranged on the left side. Also, as shown in FIGS. 31 and 32, the N-type semiconductor region 601 is arranged so as to cover almost the entire microlens ML. As shown in FIGS. 33 and 34, since there is only one N-type semiconductor region 602, only one N-type semiconductor region 603 is also arranged. The number of gate electrodes 606 may also be only one, but as shown in FIGS. 33 and 34, two gate electrodes 606 may be arranged as in FIG. 18 in order to maintain symmetry of the arrangement.

[0144] The pixel 600 of this embodiment is used to acquire an image signal, not a signal for image plane phase difference autofocus. Each N-type semiconductor region 601 of this embodiment has roughly twice the area of ​​that of the fifth embodiment, and can generate twice as many electrons. Therefore, the sensitivity of each output signal is roughly doubled. Furthermore, since only one gate electrode 606 needs to be driven during readout, readout is faster.

[0145] As described above, this embodiment provides a photoelectric conversion device capable of capturing images at high speed and with high sensitivity. The pixel 600 of this embodiment is effective for applications such as electronic viewfinders, which require high-speed and high-sensitivity image capturing. By using the pixel 600 of this embodiment as some of the multiple pixels 600 included in the pixel unit 61 of FIG. 12, thinned images for an electronic viewfinder can be obtained at high speed and with high sensitivity.

[0146] [Eleventh embodiment] A photoelectric conversion device according to an eleventh embodiment will be described. In the description of this embodiment, parts having the same functions as those of the first to tenth embodiments will be denoted by the same reference numerals, and detailed description may be omitted or simplified. The photoelectric conversion device according to this embodiment differs from the pixel 600 described in the fifth embodiment in that the shapes of the two N-type semiconductor regions 601 are different.

[0147] Fig. 35 is a plan view schematic diagram showing the arrangement of semiconductor regions according to this embodiment. Fig. 36 is a cross-sectional view schematic diagram of a photodiode according to this embodiment. Fig. 37 is a perspective view schematic diagram of a photodiode according to this embodiment. The pixel 600 in Figs. 35 to 37 differs from Figs. 15, 19, etc. of the fifth embodiment in that the two N-type semiconductor regions 601 have different shapes and areas.

[0148] 35 and 36, the shapes and areas of the two N-type semiconductor regions 601 in plan view and cross-sectional view are different from each other. Also, as shown in Fig. 37, the shapes and volumes of the two N-type semiconductor regions 601 are different from each other.

[0149] Light that has passed through the optical system of an imaging system such as a camera is incident at an angle to the imaging surface of a pixel 600 located away from the center of the pixel section 61. The angle of this incident light affects the accuracy of image plane phase detection autofocus, so a known method of reducing this effect is to displace the optical axis of the microlens ML from the center of the pixel 600. In this case, it is desirable to displace the position of the N-type semiconductor region 601, which is the sensitive region, from the center and make it have a different shape, taking into account the deviation of the optical axis of the microlens ML. With this arrangement, the areas of the two N-type semiconductor regions 601 in plan view will be different from each other.

[0150] In this embodiment, the two N-type semiconductor regions 601 can be made to have different shapes, and therefore the shapes of the two N-type semiconductor regions 601 can be appropriately designed taking into account the coordinates within the pixel unit 61 or the position of the microlens ML. This improves the accuracy of image plane phase detection autofocus over a wide range within the pixel unit 61. Alternatively, the range within the pixel unit 61 where image plane phase detection autofocus is possible is expanded. Note that the angle of incident light to the pixel 600 changes smoothly depending on the coordinates (image height) within the pixel unit 61, and therefore, taking this into consideration, it is desirable to smoothly change the shape of the N-type semiconductor region 601 according to the coordinates (image height) within the pixel unit 61.

[0151] As described above, according to this embodiment, by making the shapes of the two N-type semiconductor regions 601 different, a photoelectric conversion device is provided in which the accuracy of image plane phase difference autofocus is improved.

[0152] [Twelfth embodiment] A photoelectric conversion device according to the twelfth embodiment will be described. In the description of this embodiment, parts having the same functions as those of the first to eleventh embodiments will be given the same reference numerals, and detailed description may be omitted or simplified. In this embodiment, modifications will be described in which the arrangement method of the pixels 600 described in the fifth to seventh embodiments is changed in various ways.

[0153] Figures 38(a), 38(b), 38(c), 38(d), and 38(e) are planar schematic diagrams showing examples of pixel arrangements according to this embodiment, and Figure 38(e) shows the legends for Figures 38(a), 38(b), 38(c), and 38(d).

[0154] Specifically, in Figures 38(a), 38(b), 38(c), and 38(d), the pattern within the square frame representing pixel 600 indicates whether pixel 600 is a red pixel, a green pixel, or a blue pixel. In other words, the pattern indicates the colors of the color filters CFR, CFG, and CFB provided in pixel 600. As shown in Figures 38(a), 38(b), 38(c), and 38(d), the color arrangement of these pixels 600 forms a Bayer array in which the same arrangement is repeated for a unit of four pixels in two rows and two columns.

[0155] The direction of the line segments in the pattern within the square frame representing the pixel 600 indicates the direction of the region 604c separating the two N-type semiconductor regions 601 of the P-type semiconductor region 604. In other words, the shapes of the two figures obtained by dividing the square by the line segments schematically represent the shapes of the two N-type semiconductor regions 601. As shown in FIG. 38(e), a separation method in which two N-type semiconductor regions 601 are arranged horizontally is called horizontal separation. A separation method in which two N-type semiconductor regions 601 are arranged vertically is called vertical separation. A separation method in which two N-type semiconductor regions 601 are arranged at the lower left and upper right is called first diagonal separation. A separation method in which two N-type semiconductor regions 601 are arranged at the upper left and lower right is called second diagonal separation. These separation directions correspond to the phase difference detection directions of image-plane phase-detection autofocus.

[0156] In the example of Figure 38(a), the pixels 600 in the first and second rows are horizontally separated, and the pixels 600 in the third and fourth rows are vertically separated. Rows 5 to 8 have a similar arrangement. In this way, in the example of Figure 38(a), four rows including two horizontally separated rows and two vertically separated rows form one unit, and the same arrangement is repeated every four rows.

[0157] In the example of Figure 38(b), the pixels 600 in the first and second rows are arranged in a repeated arrangement of horizontal separation and first diagonal separation, and the pixels 600 in the third and fourth rows are arranged in a repeated arrangement of second diagonal separation and vertical separation. Rows 5 to 8 have a similar arrangement. In this way, in the example of Figure 38(b), the same arrangement is repeated in a 4 row x 4 column unit including horizontal separation, vertical separation, first diagonal separation, and second diagonal separation.

[0158] In the example of FIG. 38(c), the pixels 600 in the first row are horizontally separated, and the pixels 600 in the second row are vertically separated. This arrangement is repeated for the third row and beyond. In this way, in the example of FIG. 38(c), the same arrangement is repeated every two rows, with two rows including one horizontally separated row and one vertically separated row as one unit. In this arrangement, a red pixel and a green pixel beside the red pixel are horizontally separated, and a blue pixel and a green pixel beside the blue pixel are vertically separated. In this way, a configuration may be possible in which pixel colors and separation directions are associated with each other so that pixels of some colors have a fixed separation direction.

[0159] In the example of FIG. 38(d), the red pixels in the first row are horizontally separated, and the green pixels in the first row are vertically separated. The green pixels in the second row are vertically separated, and the blue pixels in the second row are arranged in a repeated arrangement of first or second diagonal separation. These arrangements are repeated from the third row onward. Thus, in the example of FIG. 38(d), the same arrangement is repeated in a 2-row x 4-column unit, including horizontal separation, vertical separation, first diagonal separation, and second diagonal separation. In this arrangement, the green pixels adjacent to the red and blue pixels are horizontally separated, and the green pixels adjacent to the red pixels are vertically separated. The blue pixels are first or second diagonally separated. In this way, a configuration may be adopted in which pixel colors and separation directions are associated with each other so that some pixels of a certain color have a fixed separation direction.

[0160] As described above, in this embodiment, by including the pixels 600 separated in various directions in the pixel section 61, it is possible to obtain image plane phase difference autofocus signals in a variety of detection directions.

[0161] 38(a) to 38(e), the color of the pixel 600 may be a color other than red, green, and blue. For example, the color of the pixel 600 may be a complementary color such as cyan, magenta, or yellow, or may be white. Furthermore, the pixel 600 may be an infrared pixel having an infrared filter that transmits infrared light and blocks visible light.

[0162] The arrangement of the pixels 600 is not limited to the Bayer array, and may be other arrays. For example, it may be an array in which red pixels, green pixels, and blue pixels are arranged in the same row or column, a hexagonal array in which hexagonal pixels are arranged, or a staggered array in which pixel groups, each of which is a square unit such as the Bayer array, are arranged with a half-pitch offset. Also, some of the pixels 600 may be replaced with pixels 600 of the eleventh embodiment having one photodiode.

[0163] [Thirteenth embodiment] An imaging system according to the thirteenth embodiment will be described. The imaging system of this embodiment includes a photoelectric conversion device according to any one of the first to twelfth embodiments. The imaging system is a device used to capture still or moving images, such as a digital still camera, a digital video camera, or a digital camera for a mobile phone.

[0164] 39 is a block diagram of an imaging system according to a thirteenth embodiment. The imaging system has a lens unit 1001, a lens driving device 1002, a shutter 1003, a shutter driving device 1004, a photoelectric conversion device 1005, an imaging signal processing circuit 1006, and a timing generation unit 1007. The imaging system further has a memory unit 1008, an overall control and calculation unit 1009, a recording medium control I / F (Interface) unit 1010, a recording medium 1011, an external I / F unit 1012, and a photometric device 1013.

[0165] The lens unit 1001 is a part that forms an optical image of a subject on the photoelectric conversion device 1005. The lens driving device 1002 is a device that drives the lens unit 1001. The lens driving device 1002 performs zoom control, focus control, aperture control, etc. by driving the lens unit 1001. The shutter 1003 is an optical member that blocks incident light, and for example, a mechanical shutter may be used. The shutter 1003 may also function as an aperture. The shutter driving device 1004 controls the opening and closing of the shutter 1003.

[0166] The photoelectric conversion device 1005 is a photoelectric conversion device according to any one of the first to twelfth embodiments, and acquires an optical image of a subject formed by the lens unit 1001 by converting it into an image signal. The imaging signal processing circuit 1006 is a circuit that performs various corrections, data compression, etc. on the image signal output from the photoelectric conversion device 1005. The timing generation unit 1007 is a circuit that outputs various timing signals to the photoelectric conversion device 1005 and the imaging signal processing circuit 1006.

[0167] The overall control / calculation unit 1009 is a control circuit that performs various calculations and controls the entire imaging system. The memory unit 1008 is a recording device for temporarily recording image data output from the imaging signal processing circuit 1006. The recording medium control I / F unit 1010 is an interface for recording to or reading from a recording medium 1011. The recording medium 1011 is a removable recording medium such as a semiconductor memory, and is used for recording to or reading from image data. The external I / F unit 1012 is an interface for providing various information, captured images, etc. to the outside, and may be a communication interface with other information processing devices such as a computer, or a user interface for a display device, etc.

[0168] Next, we will explain the operation during shooting when the imaging system is a digital still camera with a distance measurement function. When the main power supply of the imaging system is turned on, the power supply for controlling the imaging system and the power supply for imaging that supplies power to the imaging signal processing circuit 1006 and other components are turned on sequentially.

[0169] When a user presses a release button (not shown), photoelectric conversion device 1005 acquires an image signal, and overall control / calculation unit 1009 performs distance measurement calculations based on the image signal data and calculates the distance to the subject based on the results. Lens driving device 1002 then drives lens unit 1001 based on the calculated distance to determine whether the subject is in focus, and if not, performs focus adjustment by driving lens unit 1001 again. The distance measurement calculations may be performed using the image signal acquired by photoelectric conversion device 1005 or by a dedicated distance measurement device (not shown).

[0170] Once focus is confirmed, the imaging system starts the imaging operation. After the imaging operation is completed, the image signal output from the photoelectric conversion device 1005 is processed in the imaging signal processing circuit 1006 and written to the memory unit 1008 under the control of the overall control and calculation unit 1009. The imaging signal processing circuit 1006 performs data rearrangement, addition, etc. The data recorded in the memory unit 1008 is recorded to the recording medium 1011 via the recording medium control I / F unit 1010 under the control of the overall control and calculation unit 1009. This data may also be input to a computer or the like via the external I / F unit 1012. The computer can perform processing such as image processing on the data output from the imaging system.

[0171] The imaging system of this embodiment includes the photoelectric conversion device of any of Embodiments 1 to 12. As a result, this embodiment provides a higher quality imaging system.

[0172] [Fourteenth embodiment] An imaging system and a moving body according to the fourteenth embodiment will be described below. Figures 40(a) and 40(b) are diagrams showing the configurations of an imaging system 300 and a moving body according to this embodiment.

[0173] FIG. 40(a) shows an example of an imaging system 300 related to an in-vehicle camera. The imaging system 300 includes a photoelectric conversion device 310. The photoelectric conversion device 310 of this embodiment is the photoelectric conversion device described in any one of the first to twelfth embodiments. The imaging system 300 includes an image processing unit 312 that performs image processing on multiple pieces of image data acquired by the photoelectric conversion device 310, and a parallax calculation unit 314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion device 310. The imaging system 300 also includes a distance measurement unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax calculation unit 314 and the distance measurement unit 316 are examples of distance information acquisition means that acquires distance information to the object. That is, the distance information includes information on the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 318 may determine the possibility of a collision using any of these pieces of distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0174] The imaging system 300 is connected to a vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force on the vehicle based on the determination result of a collision determination unit 318. The imaging system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the determination result of the collision determination unit 318. For example, if the determination result of the collision determination unit 318 indicates a high possibility of a collision, the control ECU 330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0175] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the imaging system 300. Fig. 40(b) shows an example of the arrangement of the imaging system 300 when imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the imaging system 300 or the photoelectric conversion device 310. This configuration can further improve the accuracy of distance measurement.

[0176] Although an example of control to prevent collision with other vehicles has been described, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the imaging system 300 is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0177] [Modified embodiment] The present invention is not limited to the above-described embodiments and can be modified in various ways. For example, an example in which part of the configuration of one embodiment is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also an embodiment of the present invention.

[0178] The devices or systems shown in the thirteenth and fourteenth embodiments are merely exemplary configurations of devices or systems to which the photoelectric conversion device of the present invention can be applied, and therefore devices or systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 39, 40(a) and 40(b).

[0179] The conductivity types of the semiconductor regions shown in the first to twelfth embodiments can be changed, for example, all conductivity types can be reversed. The pixel arrays shown in Figures 4, 6, 12, and 38(a) to 38(e) and the circuit configurations within the pixels shown in Figures 7 and 13 are merely examples and may be different.

[0180] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0181] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0182] 15, 17 Semiconductor substrate 16A, 16B separation section 71 First semiconductor region 72 Fourth Semiconductor Region 74 Third Semiconductor Region 75 5th Semiconductor Region 76 Second semiconductor region

Claims

1. a first substrate having a first surface; a first photoelectric conversion unit and a second photoelectric conversion unit, each having an avalanche photodiode, disposed on the first substrate; an isolation region provided between the first photoelectric conversion unit and the second photoelectric conversion unit; Equipped with each of the first photoelectric conversion unit and the second photoelectric conversion unit is defined by a portion surrounded by the isolation region, and includes a first semiconductor region provided at a first depth from the first surface, a second semiconductor region of a first conductivity type surrounding the first semiconductor region at the first depth, a third semiconductor region of a second conductivity type provided at a second depth from the first surface that is deeper than the first depth, and a fourth semiconductor region provided at a third depth from the first surface that is shallower than the first depth, and is configured to detect light incident from the first surface side and transfer charges from the fourth semiconductor region to the third semiconductor region; an area of ​​the first photoelectric conversion unit and an area of ​​the second photoelectric conversion unit in a cross section at the first depth are different, In the cross section at the second depth, the first photoelectric conversion unit and the second photoelectric conversion unit have the same length in a first direction, and the first photoelectric conversion unit and the second photoelectric conversion unit have the same length in a second direction intersecting with the first direction. A photoelectric conversion device characterized by:

2. The area of ​​the first photoelectric conversion unit in the cross section at the first depth is larger than the area of ​​the second photoelectric conversion unit in the cross section at the first depth.

2. The photoelectric conversion device according to claim 1.

3. the first photoelectric conversion unit is configured to receive light that has passed through a color filter that transmits green light; The second photoelectric conversion unit is configured to receive light that has passed through a color filter that transmits red light.

3. The photoelectric conversion device according to claim 2.

4. the first photoelectric conversion unit is configured to receive light that has passed through a color filter that transmits green light; The second photoelectric conversion unit is configured to receive light that has passed through a color filter that transmits blue light.

3. The photoelectric conversion device according to claim 2.

5. The area of ​​the first photoelectric conversion unit in the cross section at the second depth is the same as the area of ​​the second photoelectric conversion unit in the cross section at the second depth.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

6. The separation region extends in three directions in the cross section at the first depth.

6. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

7. The separation region comprises a first separation region surrounding the first photoelectric conversion unit at the first depth from the first surface, and a second separation region surrounding the first photoelectric conversion unit at the second depth from the first surface; The shape of the first isolation region is different from the shape of the second isolation region.

6. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

8. The shape of the first separation region is an octagon, and the shape of the second separation region is a rectangle.

8. The photoelectric conversion device according to claim 7.

9. The separation region further includes a third separation region surrounding the second photoelectric conversion unit at the first depth from the first surface, and a fourth separation region surrounding the second photoelectric conversion unit at the second depth from the first surface; The third isolation region and the fourth isolation region have the same shape.

9. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

10. The area of ​​the region surrounded by the third isolation region is different from the area of ​​the region surrounded by the fourth isolation region.

10. The photoelectric conversion device according to claim 9.

11. The shape of the third separation region is a rectangle, and the shape of the fourth separation region is a rectangle.

11. The photoelectric conversion device according to claim 9 or 10.

12. The first photoelectric conversion unit and the second photoelectric conversion unit further include a quench circuit connected to the avalanche photodiode.

12. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

13. a plurality of first photoelectric conversion units, each of which is the first photoelectric conversion unit; The second photoelectric conversion unit is disposed between one of the plurality of first photoelectric conversion units and another of the plurality of first photoelectric conversion units in a plan view.

13. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

14. a first substrate having a first surface; a photoelectric conversion unit disposed on the first substrate and having an avalanche photodiode; an isolation region surrounding the photoelectric conversion unit; Equipped with the photoelectric conversion unit is defined by a portion surrounded by the isolation region, and includes a first semiconductor region provided at a first depth from the first surface, a second semiconductor region of a first conductivity type surrounding the first semiconductor region at the first depth, a third semiconductor region of a second conductivity type provided at a second depth from the first surface that is deeper than the first depth, and a fourth semiconductor region provided at a third depth from the first surface that is shallower than the first depth, and is configured to detect light incident from the first surface side and transfer charges from the fourth semiconductor region to the third semiconductor region, The area of ​​the photoelectric conversion portion in the cross section at the first depth is smaller than the area of ​​the photoelectric conversion portion in the cross section at the second depth. A photoelectric conversion device characterized by:

15. The photoelectric conversion section is configured so that light that has passed through a color filter that transmits red light is incident thereon.

15. The photoelectric conversion device according to claim 14.

16. The photoelectric conversion unit is configured so that light that has passed through a color filter that transmits blue light is incident thereon.

15. The photoelectric conversion device according to claim 14.

17. The photoelectric conversion unit further includes a quench circuit connected to the avalanche photodiode.

17. The photoelectric conversion device according to claim 14, wherein the first and second electrodes are electrically connected to each other.

18. a second substrate provided on a second surface side of the first substrate opposite to the first surface, The first substrate and the second substrate are bonded via bonding surfaces where insulating members are bonded to each other and metal members are bonded to each other.

18. The photoelectric conversion device according to claim 1.

19. a second substrate provided on a second surface side of the first substrate opposite to the first surface; a waveform shaping unit disposed on the second substrate for shaping a waveform of a signal output from the avalanche photodiode into a pulse signal; Further provided with 18. The photoelectric conversion device according to claim 1.

20. a counter circuit disposed on the second substrate and configured to count the pulse signals output from the waveform shaping unit; 20. The photoelectric conversion device according to claim 19.

21. The photoelectric conversion device according to any one of claims 1 to 20, a signal processing unit that processes a signal output from the photoelectric conversion device; An imaging system comprising:

22. A mobile object, The photoelectric conversion device according to any one of claims 1 to 20, a distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object comprising:

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