Power supply device

Abstract

To provide a power supply device capable of suppressing an electrical stress without increasing the size of a circuit.SOLUTION: A power supply device comprises: a bridge circuit that includes arms of a plurality of phases each of which has first to fourth switching elements connected in series; a transformation circuit that includes primary side circuits of a plurality of phases that receive output voltages of the arms and resonate, and secondary side circuits of a plurality of phases that are electromagnetically coupled with the primary side circuits and output an AC voltage; and a control circuit that outputs the first to fourth switching signals to the first to fourth switching elements. The control circuit performs first control of setting a duty of the first switching signal of an arm of a phase with the largest current among the plurality of phases to be lower than a standard value.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power supply device. [Background technology]

[0002] In a three-phase, three-level LLC converter, variations in the currents of the three phases can occur due to individual differences in components, etc. This increases the electrical stress on the components in the phases with larger currents.

[0003] Patent Document 1 describes a technique for balancing currents by providing a PFC (Power Factor Correction) circuit for each phase. However, the technique described in Patent Document 1 requires a PFC circuit for each phase, which increases the size of the circuit.

[0004] Patent Document 2 describes a technology for reducing voltage stress on switching elements using a multilevel configuration. Non-Patent Document 1 describes a method for reducing thermal imbalance in the main switch by alternately performing asymmetric duty control. However, Patent Document 2 and Non-Patent Document 1 do not describe interleaved operation, nor do they describe current balance during interleaved operation.

[0005] Patent Document 3 describes balancing the currents in the resonant paths of multiple converters by inserting the primary windings of multiple transformers into the resonant paths of multiple converters and connecting the secondary windings of the multiple transformers in parallel. However, the technology described in Patent Document 3 requires multiple transformers and the secondary windings of the multiple transformers to be connected. Therefore, the technology described in Patent Document 3 results in a large circuit size. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-163657 [Patent Document 2] Patent Publication No. 2021-35328 [Patent Document 3] JP 2016-1980 A [Non-patent literature]

[0007] [Non-Patent Document 1] Dong Liu and others, “Periodically Swapping Modulation (PSM) Strategy for Three-Level(TL) DC / DC Converters With Balanced Switch Currents”, IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, January 2018, p.412-423 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of the present invention is to suppress electrical stress without increasing the size of the circuit. [Means for solving the problem]

[0009] A power supply device according to one aspect of the present invention comprises: a bridge circuit including arms of a plurality of phases, each of which has a first switching element, a second switching element, a third switching element, and a fourth switching element connected in series, wherein a first DC voltage is input to one end on a high potential side of the first switching element, a second DC voltage lower than the first DC voltage is input to a connection point between the second switching element and the third switching element, and one end on a low potential side of the fourth switching element is electrically connected to a reference potential; a transformer circuit including a primary circuit of a plurality of phases that receives the output voltage of the arm and resonates, and a secondary circuit of a plurality of phases that is electromagnetically coupled to the primary circuit and outputs an AC voltage; a rectifier circuit that rectifies the AC voltage; a smoothing circuit that smoothes the voltage output from the rectifier circuit; a control circuit that changes a second switching signal complementarily to the first switching signal, changes a fourth switching signal complementarily to the third switching signal, and outputs the first switching signal to the fourth switching signal from the first switching element to the fourth switching element so that the voltage of the smoothing circuit becomes a command value voltage or so that the current output from the rectifier circuit becomes a command value current; Equipped with The control circuit performing a first control to reduce the duty of the first switching signal of the arm of the phase having the largest current among the plurality of phases to a value smaller than a standard value; It is characterized by:

[0010] In the power supply device, The control circuit making the duty of the first switching signal of the arm of a phase in which a current is greater than an average current value of all phases of a primary side circuit, among a plurality of phases, smaller than the standard value; It is characterized by:

[0011] In the power supply device, The control circuit setting the duty of the first switching signal of the arm of a phase of which current is greater than the current average value among the plurality of phases to a duty corresponding to the difference from the current average value; It is characterized by:

[0012] In the power supply device, The control circuit In a first case where the first to fourth switching signals have frequencies equal to or lower than a predetermined frequency, in addition to the first control, a second control is performed to change the frequencies of the first to fourth switching signals; In a second case where the first to fourth switching signals have reached the predetermined frequency, in addition to the first control, a third control is performed to maintain the frequencies of the first to fourth switching signals at the predetermined frequency and to reduce the duty of the first switching signal to be smaller than the standard value. It is characterized by:

[0013] In the power supply device, The control circuit The duty of the first switching signal of the phase to be controlled by the first control is set to a smaller duty of the duty by the first control and the duty by the third control. It is characterized by:

[0014] In the power supply device, The control circuit In the second case, the duty of the third switching signal is made smaller than the standard value. It is characterized by: [Effects of the Invention]

[0015] The power supply device according to one aspect of the present invention has an effect of suppressing electrical stress without increasing the size of the circuit. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a power supply device according to a first embodiment. [Figure 2] FIG. 2 is a diagram illustrating an example of a waveform of a primary current of a transformer of each phase of the power supply device according to the first embodiment. [Figure 3] FIG. 3 is a diagram illustrating an example of a waveform of a switching signal of the power supply device according to the first embodiment. [Figure 4] FIG. 4 is a diagram illustrating an example of a waveform of a primary current of a transformer of each phase of the power supply device according to the first embodiment. [Figure 5]FIG. 5 is a diagram illustrating an example of output voltage-output current characteristics of the power supply device according to the first embodiment. [Figure 6] FIG. 6 is a diagram showing a simulation result of the output voltage-duty characteristics of the power supply device according to the first embodiment. [Figure 7] FIG. 7 is a diagram illustrating the configuration of a control circuit of the power supply device according to the first embodiment. [Figure 8] FIG. 8 is a diagram illustrating a configuration of a switching control circuit of the power supply device according to the first embodiment. [Figure 9] FIG. 9 is a diagram illustrating an example of waveforms of the switching control circuit of the power supply device according to the first embodiment. [Figure 10] FIG. 10 is a diagram illustrating an example of waveforms of switching signals of the power supply device according to the second embodiment. [Figure 11] FIG. 11 is a diagram illustrating a configuration of a switching control circuit of a power supply device according to the second embodiment. [Figure 12] FIG. 12 is a diagram illustrating an example of waveforms of the switching control circuit of the power supply device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A power supply device according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0018] First Embodiment (Overall configuration of the power supply unit) 1 is a diagram showing the configuration of a power supply device according to Embodiment 1. The power supply device 1 is a three-phase three-level LLC converter.

[0019] In the first embodiment, the number of phases is three, but the present disclosure is not limited to this. The number of phases may be two, or four or more.

[0020] Power supply 2 has a voltage V in Resistors 3 and 4 connected in series output a voltage V inThe resistance value of resistor 3 and the resistance value of resistor 4 are the same. That is, the voltage of each of resistors 3 and 4 is V in The capacitors 5 and 6 connected in series are connected to each other at a voltage V in Stabilize / 2.

[0021] The power supply device 1 includes a bridge circuit 11 , a transformer circuit 12 , a rectifier circuit 13 , a capacitor 14 , a voltage sensor 15 , current sensors 16 , 17 , 18 and 19 , and a control circuit 20 .

[0022] The capacitor 14 corresponds to an example of a "smoothing circuit" in the present disclosure.

[0023] The bridge circuit 11 includes a first phase arm 31 , a second phase arm 32 , and a third phase arm 33 .

[0024] The first phase arm 31 includes transistors Q1 to Q4.

[0025] The source of transistor Q1 is electrically connected to the drain of transistor Q2, the source of transistor Q2 is electrically connected to the drain of transistor Q3, and the source of transistor Q3 is electrically connected to the drain of transistor Q4.

[0026] The second phase arm 32 includes transistors Q5 through Q8.

[0027] The source of transistor Q5 is electrically connected to the drain of transistor Q6, the source of transistor Q6 is electrically connected to the drain of transistor Q7, the source of transistor Q7 is electrically connected to the drain of transistor Q8.

[0028] The third phase arm 33 includes transistors Q9 to Q12.

[0029] The source of transistor Q9 is electrically connected to the drain of transistor Q10, the source of transistor Q10 is electrically connected to the drain of transistor Q11, the source of transistor Q11 is electrically connected to the drain of transistor Q12.

[0030] Each of the transistors Q1, Q5, and Q9 corresponds to an example of a "first switching element" in the present disclosure. Each of the transistors Q2, Q6, and Q10 corresponds to an example of a "second switching element" in the present disclosure. Each of the transistors Q3, Q7, and Q11 corresponds to an example of a "third switching element" in the present disclosure. Each of the transistors Q4, Q8, and Q12 corresponds to an example of a "fourth switching element" in the present disclosure.

[0031] In the present disclosure, each transistor is a MOSFET, but is not limited to this, and each transistor may be a silicon power device, a GaN power device, a SiC power device, or the like.

[0032] Each transistor has a parasitic diode (body diode) that can actively conduct current, or has a diode connected in anti-parallel: the pn junction between the back gate and the source and drain of the MOSFET.

[0033] The drains of the transistors Q1, Q5, and Q9 are electrically connected to a first input terminal 11a of the bridge circuit 11. The first input terminal 11a is electrically connected to the high potential side end of the capacitor 5.

[0034] The source of transistor Q2, the drain of transistor Q3, the source of transistor Q6, the drain of transistor Q7, the source of transistor Q10, and the drain of transistor Q11 are electrically connected to a second input terminal 11b of bridge circuit 11. The second input terminal 11b is electrically connected to the low potential side end of capacitor 5 and the high potential side end of capacitor 6.

[0035] The sources of the transistors Q4, Q8, and Q12 are electrically connected to a third input terminal 11c of the bridge circuit 11. The third input terminal 11c is electrically connected to the low potential side end of the capacitor 6.

[0036] The voltage V of the capacitor 5 is applied between the first input terminal 11a and the second input terminal 11b of the bridge circuit 11. in / 2 is entered.

[0037] The voltage V of the capacitor 6 is applied between the second input terminal 11b and the third input terminal 11c of the bridge circuit 11. in / 2 is entered.

[0038] A switching signal is input from the control circuit 20 to the gates of the transistors Q1 to Q12.

[0039] The control circuit 20 may, for example, control the phase difference between the first phase arm 31 and the second phase arm 32 to 120°. The control circuit 20 may, for example, control the phase difference between the second phase arm 32 and the third phase arm 33 to 120°. However, the present disclosure is not limited to this.

[0040] The source of the transistor Q1 and the drain of the transistor Q2 are electrically connected to a first output terminal 11d of the bridge circuit 11. The source of the transistor Q3 and the drain of the transistor Q4 are electrically connected to a second output terminal 11e of the bridge circuit 11.

[0041] The source of the transistor Q5 and the drain of the transistor Q6 are electrically connected to the third output terminal 11f of the bridge circuit 11. The source of the transistor Q7 and the drain of the transistor Q8 are electrically connected to the fourth output terminal 11g of the bridge circuit 11.

[0042] The source of the transistor Q9 and the drain of the transistor Q10 are electrically connected to a fifth output terminal 11h of the bridge circuit 11. The source of the transistor Q11 and the drain of the transistor Q12 are electrically connected to a sixth output terminal 11i of the bridge circuit 11.

[0043] The transformer circuit 12 includes transformers 41 to 43 .

[0044] The transformer 41 includes a primary winding 41a, a secondary winding 41b, and a core 41c. The primary winding 41a and the secondary winding 41b are wound around the core 41c.

[0045] The primary winding 41a includes an excitation inductance 51 and a leakage inductance 52. A capacitor 53 is provided in the primary winding 41a in series with the excitation inductance 51 and the leakage inductance 52. One end of the primary winding 41a is electrically connected to a first output terminal 11d of the bridge circuit 11. The other end of the primary winding 41a is electrically connected to a second output terminal 11e of the bridge circuit 11.

[0046] The magnetizing inductance 51, the leakage inductance 52, and the capacitor 53 form an LLC resonant circuit.

[0047] The current sensor 17 detects the current I1 in the primary winding 41a of the transformer 41 and outputs a detection signal to the control circuit 20.

[0048] The transformer 42 includes a primary winding 42a, a secondary winding 42b, and a core 42c. The primary winding 42a and the secondary winding 42b are wound around the core 42c.

[0049] The primary winding 42a includes an excitation inductance 54 and a leakage inductance 55. A capacitor 56 is provided in the primary winding 42a in series with the excitation inductance 54 and the leakage inductance 55. One end of the primary winding 42a is electrically connected to the third output terminal 11f of the bridge circuit 11. The other end of the primary winding 42a is electrically connected to the fourth output terminal 11g of the bridge circuit 11.

[0050] The magnetizing inductance 54, the leakage inductance 55, and the capacitor 56 form an LLC resonant circuit.

[0051] The current sensor 18 detects a current I2 in the primary winding 42a of the transformer 42 and outputs a detection signal to the control circuit 20.

[0052] The transformer 43 includes a primary winding 43a, a secondary winding 43b, and a core 43c. The primary winding 43a and the secondary winding 43b are wound around the core 43c.

[0053] The primary winding 43a includes an excitation inductance 57 and a leakage inductance 58. A capacitor 59 is connected to the primary winding 43a in series with the excitation inductance 57 and the leakage inductance 58. One end of the primary winding 43a is electrically connected to a fifth output terminal 11h of the bridge circuit 11. The other end of the primary winding 43a is electrically connected to a sixth output terminal 11i of the bridge circuit 11.

[0054] The magnetizing inductance 57, the leakage inductance 58, and the capacitor 59 form an LLC resonant circuit.

[0055] The current sensor 19 detects the current I3 in the primary winding 43a of the transformer 43 and outputs a detection signal to the control circuit 20.

[0056] One end of the secondary winding 41b of the transformer 41, one end of the secondary winding 42b of the transformer 42, and one end of the secondary winding 43b of the transformer 43 are electrically connected to each other.

[0057] The rectifier circuit 13 is a bridge diode and includes diodes D1 to D6.

[0058] The anode of diode D1 is electrically connected to the cathode of diode D2, the anode of diode D3 is electrically connected to the cathode of diode D4, and the anode of diode D5 is electrically connected to the cathode of diode D6.

[0059] The anode of diode D1 and the cathode of diode D2 are electrically connected to the other end of the secondary winding 41b of the transformer 41. The anode of diode D3 and the cathode of diode D4 are electrically connected to the other end of the secondary winding 42b of the transformer 42. The anode of diode D5 and the cathode of diode D6 are electrically connected to the other end of the secondary winding 43b of the transformer 43.

[0060] The cathodes of diode D1, diode D3, and diode D5 are electrically connected to the high potential side terminal of capacitor 14. The anodes of diode D2, diode D4, and diode D6 are electrically connected to the low potential side terminal of capacitor 14.

[0061] The capacitor 14 smoothes the voltage output by the rectifier circuit 13. The voltage of the capacitor 14 is equal to the output voltage V out is.

[0062] The voltage sensor 15 measures the output voltage V out and outputs a detection signal to the control circuit 20.

[0063] The current sensor 16 detects the output current I out and outputs a detection signal to the control circuit 20.

[0064] (Control Overview) Generally, in an LLC converter, the duty of each transistor is set to 0.5 (hereinafter referred to as the "standard value"). The control circuit 20 synchronizes the transistors Q1 and Q4 (same phase and same duty) and synchronizes the transistors Q2 and Q3. Similarly, the control circuit 20 synchronizes the transistors Q5 and Q8 and synchronizes the transistors Q6 and Q7. Similarly, the control circuit 20 synchronizes the transistors Q9 and Q12 and synchronizes the transistors Q10 and Q11.

[0065] 2 is a diagram showing an example of a waveform of a primary current of each phase of the transformer of the power supply device according to the first embodiment, in which the vertical axis represents current and the horizontal axis represents time.

[0066] A waveform 201 represents a current I1 in the primary winding 41a of the transformer 41. A waveform 202 represents a current I2 in the primary winding 42a of the transformer 42. A waveform 203 represents a current I3 in the primary winding 43a of the transformer 43.

[0067] Due to individual differences between components, the current in one phase may be larger than the currents in the other phases. In the example shown in Fig. 2, the current I3 (waveform 203) in the primary winding 43a of the transformer 43 is larger than the current I1 (waveform 201) in the primary winding 41a of the transformer 41 and the current I2 (waveform 202) in the primary winding 42a of the transformer 42. Therefore, the electrical stress on the components in the third phase is large.

[0068] Therefore, the control circuit 20 reduces the duty of the first transistor from the standard value while maintaining the switching frequency of the first to fourth transistors of the phase having a larger current than the other phases. In the example shown in FIG. 2, the control circuit 20 reduces the duty of transistor Q9 from the standard value while maintaining the switching frequency of transistors Q9 to Q12 of the third-phase arm 33. Hereinafter, this control will be referred to as "first control."

[0069] Fig. 3 is a diagram showing an example of the waveforms of the switching signals of the power supply device of the first embodiment. More specifically, Fig. 3 is a diagram showing an example of the waveforms of the switching signals input to the gates of transistors Q1 to Q12 when control circuit 20 performs the first control.

[0070] In FIG. 3, the dead time and the 120-degree phase difference between the phases are omitted.

[0071] 3(a) shows waveforms of switching signals input to the gates of transistors Q1 to Q4 of the first phase arm 31. Waveform 211 shows the switching signal input to the gate of transistor Q1. Waveform 212 shows the switching signal input to the gate of transistor Q2. Waveform 213 shows the switching signal input to the gate of transistor Q3. Waveform 214 shows the switching signal input to the gate of transistor Q4.

[0072] 3(b) shows waveforms of switching signals input to the gates of transistors Q5 to Q8 in the second phase arm 32. Waveform 215 shows the switching signal input to the gate of transistor Q5. Waveform 216 shows the switching signal input to the gate of transistor Q6. Waveform 217 shows the switching signal input to the gate of transistor Q7. Waveform 218 shows the switching signal input to the gate of transistor Q8.

[0073] 3(c) shows waveforms of switching signals input to the gates of transistors Q9 to Q12 in the third phase arm 33. Waveform 219 shows the switching signal input to the gate of transistor Q9. Waveform 220 shows the switching signal input to the gate of transistor Q10. Waveform 221 shows the switching signal input to the gate of transistor Q11. Waveform 222 shows the switching signal input to the gate of transistor Q12.

[0074] The frequencies of the switching signals input to the gates of the transistors Q1 to Q12 are the same.

[0075] An ON period 223 of the switching signal (waveform 211) input to the gate of the transistor Q1 is half of one cycle 224.

[0076] The on-period 225 of the switching signal (waveform 215) input to the gate of the transistor Q5 is half of one cycle 226.

[0077] The on-period 227 of the switching signal (waveform 219) input to the gate of transistor Q9 is less than half of one cycle 228.

[0078] Fig. 4 is a diagram showing an example of the waveform of the primary current of the transformer of each phase of the power supply device of the first embodiment. More specifically, Fig. 4 is a diagram showing an example of the waveform of the primary current of the transformer of each phase when the control circuit 20 performs the first control. In Fig. 4, the vertical axis represents the current, and the horizontal axis represents the time.

[0079] A waveform 231 represents a current I1 in the primary winding 41a of the transformer 41. A waveform 232 represents a current I2 in the primary winding 42a of the transformer 42. A waveform 233 represents a current I3 in the primary winding 43a of the transformer 43.

[0080] Comparing FIG. 4 with FIG. 2, the current I3 (waveform 233) in the primary winding 43a of the transformer 43 is suppressed, and the difference in current among the three phases is reduced.

[0081] This allows the power supply device 1 to suppress electrical stress on the third phase components.

[0082] The phase for which the duty is to be reduced is, for example, a phase having a current greater than the average current of the three phases, or a phase having the largest current.

[0083] Furthermore, the control circuit 20 increases the switching frequency of each transistor to increase the output voltage V outHereinafter, this control will be referred to as "second control."

[0084] However, to maintain LLC resonance and soft switching, there is an upper limit to the switching frequency. out has a lower limit (hereinafter referred to as the "second control lower limit voltage").

[0085] 5 is a diagram showing an example of the output voltage-output current characteristics of the power supply device according to the first embodiment. In FIG. 5, the vertical axis represents the output voltage V out The horizontal axis represents the output current I out Represents.

[0086] The range of output voltage-output current that the power supply device 1 can output under the second control is an area 242 in FIG. 5 above a boundary line 241 indicating the second control lower limit voltage.

[0087] Therefore, when the switching frequency reaches the upper limit, the control circuit 20 reduces the duty of the transistor Q1 (Q5, Q9) below the standard value while maintaining the switching frequency at the upper limit. Hereinafter, this control will be referred to as "third control."

[0088] The control circuit 20 sets the duty of the first switching signal of the phase targeted by the first control to the smaller of the duty obtained by the first control and the duty obtained by the third control. In the example shown in Fig. 2, the control circuit 20 sets the duty of the transistor Q9 of the third phase arm to the smaller of the duty obtained by the first control and the duty obtained by the third control.

[0089] In this way, the power supply device 1 can output a voltage that is even lower than the second control lower limit voltage by performing the third control when the switching frequency reaches the upper limit.

[0090] 6 is a diagram showing the results of a simulation of the output voltage-duty characteristics of the power supply device according to the first embodiment. In FIG. 6, the vertical axis represents the output voltage Vout The horizontal axis represents the duty.

[0091] As shown by waveform 251 in FIG. 6, the power supply device 1 reduces the output voltage V out can be lowered.

[0092] In this way, the power supply device 1 performs the third control when the switching frequency reaches the upper limit, thereby reducing the output voltage V out can be further reduced below the second control lower limit voltage.

[0093] Referring again to FIG. 5, the power supply device 1 operates when the output voltage V out Therefore, the range of output voltage-output current that can be output by the power supply device 1 is an area 244 that combines the area 242 and an area 243 below the boundary line 241 in FIG.

[0094] (Control circuit configuration) FIG. 7 is a diagram illustrating the configuration of a control circuit of the power supply device according to the first embodiment.

[0095] The control circuit 20 includes a switching control circuit 61 and a dead time generation circuit 62.

[0096] The dead time generating circuit 62 generates a plurality of switching signals S output from the switching control circuit 61. SW An arbitrary dead time is provided between the signals of the transistors that operate complementarily, and the signals are output from transistor Q1 to transistor Q12.

[0097] FIG. 8 is a diagram illustrating a configuration of a switching control circuit of the power supply device according to the first embodiment.

[0098] In the first embodiment, the switching control circuit 61 controls the output voltage V outThe switching control circuit 61 controls the output current I to a target voltage. out It is also possible to perform constant output current control so that the target current is reached.

[0099] The switching control circuit 61 includes an average value calculation circuit 71, error amplifiers 72, 73, and 74, resistors 91 and 92, a variable voltage source 93, an error amplifier 94, a voltage limiter 95, a voltage controlled oscillator 96, a constant voltage source 97, an error amplifier 98, comparators 99, 100, and 101, and inversion circuits 105, 106, and 107.

[0100] The average value calculation circuit 71 converts the current I1 of the primary winding 41a of the transformer 41 into a voltage V I1 , a voltage V obtained by converting the current I2 of the primary winding 42a of the transformer 42 into a voltage. I2 , and the voltage V obtained by converting the current I3 of the primary winding 43a of the transformer 43 into a voltage. I3 is entered.

[0101] The average value calculation circuit 71 calculates the voltage V I1 to voltage V I3 Average voltage V 21 is output to the inverting input terminals (- terminals) of the error amplifiers 72 to 74.

[0102] The non-inverting input terminal (+ terminal) of the error amplifier 72 is connected to the voltage V I1 The error amplifier 72 receives the voltage V I1 and voltage V 21 Voltage V according to the difference 22 is output to the anode of the diode 75.

[0103] The cathode of the diode 75 is electrically connected to the node N1.

[0104] The non-inverting input terminal (+ terminal) of the error amplifier 73 is connected to the voltage V I2 The error amplifier 73 receives the voltage V I2 and voltage V21 Voltage V according to the difference 23 is output to the anode of the diode 76.

[0105] The cathode of the diode 76 is electrically connected to the node N2.

[0106] The non-inverting input terminal (+ terminal) of the error amplifier 74 is connected to the voltage V I3 The error amplifier 74 receives the voltage V I3 and voltage V 21 Voltage V according to the difference 24 is output to the anode of the diode 77.

[0107] The cathode of the diode 77 is electrically connected to the node N3.

[0108] One end of resistor 91 is connected to the output voltage V out is input. The other end of the resistor 91 is electrically connected to one end of a resistor 92. The other end of the resistor 92 is electrically connected to a reference potential.

[0109] In the case of constant output current control, the output current I out is converted into voltage V Iout is entered.

[0110] The other end of the resistor 91 and one end of the resistor 92 are electrically connected to the non-inverting input terminal (+ terminal) of the error amplifier 94. The resistors 91 and 92 are connected to the output voltage V out The divided voltage V 31 is output to the non-inverting input terminal (+ terminal) of the error amplifier 94.

[0111] The variable voltage source 93 outputs an output voltage V out The command voltage V according to the target voltage o-ref is output to the inverting input terminal (- terminal) of the error amplifier 94.

[0112] In the case of output current control, the variable voltage source 93 controls the output current I outA voltage corresponding to the target current is output to the inverting input terminal (- terminal) of the error amplifier 94.

[0113] The error amplifier 94 outputs the voltage V 31 and the command voltage V o-ref Voltage V according to the difference E1 is output to the voltage limiter 95 and the non-inverting input terminal (+ terminal) of the error amplifier 98.

[0114] The voltage limiter 95 limits the voltage V E1 The voltage limiter lower limit voltage V fmin to the voltage limiter upper limit voltage V fmax Voltage V limited to the range 32 is output to the voltage controlled oscillator 96.

[0115] The voltage limiter 95 is used to limit the oscillation frequency of the voltage-controlled oscillator 96 within the range from the lower limit frequency to the upper limit frequency of the LLC resonant circuit. fmin to the voltage limiter upper limit voltage V fmax The range is up to the voltage V E1 is narrower than the range in which

[0116] The voltage controlled oscillator 96 generates a voltage V 32 A triangular wave signal V with a frequency according to tri1 , V tri2 and V tri3 are output to the non-inverting input terminal (+ terminal) of the comparator 99, the non-inverting input terminal (+ terminal) of the comparator 100, and the non-inverting input terminal (+ terminal) of the comparator 101, respectively.

[0117] The voltage controlled oscillator 96 generates a triangular wave signal V tri1 and the triangular wave signal V tri2 The voltage controlled oscillator 96 generates a triangular wave signal V tri2 and the triangular wave signal V tri3 The phase difference between

[0118] The voltage controlled oscillator 96 generates a voltage V 32 The higher the triangular wave signal Vtri1 , V tri2 and V tri3 By increasing the frequency of 32 The lower the triangular wave signal V tri1 , V tri2 and V tri3 Lower the frequency of

[0119] Triangular wave signal V tri1 , V tri2 and V tri3 The frequency of the voltage V 32 is the voltage limiter lower limit voltage V fmin The minimum is reached when the triangular wave signal V tri1 , V tri2 and V tri3 The frequency of the voltage V 32 is the voltage limiter upper limit voltage V fmax It is maximum when

[0120] The voltage controlled oscillator 96 generates a triangular wave signal V tri1 , V tri2 and V tri3 Each of these is changed in the positive and negative directions with 0V as the center.

[0121] The constant voltage source 97 supplies a voltage V fmax-ref is output to the inverting input terminal (- terminal) of the error amplifier 98.

[0122] In addition, the voltage V fmax-ref is the voltage limiter upper limit voltage V fmax It is the same as

[0123] The error amplifier 98 outputs the voltage V E1 and voltage V fmax-ref Voltage V according to the difference E2 is output to the anodes of the diodes 78 through 80.

[0124] The cathode of the diode 78 is electrically connected to the node N1.

[0125] The voltage at node N1 is V 22 and voltage V E2The voltage will be the higher of the two.

[0126] The cathode of the diode 79 is electrically connected to the node N2.

[0127] The voltage at node N2 is V 23 and voltage V E2 The voltage will be the higher of the two.

[0128] The cathode of diode 80 is electrically connected to node N3.

[0129] The voltage at node N3 is V 24 and voltage V E2 The voltage will be the higher of the two.

[0130] The voltage at node N1 is input to the inverting input terminal (- terminal) of comparator 99.

[0131] Comparator 99 outputs the triangular wave signal V tri1 If the voltage at node N1 is higher than the voltage at node N2, a high-level voltage V 33 The comparator 99 outputs the triangular wave signal V tri1 If the voltage is higher than the low-level voltage V 33 Output.

[0132] For example, voltage V 22 becomes low when the current I1 is smaller than the average value of the currents I1 to I3 (when the first phase is not subject to the first control). tri1 and voltage V E2 Compare with.

[0133] 9 is a diagram showing an example of waveforms of the switching control circuit of the power supply device according to the first embodiment. In detail, FIG. 9 shows the voltage of node N1 (voltage V output by error amplifier 98) when current I1 is smaller than the average value of currents I1 to I3 (when the first phase is not subject to the first control) or when current I2 or current I3 is larger than current I1. E2) and the triangular wave signal V output by the voltage controlled oscillator 96 tri1 10A and 10B are diagrams showing waveforms of

[0134] Waveform 261 represents the voltage at node N1 (the voltage V E2 ) Waveform 262 shows the triangular wave signal V tri1 As explained earlier, the triangular wave signal V tri1 changes in the positive and negative directions with 0V as the center.

[0135] Timing t 10 The voltage V output by the error amplifier 94 is E1 is the voltage V fmax-ref In this case, as shown by the waveform 261, the voltage at the node N1 (the voltage V output by the error amplifier 98) E2 ) is 0V. Therefore, the voltage V output by the comparator 99 is 33 The duty is the standard value (0.5).

[0136] Timing t 10 The voltage V output by the error amplifier 94 is E1 is the voltage V fmax-ref When the voltage at node N1 (the voltage V output by error amplifier 98) becomes higher than E2 ) is the voltage V E1 As the voltage rises, it rises from 0V. Therefore, the voltage V output by the comparator 99 33 The duty of decreases from the standard value.

[0137] Referring again to FIG. 8, for example, the voltage V 22 becomes high when the current I1 is greater than the average value of the currents I1 to I3 (when the first phase is the target of the first control). 22 is the voltage V E2 If it is higher than V, the triangular signal V tri1 and voltage V 22 Therefore, the voltage V 33 The duty of the

[0138] The voltage V output by comparator 99 33 is output to the gates of the transistors Q1 and Q4 via the dead time generating circuit 62.

[0139] When the switching control circuit 61 synchronizes the transistors Q1 and Q4, the voltage V output by the comparator 99 is 33 can be shared by the transistor Q1 and the transistor Q4. That is, the switching control circuit 61 can easily generate a switching signal, and the control becomes easier.

[0140] The inverter circuit 105 outputs a voltage V 33 The logically inverted voltage V 39 Output.

[0141] The voltage V output by the inverter circuit 105 39 is output to the gates of the transistors Q2 and Q3 via the dead time generating circuit 62.

[0142] When the switching control circuit 61 synchronizes the transistors Q2 and Q3, the voltage V output by the inverting circuit 105 is 39 can be shared by the transistors Q2 and Q3. That is, the switching control circuit 61 can easily generate a switching signal, and the control becomes easier.

[0143] The inverting input terminal (negative terminal) of the comparator 100 receives the voltage at the node N2.

[0144] The comparator 100 outputs a triangular wave signal V tri2 If the voltage at node N1 is higher than the voltage at node N2, a high-level voltage V 34 The comparator 100 outputs the triangular wave signal V tri2 If the voltage is higher than the low-level voltage V 34 Output.

[0145] For example, voltage V 23becomes low when the current I2 is smaller than the average value of the currents I1 to I3 (when the second phase is not subject to the first control). tri2 and voltage V E2 Compare with.

[0146] For example, voltage V 23 becomes high when the current I2 is greater than the average value of the currents I1 to I3 (when the second phase is subject to the first control). 23 is the voltage V E2 If it is higher than V, the triangular signal V tri2 and voltage V 23 Therefore, the voltage V 34 The duty of the

[0147] The voltage V output by comparator 100 34 is output to the gates of the transistors Q5 and Q8 via the dead time generating circuit 62.

[0148] When the switching control circuit 61 synchronizes the transistors Q5 and Q8, the voltage V output by the comparator 100 is 34 can be shared by the transistors Q5 and Q8. That is, the switching control circuit 61 can easily generate a switching signal, and the control becomes easier.

[0149] The inverter circuit 106 outputs a voltage V 34 The logically inverted voltage V 40 Output.

[0150] The voltage V output by the inverter circuit 106 40 is output to the gates of the transistors Q6 and Q7 via the dead time generating circuit 62.

[0151] When the switching control circuit 61 synchronizes the transistors Q6 and Q7, the voltage V output by the inverter circuit 106 is 40can be shared by the transistors Q6 and Q7. That is, the switching control circuit 61 can easily generate a switching signal, and the control becomes easier.

[0152] The voltage at node N3 is input to the inverting input terminal (negative terminal) of comparator 101.

[0153] Comparator 101 outputs a triangular wave signal V tri3 If the voltage at node N1 is higher than the voltage at node N3, a high-level voltage V 35 The comparator 101 outputs the triangular wave signal V tri3 If the voltage is higher than the low-level voltage V 35 Output.

[0154] For example, voltage V 24 becomes low when the current I3 is smaller than the average value of the currents I1 to I3 (when the third phase is not subject to the first control). tri3 and voltage V E2 Compare with.

[0155] For example, voltage V 24 becomes high when the current I3 is greater than the average value of the currents I1 to I3 (when the third phase is subject to the first control) or when the current I3 is the maximum value of the currents I1 to I3. 24 is the voltage V E2 If it is higher than V, the triangular signal V tri3 and voltage V 24 Therefore, the voltage V 35 The duty of the

[0156] The voltage V output by comparator 101 35 is output to the gates of the transistors Q9 and Q12 via the dead time generating circuit 62.

[0157] When the switching control circuit 61 synchronizes the transistors Q9 and Q12, the voltage V output by the comparator 101 is 35 can be shared by the transistor Q9 and the transistor Q12. That is, the switching control circuit 61 can easily generate a switching signal, and the control becomes easier.

[0158] The inverter circuit 107 outputs a voltage V 35 The logically inverted voltage V 41 Output.

[0159] The voltage V output by the inverter circuit 107 41 is output to the gates of the transistors Q10 and Q11 via the dead time generating circuit 62.

[0160] When the switching control circuit 61 synchronizes the transistors Q10 and Q11, the voltage V output by the inverting circuit 107 is 41 can be shared by the transistor Q10 and the transistor Q11. That is, the switching control circuit 61 can easily generate a switching signal, and the control becomes easier.

[0161] (summary) As described above, the switching control circuit 61 performs the first control to reduce the duty of the phase in which the current is greater than the average current of the three phases (or the phase in which the current is the greatest).

[0162] This allows the power supply device 1 to reduce the current of the phase with a large current, and therefore the power supply device 1 can suppress electrical stress without increasing the size of the circuit.

[0163] Furthermore, the switching control circuit 61 controls the output voltage V outWhen the switching frequency of each transistor is lowered, if the switching frequency is equal to or lower than the upper limit, the switching control circuit 61 performs a second control to increase the switching frequency. When the switching frequency of each transistor reaches the upper limit, the switching control circuit 61 performs a third control to lower the duty of the transistor Q1 (Q5, Q9) below the standard value while maintaining the switching frequency.

[0164] This allows the power supply device 1 to reduce the output voltage V out can be further reduced below the second control lower limit voltage.

[0165] It is preferable that the switching control circuit 61 sets the duty of the transistor Q4 (Q8, Q12) to be the same as the duty of the transistor Q1 (Q5, Q9).

[0166] As a result, for example, the switching control circuit 61 generates one switching signal (voltage V 33 ) can be shared by the transistor Q1 and the transistor Q4. That is, the switching control circuit 61 can easily generate a switching signal, and the control becomes easier.

[0167] (Addendum) The switching control circuit 61 may be provided with hysteresis when switching between the second control and the third control. For example, the error amplifier 94 (see FIG. 8) may be replaced with a hysteresis comparator.

[0168] This allows the switching control circuit 61 to suppress frequent switching between the second control and the third control.

[0169] The switching control circuit 61 may be configured to perform PSM control (see Non-Patent Document 1) in the case of the first control or the third control.

[0170] <Second embodiment> Of the components of the second embodiment, the same components as those of the first embodiment are denoted by the same reference numerals and description thereof will be omitted.

[0171] (Overall configuration of the power supply unit) The overall configuration of the power supply device of the second embodiment is similar to that of the power supply device 1 of the first embodiment (see FIG. 1), and therefore will not be illustrated or described again.

[0172] (Control Overview) In the first embodiment, the control circuit synchronizes (same phase and duty) transistors Q1 (Q5, Q9) and Q4 (Q8, Q12) and synchronizes transistors Q2 (Q6, Q10) and Q3 (Q7, Q11).

[0173] The current in the primary circuits of the transformers 41, 42, and 43 changes significantly when the transistor Q1 (Q5, Q9) changes from the off state to the on state and when the transistor Q3 (Q7, Q11) changes from the off state to the on state.

[0174] In the waveforms 219 to 222 shown in Figure 3(c), the timing at which the output current of the primary circuit of the transformer 43 changes significantly is biased towards the first half of one control cycle 228. Therefore, there is a possibility that a large ripple current will flow in the capacitor 14 (see Figure 1).

[0175] Therefore, in the second embodiment, the control circuit reduces the duty of the transistor Q1 (Q5, Q9) and also reduces the duty of the transistor Q3 (Q7, Q11).

[0176] It is preferable that the control circuit sets the duty of the transistor Q1 (Q5, Q9) to be the same as the duty of the transistor Q3 (Q7, Q11), which makes it easier for the control circuit to generate a switching signal, as will be described later.

[0177] Fig. 10 is a diagram illustrating an example of waveforms of switching signals of the power supply device according to the second embodiment. Specifically, Fig. 10 is a diagram illustrating an example of waveforms of switching signals input to the gates of transistors Q1 to Q12 when the control circuit performs the first control.

[0178] In FIG. 10, the dead time and the 120-degree phase difference between the phases are omitted.

[0179] 10(a) shows waveforms of switching signals input to the gates of transistors Q1 to Q4 in the first phase arm 31. Waveform 271 shows the switching signal input to the gate of transistor Q1. Waveform 272 shows the switching signal input to the gate of transistor Q2. Waveform 273 shows the switching signal input to the gate of transistor Q3. Waveform 274 shows the switching signal input to the gate of transistor Q4.

[0180] 10(b) shows waveforms of switching signals input to the gates of transistors Q5 to Q8 in the second phase arm 32. Waveform 275 shows the switching signal input to the gate of transistor Q5. Waveform 276 shows the switching signal input to the gate of transistor Q6. Waveform 277 shows the switching signal input to the gate of transistor Q7. Waveform 278 shows the switching signal input to the gate of transistor Q8.

[0181] 10(c) shows waveforms of switching signals input to the gates of transistors Q9 to Q12 in the third phase arm 33. Waveform 279 shows the switching signal input to the gate of transistor Q9. Waveform 280 shows the switching signal input to the gate of transistor Q10. Waveform 281 shows the switching signal input to the gate of transistor Q11. Waveform 282 shows the switching signal input to the gate of transistor Q12.

[0182] The frequencies of the switching signals input to the gates of the transistors Q1 to Q12 are the same.

[0183] An ON period 283 of the switching signal (waveform 271) input to the gate of the transistor Q1 is half of one cycle 284.

[0184] The on-period 285 of the switching signal (waveform 275) input to the gate of transistor Q5 is half of one cycle 286.

[0185] The on-period 287 of the switching signal (waveform 279) input to the gate of transistor Q9 is less than half of one cycle 288.

[0186] Comparing Figure 10(c) with Figure 3(c), the on-period 289 of the switching signal (waveform 281) input to the gate of transistor Q11 is shorter than the on-period 229 of the switching signal (waveform 221) input to the gate of transistor Q11 in Figure 3(c).

[0187] As a result, the control circuit can alternate the rising edges of the transistors Q1 and Q3 (at equal intervals when the phase difference is 180°), thereby shifting the timing at which the primary currents of the transformers 41, 42, and 43 change significantly. Therefore, the power supply device 1 can suppress the ripple current flowing through the capacitor 14.

[0188] Preferably, the control circuit sets the phase difference between the phase of the transistor Q1 and the phase of the transistor Q3 to 180°, which makes it easier for the control circuit to generate a switching signal, as will be described later.

[0189] (Control circuit configuration) The overall configuration of the control circuit of the second embodiment is similar to that of the control circuit 20 of the first embodiment (see FIG. 7), and therefore will not be illustrated or described.

[0190] FIG. 11 is a diagram illustrating a configuration of a switching control circuit of a power supply device according to the second embodiment.

[0191] In the second embodiment, the switching control circuit 63 controls the output voltage V out The switching control circuit 63 controls the output current I to a target voltage. out It is also possible to perform constant output current control so that the target current is reached.

[0192] Compared to the switching control circuit 61 (see FIG. 8), the switching control circuit 63 includes a voltage controlled oscillator 131 instead of the voltage controlled oscillator 96. Compared to the switching control circuit 61, the switching control circuit 63 further includes comparators 102, 103, and 104, and inverting circuits 108, 109, and 110.

[0193] The voltage controlled oscillator 131 generates a triangular wave signal V tri1 is output to the non-inverting input terminal (+ terminal) of the comparator 99.

[0194] The voltage controlled oscillator 131 generates a triangular wave signal V tri1 The inverted triangular wave signal V tri1_n is output to the non-inverting input terminal (+ terminal) of the comparator 100.

[0195] The voltage controlled oscillator 131 generates a triangular wave signal V tri2 is output to the non-inverting input terminal (+ terminal) of the comparator 101.

[0196] The voltage controlled oscillator 131 generates a triangular wave signal V tri2 The inverted triangular wave signal V tri2_n is output to the non-inverting input terminal (+ terminal) of the comparator 102.

[0197] The voltage controlled oscillator 131 generates a triangular wave signal V tri3 is output to the non-inverting input terminal (+ terminal) of the comparator 103.

[0198] The voltage controlled oscillator 131 generates a triangular wave signal V tri3 The inverted triangular wave signal V tri3_n is output to the non-inverting input terminal (+ terminal) of the comparator 104.

[0199] Comparator 99 outputs the triangular wave signal V tri1 If the voltage at node N1 is higher than the voltage at node N2, a high-level voltage V 33 The comparator 99 outputs the triangular wave signal V tri1 If the voltage is higher than the low-level voltage V 33 Output.

[0200] The voltage V output by comparator 99 33 is output to the gate of the transistor Q3 via the dead time generating circuit 62.

[0201] The inverter circuit 105 outputs a voltage V 33 The logically inverted voltage V 39 Output.

[0202] The voltage V output by the inverter circuit 105 39 is output to the gate of the transistor Q4 via the dead time generating circuit 62.

[0203] The comparator 100 outputs a triangular wave signal V tri1_n If the voltage at node N1 is higher than the voltage at node N2, a high-level voltage V 34 The comparator 100 outputs the triangular wave signal V tri1_n If the voltage is higher than the low-level voltage V 34 Output.

[0204] The voltage V output by comparator 100 34 is output to the gate of the transistor Q1 via the dead time generating circuit 62.

[0205] The inverter circuit 106 outputs a voltage V 34 The logically inverted voltage V 40 Output.

[0206] The voltage V output by the inverter circuit 106 40 is output to the gate of the transistor Q2 via the dead time generating circuit 62.

[0207] 12 is a diagram showing an example of waveforms of the switching control circuit of the power supply device of the second embodiment. In detail, FIG. 12 shows the voltage of node N1 (voltage V output by error amplifier 98) when current I1 is smaller than the average value of currents I1 to I3 (when the first phase is not subject to the first control) or when current I2 or current I3 is larger than current I1. E2 ) and the triangular wave signal V output by the voltage controlled oscillator 131 tri1 and V tri1_n 10A and 10B are diagrams showing waveforms of a switching signal input to the gate of a transistor Q1 and a switching signal input to the gate of a transistor Q3.

[0208] Waveform 291 shows the voltage at node N1 (the voltage V E2 ) waveform 292 shows the triangular wave signal V tri1_n Waveform 293 shows the triangular wave signal V tri1 The triangular wave signal V tri1_n and V tri1 changes in the positive and negative directions with 0V as the center.

[0209] Waveform 294 shows the switching signal applied to the gate of transistor Q1. Waveform 295 shows the switching signal applied to the gate of transistor Q3.

[0210] Timing t 20 The voltage V output by the error amplifier 94 is E1 is the voltage V fmax-ref In this case, as shown by the waveform 291, the voltage at the node N1 (the voltage V output by the error amplifier 98) E2) becomes 0V. Therefore, as shown by waveform 294, the duty of the switching signal input to the gate of transistor Q1 becomes the standard value (0.5). On the other hand, as shown by waveform 295, the duty of the switching signal input to the gate of transistor Q3 becomes the standard value and is out of phase with waveform 294 by 180°.

[0211] Timing t 20 The voltage V output by the error amplifier 94 is E1 is the voltage V fmax-ref When the voltage at node N1 (the voltage V output by error amplifier 98) becomes higher than E2 ) is the voltage V E1 As the voltage rises, the duty cycle of the switching signal input to the gate of transistor Q1 rises from 0 V. As shown by waveform 294, the duty cycle of the switching signal input to the gate of transistor Q1 is less than the standard value (0.5). On the other hand, as shown by waveform 295, the duty cycle of the switching signal input to the gate of transistor Q3 is less than the standard value and is 180° out of phase with waveform 294.

[0212] Referring again to Figure 11, the comparator 101 receives the triangular wave signal V tri2 If the voltage at node N1 is higher than the voltage at node N2, a high-level voltage V 35 The comparator 101 outputs the triangular wave signal V tri2 If the voltage is higher than the low-level voltage V 35 Output.

[0213] The voltage V output by comparator 101 35 is output to the gate of the transistor Q7 via the dead time generating circuit 62.

[0214] The inverter circuit 107 outputs a voltage V 35 The logically inverted voltage V 41 Output.

[0215] The voltage V output by the inverter circuit 107 41 is output to the gate of transistor Q8 via dead time generating circuit 62.

[0216] The comparator 102 outputs the triangular wave signal V tri2_n If the voltage at node N1 is higher than the voltage at node N2, a high-level voltage V 36 The comparator 102 outputs the triangular wave signal V tri2_n If the voltage is higher than the low-level voltage V 36 Output.

[0217] The voltage V output by the comparator 102 36 is output to the gate of the transistor Q5 via the dead time generating circuit 62.

[0218] The inverter circuit 108 outputs a voltage V 36 The logically inverted voltage V 42 Output.

[0219] The voltage V output by the inverter circuit 108 42 is output to the gate of the transistor Q6 via the dead time generating circuit 62.

[0220] The comparator 103 outputs the triangular wave signal V tri3 If the voltage at node N1 is higher than the voltage at node N3, a high-level voltage V 37 The comparator 103 outputs the triangular wave signal V tri3 If the voltage is higher than the low-level voltage V 37 Output.

[0221] The voltage V output by the comparator 103 37 is output to the gate of the transistor Q11 via the dead time generating circuit 62.

[0222] The inverter circuit 109 outputs a voltage V 37 The logically inverted voltage V 43 Output.

[0223] The voltage V output by the inverter circuit 109 43is output to the gate of the transistor Q12 via the dead time generating circuit 62.

[0224] The comparator 104 outputs the triangular wave signal V tri3_n If the voltage at node N1 is higher than the voltage at node N3, a high-level voltage V 38 The comparator 104 outputs the triangular wave signal V tri3_n If the voltage is higher than the low-level voltage V 38 Output.

[0225] The voltage V output by the comparator 104 38 is output to the gate of the transistor Q9 via the dead time generating circuit 62.

[0226] The inverter circuit 110 outputs a voltage V 38 The logically inverted voltage V 44 Output.

[0227] The voltage V output by the inverter circuit 110 44 is output to the gate of transistor Q10 via dead time generating circuit 62.

[0228] (summary) The power supply device of the second embodiment has the following advantages in addition to the advantages of the power supply device 1 of the first embodiment.

[0229] In the second embodiment, the switching control circuit 63 reduces the duty of the transistor Q1 (Q5, Q9) and also reduces the duty of the transistor Q3 (Q7, Q11).

[0230] As a result, the switching control circuit 63 can alternate (at equal intervals when the phase difference is 180°) the rise of transistor Q1 (Q5, Q9) and the rise of transistor Q3 (Q7, Q11), thereby shifting the timing at which the primary currents of transformers 41, 42, and 43 change significantly.

[0231] Therefore, the power supply device can suppress the ripple current flowing through the capacitor 14.

[0232] The switching control circuit 63 preferably sets the duty of the switching signal input to the gate of the transistor Q3 (Q7, Q11) to be the same as the duty of the switching signal input to the gate of the transistor Q1 (Q5, Q9).

[0233] This makes it easier for the switching control circuit 63 to generate the switching signal, and makes control easier.

[0234] The switching control circuit 63 preferably sets the phase difference between the phase of the transistor Q1 (Q5, Q9) and the phase of the transistor Q3 (Q7, Q11) to 180°.

[0235] This makes it easier for the switching control circuit 63 to generate the switching signal, and makes control easier.

[0236] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0237] 1 Power supply 2 power supply 3, 4 Resistor 5, 6, 14 capacitors 11 Bridge Circuit 12 Transformer circuit 13 Rectifier circuit 15 Voltage Sensor 16, 17, 18, 19 Current sensors 20 Control circuit 31 Phase 1 Arm 32 Phase 2 Arm 33 Phase 3 Arm 41, 42, 43 Transformers 61, 63 Switching control circuit 62 Dead time generation circuit

Claims

1. a bridge circuit including arms of a plurality of phases, each of which has a first switching element, a second switching element, a third switching element, and a fourth switching element connected in series, wherein a first DC voltage is input to one end on a high potential side of the first switching element, a second DC voltage lower than the first DC voltage is input to a connection point between the second switching element and the third switching element, and one end on a low potential side of the fourth switching element is electrically connected to a reference potential; a transformer circuit including a primary circuit of a plurality of phases that receives the output voltage of the arm and resonates therewith, and a secondary circuit of a plurality of phases that is electromagnetically coupled to the primary circuit and outputs an AC voltage; a rectifier circuit that rectifies the AC voltage; a smoothing circuit that smoothes the voltage output from the rectifier circuit; a control circuit that changes a second switching signal complementarily to the first switching signal, changes a fourth switching signal complementarily to the third switching signal, and outputs the first to fourth switching signals to the first to fourth switching elements so that the voltage of the smoothing circuit becomes a command value voltage or so that the current output from the rectifier circuit becomes a command value current; Equipped with The control circuit performing a first control to reduce the duty of the first switching signal of the arm of the phase having the largest current among the plurality of phases to a value smaller than a standard value; A power supply device comprising:

2. The control circuit making the duty of the first switching signal of the arm of a phase in which a current is greater than an average current value of all phases of a primary side circuit among a plurality of phases smaller than the standard value; 2. The power supply device according to claim 1 .

3. The control circuit setting a duty of the first switching signal of the arm of a phase of which current is greater than the current average value among the plurality of phases to a duty corresponding to a difference from the current average value; 3. The power supply device according to claim 2, wherein:

4. The control circuit In a first case where the first to fourth switching signals have frequencies equal to or lower than a predetermined frequency, in addition to the first control, a second control is performed to change the frequencies of the first to fourth switching signals; In a second case where the first to fourth switching signals have reached the predetermined frequency, in addition to the first control, a third control is performed to maintain the frequencies of the first to fourth switching signals at the predetermined frequency and to reduce the duty of the first switching signal to be smaller than the standard value.

4. The power supply device according to claim 1, wherein the power supply device comprises:

5. The control circuit a duty of the first switching signal for the phase to be controlled by the first control is set to a smaller duty of a duty by the first control and a duty by the third control; 5. The power supply device according to claim 4, wherein:

6. The control circuit In the second case, the duty of the third switching signal is made smaller than the standard value.

6. The power supply device according to claim 4 or 5.

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