Semiconductor interconnect structure and method for forming the same, semiconductor package structure

Abstract

An embodiment of the present disclosure provides a semiconductor interconnect structure, the semiconductor interconnect structure includes: a base having a first surface and a second surface opposite to each other; a plurality of conductive pillars disposed in the base and independent of each other, each of the conductive pillars extending from the first surface to the second surface, a first end of the conductive pillar exposed at the first surface, and a second end of the conductive pillar exposed at the second surface; and a first conductive connection pad disposed on the first surface of the base, the first conductive connection pad including a mesh structure, the mesh structure including a plurality of first nodes, each of the first nodes being connected to one or more first ends of the conductive pillars, or each of the first ends of the conductive pillars being connected to one or more first nodes, and the first ends of all the conductive pillars being interconnected via the first conductive connection pad. The semiconductor interconnect structure provided by the embodiment of the present disclosure has good heat dissipation performance and mechanical performance.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed with the China Patent Office on November 4, 2022, bearing application number 202211375324.4 and entitled "Semiconductor interconnect structure and method for forming the same, semiconductor packaging structure," the entire contents of which are incorporated herein by reference.

[0002] This application relates to the field of integrated circuits, and more particularly to semiconductor interconnect structures and methods for forming the same, and semiconductor packaging structures. [Background technology]

[0003] Through-silicon via (TSV) technology is a high-density packaging technology that is replacing the relatively mature wire bonding technology in current technology and is recognized as a fourth-generation packaging technology. TSV technology realizes vertical electrical interconnection in through-silicon vias by filling them with conductive materials such as copper, tungsten, or polysilicon. By providing vertical interconnection, TSV technology reduces interconnect length, signal delay, and capacitance / inductance, thereby achieving lower power consumption between chips, faster communication, higher bandwidth, and smaller device integration. Three-dimensional (3D) packaging based on TSV technology offers better electrical interconnection performance, higher bandwidth, higher interconnect density, lower power consumption, smaller dimensions, and lighter weight.

[0004] With the development of three-dimensional (3D) packaging, TSV technology is becoming more and more important. The performance of through silicon vias is directly related to the reliability and yield rate of 3D packaging. To improve the reliability and yield rate of 3D packaging, it is necessary to provide through silicon vias with high stability and reliability. Therefore, how to improve the stability and reliability of through silicon vias has become an urgent issue to be solved. Summary of the Invention

[0005] The technical problem to be solved by the present disclosure is to provide a semiconductor interconnection structure, a method for forming the same, and a semiconductor package structure that can improve the heat dissipation performance and mechanical strength of the semiconductor interconnection structure.

[0006] In order to solve the above problems, the present disclosure provides a semiconductor interconnect structure, the semiconductor interconnect structure including: a base having a first surface and a second surface opposite to each other; a plurality of conductive pillars provided in the base and independent of each other, each of the conductive pillars extending from the first surface to the second surface, a first end of the conductive pillar exposed at the first surface, and a second end of the conductive pillar exposed at the second surface; and a first conductive connection pad provided on the first surface of the base, the first conductive connection pad including a mesh structure, the mesh structure including a plurality of first nodes, each of the first nodes connected to a first end of one or more of the conductive pillars, or the first end of each of the conductive pillars connected to one or more of the first nodes, and the first ends of all of the conductive pillars interconnected via the first conductive connection pad.

[0007] In one embodiment, the first conductive connection pad includes a first shape extending along a first direction and spaced apart along a second direction, and a second shape extending along the second direction and arranged along the first direction, and an intersection of the first shape and the second shape forms the first node.

[0008] In one embodiment, the first end of the conductive pillar is located within the first node.

[0009] In one embodiment, the semiconductor interconnect structure further includes a second conductive connection pad, which is disposed on a second surface of the base and connected to a second end of the conductive pillar, and the second ends of all the conductive pillars are interconnected via the second conductive connection pad.

[0010] In one embodiment, the second conductive connection pad includes a mesh structure, the mesh structure includes a plurality of second nodes, and each of the second nodes is connected to the second ends of one or more of the conductive pillars, or the second ends of each of the conductive pillars are connected to one or more of the second nodes.

[0011] In one embodiment, the second conductive connection pad includes a third figure extending along a first direction and spaced apart along a second direction, and a fourth figure extending along the second direction and arranged along the first direction, and an intersection of the third figure and the fourth figure forms the second node.

[0012] In one embodiment, the second end of the conductive pillar is located within the second node.

[0013] In one embodiment, the thickness of the base is between 30 and 50 micrometers.

[0014] In one embodiment, the conductive pillar has a maximum dimension in a cross section parallel to the base in the range of 2 to 5 micrometers.

[0015] In one embodiment, the conductive pillar is integrally formed with the first conductive connection pad.

[0016] In one embodiment, the first surface has a recessed region, the recessed region forming a trench, and the first conductive connection pad located at least partially within the trench.

[0017] In one embodiment, the semiconductor interconnect structure further includes a seed layer disposed between the conductive pillar and the base and between the first conductive connection pad and the base.

[0018] An embodiment of the present disclosure further provides a method for forming a semiconductor interconnect structure, the method including the steps of: providing a base; forming a plurality of through holes and a plurality of trenches in the base, the plurality of trenches being connected as a network of trenches, and one intersection of the network of trenches exposing one or more of the through holes, or one or more intersections of the network of trenches exposing one of the through holes; filling the through holes and the network of trenches with a conductive material to form conductive pillars in the through holes and form first conductive connection pads in the network of trenches; and thinning the base to expose one end of the conductive pillars away from the first conductive connection pads.

[0019] In one embodiment, the step of forming the through holes and the network of trenches in the base includes the steps of: forming vias in the base arranged in an array along a first direction and a second direction; and removing a portion of the thickness of the base to form a plurality of first trenches and a plurality of second trenches, wherein the first trenches extend along the first direction and are spaced apart along the second direction, the second trenches extend along the second direction and are spaced apart along the first direction, the first trenches and the second trenches pass through the vias, and intersection regions of the first trenches and the second trenches are the intersection points.

[0020] In one embodiment, the step of forming the through holes and the network of trenches in the base includes the steps of: removing a portion of the thickness of the base to form a plurality of first trenches and a plurality of second trenches, wherein the first trenches extend along the first direction and are spaced apart in the second direction, the second trenches extend along the second direction and are spaced apart in the first direction, and intersection regions of the first trenches and the second trenches are the intersection points; and removing the base at the intersection points along a direction perpendicular to the base to form the through holes.

[0021] In one embodiment, the method further includes a step of forming a seed layer on the inner walls of the through holes and the network trenches before the step of filling the through holes and the network trenches with a conductive material, and in the step of filling the through holes and the network trenches with a conductive material, the conductive material covers the seed layer and fills the through holes and the network trenches.

[0022] An embodiment of the present disclosure further provides a semiconductor package structure including the semiconductor interconnect structure described above.

[0023] In the semiconductor interconnect structure, the method for forming the same, and the semiconductor package structure provided by the embodiments of the present disclosure, the semiconductor interconnect structure separates a single conductive pillar with a large cross-sectional area into a conductive pillar array composed of multiple conductive pillars with smaller cross-sectional areas, thereby significantly increasing the surface area of ​​the conductive pillar and improving the heat dissipation performance of the semiconductor interconnect structure, and the multiple conductive pillars are distributed on the base, which provides additional support for the conductive pillars and further improves the mechanical performance of the semiconductor interconnect structure. Furthermore, the first conductive connection pad has a mesh structure rather than a one-piece structure, thereby increasing the surface area of ​​the first conductive connection pad and further increasing the heat dissipation area of ​​the semiconductor interconnect structure. [Brief explanation of the drawings]

[0024] [Figure 1A] 1 is a top view of a semiconductor interconnect structure according to a first embodiment of the present disclosure. [Figure 1B] FIG. 1B is a schematic cross-sectional view taken along line AA' in FIG. 1A. [Figure 2] FIG. 2 is a perspective view of a semiconductor interconnect structure according to a second embodiment of the present disclosure. [Figure 3A] FIG. 2 is a top view of a semiconductor interconnect structure according to a second embodiment of the present disclosure. [Figure 3B] FIG. 3B is a schematic cross-sectional view taken along line BB' in FIG. 3A. [Figure 4] FIG. 10 is a top view of a semiconductor interconnect structure according to a third embodiment of the present disclosure. [Figure 5A] FIG. 10 is a top view of a semiconductor interconnect structure according to a fourth embodiment of the present disclosure. [Figure 5B] FIG. 10 is a top view of a semiconductor interconnect structure according to a fifth embodiment of the present disclosure. [Figure 6] FIG. 10 is a bottom view of a semiconductor interconnect structure according to a sixth embodiment of the present disclosure. [Figure 7] 10A-10C are schematic diagrams illustrating steps of a method for forming a semiconductor interconnect structure according to a seventh embodiment of the present disclosure. [Figure 8] 10 is a schematic diagram of a semiconductor structure formed by the main steps of a method according to a seventh embodiment of the present disclosure. [Figure 9] FIG. 10 is a schematic diagram of a semiconductor structure formed by the main steps of a method according to an eighth embodiment of the present disclosure. [Figure 10] FIG. 13 is a schematic diagram of a semiconductor package structure according to a ninth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0025] The following detailed description will be given of specific embodiments of the semiconductor interconnect structure, the method for forming the same, and the semiconductor package structure provided by the present disclosure with reference to the accompanying drawings. The semiconductor package structure in this specific embodiment may be, but is not limited to, a DRAM.

[0026] FIG. 1A is a top view of a semiconductor interconnect structure according to a first embodiment of the present disclosure, and FIG. 1B is a schematic cross-sectional view taken along line A-A' in FIG. 1A. Referring to FIGS. 1A and 1B, the semiconductor interconnect structure includes a base 100, a conductive pillar 110, and a first conductive connection pad 120. The conductive pillar 110 penetrates the base 100 and is connected to the first conductive connection pad 120 on a first surface 100A of the base 100. The conductive pillar 110 may include, but is not limited to, a silicon through-hole structure for electrically connecting the first conductive connection pad 120 to another semiconductor structure. In the first embodiment, one conductive pillar may be connected to multiple first conductive connection pads 120. For example, FIGS. 1A and 1B show three first conductive connection pads 120 that are independently provided from one another, and all three first conductive connection pads 120 that are independently provided from one another are connected to the same conductive pillar 110.

[0027] The present inventors discovered that the semiconductor interconnect structure according to the first embodiment had poor heat dissipation and mechanical performance and could not meet the requirements. As a result of further research, the present inventors have provided a semiconductor interconnect structure that can improve the heat dissipation and mechanical performance of the semiconductor interconnect structure.

[0028] FIG. 2 is a perspective view of a semiconductor interconnect structure according to a second embodiment of the present disclosure, FIG. 3A is a top view of the semiconductor interconnect structure according to the second embodiment of the present disclosure, and FIG. 3B is a schematic cross-sectional view taken along line B-B' in FIG. 3A. In FIG. 2, the base 200 is not shown in order to clearly show the semiconductor interconnect structure provided by the embodiment of the present disclosure. Referring to FIGS. 2, 3A, and 3B, the semiconductor interconnect structure includes a base 200 having a first surface 200A and a second surface 200B opposite to each other, a plurality of conductive pillars 210 disposed within the base 200 and independent from each other, each conductive pillar 210 extending from the first surface 200A to the second surface 200B, with a first end 210A of the conductive pillar 210 exposed to the first surface 200A and a second end 210B of the conductive pillar 210 exposed to the second surface 200B, and a plurality of conductive pillars 210 disposed between the first surface 200A and the second surface 200B. and a first conductive connection pad 220 provided on the first conductive pillar 210A, the first conductive connection pad 220 including a mesh structure, the mesh structure including a plurality of first nodes 221, each first node 221 being connected to a first end 210A of one or more conductive pillars 210, or the first end 210A of each conductive pillar 210 being connected to one or more first nodes 221, and the first ends 210A of all the conductive pillars 210 being interconnected via the first conductive connection pad 220. In the top view (e.g., FIG. 3A ), the conductive pillars 210 are shielded by the first conductive connection pad 220, and the outlines of the conductive pillars 210 are indicated by dashed lines to clearly illustrate the technical solutions of the embodiments of the present disclosure.

[0029] The semiconductor interconnect structure provided by this embodiment separates a single conductive pillar 210 with a large cross-sectional area into a conductive pillar array composed of multiple conductive pillars 210 with smaller cross-sectional areas, thereby significantly increasing the surface area of ​​the conductive pillar 210 and improving the heat dissipation performance of the semiconductor interconnect structure. The multiple conductive pillars 210 are distributed on the base 200, which provides additional support for the conductive pillars 210 and further improves the mechanical performance and deformation resistance of the semiconductor interconnect structure. Furthermore, the first conductive connection pad 220 has a mesh structure rather than a one-piece structure, which increases the surface area of ​​the first conductive connection pad 220 and further increases the heat dissipation area of ​​the semiconductor interconnect structure. At the same time, the mesh structure of the first conductive connection pad 220 also improves the deformation resistance of the conductive pillar array and improves the support performance of the semiconductor interconnect structure.

[0030] In this embodiment, the base 200 includes a substrate 201 and a protective layer 202 provided on the surface of the substrate 201, and the protective layer 202 may be an oxide layer or a nitride layer. In other embodiments, the base 200 may include only the substrate 201.

[0031] The substrate 201 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate, or the like. The substrate 201 may also be a substrate containing other elemental or compound semiconductors such as gallium arsenide, indium phosphide, or silicon carbide. The substrate 201 may have a stacked structure such as a silicon / germanium-silicon stack. The substrate 201 may also be a substrate after ion doping, and may be P-type doped or N-type doped. The substrate 201 may also have multiple peripheral devices formed therein, such as field-effect transistors, capacitors, inductors, and / or diodes. In this embodiment, the substrate 201 is a silicon substrate, and may include other device structures such as transistor structures and metal wiring structures therein, but these are not shown because they are not related to the present invention.

[0032] In this embodiment, the first surface 200A of the base 200 is the top surface of the base 200, and the second surface 200B of the base 200 is the bottom surface of the base 200, with the top surface and the bottom surface being provided opposite each other.

[0033] The conductive pillars 210 are provided independently of each other, i.e., the conductive pillars 210 do not contact each other. In this embodiment, each conductive pillar 210 extends along a direction perpendicular to the first surface 200A of the base 200 (e.g., the Z direction in FIG. 2), and the conductive pillars 210 are provided spaced apart from each other along a direction parallel to the first surface 200A of the base 200 (e.g., the X direction in FIG. 2) and parallel to each other.

[0034] Each conductive pillar 210 penetrates the base 200 in a direction perpendicular to the first surface 200A of the base 200 (for example, the Z direction in FIG. 2), with the first end 210A of the conductive pillar 210 exposed at the first surface 200A and the second end 210B of the conductive pillar 210 exposed at the second surface 200B. In this embodiment, the first surface 200A of the base 200 has a groove for embedding the first conductive connection pad 220, and the first end 210A of the conductive pillar 210 is exposed at the bottom of the groove.

[0035] When forming the conductive pillars 210 in the base 200, the through holes must be formed first, and then the conductive pillars 210 must be formed in the through holes. The aspect ratio of the through holes is affected by the thickness of the base 200 and the width of the conductive pillars 210. The thicker the base 200, the smaller the required width of the conductive pillars 210 and the larger the aspect ratio of the through holes. For through holes with a high aspect ratio, the etching material cannot fully penetrate the bottom of the through hole, and the bottom of the through hole is not completely etched, resulting in a through hole that is wide at the top and narrow at the bottom. This results in uneven widths of the conductive pillars 210 formed in the through holes. Furthermore, the conductive material forming the conductive pillars 210 is not sufficiently deposited at the bottom of the through hole, resulting in defects in the conductive pillars 210 formed at the bottom of the through hole, which affects the reliability of the conductive pillars 210. Therefore, in some embodiments, the thickness of the base 200 (the dimension along the Z direction in FIG. 2 ) is small; for example, in the second embodiment, if the thickness of the base 200 is 30 to 50 micrometers, it is possible to form the conductive pillar 210 with a small width (the dimension along the X direction in FIG. 2 ). For example, in the second embodiment, the maximum dimension of the conductive pillar 210 in a cross section parallel to the base 200 is in the range of 2 to 5 micrometers, which does not cause problems due to through holes with a high aspect ratio, and further ensures consistency and reliability of the width of the conductive pillar 210 in its extension direction (the dimension along the Z direction in FIG. 2 ).

[0036] In some embodiments, the first conductive connection pad 220 is provided on the first surface 200A of the base 200, i.e., the first conductive connection pad 220 protrudes from the base 200. In contrast, in other embodiments, the first surface 200A of the base 200 has a mesh-like recessed region that forms a trench, and the first conductive connection pad 220 is at least partially located within the trench, i.e., the first conductive connection pad 220 extends below the first surface 200A. For example, in a second embodiment, the first conductive connection pad 220 is located completely within the trench, and the top surface of the first conductive connection pad 220 is flush with the first surface 200A of the base 200. Because the first conductive connection pad 220 is fitted into the base 200, the protrusions between the trenches of the base 200 can fit into the voids of the mesh structure of the first conductive connection pad 220, thereby enhancing the mechanical strength of the first conductive connection pad 220 and further improving the mechanical strength of the semiconductor interconnect structure.

[0037] In the embodiment of the present disclosure, the first ends 210A of all the conductive pillars 210 are interconnected via the first conductive connection pads 220, and the electrical signals of the first conductive connection pads 220 are transmitted through all the conductive pillars 210, rather than through only one of the conductive pillars 210 or a portion of the conductive pillars 210. That is, all the conductive pillars 210 are used as one conductive structure, rather than as multiple conductive structures.

[0038] In some embodiments, the first conductive connection pad 220 includes a first graphic 222 extending along a first direction and spaced apart from one another along a second direction, and a second graphic 223 extending along the second direction and spaced apart from one another along the first direction, and an intersection of the first graphic 222 and the second graphic 223 forms a first node 221. In this embodiment, the first direction is perpendicular to the second direction, e.g., the first direction is the X direction and the second direction is the Y direction, the first graphic 222 is a linear graphic extending along the X direction, and the plurality of linear graphic elements are spaced apart from one another along the Y direction, and the second graphic 223 is a linear graphic extending along the Y direction, and the plurality of linear graphic elements are spaced apart from one another along the X direction.

[0039] In this embodiment, the first feature 222 is disposed perpendicular to the second feature 223. In contrast, in some other embodiments, as shown in Figure 4, which is a top view of a semiconductor interconnect structure according to a third embodiment of the present disclosure, the first feature 222 and the second feature 223 are disposed at an acute angle rather than being disposed perpendicularly at a 90 degree angle.

[0040] In this embodiment, one first node 221 is connected to the first end 210A of one conductive pillar 210, and the first nodes 221 and the conductive pillars 210 have a one-to-one relationship. In contrast, in some other embodiments, the first nodes 221 and the conductive pillars 210 have a one-to-multiple or multiple-to-one relationship. For example, as shown in FIG. 5A, which is a top view of a semiconductor interconnect structure according to a fourth embodiment of the present disclosure, each first node 221 is connected to the first ends 210A of multiple conductive pillars 210, i.e., multiple conductive pillars 210 are provided below each first node 221. Furthermore, as shown in FIG. 5B, which is a top view of a semiconductor interconnect structure according to a fifth embodiment of the present disclosure, the first end 210A of one conductive pillar 210 is connected to multiple first nodes 221, i.e., multiple first nodes 221 are provided above each conductive pillar 210.

[0041] In some embodiments, the first end 210A of the conductive pillar 210 is located within the first node 221, i.e., the projection of the conductive pillar 210 onto the substrate 201 is located within the projection of the first node 221 onto the substrate 201. Specifically, in this embodiment, the first node 221 is connected to the conductive pillar 210 in a one-to-one relationship, and the first end 210A of the conductive pillar 210 is located within the first node 221, i.e., the length W1 of the shortest side of the first node 221 is greater than the diameter D of the conductive pillar 210, in which case the conductive pillar 210 is fully utilized and the conductivity of the semiconductor interconnect structure can be improved.

[0042] In some embodiments, the conductive pillar 210 is integrally molded with the first conductive connection pad 220, i.e., the conductive pillar 210 and the first conductive connection pad 220 are fabricated in one step using the same conductive material in the same process, thereby significantly reducing the contact resistance between the conductive pillar 210 and the first conductive connection pad 220 and improving the conductivity of the semiconductor interconnect structure.

[0043] In some embodiments, the semiconductor interconnect structure further includes a seed layer 230 disposed between the conductive pillar 210 and the base 200 and between the first conductive connection pad 220 and the base 200. The seed layer 230 insulates the conductive pillar 210 from the base 200 and insulates the first conductive connection pad 220 from the base 200. The seed layer 230 may be an oxide layer, such as a silicon oxide layer.

[0044] On the second surface 200B of the base 200, another semiconductor structure (e.g., a semiconductor device) may be electrically connected to the second end 210B of the conductive pillar 210, thereby realizing electrical connection between the semiconductor structure and the first conductive connection pad 220.

[0045] To further improve the reliability of the connection between the semiconductor structure and the second ends of the conductive pillars 210, second conductive connection pads 240 are provided on the second surface 200B of the base 200. The semiconductor structure is connected to the second conductive connection pads 240 and connected to the first conductive connection pads 220 via the second conductive connection pads 240 and the conductive pillars 210. The second conductive connection pads 240 cover the second surface 200B of the base 200 and are connected to the second ends 210B of the conductive pillars 210, and the second ends 210B of all the conductive pillars 210 are interconnected via the second conductive connection pads 240.

[0046] In the second embodiment, the second conductive connection pad 240 has a one-piece structure. In contrast, in the sixth embodiment of the present disclosure, the second conductive connection pad 240 includes a mesh structure. Referring to FIG. 6 , FIG. 6 is a bottom view of a semiconductor interconnection structure according to the sixth embodiment of the present disclosure, in which the conductive pillars 210 are shielded by the second conductive connection pad 240, and the outlines of the conductive pillars 210 are indicated by dashed lines to clearly illustrate the technical solutions of the embodiments of the present disclosure. The second conductive connection pad 240 includes a mesh structure, which includes a plurality of second nodes 241, each of which is connected to the second end 210B of one or more conductive pillars 210, or the second end 210B of each conductive pillar 210 is connected to one or more second nodes 241. Since the second conductive connection pad 240 has a mesh structure rather than a one-piece structure, the surface area of ​​the second conductive connection pad 240 is increased, further increasing the heat dissipation area of ​​the semiconductor interconnection structure. At the same time, the mesh structure of the second conductive connection pad 240 can also improve the deformation resistance of the conductive pillar array and improve the support performance of the semiconductor interconnection structure.

[0047] In some embodiments, the second conductive connection pad 240 is provided on the second surface 200B of the base 200, i.e., the second conductive connection pad 240 protrudes from the base 200. In contrast, in other embodiments, such as the sixth embodiment, the second surface 200B of the base 200 has a recessed region, which forms a trench, and the second conductive connection pad 240 is at least partially located within the trench, i.e., the second conductive connection pad 240 extends below the second surface 200B. For example, in the second embodiment, the second conductive connection pad 240 is located completely within the trench, and the top surface of the second conductive connection pad 240 is flush with the second surface 200B of the base 200. Because it is fitted into the second conductive connection pad 240, the protrusions between the trenches of the base 200 can fit into the voids of the mesh structure of the second conductive connection pad 240, thereby enhancing the mechanical strength of the second conductive connection pad 240 and further improving the mechanical strength of the semiconductor interconnect structure.

[0048] In this embodiment, one second node 241 is connected to the second end 210B of one conductive pillar 210, and there is a one-to-one relationship between the second node 241 and the conductive pillar 210. In contrast, in some other embodiments, as shown in Figures 5A and 5B, there is a one-to-multiple or multiple-to-one relationship between the second node 241 and the conductive pillar 210, and this will not be described again here.

[0049] The second conductive connection pad 240 includes third figures 242 extending along a first direction (e.g., the X direction in FIG. 6 ) and spaced apart from each other along a second direction (e.g., the Y direction in FIG. 6 ), and fourth figures 243 extending along the second direction (e.g., the Y direction in FIG. 6 ) and spaced apart from each other along the first direction (e.g., the X direction in FIG. 6 ), and an intersection of the third figure 242 and the fourth figure 243 forms a second node 241. In this embodiment, the third figure 242 is disposed perpendicular to the fourth figure 243. In contrast, in some other embodiments, as shown in FIG. 4 , the third figure 242 and the fourth figure 243 are disposed at an acute angle rather than being disposed perpendicularly at a 90-degree angle.

[0050] In this embodiment, the structure of the second conductive connection pad 240 is the same as the structure of the first conductive connection pad 220. It can be understood that in some other embodiments, the structure of the second conductive connection pad 240 is different from the structure of the second conductive connection pad 240, and will not be described again.

[0051] In some embodiments, the second end 210B of the conductive pillar 210 is located within the second node 241, i.e., the projection of the conductive pillar 210 onto the substrate 201 is located within the projection of the second node 241 onto the substrate 201. Specifically, in this embodiment, the second node 241 is connected to the conductive pillar 210 in a one-to-one relationship, and the second end 210B of the conductive pillar 210 is located within the second node 241, i.e., the length W2 of the shortest side of the second node 241 is greater than the diameter D of the conductive pillar 210. In this case, the conductive pillar 210 is maximized, which can improve the conductivity of the semiconductor interconnect structure.

[0052]

[0023] The present disclosure also provides a method for forming a semiconductor interconnect structure. Referring to Figure 7, Figure 7 is a schematic diagram illustrating steps of the method for forming a semiconductor interconnect structure, including: step S70 of providing a base; step S71 of forming a plurality of through holes and a plurality of trenches in the base, the plurality of trenches being connected as a network trench, and each intersection of the network trenches exposing one or more through holes, or each intersection of the network trenches exposing one through hole; step S72 of filling the through holes and the network trenches with a conductive material to form conductive pillars in the through holes and first conductive connection pads in the network trenches; and step S73 of thinning the base to expose one end of the conductive pillars away from the first conductive connection pads.

[0053] 8A-8M are schematic diagrams of semiconductor structures formed by the main steps of a method according to a seventh embodiment of the present disclosure.

[0054] 7 and 8A, in step S70, a base 200 is provided. In this embodiment, the base 200 includes a substrate 201 and a protective layer 202 provided on the surface of the substrate 201. In other embodiments, the base 200 may include only the substrate 201.

[0055] 7, 8F, and 8G, in step S71, a plurality of through holes 300 and a plurality of trenches 310 are formed in the base 200, and the plurality of trenches 310 are connected to form a network of trenches 310, and one intersection 310A of the network of trenches 310 exposes one or more through holes 300, or one or more intersections 310A of the network of trenches 310 exposes one through hole 300. In this step, the through holes 300 extend from the first surface 200A of the base 200 toward the inside of the base 200, but do not penetrate the base 200. That is, the through holes 300 are blind holes.

[0056] As an example, a seventh embodiment of the present disclosure provides a method for forming a through-hole 300 in a base 200, which includes the following steps.

[0057] 8B and 8C, FIG. 8B is a top view, and FIG. 8C is a schematic cross-sectional view taken along line B-B' in FIG. 8B. Vias 800 are formed in the base 200 in an array along a first direction and a second direction. In this embodiment, the first direction is the X direction, and the second direction is the Y direction. In this step, a mask layer having a pattern corresponding to the vias 800 may be used as a mask to etch the base 200, transfer the pattern of the mask layer to the base 200, and then remove the mask layer. The depth of the vias 800 may be determined according to the height requirements of the conductive pillars 210 to be subsequently formed. In this embodiment, because a first trench 810 and a second trench 820 must be subsequently formed at the ends of the vias, the depth of the vias 800 is greater than the depth of the conductive pillars 210 to be subsequently formed. For example, the depth of the vias 800 is equal to the sum of the height of the conductive pillars 210 to be subsequently formed and the depth of the first trenches 810.

[0058] After forming the via 800, a portion of the thickness of the base 200 is removed to form a plurality of first trenches 810 and a plurality of second trenches 820, where the first trenches 810 extend along a first direction and are spaced apart along a second direction, the second trenches 820 extend along the second direction and are spaced apart along the first direction, the first trenches 810 and the second trenches 820 pass through the via 800, and the intersection area between the first trenches 810 and the second trenches 820 is the intersection point 310A.

[0059] 8D and 8E, FIG. 8D is a top view, and FIG. 8E is a schematic cross-sectional view along line B-B' in FIG. 8D. A portion of the thickness of the base 200 is removed to form a plurality of first trenches 810. The first trenches 810 extend along a first direction and pass through the vias 800. In this step, a mask layer having a pattern corresponding to the first trenches 810 is used as a mask to etch the base 200, transfer the pattern of the mask layer to the base 200 to form the first trenches 810, and then remove the mask layer. In this embodiment, the first direction is perpendicular to the second direction; for example, the first direction is the X direction and the second direction is the Y direction.

[0060] 8F and 8G, Fig. 8F is a top view, and Fig. 8G is a schematic cross-sectional view along line B-B' in Fig. 8F, in which a portion of the thickness of the base 200 is removed to form a plurality of second trenches 820, the second trenches 820 extending along a second direction and passing through vias 800, the intersections between the first trenches 810 and the second trenches 820 forming a network of trenches 310, and the intersection regions between the first trenches 810 and the second trenches 820 being intersection points 310A. In this step, a mask layer having a pattern corresponding to the second trenches 820 is used as a mask to etch the base 200, the pattern of the mask layer is transferred to the base 200 to form the second trenches 820, and the mask layer is then removed.

[0061] As an example, the eighth embodiment of the present disclosure further provides a method for forming a through hole 300 in a base 200, and referring to Figures 9A to 9B, the method for forming a through hole 300 in a base 200 includes the following steps:

[0062] 9A and 9B, FIG. 9A is a top view, and FIG. 9B is a schematic cross-sectional view along line B-B' in FIG. 9A, in which a portion of the thickness of the base 200 is removed to form a plurality of first trenches 810 and a plurality of second trenches 820, the first trenches 810 extending along a first direction (e.g., the X direction in FIG. 9A) and spaced apart along a second direction (e.g., the Y direction in FIG. 9A), the second trenches 820 extending along the second direction (e.g., the Y direction in FIG. 9A) and spaced apart along the first direction (e.g., the X direction in FIG. 9A), the intersections of the first trenches 810 and the second trenches 820 forming a network of trenches 310, and the intersection regions of the first trenches 810 and the second trenches 820 are intersection points 310A.

[0063] In this step, a mask layer having a pattern corresponding to the first trench 810 is used as a mask to etch the base 200, the pattern of the mask layer is transferred to the base 200 to form the first trench 810, a mask layer having a pattern corresponding to the second trench 820 is used as a mask to etch the base 200 having the first trench 810, the pattern of the mask layer is transferred to the base 200 to form the second trench 820, and the mask layer is removed after the second trench 820 is formed.

[0064] After forming the first trench 810 and the second trench 820, the base 200 is removed at the intersection 310A in a direction perpendicular to the base 200 to form the through-hole 300. For example, in this embodiment, a mask layer having a pattern corresponding to the through-hole may be used to cover the surface of the base 200, and the base 200 may be etched using the mask layer as a mask to form the through-hole 300.

[0065] 8H and 8I, FIG. 8H is a top view, and FIG. 8I is a schematic cross-sectional view taken along line B-B' in FIG. 8H. After the through-holes 300 and the network trenches 310 are formed, a seed layer 230 is formed on the inner walls of the through-holes 300. The seed layer 230 covers the inner walls of the through-holes 300 and the network trenches, and may be used to insulate the conductive pillars 210 and the first conductive connection pads 220 from the base 200. The seed layer 230 may include, but is not limited to, an oxide layer, and may be formed by a CVD method, a thermal oxidation method, or the like.

[0066] 7, 8J, and 8K, FIG. 8J is a top view, and FIG. 8K is a schematic cross-sectional view taken along line B-B' in FIG. 8J. In step S72, the through-holes 300 and the network trenches 310 are filled with a conductive material to form conductive pillars 210 in the through-holes 300 and first conductive connection pads 220 in the network trenches 310. In this step, the conductive material can be deposited using a CVD method, an ALD method, or the like, and the conductive material fills the through-holes 300 and the network trenches 310. In this embodiment, the conductive material covers the surface of the seed layer 230 and fills the through-holes 300 and the network trenches 310. In some embodiments, the conductive material further covers the first surface 200A of the base 200, and the conductive material is removed to the first surface 200A of the base 200 using a CMP method to form the first conductive connection pads 220 with a flat surface. The conductive material can include, but is not limited to, copper.

[0067] Since the first conductive connection pad 220 and the conductive pillar 210 are formed using the same conductive material in the same step, there is no substantial interface between them, resulting in lower contact resistance and better connectivity, which greatly improves the electrical and mechanical performance of the semiconductor interconnect structure.

[0068] 7 and 8L, FIG. 8L is a schematic cross-sectional view showing that in step S73, the base 200 is thinned to expose one end of the conductive pillar 210 away from the first conductive connection pad 220. In this step, the base 200 can be thinned using a CMP method or the like until the second end 210B of the conductive pillar 210 is exposed, in order to facilitate subsequent electrical connection between another semiconductor structure and the conductive pillar 210. After this step, the second end 210B of the conductive pillar 210 is exposed at the second surface 200B of the base 200.

[0069] 8M, which is a schematic cross-sectional view, in some embodiments, the method further includes forming second conductive connection pads 240 on the second surface 200B of the base 200 after thinning the base 200. In some embodiments, a conductive layer may be directly formed on the second surface 200B of the base 200, and the conductive layer may be patterned to form the second conductive connection pads 240.

[0070] In the method for forming a semiconductor interconnection structure provided by the embodiments of the present disclosure, the conductive pillar 210 and the first conductive connection pad 220 can be formed in the same step by only adopting a one-step etching process, which is simpler than forming the conductive pillar 210 and the first conductive connection pad 220 in different steps by a two-step etching process, and also avoids destruction of the connection interface between the conductive pillar 210 and the first conductive connection pad 220 due to the etching process, thereby improving the electrical performance, mechanical performance, and stability of the semiconductor interconnection structure.

[0071]

[0013] Embodiments of the present disclosure further provide a semiconductor package structure including the semiconductor interconnect structure described above. Referring to FIG. 10, FIG. 10 is a schematic diagram of a semiconductor package structure according to a ninth embodiment of the present disclosure. The semiconductor package structure includes a first semiconductor structure 1, a semiconductor interconnect structure 2, and a second semiconductor structure 3. The first semiconductor structure 1 is electrically connected to the second semiconductor structure 3 via the semiconductor interconnect structure 2. Specifically, the third conductive connection pad 10 of the first semiconductor structure 1 is connected to the third conductive connection pad 30 of the second semiconductor structure 3 via the second conductive connection pad 240, the conductive pillar 210, and the first conductive connection pad 220 of the semiconductor interconnect structure 2. The first semiconductor structure 1 and the second semiconductor structure 3 may include, but are not limited to, a circuit board, a package substrate, a logic chip, a memory chip, etc.

[0072] The semiconductor package structure utilizes the semiconductor interconnect structure 2 as a connecting intermediate layer between two semiconductor structures, which greatly improves its heat dissipation performance, mechanical performance, and stability of the semiconductor package structure.

[0073] The above description is only the preferred embodiments of the present invention, and it should be mentioned that those skilled in the art can also make some improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should fall within the protection scope of the present invention.

Claims

1. 1. A semiconductor interconnect structure comprising: a base having opposed first and second surfaces; a plurality of conductive pillars disposed within the base and independent of one another, each of the conductive pillars extending from the first surface to the second surface, a first end of the conductive pillar exposed at the first surface, and a second end of the conductive pillar exposed at the second surface; a first conductive connection pad provided on a first surface of the base, the first conductive connection pad including a mesh structure, the mesh structure including a plurality of first nodes, each of the first nodes being connected to a first end of one or more of the conductive pillars, or the first ends of each of the conductive pillars being connected to one or more of the first nodes, and the first ends of all of the conductive pillars being interconnected via the first conductive connection pad; the conductive pillar is integrally formed with the first conductive connection pad; the first surface has a recessed region, the recessed region forming a trench, and the first conductive connection pad located at least partially within the trench. Semiconductor interconnect structures.

2. the first conductive connection pad includes first figures extending along a first direction and spaced apart from one another along a second direction, and second figures extending along the second direction and arranged along the first direction, and an intersection of the first figure and the second figure constitutes the first node; a first end of the conductive pillar located within the first node; The semiconductor interconnect structure of claim 1 .

3. the semiconductor interconnect structure further includes a second conductive connection pad, the second conductive connection pad being provided on a second surface of the base and connected to a second end of the conductive pillar, and the second ends of all the conductive pillars are interconnected via the second conductive connection pad; The semiconductor interconnect structure of claim 1 .

4. the second conductive connection pad includes a mesh structure, the mesh structure includes a plurality of second nodes, each of the second nodes being connected to the second ends of one or more of the conductive pillars, or the second ends of each of the conductive pillars being connected to one or more of the second nodes; the second conductive connection pad includes third figures extending along a first direction and spaced apart from one another along a second direction, and fourth figures extending along the second direction and arranged along the first direction, and an intersection of the third figure and the fourth figure constitutes the second node; a second end of the conductive pillar located within the second node; 4. The semiconductor interconnect structure of claim 3.

5. the thickness of the base is 30 to 50 micrometers; the conductive pillars have a maximum dimension in a cross section parallel to the base ranging from 2 to 5 micrometers; the semiconductor interconnect structure further includes a seed layer disposed between the conductive pillar and the base and between the first conductive connection pad and the base; The semiconductor interconnect structure of claim 1 .

6. 1. A method for forming a semiconductor interconnect structure, comprising: providing a base; forming a plurality of through holes and a plurality of trenches in the base, the plurality of trenches being connected as a network of trenches, with one intersection of the network of trenches exposing one or more of the through holes, or one or more intersections of the network of trenches exposing one of the through holes; filling the through holes and the network of trenches with a conductive material to form conductive pillars in the through holes and first conductive connection pads in the network of trenches; thinning the base to expose an end of the conductive pillar remote from the first conductive connection pad; the conductive pillars are integrally formed with the first conductive connection pads, and the first conductive connection pads are at least partially located within the reticulated trenches; A method for forming a semiconductor interconnect structure.

7. The step of forming the through holes and the reticulated trenches in the base comprises: forming vias in the base arranged in an array along a first direction and a second direction; removing a portion of the thickness of the base to form a plurality of first trenches and a plurality of second trenches, the first trenches extending along the first direction and spaced apart along the second direction, the second trenches extending along the second direction and spaced apart along the first direction, the first trenches and the second trenches passing through the vias, and intersection regions of the first trenches and the second trenches being the intersection points; Or, The step of forming the through holes and the reticulated trenches in the base comprises: removing a portion of a thickness of the base to form a plurality of first trenches and a plurality of second trenches, the first trenches extending along a first direction and spaced apart along the second direction, the second trenches extending along the second direction and spaced apart along the first direction, and intersection regions of the first trenches and the second trenches being the intersection points; and removing the base at the intersection along a direction perpendicular to the base to form the through hole.

7. The method of claim 6 for forming a semiconductor interconnect structure.

8. The method further includes forming a seed layer on an inner wall of the through hole and the network trench before filling the through hole and the network trench with a conductive material; In the step of filling the through holes and the network trenches with a conductive material, the conductive material is filled to cover the seed layer and fill the through holes and the network trenches.

7. The method of claim 6 for forming a semiconductor interconnect structure.

9. A semiconductor package structure comprising the semiconductor interconnect structure according to any one of claims 1 to 5.

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