Sample holder and superconducting quantum computer

Abstract

To provide a sample holder that raises the chip mode resonance frequency.SOLUTION: A sample holder includes a metal pedestal, and a printed circuit board (PCB) placed on the pedestal. A through hole is formed in the PCB to penetrate from the front surface to the back surface. On the side of the pedestal on which the PCB is placed, a bottomed top opening type cavity is formed at a portion corresponding to directly below the through hole in the PCB, and a part of the cavity protrudes outward from a position corresponding to the through hole when the side of the pedestal on which the PCB is placed is viewed from above.SELECTED DRAWING: Figure 10B

Description

[Technical Field]

[0001] The present disclosure relates to a sample holder. [Background technology]

[0002] A superconducting quantum circuit is formed using a wiring layer of a superconducting material such as Nb (niobium) or Al (aluminum) fabricated on the surface of a substrate such as a silicon substrate. Here, a superconducting quantum circuit formed on a substrate is called a "chip." A superconducting quantum circuit is operated by mounting the chip on a sample holder. Sample holders with various structures are known. Methods for mounting a chip on a sample holder include a method of mounting the chip without flipping the circuit side of the chip (the side on which the superconducting quantum circuit is formed, also abbreviated as "circuit side") onto a printed circuit board, as described in Non-Patent Document 1, for example, and a method of mounting the chip with the circuit side of the chip flipped over onto a printed circuit board (flip-chip mounting), as described in Patent Document 1, for example. The following explanation will be based on the former mounting method.

[0003] For example, a structure is known in which a printed circuit board (hereinafter also abbreviated as "PCB") is placed on the (mounting surface) of a metal pedestal that constitutes a sample holder. That is, a through-hole is provided near the center of the PCB, and a chip is placed in this through-hole. Then, the pads on the circuit surface of the chip placed in the through-hole are electrically connected to the corresponding pads on the PCB, and the ground on the circuit surface of the chip is electrically connected to the ground on the PCB, each using bonding wires such as Al. In such a case, the surface of the chip opposite the circuit surface (back surface) is in contact with (abuts against) the metal pedestal.

[0004] When a chip is mounted on the sample holder described above, and a signal of a specific frequency is input to the chip's superconducting quantum circuit, resonance occurs. This resonance is called "chip mode resonance."

[0005] When the resonance of the chip mode couples with the superconducting quantum circuit on the chip, it causes decoherence in the superconducting quantum circuit. One known measure to reduce the effects of this decoherence is to make the resonance frequency of the chip mode as high as possible. For example, Non-Patent Document 1 describes a method for suppressing the effects of the chip mode in the above-mentioned structure (where the chip is placed in a through-hole in a PCB placed on a pedestal, and the back surface of the chip is in surface contact with the pedestal), in which a cavity is formed directly below the chip by hollowing out a part of the mounting surface of the metal pedestal directly below the chip. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-299503 [Non-patent literature]

[0007] [Non-Patent Document 1] B. Lienhard, et al., “Microwave Packaging for Superconducting Qubits,” arXiv: 1906.05425v1 [quant-ph] 12 Jun 2019. Summary of the Invention [Problem to be solved by the invention]

[0008] When a chip is mounted on a sample holder, there is a demand for a higher resonant frequency than that of the technology described in Non-Patent Document 1, which occurs when a signal of a specific frequency is input to the chip. The present disclosure aims to solve the above problems and provide a sample holder that can increase the resonant frequency of the chip mode in a superconducting quantum circuit. [Means for solving the problem]

[0009] According to one aspect of the present disclosure, there is provided a sample holder comprising a metal base and a PCB (Printed Circuit Board) placed on the base, the PCB having a through hole formed therein that penetrates from the front surface to the back surface, and a bottomed, open-top cavity formed on the side of the base on which the PCB is placed, directly below the through hole of the PCB, and a configuration in which the side of the base on which the PCB is placed is viewed from above, with a portion of the cavity extending outside the through hole. [Effects of the Invention]

[0010] According to the present disclosure, when a chip is mounted on a sample holder, it is possible to increase the resonant frequency of the resonance that occurs when a signal of a specific frequency is input to the chip. [Brief explanation of the drawings]

[0011] [Figure 1A] FIG. 1 is an explanatory diagram showing an example of a sample holder for storing a chip on which a superconducting quantum circuit is formed. [Figure 1B] FIG. 1B is a side view of the sample holder shown in FIG. 1A. [Figure 2A] Top view of the PCB. [Figure 2B] This is a bottom view of the PCB. [Figure 2C] A side view of the PCB. [Figure 2D] This is a perspective view of the PCB. [Figure 2E] This is an enlarged view of the PCB near the through hole. [Figure 3A] FIG. 2 is a perspective view showing a configuration in which a superconducting quantum circuit chip is mounted on the sample holder shown in FIGS. 1A and 1B. [Figure 3B] 3A is an end view of a configuration in which a superconducting quantum circuit chip is mounted on the sample holder shown in FIGS. 1A and 1B, cut along a plane parallel to the xz plane including the cutting line A-AA shown in FIG. 3A. [Figure 4A] FIG. 1 is a top view of a chip used in a simulation. [Figure 4B]FIG. 2 is an enlarged view of the vicinity of the tip of the first coplanar waveguide. [Figure 5A] FIG. 4B is a perspective view showing an example in which the chip shown in FIGS. 4A and 4B is mounted on the sample holder shown in FIGS. 1A and 1B. [Figure 5B] FIG. [Figure 6A] 5B is an explanatory diagram showing reflection (S11) to Port 1 when a high-frequency signal is input from Port 1 shown in FIG. 5A. FIG. [Figure 6B] 5B is an explanatory diagram showing transmission (S21) to Port 2 when a high-frequency signal is input from Port 1 shown in FIG. 5A. FIG. [Figure 7A] FIG. 1 is a perspective view of a sample holder having a cavity formed in a base. [Figure 7B] FIG. 1 is a top view of a sample holder having a cavity formed in a base. [Figure 7C] 7C is an end view of a sample holder having a cavity formed in a base, cut along a plane parallel to the xz plane including the cutting line B-BB shown in FIG. 7B. [Figure 8] 5A and 5B are explanatory diagrams showing the simulation results of reflection (S11) to Port 1 when a high-frequency signal is input from Port 1 shown in FIG. 5A in the case where the chip shown in FIGS. 4A and 4B is mounted on the sample holder shown in FIGS. 7A, 7B, and 7C. [Figure 9] FIG. 2 is an explanatory diagram showing a sample holder according to the first embodiment. [Figure 10A] FIG. 2 is a perspective view showing a sample holder according to the first embodiment. [Figure 10B] FIG. 2 is a top view of the sample holder of the first embodiment. [Figure 10C] FIG. 2 is a perspective view of the sample holder of the first embodiment as seen from the positive y-axis direction. [Figure 11A] FIG. 2 is a top view of a PCB used in the sample holder of the first embodiment. [Figure 11B] FIG. 2 is a bottom view of a PCB used in the sample holder of the first embodiment. [Figure 11C] FIG. 2 is a side view of a PCB used in the sample holder of the first embodiment. [Figure 11D] FIG. 2 is a perspective view of a PCB used in the sample holder of the first embodiment. [Figure 11E] FIG. 2 is an enlarged view of the vicinity of a through-hole of a PCB used in the sample holder of the first embodiment. [Figure 12] FIG. 10 is an explanatory diagram showing a simulation result of S11 when a chip is mounted on a sample holder according to the first embodiment with a bonding wire. [Figure 13A] FIG. 10 is a perspective view showing a sample holder according to a modified example of the first embodiment. [Figure 13B] FIG. 10 is a top view of a sample holder according to a modified example of the first embodiment. [Figure 13C] FIG. 10 is a perspective view of a sample holder according to a modified example of the first embodiment, viewed from the positive direction of the y-axis. [Figure 14] FIG. 10 is an explanatory diagram showing a simulation result of S11 when a chip is mounted on a sample holder with bonding wires according to a modified example of the first embodiment. [Figure 15A] FIG. 10 is a perspective view showing a sample holder according to a second embodiment. [Figure 15B] FIG. 10 is a top view of the sample holder of the second embodiment. [Figure 15C] FIG. 10 is a perspective view of the sample holder of the second embodiment as seen from the positive y-axis direction. [Figure 16] FIG. 10 is an explanatory diagram showing a simulation result of S11 when a chip is mounted on a sample holder according to the second embodiment with a bonding wire. [Figure 17A] FIG. 10 is a perspective view showing a sample holder according to a third embodiment. [Figure 17B] FIG. 10 is a top view of the sample holder of the third embodiment. [Figure 17C] FIG. 10 is a perspective view of the sample holder of the third embodiment as seen from the positive y-axis direction. [Figure 18] FIG. 11 is an explanatory diagram showing a simulation result of S11 when a chip is mounted on a sample holder according to the third embodiment with a bonding wire. [Figure 19A]FIG. 10 is a perspective view showing another example of a sample holder according to the third embodiment. [Figure 19B] FIG. 10 is a top view of another example sample holder of the third embodiment. [Figure 19C] FIG. 10 is a perspective view of another example of a sample holder of the third embodiment, viewed from the positive y-axis direction. [Figure 20] FIG. 11 is an explanatory diagram showing a simulation result of S11 when a chip is mounted with a bonding wire on a sample holder according to another example of the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Below, embodiments of a sample holder and a superconducting quantum computer according to the present disclosure will be described in detail with reference to the drawings. However, the drawings schematically show the configuration of the embodiments of the present disclosure. Furthermore, the embodiments of the present disclosure described below are examples and can be modified as appropriate within the scope of their essence. Furthermore, in the following description of the drawings, identical or similar parts are designated by identical or similar reference numerals. Furthermore, in the following drawings, elements not used in the description will be omitted as appropriate. Furthermore, in the following description, ground (also referred to as "ground") may be referred to as "GND." For example, a surface ground will be referred to as a surface GND, and a back ground will be referred to as a back GND.

[0013] To clarify the effect of the sample holder according to each embodiment, the results of a simulation using a model of a sample holder similar to the sample holder described in Non-Patent Document 1 are compared with the results of a simulation using a model of the sample holder according to each embodiment. Therefore, before describing each embodiment in detail, the problem of the chip mode in superconducting quantum circuits will first be explained in more detail. Then, the results of a simulation using a model of a sample holder similar to the sample holder described in Non-Patent Document 1 will be explained.

[0014] A sample holder similar to the one described in Non-Patent Document 1 has a PCB mounted on a metal base. Furthermore, this sample holder has a through-hole near the center of the PCB. Furthermore, this sample holder has a hollowed-out portion of the metal base directly below the chip, forming a cavity directly below the chip.

[0015] In addition, in each drawing, in order to clarify each direction, the description will be given using x-axis, y-axis, and z-axis as a three-dimensional coordinate system.

[0016] FIG. 1A is an explanatory diagram showing an example of a sample holder for storing a chip on which a superconducting quantum circuit is formed. FIG. 1B is a side view of sample holder 101 in FIG. 1A, seen in the y-axis direction. As shown in FIG. 1A, sample holder 101 has a configuration in which PCB 103 is placed on metal pedestal 102. In FIG. 1A, pedestal 102 has a three-dimensional shape of a rectangular parallelepiped or cube. Near the center of the surface of PCB 103, a through-hole (through opening) 104 is provided, penetrating PCB 103 from the front surface to the back surface.

[0017] An example of PCB 103 is shown in Figures 2A to 2E. Figure 2A is a top view of PCB 103 in Figure 1A. Figure 2B is a bottom view of PCB 103 in Figure 1A. Figure 2C is a side view of PCB 103 in Figure 1A as viewed in the y-axis direction. Figure 2D is a perspective view of PCB 103. Figure 2E is an enlarged view of the vicinity of through-hole 104 of PCB 103 in Figure 1A.

[0018] As shown in FIGS. 2A to 2E, the PCB 103 has a structure in which, for example, a surface GND 109 and a core 110 of a coplanar waveguide are formed on one surface of a plate-like dielectric 108 extending parallel to the xy plane, and a back GND 111 is formed on the other surface of the dielectric 108.

[0019] The core wire 110, the front GND 109, and the back GND 111 are conductors, such as metals. Here, the coplanar waveguide is a waveguide having a structure that is composed of a central conductor (hereinafter abbreviated as "center conductor") and two GND planes arranged on both sides of the center conductor on the xy plane with a gap between them, and the central conductor and the two GND planes are arranged on approximately the same plane (xy plane).

[0020] 2A and 2E, the two GND planes on both sides of core wire 110, which is the central conductor of the coplanar waveguide, are formed by surface GND 109. In PCB 103 shown in FIGS. 2A to 2E, a coplanar waveguide is formed by forming surface GND 109 on both side surfaces of core wire 110 with gaps in the xy plane. In the example shown in FIGS. 2A to 2E, as a non-limiting example, a total of eight coplanar waveguides are formed on the surface of PCB 103 between each side of through hole 104 near the center and the outer periphery opposite each side, one along the x-axis and three along the y-axis.

[0021] 2D, the PCB 103 is provided with a plurality of through holes 112. These through holes 112 penetrate the dielectric 108 and electrically connect the front surface GND 109 and the back surface GND 111. The through holes 112 are fabricated, for example, by forming holes that penetrate the dielectric 108, the front surface GND 109, and the back surface GND 111, and then plating the inside of the holes with metal.

[0022] 1A and 1B, the back surface GND 111 of the PCB 103 is in contact with the entire surface of the base 102. Therefore, the metal base 102, the back surface GND 111 of the PCB 103, the multiple through holes 112 of the PCB 103, and the front surface GND 109 of the PCB 103 are electrically connected.

[0023] Furthermore, the opening surface of through-hole 104 provided near the center of PCB 103 has the same planar shape, that is, a rectangular or square shape (rectangular shape), as the chip of the superconducting quantum circuit mounted on sample holder 101. Furthermore, since the chip is housed inside through-hole 104 of PCB 103, the area of ​​through-hole 104 is larger than the area of ​​the chip.

[0024] Next, FIGS. 3A and 3B show a configuration in which a superconducting quantum circuit chip is mounted on the sample holder 101 shown in FIGS. 1A and 1B. FIG. 3A is a perspective view showing a configuration in which a superconducting quantum circuit chip 107 is mounted on the sample holder 101 shown in FIGS. 1A and 1B. FIG. 3B is a diagram showing an end face cut along a plane parallel to the xz plane including the cutting line A-AA in FIG. 3A, which shows the configuration in which a superconducting quantum circuit chip 107 is mounted on the sample holder 101 shown in FIGS. 1A and 1B. In FIGS. 3A and 3B, the PCB 103 described with reference to FIGS. 2A to 2E is used as the PCB 103.

[0025] As shown in FIGS. 3A and 3B, a chip 107 is accommodated inside a through-hole 104 of a PCB 103. The chip 107 accommodated in the through-hole 104 is placed on a base 102. Pads on the circuit surface of the chip 107 are electrically connected to core wires 110 on the surface of the PCB 103 by bonding wires 113 made of aluminum (Al) or the like, and a GND (ground) plane (not shown) on the circuit surface of the chip 107 is electrically connected to a GND 109 on the surface of the PCB by bonding wires 113 made of aluminum or the like. The pads of the chip 107 refer to terminals (electrodes) for signal input / output formed on the circuit surface of the chip 107. In the example shown in FIGS. 3A and 3B, the entire back surface of the chip 107 (the lower surface of the chip 107 in FIG. 3B) is in contact with (abuts against) the metal base 102.

[0026] When a chip 107 is mounted on the sample holder 101 shown in Figures 1A and 1B, resonance occurs when a signal of a specific frequency is input to the chip 107. To identify the cause of this chip mode resonance, a simulation is performed using electromagnetic field analysis software. Here, the simulation was performed using ANSYS (registered trademark) HFSS manufactured by ANSYS Japan, Inc. The same tool is used for subsequent simulations.

[0027] The chip is shown in FIGS. 4A and 4B. FIG. 4A is a top view of the chip 107 used in the simulation. FIG. 4B is an enlarged view of the tip of the first coplanar waveguide 71. As shown in FIG. 4A, the chip 107 has a rectangular or square planar shape, and the lengths of each side of the chip 107 are v and w, respectively. In the following description, in the simulation, the shape of the chip 107 is assumed to be square, and the length of each side of the chip 107 is assumed to be v = w = 5 mm (millimeters). Furthermore, in the chip 107 used in the simulation, a circuit pattern is formed by depositing a metal film, for example, 200 nm (nanometers) thick, on the entire surface of a silicon substrate having a thickness of 380 μm (micrometers), and then removing predetermined portions (regions) of the metal film. Alternatively, a resist may be applied to the silicon substrate and patterned, and a metal film may be deposited on the entire surface, and then the resist may be removed to form a metal pattern (circuit pattern) in the areas where there was no resist.

[0028] 4A and 4B, a first coplanar waveguide 71 and a second coplanar waveguide 72 are arranged facing each other and extending in the x-axis direction, symmetrically about the y-axis. The first coplanar waveguide 71 and the second coplanar waveguide 72 have the same shape. The characteristic impedance of the first coplanar waveguide 71 and the second coplanar waveguide 72 is designed to be 50 Ω, and the length is 1 mm.

[0029] 4B shows an enlarged view of the vicinity of the tip of the first coplanar waveguide 71. As shown in FIG. 4B, the tip of the first coplanar waveguide 71 is not in contact with the GND plane 73. As shown in FIG. 4A, the first coplanar waveguide 71 and the second coplanar waveguide 72 are not connected. Similarly, the tip of the second coplanar waveguide 72 is not in contact with the GND plane 73. One end of the first core wire 74 is connected to the first pad 76, and one end of the second core wire 75 is connected to the second pad 77.

[0030] 5A is a perspective view showing an example in which the chip 107 shown in FIGS. 4A and 4B is mounted on the sample holder 101 shown in FIGS. 1A and 1B. FIG. 5B is an enlarged view of the vicinity of the chip 107 in FIG. 5A. As shown in FIGS. 5A and 5B, a first pad 76 of the chip 107 is electrically connected to a first core wire 110a of the PCB 103 by an Al bonding wire 113. A second pad 77 of the chip 107 is electrically connected to a second core wire 110b of the PCB 103 by an Al bonding wire 113, and a GND plane 73 of the chip 107 is electrically connected to a surface GND 109 of the PCB 103 by an Al bonding wire 113.

[0031] As shown in FIG. 5A, one end of the first core wire 110a of the PCB 103 is connected to the first pad 76 of the chip 107. The other end of the first core wire 110a of the PCB 103 is designated Port 1. One end of the second core wire 110b of the PCB 103 is connected to the second pad 77 of the chip 107. The other end of the second core wire 110b of the PCB 103 is designated Port 2. In the simulation, for example, when a high-frequency signal is input from Port 1, the reflection to Port 1 and transmission to Port 2 are calculated. The reflection to Port 1 (the input reflection coefficient indicating the proportion of the signal reflected at Port 1 relative to the signal input to Port 1) is designated S11, and the transmission coefficient from Port 1 to Port 2 is designated S21.

[0032] FIG. 6A is an explanatory diagram showing the reflection coefficient (S11) at port 1 when a high-frequency signal is input from port 1 in FIG. 5A. FIG. 6B is an explanatory diagram showing the transmission coefficient (S21) to port 2 when a high-frequency signal is input from port 1 in FIG. 5A. In FIGS. 6A and 6B, the horizontal axis is frequency (unit: GHz (GigaHertz)). S11 and S21 on the vertical axis are expressed in decibels (dB). In other words, S11 and S21 on the vertical axis are expressed in logarithms. Note that in the following explanation of the simulation results, the horizontal axis also represents frequency (unit: GHz), and S11 and S21 on the vertical axis are expressed in decibels (dB).

[0033] 6A and 6B, when a signal of a certain frequency is input, S21 becomes extremely large and S11 becomes extremely small. As shown in FIGS. 4A and 4B, the first coplanar waveguide 71 and the second coplanar waveguide 72 of the chip 107 are not connected. Therefore, even if a signal is input to Port 1, it is expected that the signal will not be transmitted to Port 2.

[0034] However, as shown in the simulation results in FIG. 6B, when a signal of some specific frequencies is input from Port 1, S21 becomes very large. For example, according to the simulation results in FIG. 6B, when an 8.9 GHz signal is input from Port 1, S21 is approximately -1.9 dB. In other words, approximately 65% ​​of the energy of the signal input from Port 1 is transmitted to Port 2. At specific frequencies where S21 becomes very large, the simulation results in FIG. 6A show that S11 becomes very small.

[0035] The simulation results shown in Figures 6A and 6B reveal the following: In a system in which superconducting quantum circuit chip 107 is mounted on sample holder 101 as shown in Figures 5A and 5B, the space between GND plane 73 on the surface of chip 107 and metal pedestal 102, i.e., the silicon substrate of chip 107, forms a cavity resonator.

[0036] The first coplanar waveguide 71 and the second coplanar waveguide 72 on the surface (circuit surface) of the chip 107 are coupled to a cavity resonator (the silicon substrate of the chip 107). Therefore, when a signal having a frequency equal to the resonant frequency of the cavity resonator is input to the chip 107, for example, from port 1, the cavity resonator is excited to resonate. This causes standing waves to form in the silicon substrate, and electromagnetic field energy accumulates in the silicon substrate. Because the second coplanar waveguide 72 of the chip 107 is also coupled to the cavity resonator, part of the electromagnetic field energy accumulated in the silicon substrate is transmitted through the second coplanar waveguide 72 of the chip 107 to port 2.

[0037] 3A and 3B, regardless of the type of circuit formed on chip 107. Furthermore, this phenomenon can occur not only when coplanar waveguides 71 and 72 as shown in FIGS. 4A and 4B are formed on chip 107, but also when any superconducting quantum circuit is formed on chip 107. In the mounting system exemplified in FIGS. 3A and 3B, resonance caused by the space sandwiched between GND plane 73 on the surface of chip 107 and metal base 102, i.e., the silicon substrate, forming a cavity resonator, is included in the "chip mode resonance" described above in this specification.

[0038] 6A and 6B, certain frequencies at which S21 becomes very large and S11 becomes very small are hereinafter referred to as "chip mode resonance frequencies." When a signal having a frequency equal to or close to the chip mode resonance frequency is input to the chip 107, chip mode resonance occurs.

[0039] According to the simulation results shown in FIGS. 6A and 6B, the lowest resonant frequency of the chip mode in the system shown in FIGS. 5A and 5B is 8.9 GHz. In the system shown in FIGS. 3A and 3B (a system in which a chip 107 with a superconducting quantum circuit formed thereon is mounted on the sample holder 101 shown in FIGS. 1A and 1B), when the chip mode couples with the superconducting quantum circuit formed on the chip 107, decoherence of the superconducting quantum circuit occurs, as described above. It is known that in order to reduce the effects of this decoherence, it is necessary to increase the resonant frequency of the chip mode as much as possible. For this reason, there is a demand for a technology to increase the resonant frequency of the chip mode. As an example of such a technology, the aforementioned Non-Patent Document 1 (particularly, FIG. 2 and the related explanation) describes that the effects of the chip mode can be reduced by hollowing out a portion of the base 102 directly below the chip 107 to form a cavity directly below the chip 107.

[0040] 7A to 7C are enlarged views of the vicinity of through-hole 104 in PCB 103 of sample holder 101, in which a cavity similar to that described in Non-Patent Document 1 is formed in base 102. FIG. 7A is a perspective view of sample holder 101, in which a cavity similar to that described in Non-Patent Document 1 is formed in base 102. FIG. 7B is a top view of sample holder 101, in which a cavity is formed in base 102. FIG. 7C is a diagram showing an end face of sample holder 101, in which a cavity is formed in base 102, cut along a plane parallel to the xz plane including cutting line B-BB in FIG. 7B. As shown in FIGS. 7A to 7C, a cavity 105 is formed in base 102 directly below through-hole 104 in PCB 103. 7A to 7C, a cavity 105 is formed in the base 102 in a portion that would be directly below the chip 107 when the chip 107 is mounted on the sample holder 101. Also, in FIGS. 7A to 7C, the cavity 105 has the shape of a rectangular prism (a hollow rectangular prism with a bottom) having an upper surface (opening) and a bottom surface with the same area as the chip 107. The base 102 has a structure in which pillars 106 remain at the four corners of the cavity 105. The pillars 106 are made of, for example, metal. In FIG. 7C, pads 76 and 77 of the chip 107 in the sample holder 101 are connected to first and second core wires 110a and 110b of the PCB 103 by bonding wires 113.

[0041] In Figures 7A, 7B, and 7C, the pillars 106 are depicted with a different pattern than the base 102. This is to clearly identify the pillars 106 in each of the figures. The metal pillars 106 at the four corners are integrated with the base 102 and form part of the base 102. The top surfaces of the metal pillars 106 at the four corners shown in Figures 7A, 7B, and 7C contact (abut) the back surface of the chip 107. As shown in Figures 7A and 7B, the metal pillars 106 are triangular pillars with a right-angled isosceles triangle as their base. As shown in Figure 7C, a simulation was performed on the sample holder 101 of Figures 7A, 7B, and 7C, with the length of two equal sides of the base of the pillars 106 set to 1 mm (millimeter) and the height of the cavity 105 set to 3 mm, and the chip 107 of Figures 4A and 4B mounted thereon.

[0042] 8 is an explanatory diagram showing a simulation result of reflection (S11) to port 1 in Fig. 5A when a high-frequency signal is input from port 1 in sample holder 101 shown in Fig. 7A, 7B, and 7C, in the case where chip 107 in Fig. 4A and 4B is mounted on PCB 103 with bonding wire 113. The simulation result in Fig. 8 shows that when cavity 105 shown in Fig. 7A, 7B, and 7C is formed in base 102, and chip 107 in Fig. 4A and 4B is mounted on PCB 103 with bonding wire 113, the minimum resonance frequency of the chip mode can be increased to 19.9 GHz.

[0043] In contrast, in the simulation results (FIGS. 6A and 6B) when the cavity 105 is not formed in the base 102, the lowest resonance frequency of the chip mode is 8.9 GHz.

[0044] This shows that the resonant frequency of the tip mode can be significantly increased by using the sample holder 101 in which the cavity 105 shown in FIGS. 7A, 7B, and 7C is formed in the base 102.

[0045] The reason why the formation of the cavity 105 in the base 102 can increase the resonant frequency of the chip mode is that when the cavity 105 is formed in the portion of the base 102 directly below the chip 107, the inside of the cavity resonator formed by the space sandwiched between the GND plane 73 on the surface of the chip 107 and the base 102 (the bottom of the cavity 105 in this case) is presumed to consist of the silicon substrate of the chip 107 (thickness 380 μm in the simulation) and vacuum (thickness 3 mm in the simulation), as shown in Fig. 7C. This is presumed to be because the effective dielectric constant inside the cavity resonator is lowered compared to when the cavity 105 is not formed in the base 102 (i.e., when the inside of the cavity resonator consists almost entirely of the silicon substrate of the chip 107).

[0046] While the relative permittivity εr of a vacuum is 1, the relative permittivity εr of silicon is extremely high at 11.9. In general, the lower the permittivity of the medium filling the inside of a cavity resonator, the higher the resonant frequency of the cavity resonator.

[0047] In this way, by using the sample holder 101 in which the cavity 105 is formed in the base 102, the resonant frequency of the chip mode can be increased. However, in order to reduce the influence of the chip mode on the superconducting quantum circuit, it is necessary to increase the resonant frequency of the chip mode as much as possible. Furthermore, as the number of quantum bits integrated on the chip 107 increases toward the practical application of quantum computers, it is predicted that a chip 107 with an area larger than, for example, 5 mm x 5 mm will be required.

[0048] The larger the area of ​​the chip 107, the lower the resonant frequency of the chip mode. This is because the larger the area of ​​the chip 107, the larger the dimension (area) of the bottom surface of the cavity resonator formed by the space between the GND plane 73 on the surface of the chip 107 and the base 102. Therefore, even if a sample holder 101 having a cavity 105 formed in the base 102 as shown in FIGS. 7A to 7C is used, the larger the area of ​​the chip 107, the lower the resonant frequency of the chip mode, and it is predicted that this will have a greater impact on the superconducting quantum circuit. For these reasons, there is a need to develop a technology that can further increase the resonant frequency of the chip mode as much as possible compared to the case where a sample holder 101 having a cavity 105 formed in the base 102 as described in Non-Patent Document 1 is used.

[0049] Therefore, several embodiments that can increase the resonant frequency of the chip mode compared to the technique described in Non-Patent Document 1 will be described.

[0050] (First embodiment) In the first embodiment, a configuration example will be described in which a PCB in contact with (placed on) a pedestal has a dielectric, a front GND formed on the front surface of the dielectric, a back GND formed on the back surface of the dielectric, and a through-hole (through opening) that penetrates from the front GND to the back GND and in which a chip is stored. In the first embodiment, an example will be described in which a cavity is formed in at least a part of the pedestal below the through-hole, and the cavity has a support structure that supports the surface of the chip and is conductive to the pedestal.

[0051] 9 is an explanatory diagram showing a sample holder of the first embodiment. Referring to FIG. 9, the sample holder 1 of the first embodiment has a configuration in which a PCB 3 is mounted on a metal pedestal 2. A through-hole 4 (through-opening) that penetrates the PCB 3 is provided near the center of the PCB 3. The shape of the pedestal 2 is not particularly limited, and may be, for example, a rectangular parallelepiped or a cube. The sample holder 1 has a cavity 5 in the portion of the pedestal 2 directly below the through-hole 4 in the PCB 3.

[0052] By aligning the height of the circuit surface of the chip (not shown) and the height of the surface of the PCB 3 as much as possible, wire bonding can be performed easily and the bonding wire can be shortened. The shorter the bonding wire, the better the electrical characteristics. Furthermore, by forming a through hole 4 in the PCB 3, the resonant frequency of the chip mode can be increased. If a dielectric or conductor is present on the back surface (opposite the circuit surface) of the chip (not shown), the resonant frequency of the chip mode will decrease. Therefore, in the first embodiment, the back surface of the chip is configured to be in contact with vacuum as much as possible in order to increase the resonant frequency of the chip mode.

[0053] If a chip is placed on the PCB 3 without forming the through-hole 4 in the PCB 3, the back surface of the chip will come into contact with the dielectric or conductor of the PCB 3. As a result, the resonant frequency of the chip mode cannot be increased.

[0054] Therefore, in the first embodiment, a through hole 4 is formed in the PCB 3, a chip is placed in the through hole 4, and a cavity 5 is further formed in the base 2 directly below the chip, thereby creating a structure in which as large an area as possible of the back surface of the chip comes into contact with the vacuum.

[0055] 10A to 10C are enlarged views of the vicinity of the through-hole 4 of the PCB 3 of the sample holder 1 of the first embodiment. FIG. 10A is a perspective view showing the sample holder 1 of the first embodiment. FIG. 10B is a top view of the sample holder 1 of the first embodiment. FIG. 10C is a perspective view (perspective side view) of the sample holder of the first embodiment as viewed from the positive direction of the y-axis. In FIG. 10C, the chip 7 is mounted on the PCB 3 of the sample holder 1 by connecting the pads of the chip 7 with bonding wires 13 (wire bonding mounting).

[0056] The sample holder 1 has a cavity 5 in at least a portion of the base 2 below the through-hole 4. In Figures 10A to 10C, the sample holder 1 has the cavity 5 in the portion of the base 2 that is directly below the through-hole 4 in the PCB 3. In other words, in Figures 10A to 10C, the sample holder 1 has the cavity 5 in the portion of the base 2 that is directly below the chip 7 when the chip 7 is mounted on the sample holder 1 with bonding wires 13.

[0057] In this embodiment, the cavity 5 formed in the base 2 is the cavity 5 of Non-Patent Document 1 described with reference to Figures 7A, 7B, 7C, etc., with portions of the four side walls of the cavity extended outward by a length u. Therefore, as shown by the dashed line in Figure 10B, when viewed from the front surface side (positive direction of the z-axis) of the PCB 103, the cavity 5 has a cross-shaped planar shape; in other words, the bottom surface of the cavity 5 has a substantially cross-shaped shape. When viewed from the front surface side (positive direction of the z-axis) of the PCB 3, portions of the four sides (excluding the portions of the pillars 6 at the four corners) of the bottom surface of the cavity 5 (see the cavity 5 shown by the dashed line in Figure 10B) protrude outward by a length u beyond the area where the chip 7 is placed. That is, the cavity 5 of the base 2 has an area (the area of ​​the cavity 5 shown by the dashed line in Figure 10B) that extends outward by a length u from each side connecting two adjacent corners of the through hole 4 (square or rectangle) of the PCB 3, and this area corresponds to the area between the sides (equidistant: length s) of two adjacent pillars 6 (cross-sectional shape of an isosceles triangle).

[0058] If the dimensions of the chip 7 mounted on the sample holder 1 are v × w, the dimensions a and b shown in the cavity 5 in FIG. 10B can be, for example, a = v and b = w. Directly below the through-hole 4 is a support structure (pillar 6 in the example of FIGS. 10A to 10C) that supports the backside of the chip 7 and is electrically connected to the base 2. The support structure is made of, for example, metal. Specifically, the material of the pillar 6 (support structure) may be a mixture containing metal, such as resin mixed with metal particles or filler. As shown in FIGS. 10A and 10B, this support structure may have the shape of a triangular prism with a right-angled triangular base.

[0059] 10A to 10C, the support structure may be a pillar 6. Although not shown, the support structure may be, for example, a protrusion that protrudes from the side surface of the cavity 5 into the cavity 5 and extends from the front to the back of the cavity 5.

[0060] Here, the support structure will be described using the pillars 6 shown in Figures 10A to 10C as an example. The number and shape of the pillars 6 are not particularly limited. In Figures 10A to 10C, multiple pillars 6 are provided directly below the through-hole 4. More specifically, the pillars 6, which are conductive, are arranged directly below the through-hole 4.

[0061] 10A to 10C, in order to clearly show the pillar 6, the pillar 6 is shown in grayscale as the base 2. Note that in FIGS. 10A to 10C, the base of the pillar 6 is in the shape of a right-angled isosceles triangle. The length of the two equal sides (equal sides) of the base of the pillar 6 is s. The height of the pillar 6 is d. The pillar 6, whose base is a right-angled isosceles triangle, abuts at points corresponding to its vertices on the four corners of the cavity 5, whose opening is rectangular (square or oblong). In other words, the conductive pillar 6 is in electrical contact with the base 2.

[0062] 10A to 10C, the four conductive pillars 6 may be separate from the base 2. Alternatively, in FIGS. 10A to 10C, the pillars 6 may be made of the same material as the base 2. In this case, for example, the base 2 and the pillars 6 may be integrated. When the chip 7 is mounted on the sample holder 1 with bonding wires 13, the top surfaces of the four pillars 6 abut (contact) against the four corners of the back surface (square or rectangular) of the chip 7.

[0063] Here, the effect of using the pillars 6 will be explained. Without the pillars 6, there is a concern that the chip 7 may fall into the cavity 5. The chip 7 and PCB 3 are connected by bonding wires. Therefore, basically, the chip 7 will not fall into the cavity 5 even without the pillars 6. However, there is a possibility that the chip 7 may fall into the cavity 5 due to vibration or the like, or that some of the bonding wires may come loose, causing the chip 7 to fall into the cavity 5. By providing the metal pillars 6, it is possible to prevent the chip 7 from falling into the cavity 5 and prevent the bonding wires from coming loose.

[0064] Furthermore, the metal pillar 6 can strengthen the thermal path between the chip 7 and the pedestal 2. The superconducting quantum circuit chip 7 is operated by being cooled to an extremely low temperature, for example, about 10 mK (millikelvin) in a refrigerator, and the pedestal 2 is generally in thermal contact with the cold stage (the coldest part) of the refrigerator. In other words, the pedestal 2 becomes extremely cold. The stronger the thermal path (thermal conduction path) between the pedestal 2 and the chip 7, in other words, the smaller the thermal resistance between the pedestal 2 and the chip 7, the better the chip 7 is cooled.

[0065] If the chip 7 is not cooled to an extremely low temperature, it will be impossible to bring out the best performance of the quantum circuit formed on the chip 7. For this reason, it is desirable to cool the chip 7 to as low a temperature as possible. Therefore, it is preferable that the thermal resistance between the base 2 and the chip 7 is as small as possible. The metal pillars 6 reduce the thermal resistance between the base 2 and the chip 7.

[0066] To maximize the thermal conduction path between the chip 7 and the base 2, for example, a structure without a cavity 5 in the base 2 is conceivable. However, if a cavity 5 is not formed in the base 2, there is a problem with chip mode. Therefore, to solve the problem of chip mode, if a cavity 5 is formed in the base 2, part of the upper surface of the pillars 6 arranged in the cavity 5 is made parallel to the back surface of the chip 7. In other words, in the support structure arranged in the cavity 5, at least part of the part supporting the chip 7 is parallel to the back surface of the chip 7. The upper surface of each of the four pillars 6 has an abutment surface that makes surface contact with the corresponding area at the four corners of the back surface (square or rectangular) of the chip 7. This reduces the thermal resistance between the base 2 and the chip 7.

[0067] The PCB 3 used in this embodiment is similar to the PCB 3 described with reference to Figures 2A to 2E. Figures 11A to 11E correspond to Figures 2A to 2E, respectively. Figure 11A is a top view of the PCB 3 used in the sample holder 1 of the first embodiment. Figure 11B is a bottom view of the PCB 3 used in the sample holder 1 of the first embodiment. Figure 11C is a side view of the PCB 3 used in the sample holder 1 of the first embodiment. Figure 11D is a perspective view of the PCB 3 used in the sample holder 1 of the first embodiment. Figure 11E is an enlarged view of the vicinity of the through-hole 4 of the PCB 3 used in the sample holder 1 of the first embodiment.

[0068] As shown in FIGS. 11A and 11E, the PCB 3 has, for example, a plate-shaped dielectric body 8 (substrate) extending parallel to the xy plane. The PCB 3 has a structure in which a surface GND 9 and a core wire 10 of a coplanar waveguide are formed on one surface (surface) of the dielectric body 8. The PCB 3 has a structure in which a back surface GND 11 is formed on the other surface (back surface) of the dielectric body 8. The core wire 10, the surface GND 9, and the back surface GND 11 are conductors, such as metals. Examples of such metals include Cu (copper) and Au-plated Cu. In FIG. 11A, eight coplanar waveguides are formed on the PCB 3. The coplanar waveguides are as described in FIG. 2A. However, the number of coplanar waveguides formed on the PCB 3 is not particularly limited and may be any number. As shown in FIG. 11D, the PCB 3 has a plurality of through holes 12. These through holes 12 penetrate the dielectric 8 and electrically connect the front surface GND 9 and the back surface GND 11. The through holes 12 are produced, for example, by forming holes that penetrate the dielectric 8, the front surface GND 9, and the back surface GND 11, and then plating the inside of the holes with metal.

[0069] In FIG. 9, the backside GND 11 of the PCB 3 (FIG. 11C) is in contact with the mounting surface of the PCB 3 on the pedestal 2. Therefore, the metal pedestal 2, the backside GND 11 of the PCB 3, the through-hole 12 of the PCB 3, and the frontside GND 9 of the PCB 3 are electrically connected. In addition, a through-hole 4 is provided near the center of the PCB 3. This through-hole 4 may have the same planar shape as the planar shape of the chip 7 of the superconducting quantum circuit mounted on the sample holder 1, for example, a rectangular or square shape. Furthermore, the area of ​​the through-hole 4 is larger than the area of ​​the chip 7 so that the chip 7 can fit inside the through-hole 4.

[0070] FIG. 12 shows the simulation results of the S parameter S11 of a system in which the chip 7 shown in FIG. 4A is mounted with bonding wires 13 on the sample holder 1 of the first embodiment shown in FIG. 9. Here, S11 is the reflection coefficient to Port 1 when a high-frequency signal is input from Port 1 shown in FIG. 11A, as described above. FIG. 12 is an explanatory diagram showing the simulation results of S11 when the chip 7 shown in FIG. 4A is mounted with bonding wires 13 on the sample holder 1 of the first embodiment. In the simulation of FIG. 12, the area of ​​the chip 7 was set to 5 mm×5 mm, and a = 5 mm, b = 5 mm, d = 3 mm, s = 1 mm, and u = 0.5 mm.

[0071] As shown in Fig. 12, the lowest resonance frequency in the chip mode is 20.5 GHz. Therefore, as shown in Fig. 12, according to the first embodiment, the lowest resonance frequency in the chip mode can be made higher than the simulation result shown in Fig. 8 (the simulation result of the S parameter S11 of a system in which the chip 7 shown in Fig. 4A is mounted on the sample holder 101 of Figs. 7A to 7C with bonding wires 13).

[0072] The reason why the resonant frequency of the tip mode can be increased by using the sample holder 1 of the first embodiment is believed to be as follows: As found by simulation, in this embodiment, the bottom area of ​​the cavity 5 is made larger than in the cases of Figures 7A to 7C, and therefore the proportion of the component inside the cavity 5 in the electric field generated when the tip mode is excited increases. Therefore, in the case of this embodiment, the effective dielectric constant is lower than in Non-Patent Document 1, and as a result, the resonant frequency of the tip mode is thought to be higher.

[0073] Simulations have shown that the larger w (where w is the dimension of the chip 7, v × w), the greater the effect of lowering the effective dielectric constant. However, the larger w is, the lower the resonant frequency of the cavity itself. Therefore, a trade-off between these two factors determines the w that maximizes the resonant frequency of the chip mode. When the bottom area of ​​the chip 7 is square and the area of ​​the chip 7 is v × v, simulations have shown that u is preferably greater than 0 and equal to or less than 0.3v.

[0074] According to a simulation, the greater the height d of the cavity 5, the higher the resonant frequency of the chip mode. However, once d is increased to a certain extent, the resonant frequency of the chip mode remains almost unchanged even if d is further increased.

[0075] Therefore, in the first embodiment, if the thickness of the chip 7 mounted on the sample holder 1 is t, the height d of the cavity 5 shown in Figures 10A to 10C is preferably 2t or more, more preferably 3t or more, and even more preferably 5t or more.

[0076] Furthermore, in the first embodiment, the smaller the upper area (top area) of the pillars 6 shown in FIGS. 10A to 10C is, the smaller the contact area between the back surface of the chip 7 and the tops of the pillars 6 of the base 2 can be, and therefore the higher the resonant frequency of the chip mode can be. Therefore, when the chip 7 mounted on the sample holder 1 is rectangular and the length of the short side of the chip 7 is v, it is preferable that s is 0.5v or less. Furthermore, it is preferable that s is 0.3v or less, and more preferably 0.2v or less. On the other hand, when the chip 7 mounted on the sample holder 1 is square and the length of one ...

[0077] (Modification of the first embodiment) As shown in FIG. 9, the sample holder 1 of the modified first embodiment has a configuration in which a PCB 3 is placed on a metal pedestal 2. In the modified first embodiment, a PCB 3 having the structure shown in FIGS. 11A to 11E is used, as in the first embodiment. In the modified first embodiment, a cavity 5 having the structure shown in FIGS. 13A to 13C is formed in the pedestal 2. FIGS. 13A, 13B, and 13C are, respectively, a perspective view, a top view, and a transparent view (transparent side view) of the sample holder 1 of this modified embodiment as seen from the positive y-axis direction.

[0078] In a modification of the first embodiment, a cavity 5 similar to that of the first embodiment (FIGS. 10A and 10C) is formed in a portion of the base 2 directly below the through-hole 4 of the PCB 3, in other words, in a portion directly below the chip 7 (FIG. 10C) when the chip 7 is mounted on the sample holder 1. That is, the cavity formed in the base in this modification is the cavity described in Non-Patent Document 1 (cavity 5 in FIGS. 7A to 7C) with portions of the four side walls of the cavity 5 extended outward by a length u. Therefore, as shown by the dashed line in FIG. 13B, when viewed from the front surface side of the PCB 3 (positive direction of the z-axis), the cavity 5 has a substantially cross-shaped planar shape. In other words, the bottom surface of the cavity 5 has a substantially cross shape, and when viewed from the front surface side of the PCB 3 (positive direction of the z-axis), a portion of the bottom surface of the cavity 5 (dashed line in FIG. 13B) extends outward by a length u beyond the area of ​​the chip (FIG. 13C). A support structure that supports the surface of the chip 7 and is electrically connected to the base 2 is provided directly below the through-hole 4. The support structure is made of, for example, a metal. Specifically, the support structure may be made of, for example, a mixture containing metal, such as a resin mixed with metal particles or a filler.

[0079] The difference between the modified example of the first embodiment (this modified example) and the structure of the cavity 5 in the first embodiment (FIGS. 10A to 10C) is that in this modified example, at least a part of the upper surface of the pillar 6, i.e., the surface facing the back surface of the chip 7 when the chip 7 is mounted by wire bonding on the sample holder 1, is not parallel to the back surface of the chip 7. In other words, at least a part of the top surface of the pillar 6 is not parallel to the top surface of the base 2.

[0080] As shown in FIG. 13C , in a modification of the first embodiment, the pillar 6 used in the sample holder 1 has a structure in which an upper portion 61 and a lower portion 62 are connected. The lower portion 62 has a triangular pillar shape, and the bottom surface of the lower portion 62 has a right-angled isosceles triangle shape. The length of two equal sides (equal sides) of this base is s, and the height of the lower portion 62 is d1. The upper portion 61 has a triangular pyramid shape. The bottom surface of the upper portion 61 has a right-angled isosceles triangle shape, and the height of the upper portion 61 is d2, where d1 + d2 = d. The bottom surface of the upper portion 61 and the upper surface (bottom surface) of the lower portion 62 have the same shape and dimensions. The upper portion 61 may also be a truncated triangular pyramid with the upper apex of the triangular pyramid cut off.

[0081] In this structure, when the chip 7 is mounted on the sample holder 1, at least a portion (upper vertex) of the upper portion 61 of each pillar 6 comes into contact (point contact) with the four corners of the back surface of the chip 7. With this structure, the contact area between the back surface of the chip 7 and the conductive pillars 6 can be reduced compared to the first embodiment (where the top surface of the pillars 6 (triangular pillars) has the same area as the bottom surface).

[0082] 14 shows the simulation results of S11 when a chip 7 is mounted on a sample holder 1 of a modified example of the first embodiment using bonding wires 13. In the simulation, the chip area was set to 5 mm × 5 mm, with a = 5 mm, b = 5 mm, d = 3 mm, d1 = 2 mm, d2 = 1 mm, s = 1 mm, and u = 0.5 mm. As shown in FIG. 14, the lowest resonant frequency of the chip mode can be increased to 22.6 GHz, which is higher than that of the first embodiment.

[0083] In this way, the sample holder 1 of the modified example of the first embodiment has the effect of being able to increase the resonant frequency of the tip mode compared to the sample holder 1 of the first embodiment.

[0084] The reason why the chip mode resonance frequency in the modified example of the first embodiment can be made higher than in the first embodiment is believed to be as follows. That is, in the first embodiment, the electric field of the standing wave generated when the chip mode resonance occurs spreads mainly within the silicon substrate of the chip and the cavity 5 (vacuum) provided in the base 2. However, in the portion directly above the pillar 6 (top surface), the space between the GND plane 73 on the surface of the chip 7 and the top surface of the pillar 6 is occupied only by the silicon substrate, and the electric field cannot spread into the vacuum. Therefore, the effective dielectric constant is high in the portion directly above the pillar 6. In contrast, in the modified example of the first embodiment, at least a portion of the top surface of the pillar 6 is not parallel to the back surface of the chip 7 (the top of the pillar 6 does not abut the four corners of the back surface of the chip 7). Therefore, in the portion directly above the top 61 of the pillar 6, the space between the GND plane 73 on the surface of the chip 7 and the top 61 of the pillar 6 becomes the silicon substrate and the cavity 5 (vacuum). Therefore, in this portion (between the upper portion 61 of the pillar 6 and the back surface of the four corners of the chip 7), the electric field can spread even in a vacuum, which is thought to be why the effective dielectric constant in the portion directly above the pillar 6 is lower than in the first embodiment.

[0085] (Second embodiment) As shown in FIG. 9, the sample holder 1 of the second embodiment has a configuration in which a PCB 3 is placed on a metal pedestal 2. In the second embodiment, as in the first embodiment, a PCB 3 having the structure shown in FIG. 11 is used. In the second embodiment, a cavity 5 having a structure as shown in FIGS. 15A-15C is formed in the portion of the pedestal 2 directly below the through-hole 4 of the PCB 3, in other words, directly below the chip when mounted on the sample holder 1. FIGS. 15A, 15B, and 15C are a perspective view, a top view, and a perspective view (perspective side view) of the sample holder 1 of the second embodiment, respectively, as viewed from the positive y-axis direction. As shown in FIGS. 15A-15C, in the second embodiment, the cavity 5 formed in the pedestal 2 has a bottomed hollow cylindrical shape. The diameter of the cylinder is longer than the length of one side of the base area (rectangle) of the chip 7 (FIG. 15C) and shorter than the diagonal of the base area (rectangle) of the chip 7. Therefore, as shown in FIG. 15B, when viewed from the front side of PCB 3 (positive direction of the z-axis), cavity 5 appears circular, with a portion of its circumference extending beyond the edge of chip 7 (the edge corresponding to through-hole 4 of PCB 3), while another portion of the circumference of cavity 5 is located inside the edge of chip 7 (the edge corresponding to through-hole 4 of PCB 3). With this structure, when the chip is mounted on sample holder 1, chip 7 is supported by pedestal 2. This prevents the chip from falling into cavity 5. Note that in FIGS. 15A to 15C, cavity 5 is shown in a different color (tone) from PCB 3, etc., to clearly indicate it.

[0086] Fig. 16 shows the simulation results of S11 when a chip 7 is mounted on the sample holder 1 of the second embodiment using bonding wires 13. In the simulation, the chip area was set to 5 mm x 5 mm, with d = 3 mm and a = 5.84 mm. As shown in Fig. 16, the lowest resonant frequency of the chip mode can be increased to 20.9 GHz, which is higher than that in Non-Patent Document 1.

[0087] The second embodiment differs from the first embodiment in the shape of the cavity 5. However, the second embodiment shares the technical concept of the first embodiment in that a portion of the cavity 5 extends beyond the sides of the bottom surface (rectangle) of the chip 7 when viewed from the front surface side of the PCB 3 (the positive direction of the z-axis). The reason why the chip mode resonance frequency of this embodiment can be higher than that of Non-Patent Document 1 is believed to be because the second embodiment uses substantially the same mechanism as the first embodiment. As with the modified example of the first embodiment, the chip mode resonance frequency can be further increased by obliquely deforming at least a portion of the contact surface of the base 2 at the portion that contacts the back surface of the chip 7 (the four corners of the through-hole 4 of the PCB 3 shown in white in Figures 15A and 15B) so that it is not parallel to the back surface of the chip 7.

[0088] (Third embodiment) As shown in FIG. 9, the sample holder 1 of the third embodiment has a configuration in which a PCB 3 is placed on a metal pedestal 2. The third embodiment uses the same PCB 3 as described with reference to FIGS. 11A to 11E in the first embodiment. In the third embodiment, a cavity 5 having a structure as shown in FIGS. 17A to 17C is formed in the portion of the pedestal 2 directly below the through-hole 4 of the PCB 3—in other words, in the portion of the sample holder 1 directly below the chip when the chip is mounted on the pedestal 2. FIGS. 17A, 17B, and 17C are a perspective view, a top view, and a perspective view (perspective side view) of the sample holder 1 of the third embodiment, respectively, as viewed from the positive y-axis direction. As shown in FIG. 17A, the cavity 5 formed in the pedestal 2 in this embodiment has a hemispherical (hollow hemispherical) shape. The diameter a of the hemisphere is longer than the length of one side of the rectangular bottom surface of the chip (FIG. 17C). Therefore, as shown in FIG. 17B, when viewed from the front surface side of PCB 3 (positive direction of the z-axis), the upper surface of cavity 5 appears circular, and at least a portion of the circumference extends beyond the edge of chip 7 (the edge corresponding to through-hole 4 of PCB 3). In the third embodiment, cavity 5 has a hemispherical shape, and therefore becomes narrower as it goes downward. Therefore, even if the diameter a of cavity 5 is equal to the diagonal line of the bottom surface of chip 7, it is possible to prevent chip 7 from falling into the cavity when mounted on sample holder 1. Therefore, the upper limit of diameter a of cavity 5 can be set to the same length as the diagonal line of the bottom surface of chip 7. In FIGS. 17A to 17C, cavity 5 is shown in a different gradation (color) from PCB 3, etc., in order to clearly indicate cavity 5.

[0089] 18 shows the simulation results of S11 when the chip 107 of FIG. 4 is mounted on the sample holder 1 of the third embodiment with bonding wires 13. In the simulation, the chip area was set to 5 mm × 5 mm, and a = 5.84 mm. As shown in FIG. 18, the lowest resonant frequency of the chip mode can be increased to 20.9 GHz, which is higher than that of FIG. 6A (in the case of Non-Patent Document 1).

[0090] The third embodiment differs from the first and second embodiments in the shape of the cavity, but has the same concept as the first and second embodiments in that, when viewed from the front surface side (positive direction of the z-axis) of the PCB 3, part of the cavity 5 extends to the outside of the chip 7. It is believed that the reason why the third embodiment was able to increase the resonant frequency of the chip mode compared to Non-Patent Document 1 is due to the same mechanism as the first and second embodiments.

[0091] (Another example of the third embodiment) 19A, 19B, and 19C show another example of the sample holder 1 according to the third embodiment. In this example, the diameter a of the cavity 5 formed in the base 2 is set to be approximately the same as the diagonal length of the rectangular bottom surface of the chip 7 (FIG. 19C) (the diagonal length of the through-hole 4 in the PCB 3). The cavity 5 has a hemispherical shape and narrows downward. This prevents the chip 7 from falling into the cavity 5 when the chip 7 is mounted on the PCB 3 of the sample holder 1 using bonding wires 13. FIG. 20 shows the simulation results of the S-parameter S11 when the pads of the chip 7 are mounted on the PCB 3 using bonding wires 13 on the sample holder 1 according to this example. In the simulation, the chip area was set to 5 mm × 5 mm, and a = 7.08 mm. As shown in FIG. 20, according to the modified example of the third embodiment, the lowest resonant frequency of the chip mode can be further increased to 23.1 GHz. The reason why the resonant frequency was able to be made higher than in the case of Figure 18 is that in the case of Figure 18, the space between the GND plane of chip 7 and base 2 in the four corner areas of chip 7 is made of silicon and therefore has a high dielectric constant, whereas in the case of this example, the space between the GND plane of chip 7 and base 2 in the four corner areas of chip 7 is made of silicon and vacuum, which results in a lower effective dielectric constant.

[0092] (Other embodiments) In the first to third embodiments and their modifications, the method for mounting a superconducting quantum circuit chip has been described as being such that the chip 7 is placed directly on the metal pedestal 2, but the mounting method is of course not limited to this. For example, even in a mounting form in which a resin material such as varnish is applied to the metal pedestal 2 and then the chip 7 is placed on the resin material such as varnish, the effect of each embodiment, i.e., the effect of being able to further increase the resonant frequency of the chip mode, can be achieved.

[0093] Furthermore, in the first to third embodiments and their modifications, the sample holder 1 is configured such that the PCB 3 is placed directly on the metal pedestal 2. However, the effects of each embodiment can also be achieved with a sample holder 1 configured such that a metal sheet, such as In (indium), is placed on the metal pedestal 2, and the PCB 3 is placed on the metal sheet. By sandwiching a soft metal sheet, such as In, between the pedestal 2 and the PCB 3, it is possible to reduce the occurrence of a gap between the GND 11 on the back surface of the PCB 3 and the pedestal 2. This may improve the high-frequency characteristics of the sample holder 1. Specifically, if a gap exists between the back surface of the PCB 3 and the pedestal 2, the gap will form a new cavity resonator. This may cause resonance when a signal of a specific frequency is input to the chip. For this reason, it is preferable to eliminate a gap between the GND plane 11 on the back surface of the PCB 3 and the pedestal 2.

[0094] Furthermore, in the first to third embodiments and their modifications, the sample holder 1 has been described as being configured such that the PCB 3 is placed on the metal pedestal 2. However, a metal lid may be placed on the PCB 3. Even when a lid is placed, the effects of each embodiment can be obtained. In such a sample holder 1, the metal lid is in electrical contact with the surface GND 9 of the PCB 3. However, the lid should not come into contact with the core wires 10 of the PCB 3 or the chip 7. This is to prevent the core wires 10 of the PCB 3 and the circuits and wiring of the chip 7 from coming into contact with the GND. For the same reasons as above, it is preferable that there be no gap between the lid and the surface GND 9 of the PCB 3. For this reason, a sheet of In or the like may be sandwiched between the lid and the surface GND 9 of the PCB 3.

[0095] In the first to third embodiments and their modifications, the pedestal 2 is exemplified as a rectangular parallelepiped or cubic shape as the shape of the sample holder 1, but the effects of the above embodiments can be achieved even if the shape of the pedestal 2 is another shape, such as a cylinder. Similarly, the effects of the above embodiments can be achieved even if the shape of the PCB 3 is a shape other than a rectangle or a square, such as a circle.

[0096] The disclosure of the first to third embodiments and their modifications can be applied to the implementation technology of superconducting quantum circuits.

[0097] The disclosures of Patent Document 1 and Non-Patent Document 1 are incorporated herein by reference. Modifications and adjustments of the embodiments and examples are possible within the scope of the entire disclosure of the present invention (including the scope of the claims), and further based on the basic technical idea. Furthermore, various combinations and selections of the various disclosed elements (including each element of each claim, each element of each example, each element of each drawing, etc.) are possible within the scope of the claims of the present invention. In other words, the present invention naturally includes various modifications and alterations that would be possible for a person skilled in the art based on the entire disclosure, including the scope of the claims, and the technical idea. [Explanation of symbols]

[0098] 1 sample holder 2 pedestal 3 PCB 4 PCB through holes 5 cavities 6 pillars 61 Upper 62 Lower 7 chips 71 First Coplanar Waveguide 72 Second Coplanar Waveguide 73 GND plane 74 First Core Wire 75 Second core wire 76 First Pad 77 Second Pad 8 Dielectrics 9 PCB surface GND 10 PCB core wire 11 PCB backside GND 12 through holes 13 Bonding wire 101 Sample Holder 102 Pedestal 103 PCB 104 PCB through holes 105 Cavity 106 pillars 107 chips 108 Dielectric 109 PCB surface GND 110 PCB core wire 110a PCB first core 110b PCB second core 111 PCB backside GND 112 through hole 113 Bonding Wire

Claims

1. A metal base and a PCB (Printed Circuit Board) placed on the base; Equipped with The PCB has a through hole formed therein that penetrates from the front surface to the back surface, a bottomed, open-top cavity is formed directly below the through hole on the side of the base on which the PCB is placed, When the side of the base on which the PCB is placed is viewed from above, a part of the cavity protrudes outward from the through hole. Sample holder.

2. The cavity has a cross shape at least on the top surface. The sample holder of claim 1 .

3. The cavity has a shape of a hollow cylinder with a bottom and an open top. The sample holder of claim 1 .

4. The cavity is in the shape of a hollow hemisphere with an open top. The sample holder of claim 1 .

5. When the chip is mounted in the through hole of the PCB, at least a part of the contact surface of the base that comes into contact with the chip is not parallel to the back surface of the chip. A sample holder according to any one of claims 1 to 4.

6. the through hole of the PCB is a rectangular opening without a bottom corresponding to the rectangular planar shape of the chip to be mounted in the through hole, The cavity formed in the base is a rectangular, bottomed upper opening corresponding to the planar shape of the through hole; support members are provided at four corners of the rectangular bottomed top opening to support the chip when the chip is mounted; The configuration of the side of the base on which the PCB is placed as viewed from above is as follows: The cavity protrudes outward by a predetermined width in a part or all of the areas excluding the area where the support member is disposed with respect to a part or all of the sides connecting two adjacent corners of the through hole.

3. A sample holder according to claim 1 or 2.

7. the support member is made of a pillar disposed at each corner of the rectangular bottomed top opening, The pillar is a triangular pillar, or the upper part is a triangular pyramid or a triangular pyramid truncated.

7. The sample holder of claim 6.

8. the through hole of the PCB is a rectangular opening without a bottom corresponding to the rectangular planar shape of the chip to be mounted in the through hole, When the side of the base on which the PCB is placed is viewed from above, the cavity of the hollow cylinder has a region in which at least a circular opening on the upper surface protrudes radially outward by a predetermined length with respect to some or all of the sides connecting two adjacent corners of the through hole.

4. The sample holder of claim 3.

9. the through hole of the PCB is a rectangular opening without a bottom corresponding to the rectangular planar shape of the chip to be mounted in the through hole, When the side of the base on which the PCB is placed is viewed from above, the cavity of the hollow hemisphere has a region in which a circular opening on an upper surface thereof protrudes radially outward by a predetermined length with respect to some or all of the sides connecting two adjacent corners of the through hole.

5. The sample holder of claim 4.

10. a chip on which a superconducting quantum circuit is formed is placed at the through-hole of the sample holder according to any one of claims 1 to 9; The chip and the PCB are electrically connected. Superconducting quantum computer.

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